TWI515879B - Wafer level microelectronic imager - Google Patents

Description

Wafer-level microelectronic imager

This invention relates to a microelectronic imager, and more particularly to a wafer level microelectronic imager.

With the advancement of electronic technology, microelectronic imagers are increasingly used in electronic devices. Microelectronic imagers can be applied to portable electronic devices such as tablet computers, handheld game devices or mobile phones. A general microelectronic imager is mainly composed of a plurality of optical lenses and at least one image sensing die, wherein a plurality of optical lenses are stacked according to an optical axis of the optical lens to form an optical lens stack, and the image sensing die is adjacent. It is provided in the above optical lens stack. In addition, the image sensing die described above may be, for example, a Charge-coupled Device (CCD) die or a Complementary Metal-Oxide-Semiconductor (CMOS) die.

The microelectronic imager mainly uses an optical lens stack to receive external light, and when the external light passes through the plurality of optical lenses to the image sensing die, the image sensing die can convert the received optical signal into an electronic digital position. Signals to facilitate subsequent steps such as storage.

In microelectronic imagers, optical performance requirements are primarily achieved by varying the relative position of multiple optical lenses to each other. When the relative positions of the plurality of optical lenses are changed from each other, the traveling path of the light between the adjacent optical lenses and the traveling path of the light emitted from the optical lens at the end of the optical lens stack are changed accordingly, so that This adjusts the optical performance of the microelectronic imager.

However, in the microelectronic imager currently on the market, there is usually a disadvantage that the overall thickness is too large, so that the thinning of the electronic device using the microelectronic imager is rather disadvantageous.

Therefore, the object of the present invention is to provide a wafer level microelectronic imager, wherein the image sensing die is not covered by a component such as a glass substrate before being bonded to the optical lens stack, so the image sensing die After being bonded to the optical lens stack, it is directly adjacent to one side of the optical lens stack.

According to an embodiment of the present invention, a wafer level microelectronic imager suitable for an electronic device includes a housing having an internal space, an optical lens stack fixedly disposed in the internal space, and an optical lens disposed adjacent to the optical lens The image sensing die on one side of the stack, and the transparent bonding medium. The optical lens stack includes a plurality of optical lenses stacked along an optical axis, and at least one first spacer element disposed between the optical lenses. The first spacer element forms a sealed first space between adjacent ones of the plurality of optical lenses. In addition, the housing, the image sensing die, and one of the plurality of optical lenses define a second space, and the transparent bonding medium fills the second space.

In accordance with another embodiment of the present invention, in the wafer level microelectronic imager module described above, the transparent bonding medium is a bonding paste.

The invention has the advantages that the overall thickness of the wafer level microelectronic imager can be reduced by reducing the package components of the image sensing die, thereby facilitating the thinning of the electronic device using the wafer level microelectronic imager. Reducing the package components further reduces the manufacturing cost of the wafer level microelectronic imager.

In addition, since the space defined by the housing, the image sensing die, and one of the plurality of optical lenses is filled with the transparent bonding medium, the image sensing die and the optical lens stack can be brought more. Good bond strength, thereby increasing the durability of wafer level microelectronic imagers.

Please refer to FIG. 1 , which is a cross-sectional view showing a wafer level microelectronic imager according to an embodiment of the present invention. The wafer level microelectronic imager 100 is suitable for use in electronic devices such as portable tablets, handheld game devices or cell phones. In the general case, a plurality of wafer level microelectronic imagers 100 are first formed on a wafer and sliced by a wafer saw to produce a single wafer level microelectronic imager 100.

In the present embodiment, the wafer level microelectronic imager 100 includes a housing 102, an optical lens stack 104, image sensing dies 106, and a transparent bonding medium 114. In the housing 102, it has an internal space 102a. The primary function of the housing 102 is to cover and secure the various components of the optical lens stack 104 to be described below, as well as the image sensing die 106, thereby forming a single wafer level microelectronic imager 100.

As described above, the optical lens stack 104 is fixedly disposed in the internal space 102a of the above-described housing 102. In addition, optical lens stack 104 includes a plurality of optical lenses 108a and 108b and at least a first spacer element 110. In the present embodiment, optical lens stack 104 includes only two optical lenses 108a and 108b. In a particular embodiment, the number of optical lenses can be adjusted as needed, which is not limited to this embodiment. Further, in the present embodiment, the optical lenses 108a and 108b are stacked along their own optical axis 108c. Specifically, the two optical axes 108c of the two optical lenses 108a and 108b overlap each other. However, in a particular embodiment, the plurality of optical lenses have a plurality of optical axes 108c that do not overlap each other, and the optical axes 108c are arranged only in a mutually parallel manner.

As for the first spacer element 110, it is mainly disposed between the two optical lenses 108a and 108b such that a sealed first space 110a is formed between the adjacent two optical lenses 108a and 108b. The number of the first spacer elements 110 is mainly adjusted according to the number of optical lenses. The number of the first spacer elements 110 needs to be at least one less than the number of optical lenses, thereby forming an adjacent optical lens. The sealed first space 110a is shown in Fig. 1. However, in the present embodiment, the optical lens stack 104 includes, in addition to the first spacer element 110 disposed between the two optical lenses 108a and 108b, two second spacers disposed outside the optical lenses 108a and 108b. Element 116 and second spacer element 118. The relative position and effect of the two additional second spacer elements 116 and second spacer elements 118 with other elements will be further described below.

The image sensing die 106 is disposed adjacent to one side of the optical lens stack 104, wherein the image sensing die 106 is mainly used to receive an image light source from the optical lens stack 104, and the image light source is Convert to digital signal. In this embodiment, the image sensing die 106, the housing 102, and the optical lens 108b define a second space 120, and the second space 120 is mainly used to accommodate the transparent bonding medium 114. That is, the transparent bonding medium 114 fills the second space 120. In addition, since the housing 102, the image sensing die 106, and the second space 120 defined by the optical lens 108b are filled with the transparent bonding medium 114, the image sensing die 106 and the optical lens stack 104 may be This results in better bond strength, thereby increasing the durability of the wafer level microelectronic imager 100.

As shown in FIG. 1 , between the image sensing die 106 and the housing 102 , the image sensing die 106 has a specific distance from the housing 102 due to the filling of the transparent bonding medium 114 . However, in certain embodiments, the amount of fill of the transparent bonding medium 114 can be reduced such that the image sensing die 106 is in direct contact with the housing 102. In addition, in other embodiments, the volume of the image sensing die 106 can be reduced, and only the image sensing die 106 can receive the image light source from the optical lens stack 104.

In a conventional process, before the image sensing die 106 is bonded to one side of the optical lens stack 104, the image sensing die 106 is typically packaged with a package component such as a glass substrate, and then packaged. The image sensing die 106 is bonded to the optical lens stack 104. However, compared with the conventional process, the wafer-level microelectronic imager 100 of the present invention omits the above-mentioned package components, so that the overall thickness of the wafer-level microelectronic imager 100 can be effectively reduced, which is advantageous for adoption. The electronic device of the wafer level microelectronic imager 100 is thinned. In addition, the above-described package components are omitted, and the process of packaging the image sensing die 106 by the package components can be omitted, thereby reducing the manufacturing cost of the wafer-level microelectronic imager 100.

Additionally, in certain embodiments, image sensing die 106 can be a CCD die or a CMOS die. In a particular embodiment, the transparent bonding medium 114 is a bonding glue.

As shown in FIG. 1 , in the present embodiment, the optical lens stack 104 of the wafer level microelectronic imager 100 further includes a second spacer element 116 and a second spacer element 118 . The second spacer element 116 is disposed in the inner space 102a of the housing 102 and is in contact with the inner side surface of the housing 102. In addition, the second spacer element 116 is disposed adjacent to the other side of the optical lens stack 104 opposite to one side of the image sensing die 106. Furthermore, the arrangement of the second spacer element 116 can be used to enhance the strength of the housing 102 and increase the pressure resistance of the housing 102.

The second spacer element 118 is disposed in the second space 120 defined by the image sensing die 106, the housing 102, and the optical lens 108b, and the second spacer component 118 and the housing 102. Side contact. Wherein, the second spacer element 118 is similar to the second spacer element 116 and can also be used to strengthen the strength of the housing 102, thereby increasing the pressure resistance of the housing 102. However, the arrangement of the second spacer elements 118 can further reduce the amount of use of the transparent bonding medium 114 while increasing the contact area of the transparent bonding medium 114 that can be adhered, thereby improving the durability of the wafer level microelectronic imager 100.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100. . . Wafer-level microelectronic imager

102. . . case

102a. . . Internal space

104. . . Optical lens stack

106. . . Image sensing grain

108a-108b. . . optical lens

108c. . . Optical axis

110. . . First spacer element

110a. . . First space

114. . . Transparent bonding medium

116. . . Second spacer element

118. . . Third spacer element

120. . . Second space

For a better understanding of the present invention, reference is made to the above detailed description and the accompanying drawings. It is emphasized that, in accordance with the standard of the industry, the various features in the drawings are not to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced in order to clearly illustrate the above embodiments. The relevant schema description is as follows.

1 is a cross-sectional view of a wafer level microelectronic imager in accordance with an embodiment of the present invention.

100. . . Wafer-level microelectronic imager

102. . . case

102a. . . Internal space

104. . . Optical lens stack

106. . . Image sensing grain

108a-108b. . . optical lens

108c. . . Optical axis

110. . . First spacer element

110a. . . First space

114. . . Transparent bonding medium

116. . . Second spacer element

118. . . Third spacer element

120. . . Second space

Claims (4)

A wafer level microelectronic imager for an electronic device, wherein the wafer level microelectronic imager comprises: a housing having an internal space; and an optical lens stack fixedly disposed in the internal space, wherein the The optical lens stack includes: a plurality of optical lenses stacked along an optical axis of the optical lenses; and at least one first spacer element disposed between the optical lenses such that the optical lenses are formed adjacent to each other One of the first spatial spaces is sealed; an image sensing die is disposed adjacent to one side of the optical lens stack, wherein the housing, the image sensing die, and one of the optical lenses define a second And a transparent bonding medium filling the second space for bonding the optical lens stack and the image sensing die, wherein the transparent bonding medium is a bonding glue. The wafer level microelectronic imager of claim 1, wherein the optical lens stack further comprises: a second spacer element disposed in the second space and in contact with an inner side surface of the housing. A wafer level microelectronic imager as claimed in claim 1, wherein the light The lens stack further includes: a second spacer element disposed in the inner space of the housing, in contact with an inner side surface of the housing, and the second spacer element is disposed adjacent to the other side of the optical lens stack . The wafer level microelectronic imager of claim 1, wherein the image sensing die is selected from the group consisting of a charge coupled device die and a complementary metal oxide semiconductor die.