TWI515759B - Data path for a charged particle lithography apparatus - Google Patents

Description

Data path for charged particle lithography equipment

The present invention relates to maskless charged particle lithography apparatus, and more particularly to data paths, methods for implementing the modifications, and scanning methods for such devices.

The design for the integrated circuit is typically represented in a computer readable file. The GDS-II file format (GDS standard for graphic data signals) is a database file format, which is a lithography industry standard for data exchange of integrated circuit or IC layout original drawings. For lithographic machines that use a mask, it is typical to use a GDS-II file to make a mask or set of masks that are then used by the lithography machine. For unshielded lithography machines, the GDS-II file is electronically processed to make it a format suitable for controlling lithography machines. For charged particle lithography machines, the GDS-II file is converted into a set of control signals for controlling the charged particle beam used in the lithography process.

A pre-processing unit can be used to process the GDS-II file to generate intermediate data for the current lithography system. Depending on the architecture options, this intermediate data is in a bitmap format or a region description in vector format. Current lithography systems use intermediate data to use a large number of electron beams to write patterns to the wafer.

The architecture of the data path must be defined to implement all of the features it needs to be able to scale up to the high capacity of the universe at the lowest cost. The data path characteristics required for a global high volume machine contain different types of corrections required for tool calibration and process variation.

In one aspect, the present invention provides a charged particle lithography system for exposing a wafer based on pattern data. The system comprises: an electron optical column for generating a plurality of electron beamlets for exposing the wafer, the electron optical column comprising a beamlet extinguisher array for turning the beamlets on or off; a data path for And transmitting a beamlet control data for small beam switching control; and a wafer positioning system for moving the wafer below the electron optical column in the x direction. A wafer positioning system having a synchronization signal from the data path is supplied to align the wafer with the electron beam from the electron optical column. The data path further includes one or more processing units for generating beamlet control data and one or more transmission channels for transmitting the beamlet control data to the beamlet blanker array.

The transmission system can include a plurality of transmission channels, each of which is for transmitting data for the corresponding beamlet group. The beamlets may be arranged in a plurality of groups, each of the transmission channels being for transmitting beamlet control data for one of the beamlet groups. The data path can include a plurality of multiplexers, each multiplexer being multiplexed to transmit beamlet control data for a small bundle group. The system may further comprise a plurality of demultiplexers, each demultiplexer being used to demultiplex transmission of small beam control data for a small bundle group. The data path can include an electrical to optical conversion device for converting the beamlet control data generated by the processing units into an optical signal for transmission to a charged particle lithography machine.

The transmission channel can include an optical fiber for directing an optical signal, and the beamlet blanker array can include an optical to electrical conversion device for receiving the optical signal and converting it to an electrical signal for control of the beamlets . The transmission system can include a lens array for directing optical signals onto the mirror, and a mirror mirror for the beamlet extinguisher array for reflecting optical signals to the charged particle lithography machine.

The system can further include: a first number of processing units sufficient to process the pattern data to generate a first small subset of the first subset of the beamlets allocated for exposing the first portion of the wafer Beam control data. The system can further include a cross-connect switch for connecting the processing unit to a subset of the transmission channels.

The beamlets may be arranged in a plurality of groups, each processing unit is configured to generate beamlet control data for any of the beamlet groups, and each of the transmission channels is dedicated to transmission for the beamlet groups The small bundle of control data for one. Seven processing units are available for every twelve transmission channels.

The charged particle lithography system can have a first subset of the sub-beams that are used to expose a first portion of the wafer and a second subset of the sub-beams that are used to expose a second portion of the wafer, and A cross-connect switch can connect the processing units to a first subset of the transmission channels corresponding to a first subset of the sub-beams for a first partial scan of the wafer, and the cross-connect switch can An equal processing unit is coupled to the second subset of the transmission channels, which corresponds to a second subset of the sub-beams for the second partial scan of the wafer. The first number of processing units may be sufficient for processing the pattern data to generate the first beamlet control data and processing the pattern data to generate the second beamlet control data, but the south is insufficient for processing the pattern data to simultaneously generate the first One and the second small beam control data.

The lithography system is adapted to expose the wafer by two scans, wherein the first portion of the wafer is exposed according to the first pattern data and then the second portion of the wafer is exposed according to the second pattern data, and the The processing unit may include a memory, and the memory is divided into a first memory portion for storing the first pattern data and a second memory portion for storing the second pattern data, and the crystal in the current batch During the second partial exposure of one of the wafers, the first pattern data for one of the next batch of wafers can be loaded into the first memory portion.

In another aspect, the invention comprises a method for exposing a wafer in a charged particle lithography system. The method comprises: generating a plurality of charged particle beamlets, the beamlets are arranged in groups, each group comprising a beamlet array; the wafer is scanned at a wafer speed in a first direction under the beamlets Moving; deflecting the beamlets at a deflection scan speed toward a second direction substantially perpendicular to the first direction; and adjusting the wafer scanning speed to adjust a dose applied to the wafer by the beamlets. The beamlets may use a parallel projection write strategy to expose the wafer, and the deflection scan speed may include a beamlet scan speed and a flyback speed.

Each of the beamlet arrays may have a projection pitch P _proj in a first direction between the _beamlets of the array, and a group distance equal to a projection pitch P _proj multiplied by the number of _beamlets in the array, and which corresponds to each scan The scan step between the beamlets and the wafer in the x direction is equal to the group distance divided by the integer K. The scan step can be adjusted by adjusting the beamlet scanning speed and/or the flyback speed, or by adjusting the beamlet deflection period, which includes a small beam scan time and small beam return for the y direction. Chi time. The deflection period can be equal to the group distance divided by the integer K divided by the beamlet scanning speed. This method can be such that K satisfies the requirement that K is the largest common denominator of the number of beamlets in each array.

In yet another aspect, the present invention is directed to a method for exposing a wafer in a charged particle lithography system. The method includes: generating a plurality of charged particle beamlets, the beamlets are arranged in groups, each group comprising a beamlet array; moving the wafer below the beamlets in a first direction at a wafer scanning speed The beamlets are deflected at a deflection scan speed in a second direction substantially perpendicular to the first direction; when the beamlets are deflected to expose pixels on the wafer, the beamlets are based on the pattern data Turning on and off; and adjusting the wafer scanning speed relative to the deflection scanning speed to adjust the pixel width in the first direction.

The beamlets can use a parallel projection write strategy to expose the wafer, and the deflection scan speed includes a beamlet scanning speed and a flyback speed. Each of the beamlet arrays may have a projection pitch P _proj in the first direction between the _beamlets of the array and a group distance equal to the projection pitch P _proj multiplied by the number of _beamlets in the array, and may correspond to each scan room The scan step relative to the relative movement between the beamlets and the wafer in the x direction is equal to the group distance divided by the integer K. The scan step can be adjusted by adjusting the beam scan speed and/or the flyback speed. The scan step can be adjusted by adjusting the beamlet deflection period, which includes a time for a small beam scan toward the y direction and a small beam flyback time. The deflection period can be equal to the group distance divided by the integer K divided by the beamlet scanning speed. This method can be such that K satisfies the requirement that K is the largest common denominator of the number of beamlets in each array.

In yet another aspect, the present invention provides a method for exposing a wafer in a charged particle lithography system. The method includes: generating a plurality of charged particle beamlets, the beamlets being arranged in groups, each group comprising a beamlet array; causing relative movement between the beamlets and the wafer in a first direction; The beamlets are deflected at a deflection scan speed in a second direction substantially perpendicular to the first direction such that each beamlet exposes a plurality of scan lines on the wafer; and, adjusting the relative movement toward the first direction The beam deflection in the second direction adjusts the dose given to the wafer by the beamlets. Each array having between beamlets of the array of beamlets in a first direction and a projection pitch P _proj is equal to the projection pitch P _proj group multiplied by the number of beamlets in the array the distance between each scan and in such The relative movement between the beamlet and the wafer in the x direction is equal to the group distance divided by the integer K.

The value K can be chosen such that the maximum common denominator of K and the number of beamlets in each array is one. The width of the scan line can be the projection pitch P _proj divided by the integer K. When the beamlets are deflected to expose pixels on the wafer, the beamlets can be turned on and off according to the pattern data, and the pixel width in the first direction can be the projection pitch P _proj divided by Integer K.

The various embodiments of the invention are described below by way of example only and with respect to the drawings.

Charged particle lithography system

1 is a conceptual diagram showing a charged particle lithography system 100 that is divided into three higher order subsystems: a wafer positioning system 101, an electron optical column 102, and a data path 103. The wafer positioning system 101 moves the wafer below the electron optical column 102 in the x direction. The wafer positioning system 101 is supplied with a synchronization signal from the data path 103 to align the wafer with the electron beamlets produced by the electron optical column 102.

2A shows a simplified schematic of an embodiment of a charged particle lithography system 100 showing details of an electron optical column 102. For example, such lithography systems are described in U.S. Patent Nos. 6,897,458, 6,958,804, 7,019,908, 7, 084, 414, and 7, 129, 502, U.S. Patent Application Publication No. 2007/0064213 Patent Application Serial Nos. 61/031,573, 61/031,594, 61/045,243, 61/055,839, 61/058,596 and 61/101,682, all of which are for the transfer of US patents. The owner of the present application and the entirety thereof is incorporated herein by reference.

In the embodiment illustrated in FIG. 2A, the lithography system includes a charged particle source 110, such as an electron source for generating an extended electron beam 130. The extended electron beam 130 impinges on the aperture array 111, which blocks a portion of the beam to produce a plurality of beamlets 131. The system produces a plurality of small bundles, preferably in the range of about 10,000 to 1,000,000 small bundles.

The electron beamlet 131 passes through a concentrating lens array 112 that focuses the electron beamlets 131. The beamlet 131 is collimated by the collimator lens system 113. The collimated electron beamlets pass through the XY deflector array 114, the second aperture array 115, and the second concentrating lens array 116. The resulting beamlets 132 then pass through a beamer array 117 that includes a plurality of extinguishers to deflect one or more of the beamlets. The beamlets pass through the mirror 148 and arrive at a stop array 118 having a plurality of apertures. The beamlet blanker array 117 operates in conjunction with the beam stop array 118 to turn the beamlets on or off by blocking or passing the beamlets. The beamlet blanker array 117 can deflect the beamlets such that they will not pass through the corresponding apertures in the beam stop array 118 but will be blocked. If the beamlet blanker array 117 does not deflect the beamlets, it will pass through the corresponding apertures in the beam stop array 118. The undeflected beamlets pass through the beam pupil array and through the beam deflector array 119 and the projection lens array 120.

Beam deflector array 119 provides deflection of each beamlet 133 in the X and/or Y direction (substantially perpendicular to the direction of the undeflected beamlets) to scan the beamlets throughout the surface of target 104. This deflection is different from the deflection used by the beamletter array to turn the beamlets on or off. Next, the beamlets 133 pass through the projection lens array 120 and are projected onto the target 104. The projection lens configuration preferably provides a reduction of about 100 to 500 times. The beamlets 133 impinge on the surface of the target 104, which is positioned on the movable stage of the wafer positioning system 101. For lithography applications, the target typically includes a wafer that provides a charged particle sensitive layer or a resist layer.

The representative diagram shown in Fig. 2A is extremely simplified. In a preferred embodiment, a single electron beam is first segmented into a plurality of smaller beamlets, which are then divided into more beamlets. Such a system is described in U.S. Patent Application Serial No. 61/045,243, the entire disclosure of which is incorporated herein by reference.

In this system, each sub-beam is divided into several small beams, which can be regarded as a pattern bundle. In one embodiment, each beamlet is divided into 49 beamlets arranged in a 7x7 array. The beamlet blanker array preferably includes a hole having associated extinguisher electrodes for each beamlet to enable on/off switching of individual individual beamlets. Figures 3 and 4 show a portion of the beamlet blanker array, with each bundle being arranged in a 3x3 array for each of the pattern bundles having nine beamlets. The beamlet arrangement and writing strategy in the pattern bundle is described, for example, in U.S. Patent Application Serial No. 61/058,596, the disclosure of which is incorporated herein by reference.

The beam deflector array and the projection lens array preferably include only one aperture and lens for each pattern bundle (e.g., a small aperture or lens for each of the 49 small bundles that make up a pattern bundle). A small bundle is typically combined (interleaved/multiplexed) in a group in which it is written into a single stripe.

Data path architecture

A simplified block diagram of one embodiment of data path 103 is shown in Figure 2B, and a portion of the data path also appears in Figure 2A. The switching of the beamlet blanker array 117 is controlled via a data path. The pre-processing unit 140 receives information describing the layout of the device to be manufactured by the lithography machine. This information is typically provided in the GDS-II file format. The pre-processing unit performs a series of transformations of the GDS-II file to generate an on/off control signal to control the beamlet blanker array 117.

The control signal is transmitted to an electro-optical conversion device 143 (such as a laser diode) to convert the electrical control signal into an optical signal. The optical control signal is directed through fiber 145. The beam 146 at the output of the fiber is directed through the lens 147 of the array onto the apertured mirror 148. From the mirror, the beam is reflected onto the bottom side of the beam extinguisher array 117. The individual beams are directed to a plurality of photoelectric conversion devices (such as photodiodes) on the bottom side of the beam extinguisher array 117. Preferably, the beamlet extinguisher array has a photodiode for each fiber 145. The photodiode operates to actuate individual beam extinguisher electrodes to control the deflection of the beamlets 132 to turn individual beamlets on or off.

The control signals for controlling the individual beamlet extinguisher electrodes are preferably multiplexed such that each beam 146 carries a control signal for a channel that includes a plurality of beamlets that share a fiber and a photodiode . The multiplex beam is received by the photodiode and converted to an electrical signal. The beamlet blanker array 117 includes logic operations for demultiplexing the control signals received by the photodiodes to derive control signals for individually controlling the plurality of beamlet extinguisher electrodes. In a preferred embodiment, the individual control signals for controlling the 49 beamlets of a pattern beam are time multiplexed for transmission on a single fiber and are a single photodiode on the beamlet extinguisher array. Received.

In addition to multiplexing, the beamlet control signal can also be framed for transmission and can have synchronization bits and additional coding to improve transmission, for example, using coding techniques to achieve frequent signal transitions to prevent DC coupling. The method uses a laser diode and a photodiode. By forcing the transition, the clock signal is automatically distributed in the optical signal. Figure 12 shows an example of a beamlet control signal with 49 small bundles of framing, sync bits and multiplex control bits (of a pattern bundle).

At a closer proximity to the wafer, a beam deflector array 119 is used to deflect the electron beamlets in the y-direction (and a small amount of deflection in the x-direction) to achieve electron beam scanning across the surface of the wafer 104. In the illustrated embodiment, wafer 104 is mechanically moved in the x-direction by wafer positioning system 101, and the electron beamlets are scanned throughout the wafer in a y-direction substantially perpendicular to the x-direction. When data is written, the beamlet is slowly deflected in the y direction (as compared to the flyback time). At the end of the sweep, the beamlet is moved quickly back to the starting position of the y range (this is called the flyback). Beam deflector array 119 receives timing and synchronization information from data path 103.

aisle

The data path can be divided into several channels. The channel is an electronic data path from the preprocessing unit to the lithography system. In one embodiment, the channel includes an electrical to optical converter (eg, a laser diode), a single fiber for transmitting a beamlet control signal, and an optical to electrical converter (eg, a photodiode). This channel can be specified to transmit control signals for a single pattern bundle, which contains several individual beamlets (eg, 49 beamlets that make up a pattern beam). A pattern bundle can be used to write a single strip on the wafer. In this configuration, the channel represents a data path component dedicated to controlling a pattern bundle containing a plurality of beamlets (eg, 49 beamlets) and carrying a beamlet control signal to write a bar based on the pattern data. band. A subchannel represents a data path component that is dedicated to control a single beamlet within a pattern bundle.

Data processing

The data path 101 transforms the layout data into an on/off signal for controlling the electron beamlet. As described above, this transformation can be performed at pre-processing unit 140, which performs a series of transformations on layout data, typically in the form of GDS-II or similar files. This process typically includes: flattening/preprocessing, rasterization, and multiplexing steps.

The flattening/preprocessing step transforms the layout data format into a dose map. The dose map describes the area on the wafer in a vector format with associated dose rate values. This step may include some pre-processing such as proximity effect correction. Because of the complexity of the pre-processing, this step is preferably performed offline. The rasterization step transforms the dose map into a streamed control (on/off) signal. The multiplex step is to package the beamlet control signal according to the multiplex scheme.

The method for writing a wafer in a lithography machine can be roughly described in the order of the following steps. The wafer 104 is mounted on a stage of the wafer positioning system 101, the column 102 is maintained under vacuum conditions, and the beamlets are calibrated. The wafer is mechanically aligned and is calculated according to the alignment (offset) of the field. The wafer is moved by the station in the +x direction and the column begins to write to the first field. When the aperture of the leading column of the beamlet blanker array passes through a field boundary, the offset correction is set for the next field. Therefore, when the first field is still being written, the lithography system will begin writing to the next field. After writing the last field in a column, the station will be moved to position the field of the next column on the wafer below the beamlet blanker array. When the station moves in the -x direction, a new run will begin. The scanning deflection direction is preferably unchanged.

Correction

The data processing performed by the data path provides some different adjustments to the beamlet control signal for various types of corrections and compensation. For example, such corrections and compensations can include proximity correction and resist heating correction to compensate for the effects that occur as a result of using resist properties. Data adjustments may also include modifications designed to compensate for errors or failures that occur in the lithography machine.

In a preferred embodiment of a charged particle lithography machine, the lithography machine does not have any built-in facilities for adjusting individual electron beamlets to correct for errors in beam position, size, current, or other characteristics of the beam. Missing is such as: misalignment or failure of small bundles, low beam currents of low or high, and incorrect deflection of beamlets. Such deletions may be the result of defects or tolerance changes in the manufacture of lithographic machines, the blocking of small bundles or the turning off of dirt or dust that is charged and deflected, the failure or degradation in machine components, and the like. The lithography machine omits corrective lenses or circuits for making individual corrections to the beamlets to avoid the additional complexity and cost involved in incorporating additional components into the electron beam to make the actual beam correction, and avoiding the inclusion of such Additional components require an increase in the size of the column. However, the modulation of the beamlet control signals and/or the additional scanning of the wafer can compensate for these types of problems. Failures that occur in the data path can also be corrected by the modulation of the control signal and along with the rescan of the wafer. The various methods used to make these modifications are described below.

Redundant scan

The above described charged particle lithography machine embodiment has a plurality of optical fibers and laser diodes in the data path, a plurality of electrostatic lenses and deflectors for each pattern bundle, and a plurality of arrays in the beamlet extinguisher array. Extinguisher component. It is highly probable that failures may occur in some of these components or some of these components will degrade or be affected by contaminants so that they are not implemented within specifications. In order to maximize the time between system maintenance, periodic checks can be performed to identify failed or substandard beamlets or data channels. This inspection can be performed prior to each wafer scan, prior to each first scan of the wafer, or at some other convenient time. The inspection may include one or more beam measurements, for example, as described in U.S. Patent Application Serial No. 61/122,591, the disclosure of which is incorporated herein in its entirety by reference. This article. The main goal of redundant scanning is to compensate for the failure that occurs in the EO column due to the time-consuming replacement of the failed portion in the column. However, redundant scanning can also be used to deal with failures in the data path. For example, a failed fiber or laser diode in one channel can be written by the channel that is to be written by the failed channel by cutting the channel during the redundant scan and using another channel. Make corrections.

In the case of a failed or substandard beamlet being detected, the beamlet can be severed such that the strip to be exposed by the beamlet is unwritten. A second scan (referred to as a redundant scan) is then used to write the wafer strips that were omitted during the first scan. In a pattern beamlet system such as that described above, the complete channel including the failed or out-of-spec beamlets can be severed and will not be written to the full strip of the wafer field to be exposed by the beamlets of the channel. band. After the first scan of the entire wafer is performed, a redundant scan can then be performed to fill the missing strips (and any other missing strips for other channels with failed beamlets).

For redundant scanning, the wafer is returned to the starting position after the first scan and is shifted to ensure that the appropriate active channel is the location available for writing the missing strip. The pattern data for the redundant scan is preferably prepared in the lithography system during the first scan, so that the redundant scan can begin as soon as the first scan is completed. Preferably, there is no significant delay between the end of the first scan and the beginning of the redundant scan, so that the data for the redundant scan is preferably fast available on the appropriate node.

The lithography machine preferably is capable of writing a continuous in-line field in one scan and writing in two directions parallel to the x-direction of the mechanical scan (ie: -x and +x directions). . The machine also preferably includes a spare bundle (or pattern bundle) that is typically located at the edge of the column.

In order to write a missing strip during a redundant scan by an appropriate active channel, the wafer can be shifted (offset) in the y-direction and/or the x-direction relative to the number of strips until the strip has the appropriate effect. The beam's channel is positioned to write the missing strip position. This is preferably achieved by mechanical offset of the wafer on the stage. In order to better handle all kinds of error locations (eg, failure of the first and last channels), an offset to the first and second scans may be required.

Multiple scans

In the "multiple scan" embodiment, a second scan can be used to enhance the first scan for the effect beamlet and the defect beamlet, while still achieving a redundant scan. In multiple scans, the first scan of the wafer is written to a portion of the field strip and the second scan is the remainder of the write strip, resulting in all strips written to each field of the wafer. This principle can also be extended to three or four scans, etc., although more than one scan increases the total time used to expose the wafer and reduces wafer throughput. Therefore, a secondary scan or a two scan mode is preferred.

Combining the second scan with the redundant scan is possible because the beamlet failure rate is typically low. Beam measurements can be performed prior to the first scan to detect failed and sub-sized beamlets. Using this information, the first and second scans can be calculated, causing them to specify each pixel of the wafer scanned by the active beamlet. As in redundant scanning, preferably, when a failed or out-of-spec beam is detected, it cuts off the entire channel including the beamlet and uses another active channel (with all beamlets that meet specifications) To write the strip that it will be written by the failed channel.

A variety of algorithms can be used to calculate the channels to be used for the first and second scans and the wafer offsets required for each scan, causing all strips to be written by the active channel. For the second scan, the algorithm looks for a 50/50 split channel between the individual scans without any channels. A "brute force" approach can be used to test various channel assignments and wafer offsets to find a suitable combination, or a more complex matching algorithm can be used.

Therefore, the total exposure current for the wafer is distributed between two (or more) scans. In multiple scans, a second scan (or a third scan or a fourth scan, etc.) can be used to scan the strips assigned to the failed channel in the first scan, as in a redundant scan. . Multiple scans can also be used when there are no small bundles that are ineffective or out of alignment. The advantage of dividing the exposure current into two or more scans is that the instantaneous heating of the wafer becomes less of a problem. Because the total beam current is reduced for each scan, the heating of the wafer for each scan is also reduced. Although the total heat load remains substantially the same, the total heat load is dispersed over multiple scans, resulting in less local or transient thermal loading.

The use of multiple scans also reduces the required capacity in the data path. When a secondary scan is used for each wafer, the data transfer capacity of the data path is theoretically halved because each scan requires only half of the amount of small beam control data. This reduction in demand capacity is due to the large data transfer capacity required for the data path and the associated high cost. For the embodiment described above, each of the pattern bundles containing one channel has 49 beamlets, and each channel is expected to have a transmission capacity of about 4 Gbit/sec. Machines with 13,000 pattern bundles (each bundle contains 49 small bundles) will require 13,000 channels each with a capacity of 4 Gbit/sec. Therefore, the required capacity for the data path is significantly reduced.

Write strategy

The current industry standard is 300mm wafers. The wafer is divided into fixed-size fields with a maximum dimension of 26 mm x 33 mm. Each field can be processed to produce multiple ICs (ie, the layout for multiple wafers can be written into a single field) and the IC does not cross the field boundaries. For a maximum size of 26mm x 33mm, there are 63 fields available on a single standard wafer. Smaller fields are possible and will result in more fields per wafer. Figure 5 shows the wafer divided into fields and the direction of the write field. The field is a rectangular area on the wafer, typically having a maximum size of 26 mm x 33 mm. The GDS-II file is a feature that describes the field. It is also possible to write a partial (incomplete) field, for example by writing the full field as a partial field and across the wafer boundary.

In a preferred embodiment of the lithography machine, the machine produces 13,000 beamlets and each beamlet is split into 49 beamlets, resulting in 637,000 beamlets (i.e., 13000 x 49). The beamlet extinguisher array contains 13,000 photodiodes and 637,000 holes in a 26x26 mm area. Each photodiode in the beamlet blanker array receives a multiplex control signal for the control of 49 (7 x 7) extinguisher holes/beamlets. The 13,000 beamlets at a distance of 26 mm caused a strip of 2 μm width in the y direction (perpendicular to the mechanical scan) and as long as the field in the x direction. The 49 small bundles of each beamlet are written into a single strip.

The wafer is preferably written (exposure) by the lithography machine in the x direction of the reverse and forward directions. The writing direction in the y direction (by the deflector) is usually in one direction.

When the size (height) of the field is chosen to be smaller than the size of an electron-optical (EO) crack (ie, the size of a complete array of small beams as projected onto the wafer) (eg, a maximum size of less than 26 mm) ), multiple fields can be placed on the wafer, but not all of the electron beamlets will be used to be written on the wafer. The EO crack will have to scan the wafer multiple times and the overall throughput will be reduced.

When the machine is writing the pattern to the field, at some point, the beamletter array enters the next field and begins to write the pattern, so the machine should be able to write to both fields simultaneously. If the field is small enough, the machine should be able to write to three fields simultaneously.

A simplified version of the beam blanker array is shown in Figures 3 and 4, where there are only 16 photodiodes, each receiving a multiplex control signal for 9 (3 x 3) extinguisher holes/beamlets. . A extinguisher aperture with an associated extinguisher electrode can block or pass a small beam (or electron beam). The small beam passing through the extinguisher hole will be written to the resist on the wafer surface.

In Figure 3, the configuration of the extinguisher holes is shown for the parallel projection write strategy; in Figure 4, this is for the vertical write strategy. In Figure 4, the beam blanks for the beamlets are distributed over the entire strip width, i.e., each beamlet and adjacent beamlets are equidistantly positioned in a direction perpendicular to the write (scan) direction. This is possible, but for a small number of holes, the efficiency of this configuration will be extremely low in terms of the ratio between beam and beam current. One measure of efficiency is the fill factor, which is the ratio of the total area of the extinguisher holes to the area of the group of holes for a pattern bundle. The fill factor is useful for evaluating the efficiency of a particular grid geometry with respect to current input (beam current) and current output (total beam current). When the area of the small beam group is small, the fill factor will increase to a better value.

A write strategy for a small number of holes is a "parallel projection" write strategy (see: Figure 3), where (in its simplest form) individual beamlets are interleaved and the entire strip width is written (as in Figure 8B) Shown). A write strategy of this type is described in U.S. Patent Application Serial No. 61/058,596, the disclosure of which is incorporated herein by reference.

Scanning line

For all beamlets in parallel, the beam deflector array 119 will produce a triangular deflection signal. The deflection signal includes a scanning phase and a kickback phase, as shown in the schematic diagram of FIG. During the scanning phase, the deflection signal slowly shifts the beamlet (when turned on) in the y direction and the beamlet extinguisher array turns the beamlet on and off according to the beamlet control signal. After the scanning phase, the kickback phase begins. During the flyback phase, the beamlet is cut and the deflection signal quickly moves the beamlet to the position where the next scanning phase will begin.

The scan line is the beamlet path on the wafer surface during the scan phase. Without special measures, the scan line will not actually be written onto the wafer in the y-direction, but will be slightly skewed to also have a small x-direction component because of the continuous table movement in the x-direction. This error can be corrected by adding a small x-direction component to the deflection field to match the station movement. This correction can be processed in the EO column so that the data path does not need to correct this error. This component in the x direction is small because the table movement is slower than the y-direction deflection scan speed (a typical x:y relative speed ratio can be 1:1000). However, the effect of this x-direction component is greatly improved in systems with pattern bundles. First, the deflection speed can be reduced in proportion to the number of beamlets per bundle. Second, due to the tilt of the beamlet array (as shown in the examples of Figures 3, 4, and 9), the skew of the scan lines on the wafer will cause changes to the scan lines made by the different beamlets. The distance between them. A sufficiently large deflection may cause the scan lines to overlap or change the position relative to each other.

The scan line (see: the right side of Figure 6) is divided into three segments: the beginning of the scan segment, the pattern segment, and the end overscan segment. The beamlet is deflected in the y direction. The beamlet is deflected in a distance that is typically wider than its strip should be written. Overscan provides space for shifting and scaling the position at which the beamlet is written. Overscan is a single excess. If the strip width is 2 pm and the overscan is 0.5 pm (or 25%), this results in a scan line length of 3 pm. The overscan segment of the scan line bit frame holds the bit that it is not used to write the pattern (pattern segment bit). The overscan bit is always off, but is transmitted on the fiber. The pattern segment of the scan line bit box holds the bit that describes the rasterized pattern. The bits in this segment are actively turned "on" and "off" for writing features.

In (left side of) in Figure 6, the scan line is depicted for the case where only one small beam is written to the strip. The beamlet path during the deflection period is A-B-C. AB is the scan line movement during the scan phase, and BC is the flyback during the beamlet cut. Strip boundaries are labeled D and E. On the right side of Figure 6, the overscan and pattern segments are identified. The entire set of bits used to switch the beamlet control signal on the scan line is referred to as a scan line bit box.

The beamlets are controlled by the lithography system throughout the scan line. In the overscan segment, the beamlet will be cut. In the pattern segment, the beamlets are switched as needed to be written in the field of the wafer field. The bits in the scan line bit box for the overscan segment and the pattern segment represent data to be transferred to the beamlet blanker array. The bits/pixels in the overscan segment appear to be useless and consume the bandwidth of the data path. However, the bits/pixels in the overscan segment can provide space for corrections (such as pattern shifting and pattern scaling), provide space for stitching algorithms, and when the write strategy is used for all small bundles The entire strip width (parallel projection) is written to provide a space for the difference in the position of the beamlets at the extinguisher holes y.

Assuming that for a fixed bit rate of a beamlet control signal that controls the beamlet and a certain pixel size, the scan line can be mapped to a fixed length bit box, ie, a scan line bit box.

In Figure 7, an example of pattern offset and pattern scaling is presented. Scan line A is a vertical scan line that is not offset or scaled, wherein the beamlets written to the scan line are properly aligned and properly deflected to properly expose the desired features on the wafer. Scan line B is not optimally aligned with the strip, for example due to misalignment of the beamlets. This can be corrected by adjusting the timing of the beamlet switching by shifting the data in the beamlet control signal by one full pixel. This can be achieved by shifting the control bits within the scan line bit box.

The scan line C is not being determined to match within the strip boundaries D and E, for example, due to the deflection of the beamlets whose local is weaker than the normal. Thus, the pattern segment consumes more bits of the control signal, while the overscan segment uses fewer bits. The pattern written to the strip requires multiple bits for the stripe width. From the point of view of the bit box, shifting and scaling can only be performed with full pixel resolution. However, the rasterization method is capable of processing sub-pixel resolution corrections (eg, 0-1 pixels). Combining the two will allow for shifting, such as a shift of 2.7 pixels.

Beamlet writing strategy

In the above embodiment, each sub-beam is divided into 49 small bundles and the channel combines 49 small bundles for writing the strip. There are multiple different write strategies for writing stripes. The beamlet writing strategy defines how the beamlets are arranged for writing stripes. The solution can be a combination of stacking, interleaving or overlapping. The beamlet is deflected in two phases: scanning and returning. During the scanning phase, the beamlet is deflected (as it is turned on) along its scan line on the wafer. The pattern segments of the scan line bit box will be filled with the bit pattern to expose the desired wafer features.

In Figure 8, several examples show possible interleaving schemes that use four beamlets for writing strips. These instances do not immediately show how the small bundle is written, but rather which bundle is the portion of the strip that has been written when the write has completed.

Example A shows stacking small bundles. Each beamlet writes its own substrip. For this configuration, each beamlet is only written to a small number of bits before it is retracted. The frequency of the deflection signal is high and its amplitude is small. This writing strategy is applied in the case where clusters of small bundles are arranged such that the group width (the number of _beamlets N _× projection pitch P _proj ) is equal to the strip width (vertical projection).

Vertical projection is a series of write strategies. For the basic form of vertical projection, all small bundles are written into small sub-strips. The sub-strip width is a small portion of the strip width. The size of the extinguisher hole mesh is typically related to the strip width.

In Example B, the beamlets were interleaved over the entire strip width. The frequency of the deflection signal is low and its amplitude is large. The write strategy for matching interleaved scan lines is a parallel projection write strategy. Especially for a relatively small number of small bundles in a group, this strategy allows for smaller group sizes and improved fill ratios. Because of the small number of small bundles, the group size on the wafer is significantly smaller than the strip due to a reasonable fill factor. For this write strategy (parallel projection), it can be computed as a series of pixel sizes for a particular number of beamlets and a small beam spacing in a group. Therefore, the pixel size is not an arbitrary value. Additional bits can be added in the scan line bin to compensate for the worst case offset between the beam blanker hole and the center of the strip.

Parallel projection is a series of write strategies. For parallel projection, all small bundles are interleaved to the entire strip width. The Extinguisher hole grid has no strip width.

Example C is a combination of interleaving and stacking. For Example D, the continuous interleaved layers overlap like brick walls. This configuration will provide a better average between the beamlets than in Example C. At the strip boundary, there is a small bundle that will be written across the strip boundary.

Figure 8 shows an example of how the scan line fills the strip. The write strategy is to determine how the scan line will be written using the hole pattern for the beamlet on the beamletter array. One advantage of the "parallel projection" write strategy is its efficiency. An electron beam is used to make the beamlets. The efficiency depends on the ratio of the total area of the holes (small beam output current) to the area of the hole group (beam input current). For a relatively small number of holes (49), the area of the bundle (small bundle group) must be small for acceptable efficiency. For "parallel projection", the bundle (group) size is less than the strip width.

Pixel size is an important system parameter. The correlation between the grid of the extinguisher (hole) and the pixel size is explained below.

Figure 9 shows a simplified beamlet blanker array. For each beamlet, there is one corresponding hole in the beamlet extinguisher array and the extinguisher electrode in each hole. The extinguisher includes an electronic circuit that turns off or turns on the beamlet by energizing or de-energizing the extinguisher electrode. An array with only four holes is shown as a simple example, and the pattern bundle is composed of four small bundles.

According to the grid, the five-column scan line pattern is drawn similar to the pattern of Figure 8. The five columns are plotted for specific K values in the range of 1 to 5. K is a factor about the distance between the scan lines (for example, caused by the movement of the table between scans). A different K factor can be achieved by adjusting the relative speed of the table movement in the x direction and the deflection speed in the y direction (scan phase and flyback phase).

In the column for K=1 in Fig. 9, the pattern is displayed when the distance of the group moving group width is displayed. The distance between the scan lines is equal to the distance between the extinguisher holes for this projection, ie the projection pitch (P _proj ). In fact, the throw pitch will be much larger than the pixel size and a constant (design parameters of the lithography machine). The other columns in Figure 9 show what happens to the scan line distance in the x direction when the station only moves the integer fraction of the group size. K is this score.

Some K values will cause the previous scan line to be overwritten. These K values should not be used. The K value to avoid this is defined by the equation GCD(N,K)=1, where GCD indicates the maximum common denominator and N is the number of holes in a beamlet extinguisher for one channel (ie: in each pattern bundle) The number of beamlets in the middle), and K is the score of the station movement to the group size. If the number of holes in the grid and the maximum common denominator of the K value are equal to 1, then the K value is acceptable. When a value of K = 5 is used, the distance between the scan lines will also decrease with the same factor. The pixel size (at least in the x direction) can be determined using "parallel projection" and selecting the appropriate K value. However, one limitation is that this results in only a fixed set of pixel sizes. The factor K links the deflection frequency to the table speed.

Figure 65 illustrates a write strategy with a factor K = 1 at the top and K = 3 at the bottom. Figure 66 illustrates the possible K values for a pattern bundle with 4 small bundles.

An example of a grid of 49 holes (eg, a 7x7 array) is provided in the table of Figure 10, which describes the pixel size (in nanometers) for the number of significant K values in the x direction, assuming a beam spacing of 61 nm (25% fill ratio will be given given a typical hole size). For these parameters, the throw pitch P _proj will be 8.6 nm. The mesh width for this geometry is W _proj = 414 nm. Therefore, the bit box is capable of controlling the write strategy shift of +/- 207 nm.

Figure 11 is a legend of an array of nine small bundles showing some definitions of terms used including: beam spacing P _b , projection pitch P _proj , grid width W _proj and tilt angle α _array . Figure 63 is another example showing an array of four beamlets.

Figure 57 shows a table of pixel size and grid width, depending on the number of beamlets (N _{pat_beams} ), array tilt angle (α _array ), projection pitch (P _proj ), and K factor for each pattern bundle. In order to reduce the amount of control data that it needs to be generated and transmitted through the data path and increase throughput, large pixel sizes are desirable. However, the pixel size is limited by the desired CD and resist properties. In the table, it is assumed that the optimal pixel size (L _{pix_X} ) in the x direction is 3.5 nm, and the fourth line from the left side shows its calculated value based on the projection pitch and the K of the optimal pixel size. Given the number of beamlets per pattern bundle, the closest acceptable K value is shown in the fifth row from the left. The sixth and seventh rows show the number of beamlets, the array tilt angle, the projected pitch, and the pixel size in nanometers and the grid width that would be caused by the K factor for each given pattern bundle.

A higher K indicates a faster deflection scan speed (relative to the table movement) and results in smaller pixels in the x direction. At a fixed data rate, the pixels will become larger in the y direction, causing the pixel shape to change from approximately square to rectangular.

Small bundle write strategy correction

The beamlet is oriented to a non-overlapping scan line for an angle to the EO crack. The tilt of the EO crack associated with the deflection direction causes a positional difference in the y direction, as shown in FIG. This location gap can be corrected. For each beamlet, the value used for the shift is a multiple of the projected pitch. In Figure 11, the difference between the top hole and the center hole is equal to W _proj /2. This value will result in a full pixel shift component and a subpixel shift component. The full pixel shift component is preferably always compensated, but the subpixel component can only be compensated for using instant rasterization.

Multiplex, framing, coding, and synchronization

To reduce system cost, an optical fiber can be used to control multiple (eg, 7x7=49) extinguisher holes. In one embodiment, the continuous control bits transmitted through the individual fibers are continuous extinguisher holes for controlling the beam blanker array (i.e., for controlling a series of beamlets). In one embodiment, each fiber contains channel transfer control information for 49 sub-channels for control of 49 beamlets on a single pattern bundle. This control information can be buffered before being applied to the extinguisher electrodes for each beamlet, or control information can be applied directly without buffering. For this purpose, a buffer can be provided on the beamlet blanker array. A schematic diagram of a data path with interleaved/multiplexed subchannels is shown in FIG. 55, and a schematic diagram of a demultiplexing scheme is shown in FIG. 56, which uses a column selector and a row selector to decode a multiplexed subchannel. To separate the individual control bits for each beamlet.

In order to synchronize and indicate which bit in the control information stream belongs to which beamlet, it is preferred to use some sort of framing, as shown in the example of FIG. In this example, the box start indicator bit (in this example, 7 bits) is used in the loop pattern to which the framer on the beamletter will be synchronized.

When the DC balance sequence requires an AC coupled optical transmitter for the photodiode side and automatic threshold adjustment, it is preferred to use some encoding. An example is for example 8b/10b encoding. However, this will result in a higher bit rate, which will increase the bit rate by 25% with 8/10b encoding.

The frame and coding of the signal can also be combined, for example: using a specific code block to indicate the beginning of the frame.

Each channel will carry data for several individual beamlets (eg, 49 beamlets). The information will be transmitted from the data path to the extinguisher in tandem. Depending on the multiplex and on-time implementation of the extinguisher, it may be necessary to compensate for the "extinguishing device timing offset", which is caused by the extinguisher receiving control information for different beamlets at different times due to serial data transmission. . There are several possible small beam synchronization options. Synchronous implementation is primarily dependent on the likelihood of implementation on the extinguisher.

Beamlet synchronization can be performed in different ways, for example: synchronizing all beamlets to one sync signal, synchronizing all beamlets in a row, synchronizing all beamlets in a column, or not synchronizing beamlets. For an embodiment with 49 beamlets per pattern bundle arranged in a 7x7 array, in order to synchronize all beamlets to one synchronization signal, control data for 49 beamlets can be buffered and simultaneously applied to small Each of the 49 extinguisher electrodes that are switched by the beam. In order to synchronize all of the beamlets in a row, the control data for the seven channels in each row can be buffered and applied simultaneously to the seven extinguisher electrodes for the beamlet of the row. In order to synchronize all of the beamlets in a column, the control data for the seven channels in each column can be buffered and applied simultaneously to the seven extinguisher electrodes for the column beamlets. When no synchronization is performed, all of the 49 beamlet control data can be applied directly to the extinguisher electrode as the data is received by the extinguisher.

Individual beamlet timing will be different for row sync, column sync, or no sync. When there is a timing difference between the beamlets, the difference can be compensated by shifting the pixel in the y direction. This shift will always be in the sub-pixel range. Since the shift is dependent on the beamlet combination, the compensation is only possible when rasterization is performed on the fly.

Stitching

Since the field is written by multiple beams, it is preferred to use stitching between the fields of the field written by the different beams. The stitching error (the shift of the pattern written by a bundle relative to the pattern written by the adjacent bundle) causes two types of lithographic errors: critical dimension (CD) error (line at the border of the seam) Too thick or too thin) and overlap error. For overlay errors, typically 5 nm is tolerated. The stitching method is a method of exempting the CD error, and the CD error is caused by the stitching error. Different stitching strategies can be used. Such strategies are for example: seamless splicing, irregular edges, soft edges and smart boundaries.

For a seamless splicing strategy, it is expected that no specific means are required other than the good alignment of the bundle. A bunch ends at the beginning of the other bunch. If misalignment occurs, the line will appear where the dose is too low or too high. The beam spot will average this effect to some extent. However, seamless splicing is not preferred.

The irregular edge stitching strategy is described, for example, in U.S. Patent Publication No. 2008/0073588, which is incorporated herein in its entirety by reference.

For soft edge strategies, the beam write range will overlap. Figure 58B shows a legend illustrating the soft edge strategy. The pattern is faded out at the two ends of the two-beam write (before dithering). This strategy has the effect that its error is spread over a region, as shown by the 1 μm soft edge in the figure. A side effect of this strategy is that some pixels may be doubled (ie, with a 200% dose). Because of the large beam size, the dose will spread across several pixels.

A smart boundary policy defines overlapping write ranges, but only writes a bundle to this area. Figure 58A shows a legend illustrating a smart boundary strategy. In the illustrated example, a 100 nm overlap write range is used, for example: 25 pixels with 4 nm pixels. The boundary between the two strips or the field or the critical portion of the pattern data feature near the boundary will be identified and placed in one strip or the other. This causes the actual write boundary between the two strips to be moved to avoid crossing the critical portion of the feature so that the critical feature will always be written by a single bundle.

The soft edge stitching strategy is to smooth out the two borders to the area of the next strip. For soft edge stitching strategies, a maximum overscan length of 0.5 μm can be used. If a 5 nm stitching error occurs, this results in a 100% dose error in the 5 nm x line width region. If the stitching overlap is 1 μm, the 100% dose error is reduced to 100% x 5 nm / 1 μm = 0.5%. The total dose error budget can be set to 3%, and the 0.5% dose error is a reasonable budget for the stitching error from this dose error budget.

The stitching method (soft edge or smart border) and overscan length can be chosen for each scan. Lowering the overscan length will result in higher machine throughput. The user preferably has the option of selecting a soft edge or a smart border stitching strategy and a soft edge size.

Reduced capacity of the required data path

The use of multiple scans with two scans causes the lithography machine to write at half its maximum capacity. This reduction in write capacity allows the amount of hardware required for the data path to be significantly reduced.

A channel is a unit of work in the data path. One channel is capable of writing a strip during the scan. The components of the data path involved in the instant processing are: fast memory, processing unit, laser, fiber optic, and extinguisher. Since only 50% of the channels are now used for one scan, the number of processing units may be reduced by approximately the same factor.

At the same time, the processing unit that streams fewer channels has the following advantages: fewer cells required for each channel, hard limits on the fast memory bandwidth required for each channel node, and the required The size of the fast memory storage may be reduced. Reducing the number of processing units also has the disadvantage that there must be a way to connect the processing unit to the laser for the appropriate channel, and new restrictions may invalidate the scan, especially if a large number of successor (cluster) channel errors occur.

In the following description, the concept of a node is used. One node has Y (optical) channels connected and has X processing units available. Figure 13 shows a model for such a node. Commercially available electrical to optical (E/O) converters typically have 12 channels (i.e., Y = 12). An E/O converter (eg, a laser diode) converts electrical control data from the processing unit into optical data that is transmitted through the fiber to the extinguisher of the lithography machine. The processing unit driven by the E/O converter (for example, a field programmable gate array (FPGA)) contains X channels. The X*Y intersection can be used to switch any of the processing units to any of the E/O converters. The X*Y intersection is a separate device or integrated into the processing unit. With the intersection, it is possible to route any of the processing unit outputs (X) to any of the data path outputs (Y).

In case some optical channels fail, the possibility of a shift between the first and second scans must first be determined, wherein all strip positions are covered by at least one suitably working channel. When the possible shift position is known, it is determined whether the available processing unit is a strip that is allocated between scans and covers 100%.

In Fig. 14, the channel position of each scan is shown in a conceptual diagram. The strip (blue) as shown in Figure 14 is written with the channel error of this particular combination and two individual shift values. It is important to distinguish between overlapping and non-overlapping channel locations. For strips that will be correctly written at overlapping channel locations, this location must be available for a scanned working channel. For non-overlapping channel locations, wafer shift between the first and second scans will result in two regions where only one particular scan can be used to write the strip. A failed channel in this area will interrupt the sequence of good channels. The leftmost channel error (see: the red arrow pointing to it in the figure) forces the strip to start on its right side. On the left side, the channel is not available. Typically, the shift is used such that the overlap region becomes error free (using two scans) and some of the channels in the overlap region can be used to reach the desired number of stripes to be written.

The probability of not being able to write to a location in a non-overlapping region is relatively high compared to the possibility of being unable to write to a location in the overlapping region. Thus, typically, the "good channel" sequence in non-overlapping regions is short. Therefore, using 12870 channels to cover 13,000 strips in two scans would be difficult because of the considerable sequence availability of good channels in non-overlapping regions. Using 13130 channels to cover 13,000 strips in two scans will be much easier, as success will not depend too much on non-overlapping areas. In fact, it is likely that the complete sequence of bands is found in the overlapping region.

New constraints are introduced when the number of processing units is reduced. In addition to finding the appropriate shift, a successful allocation of processing units to channels for the first and second scans must be found. In Fig. 15, an example of this is shown. For this example, assume that it manages 5 channels and 3 processing unit nodes. The white point indicates that the channel is cut, while the black dot indicates that it is used and the processing unit is the assigned channel. The red cross mark indicates the channel error. It is verifiable that there is no node violation that limits the maximum of three processing units acting on a node for a particular scan.

Figure 16 shows the results of using fewer processing units compared to channels for non-overlapping regions. This figure shows that the maximum sequence of good channels is obtained with a limit of three processing units for every five channels of a node. The maximum length is equal to twice the number of processing units per node. For other shift values (the shift of Figure 16 is ideal), the useful sequence in the non-overlapping region will be substantially smaller (see what happens when the shift is incremented by one). Therefore, the channels in the non-overlapping regions are even less useful than previously (without considering reducing the amount of processing units).

In addition to the poor utilization of channels in non-overlapping regions, another weakness based on the same constraints occurs in overlapping regions. In the overlap region, reducing the number of processing units per node is a change to sensitivity to an error sequence (error cluster). For a configuration of 7 processing units for each of the 12 channel nodes, a double of the number of processing units plus one of the clusters will result in a failed allocation. If the cluster is mapped on a single node, the allocation will fail for the cluster with the processing unit size plus one. Whenever the cluster is controlled as the actual bottleneck, there is still the possibility of scaling the node size (for example: 24 channels and 14 processing units). This will reduce the sensitivity to large clusters. Importantly, the system is robust to channel errors up to a certain level. Furthermore, if a reduction processing unit occurs, the robustness to the channel error is maintained at a reasonable level.

The key parameters for the redundant scanning concept are the number of stripes, the number of channels, the expected number of error channels, the expected size of the error cluster, the number of channels per node, and the number of processing units per node. After identifying the channel error, the system will find a possible shift combination that results in a "good" sequence of length equal to or greater than the number of strips required. A "good" sequence consists of a "good" channel position in a non-overlapping region or a position in an overlapping region where at least one of the channels is "good". This process will result in a shifted list with the start and size of the "good" area.

A successful wafer shift is a successful condition if a one-to-one relationship between the channel and the processing unit occurs (ie, there is no reduction in data path capacity). If the processing unit is less than the channel, a successful assignment is an additional requirement. The assignment is successful when all strip positions are written by one of the two scans using only "good" channels. According to the scan, the node cannot allocate more processing units than the available ones.

A possible allocation strategy is to first assign a channel that must be written to certain stripe locations. These locations are typically locations in non-overlapping regions and locations in overlapping regions of one scan, which correspond to error locations in other scans. If any node needs more processing units than is available, the allocation attempt will fail.

Starting from one side, the distribution is repeated by the position of the strip. The processing unit is allocated from the node from which it will leave the earliest. In case such a node is fully allocated, nodes from other scans should allocate processing units to write locations. If any node needs more processing units than is available, the allocation attempt will fail. Other strategies can be used that give better results and find the possibility of allocation if the previous rejection is made.

Typical reasons for failure of an allocation scheme are failure limits in non-overlapping regions, no spare processing units, and large error clusters. The particular shift value combined with the error channel at a particular location often results in a failed allocation. For two scans, the alternate processing unit is a processing unit that exceeds half the number of channels that the node should supply. For example, a configuration of 12 channels and 6 processing units per node does not have any spare processing units.

The large error cluster will eventually exhaust the number of processing units at a particular node. The impact of the cluster is heavily dependent on its location, as it is determined whether one or two nodes should allocate processing units to write error locations. For each of the 12 channel nodes, there are 7 processing units, one node can absorb up to 7 errors, and the two nodes can absorb up to 14 errors.

17 through 23 are graphs illustrating simulation experiment results for determining the effect of varying the data path capacity with respect to lithographic machine capacity. The graph is showing the number of successes from 50 experiments. Success means that a successful shift and assignment has been found. Since many simulations are about changing a single parameter, unless otherwise specified, define it as a preset parameter set: the number of stripes = 13000; the number of channels = 13130; the number of processing units per node = 7; And, the number of channels per node = 12.

A node with 12 processing units for 12 channels is called a 12/7 configuration. In Figure 17, the effect of each node being a different number of processing units is shown, assuming no large error clusters (only small natural clustering cases). The 12/6 configuration is considered to be the lower limit of the reduction, since the configuration of 5 processing units per 12 channels will always fail. The 12/12 configuration is actually a configuration that does not reduce any processing nodes; its success depends only on finding a successful shift (no allocation limit). The simulation results show that the robustness for the 12/6 and 12/7 configurations will be slightly reduced compared to the 12/12 configuration.

Figure 18 is an effect for error clustering of the same configuration as in Figure 17. The 12/6 configuration is particularly sensitive to error clusters of size 5, and the error cluster of size 5 is due to the lack of spare processing units in the nodes. An error at a critical location will cause an execution failure. The 12/7 and 12/12 configurations do not show the special sensitivity for clusters of size 5.

The effect of changing the number of channels is shown in Figure 19. If the number of processing units is reduced, non-overlapping areas are almost useless. This explanation is a poor result for using 13,000 channels. A configuration with more channels will give more opportunities for shifts with a "good" sequence, mainly due to the wider overlap area. Simulation experiments show that 13130 channels with 200 errors will result in an average of 26 successful shifts, while 13260 channels will result in an average of 41 successful shifts for the same number of errors. Using an average of 14 successful shifts using 13,000 channels. For a typical 12/7 configuration, increasing the number of channels increases the robustness.

Figure 20 shows the results when the previous simulation was expanded with an effect of an error cluster of 5. No significant effect of binding to change the number of channels was observed.

As mentioned earlier, the robustness decreases as the number of processing units is reduced from 12 to 7, and increasing the number of channels will improve robustness. Figure 21 presents the results when the use of more channels is attempted to compensate for the loss of robustness due to the processing unit. As can be seen, the loss of robustness when changing the configuration from 12/12 to 12/7 can be compensated by increasing the number of channels by only about 1% (eg, increasing the number of channels from 13130 to 13280).

Note that the clusters used in the simulation are "single clusters" of a particular size that appear to be the worst condition. Other clustering strategies tend to provide more positive results. Figure 22 shows a comparison of the three strategies: only injecting a single cluster; injecting as many similar clusters as possible at a fixed distance (65 from the starting position to the starting position); and, injecting as many as possible at random locations A similar cluster (however, the minimum distance between 20 good channels is maintained). Note that the fixed distance between error clusters produces a lot of correlation and will result in a large number of successful shifts.

When reducing the number of processing units, clusters larger than size 5 will have a severe impact on robustness. This can be seen in Figure 23, where the difference in robustness between 12/07 (12/07@5) with cluster size 5 and 12/07 (12/07@8) with cluster size 8 is Obvious.

If error clusters greater than 5 occur more frequently, an alternative approach can be used in conjunction with reducing the number of processing units to reduce cluster sensitivity. Increasing the node size and using comparable ratios (such as 24/14 configuration) is one such alternative. The effect of this can be seen in Figure 23, which shows the greater robustness of the 24/14@8 configuration compared to the 12/07@8 configuration.

Other alternatives are to randomly align channels across nodes, or to systematically distribute channels across nodes. These will result in an error cluster that corresponds to multiple different nodes rather than being concentrated in one or two nodes. In this configuration, all mirror positions where the cluster error is written will not be 1 or 2 nodes but the task of many of them. However, randomly arranging or spreading the channels may have other negative side effects because the concept of neighbors (and potentially shared information) disappears.

Allocation strategy optimization: In addition to checking allocation constraints, an important task of assigning functionality may be to minimize the number of stitches between scans.

The conclusions that can be drawn from the above simulations are as follows. Reducing the number of processing units per node can significantly reduce the amount of hardware. Reducing the number of processing units per node will slightly reduce the robustness. For two scans, 50% (eg 12/6 configuration) is the lower limit for reducing the number of processing units per node. Nearly 50% of the configuration is particularly sensitive to small cluster errors (size = 5). The 12/6 configuration is therefore not as good as the 12/7 configuration, which is not shown in the 12/7 configuration. The 12/7 configuration seems to be a reasonable lower limit for the number of processing units per 12 channels. For good robustness, the number of channels is preferably greater than the number of strips (+1%). Increasing the number of channels significantly improves robustness. Because the loss of robustness in reducing the number of processing units per node can be easily compensated by using an additional 1% channel. A large error cluster (>5) will dramatically reduce the robustness.

Data path requirements

The flowchart in Figure 24 is an overview of the processing involved in the lithography system and its dependencies. Understanding the dependence allows analysis of performance (in terms of duration) and reveals opportunities for parallel execution to increase yield. The important main idea is that for a scanned pattern data it can be processed and/or loaded into RAM while the previous scan is being performed.

Different dependencies and their different probabilities or limitations may occur in different architectures. For example, the dependency between E1 (wafer measurement and positioning) and C1 (inline processing and/or loading data for initial scanning to RAM). For architecture option A (offline processing), this dependency does not exist. For option C, this dependency may exist, whereas for instant rasterization, this dependency will exist (immediate combination of beamlets and scan lines).

Typical performance requirements for processing: downloading a new pattern from the server to the local storage of the streamer node <60 minutes; the number of patterns to be stored in the local storage of the streamer node >=10; the machine is The time taken to go offline due to loading a new image is <60 seconds; if each wafer is rasterized once, the maximum time between correcting the parameter update to being ready to write is 36 seconds (6 minutes) 10%); and, during the scanning exposure period is <3 minutes.

Timing and synchronization

The clock and sync signals can be distributed through optical fibers to other subsystems (such as deflectors and wafer tables). This has the advantage of galvanic isolation between subsystems and insensitivity to electromagnetic effects. Clock changes can be used to change the dose. However, since the dose variation can be compensated by changing the pixel size, it is preferable to avoid clock changes to simplify the implementation of the actual portion of the data path responsible for transferring data to the extinguisher and to resynchronize after the clock frequency change The time required.

The advantage of using a fixed clock rate is that the clock does not need to be distributed between different components of the data path. With a standard phase-locked loop (PLL) (on the inside of the FPGA), changes in the local clock frequency can be compensated. When large changes are required (such as ±10%), special preparations are needed to enable the data path subsystem to synchronize.

The data path preferably operates as a clock master for the entire lithography system and provides timing and synchronization signals to other subsystems such as an electron-optical column (deflector) and a wafer positioning system.

Correction

In the embodiment of the charged particle lithography machine described above, there is no facility built into the lithography machine to adjust the individual electron beamlets to correct for errors in beamlet position, size, current, or other beam characteristics. The lithography machine omits the modified lens or circuit to make individual corrections for the beamlets to avoid the additional complexity and cost involved in incorporating the additional components into the electron beam for actual beam correction, and avoids the inclusion of such additional The component needs to be increased in column size.

Therefore, adjustments to correct for changes in beam position, size, current, etc. are made by making correction adjustments to the control signals provided by the data path. For various reasons, several types of corrections are made. These amendments include amendments to compensate:

● Changes in the beam position. Due to variations in the manufacture of the column, such as: true positioning and dimensional changes of the holes in the array of apertures or beamlet extinguishers, or the strength of the electric field generated by the collecting lens or projection lens or deflection electrode Differences, small bundles may be out of alignment. Such misalignment can be corrected with "pattern shift".

● Mechanical position error. These may cause the entire wafer field to shift in the x and / or y directions. This type of field shift can also be corrected with "pattern shift".

● Delay errors in the data path (eg caused by differences in fiber lengths in the data path). This error can be corrected by shifting in the y direction.

● Extinguisher timing offset. Due to the multiplexed control of the beamlet control signal, multiple beamlets are controlled through one channel and the beamlet control signals are in-line reception, ie, the control signals for different beamlets are by the beamlet extinguisher array at different times Received. Depending on the design of the extinguisher, the small beam will be switched on and off (eg, the beamlets can be switched in units of columns or rows) or individual beamlets will be subject to different offsets. Depending on the strategy for implementing control bits (beamlets are switched), this may cause a particular beamlet to be switched at a later time compared to another beamlet. The effect of this error is in the sub-pixel range. The result is the offset of each beamlet.

● Changes in the hole position of the small beam extinguisher array. Each beamlet passes through the aperture in the beamlet blanker array and is switched by the extinguisher electrode at the aperture. Variations in the manufacture of the beamlet blanker array may result in mechanical offsets in both the x and y directions of the holes and thus the position of the corresponding beamlets, as compared to the reference position. The effect of this error is typically a number of pixels, and the result is the offset of each beamlet. The full pixel (integer) portion of this error will typically be compensated for during execution. The remaining sub-pixel (fractional) portions can be compensated for by instant rasterization.

‧ Changes in deflection strength. These may be due to spatial differences in the electrical deflection field strength of the beamlet deflector, which must be corrected for "patterning" and "dose correction". It is also possible to have a small beam offset component that differs in deflection, which can be corrected by "pattern shift".

‧Changes during control signal pulses. Because of the different timing behaviors used to turn the beamlet extinguisher array electrodes on and off, the effective dose rate will vary from beam to beam. This effect is significant when the control signal is not multiplexed (eg, 10%). For the multiplexed control signal transmission of 49 small beams in one channel, the significance is reduced because the transition effect is the same, but the minimum pulse width is 49 times larger than the unmultiplexed transmission case. (Assume 10%/49=0.2%). Moreover, this error is dependent on the dose rate. The error will be written to be small for the 100% dose rate, while the error is written to the maximum at the 50% dose rate.

Overall pattern shift

When the pattern is written on the wafer, the beamlets of the write pattern are unlikely to be fully aligned. To correct for this misalignment and cause the beamlet to be able to write to the alignment strip, the pattern data is adjusted to compensate for the misalignment error. This adjustment can be made using software or hardware and can be done at different stages during the processing of the pattern data. For example, corrections can be made to graphics data in vector format, or in multi-level grayscale format, or in second-order B/W bit maps.

The offset may occur in the x direction (stage movement direction) or the y direction (small beam scan deflection direction) or both. The offset may occur with full pixel shifting and/or sub-pixel shifting. Full pixel shifting can be achieved by shifting several pixels after rasterization. Subpixel shifting can be achieved as part of the rasterization process.

The overall pattern shift (ie, the shift of all beamlets in one channel) can be used for strip position correction (in the x and y directions) and field position correction (in the x and y directions). An example of x and y pattern shifting for strip position correction is shown in FIG. On the left side of the figure, the strip is displayed with the desired pattern with its overlap at the intended position. On the right side of the figure, the strip is a pattern that has overlaps that will be written if no corrections have been made. As can be seen, the overall pattern shift is required such that all of the beamlets of the channel are written at positions shifted up and to the left.

Typically, the beam shift is performed frequently (once per wafer or field) after calibration. It can be assumed that the beamlets are fully aligned with respect to other beamlets in the same channel such that all beamlets in the channel get the same pattern offset.

A typical requirement for pattern shifting is the individual X and Y shift settings for each channel of the overall shift, and the parameters are updated once for each field. Typical maximum shift range is from +200 nm to -200 nm with a 0.1 nm shift accuracy. This correction is for each channel of the overall shift, it is expected that all beamlets in the pattern bundle use the same offset value. For the overall pattern shift, the channel pattern is shifted overall regardless of the beam interleaving strategy.

Extinguisher timing offset correction

The beamlet control signal for multiple subchannels is preferably multiplexed over a single channel. Depending on the design of the extinguisher, this will cause individual beamlets to switch to the next pixel at different times. The extinguisher timing offset correction needs to be corrected for the subchannel at Y, typically with a maximum shift range of less than one pixel and a shift accuracy of 0.1 nm. The shift parameter is static, since the extinguisher timing offset is dependent on the extinguisher design.

Extinguisher hole offset correction

Because of the extinction geometry, the different holes have different offsets from a certain reference point. Use the offset of the hole X to create an interpolated pattern (see: Figure 9). The predictable timing delay will be considered immediately and is not considered part of this correction. The offset of Y relative to the reference (eg, the middle strip) is compensated. The error is divided into full-pixel and sub-pixel components. Full pixel shifting should always be compensated, while only instant rasterization can handle sub-pixel components. The extinguisher hole offset correction needs to be corrected for the sub-pixel component in Y according to the sub-channel, typically with a maximum shift of +/- W _proj /2 or +/- 210 μm (ie: (N-1)*P _proj ) The bit range and the displacement accuracy of 0.1 nm. The correction parameters are static because the extinction hole offset is based on the extinction geometry.

Dose correction

Because of the manufacturing tolerances in lithography machines, the effective dose is varied in small bundles. A change in the deflection intensity of the beamlet scan can also result in a change in dose intensity. The dose rate can also be corrected using a dose factor: causing dose rate = dose rate map * dose factor. This formula is modified in mathematical terms, but the dose correction is preferably achieved by adjusting the pixel white value and/or threshold in the dithering process. For example, when the beamlet is calibrated with a 90% dose factor, its intensity is 100%/90% = 111.1%. Therefore, if 100 is the preset value, the white value for dithering will be 111.1; and if the preset value is 50, the dithering threshold will be 55.6.

The dose correction is performed in small bundles and the correction parameters are updated once per wafer. Typical requirements/values for dose correction are 50%-100% pattern dose mapping, 0.2% step size pattern dose accuracy, 80%-100% beam dose factor, and 0.2% step size beam dose Accuracy. The resulting dose rate should be rounded to the nearest value.

Graphic scaling

The beam is deflected in the y-direction during each scan and the pattern is written from one side of the strip to the other. The deflection distance is preferably two times the strip width and the overscan distance. If the deflection is not exactly the same, one beam is deflected stronger than the others and therefore the deflection distance will be different. Due to the voltage drop across the array, the difference in scan deflection strength occurs on the surface of the scan deflection array. These voltage drops cause a weaker deflection field at the far end of the array, and the deflection distance will be shorter for a small beam that experiences a weaker deflection field.

This is done using pattern scaling to compensate. An example of a pattern calibration is shown in FIG. In the left part of the figure, the strip is shown as having the desired pattern covered by the iconic representation of the graphical features between the dashed lines. On the right side of the figure, the strip is shown as having a pattern that will be overwritten if no scaling corrections have been made. As can be seen, pattern calibration correction is required to reduce the deflection of all beamlets of the channel to properly calibrate the feature write.

Calibration can be achieved by adjusting the bit rate of the data signal transmitted to the extinguisher, spreading the exposure pattern over a different number of pixels. Due to synchronization considerations, changing the bit rate is not preferred. To avoid this, scaling can be performed by spreading the pattern over a different number of bits/pixels. It is assumed that the beamlets of the same group have the same deflection strength. This is because it is deflected by the same deflector. So for all beamlets of a group, the pattern scaling factor is the same.

Pattern calibration requires correction for each channel, and the correction parameters are preferably updated once for each redundant scan recombination. The maximum range is typically 1 to 1.1 (eg 2 μm to 2.2 μm) with an accuracy of 0.1 nm / 1 μm = 1 / 10,000. It is assumed that the deflection strength is the same for all beamlets in the channel because the beamlets share the same deflection array and are approximately the same position in this deflector.

Figure 27 is a table summarizing various types of corrections and typical parameters and ranges. Note that when using the first scan and the second (or redundant) scan, the dose correction is preferably performed before the two scans.

Dynamic pattern shift

Dynamic pattern shifting can also be provided to compensate for wafer heating. This can use the X and Y offset tables for each channel, which have values that vary with time. A maximum slope of 0.1 nm per 1 ms (equal to -10 μm at X) and an offset table with 30,000 items per 300 mm (wafer size) can be used.

Pattern sizing correction

Because of the difference in beamlet deflection tensities across the surface of the scanning deflection array, the deflection distance of the beamlets will change. This can be compensated using the (above) pattern scaling or pattern sizing correction. The requirement for pattern size correction is summarized as the same as the pattern calibration.

Data path architecture

The data path receives layout data in a specified format and processes the data such that it can be written on the wafer using an electron beam. The data path also implements adjustments to the pattern data to compensate for errors in the lithography machine and to provide synchronization signals to other subsystems.

Figure 28 shows a functional block diagram of the data path showing the flow from the GDS-II pattern data file to the bit stream it transmits through the fiber. This figure also shows the corrections that occurred in the appropriate function block. Depending on the architectural options, corrections can be made at different points within the data path processing.

Input data format

The input to the data path subsystem will be the pre-processed format (usually from an industry standard file format such as GDS-II or MEBES) containing layout information that will be "written" onto the wafer. With this industry standard file format, pre-defined system compensation is applied by off-line processing. After offline processing, the data will be stored for the next phase of the data path. The data can be stored in a file format that facilitates subsequent processing, for example, each individual channel is a file.

Dose mapping data format

A dose map is typically a region that uses a vector format to define a single dose rate. The dose rate is the intensity of radiation per unit area. It is necessary to write the pattern with the appropriate dose rate, otherwise the written pattern will not appear correctly in the resist. For example, the range of dose rates may be 50-100% in 0.2% steps, and the spatial resolution of the dose mapping may be 10-15 nm. The regions are non-overlapping, so the lines describing the polygons of the regions do not intersect. These regions can be defined in a vector format using lines at angles of 0, 45 or 90 degrees. If an immediate transfer occurs, the offline process can decompose the complex polygon into a simpler one. For example, the polygon can be simplified so that the scan line only intersects the boundary at most twice. This simplifies the transfer in hardware.

Pretreatment

Pretreatment is typically performed once for each design. This step requires a lot of computing power. The following functionality is typically incorporated into the pre-processing: (a) reading out the GDS-II wafer design and taking the information needed for the particular steps in the wafer fabrication process. This typically results in a polygonal map of the features required in this step. (b) Apply resist heating correction to the dose mapping. This correction typically results in an adjustment to the feature location. (c) Apply proximity correction on the polygon. This correction will result in a dose mapping of more polygons with different dose rates attached. (d) The dose mapping for each field in the vector format will be output.

Channel division (sp1itting)

The channel is preferably used as a unit for further processing. To make this possible, the field dose mapping is divided into dose maps for each channel. The polygon is reduced to the stripe area written by one channel. The strip area is preferably extended beyond the boundaries of the strip to account for the stitching strategy and the coloring initiation artifact. If a "smart boundary" stitching strategy is used in which critical features are assigned to a single channel/strip, the critical feature polygons on the stripe boundary are assigned to a particular channel when the dose map is divided.

Generalizing (rendering)

A roll-to-roll is the first step in the rasterization process. Shape information and dose information are categorized in pixels. Figure 29 shows the layout pattern features that are superimposed on the strip to illustrate the transition process. Shape information and dose information are described in a vector format in the dose map and are typically field based. The pixel boundary value at X is fixed by the starting point of the machine (also assuming that the first column will be written by beamlet 0). This will determine the relationship between all pixel X coordinates (pixel X idx in Figure 29) and its corresponding beamlet (the beamlet idx in Figure 29) to which the scan line is written. The scan line is a column of pixels in the Y direction.

From the typical X position of the field on the wafer and the X offset determined from the routine metrology process, the first scan line (the first field pixel column) of the particular field can be determined. The pixels in this example are misaligned with the field origin. Thus, "sub pix offs X" defines the offset of the left pixel X boundary (as a reference for the vector format) from the origin of the field origin.

Pixel size, strip width, overscan, and pattern scaling at Y will cause it to be an integer number of pixels needed. An extra pixel may be added to allow sub-pixel shifting. The pattern scaling factor will be the same for all beamlets and therefore all pixels will be the same Y size.

The shift can always be divided into an integer part (full pixel shift) and a fractional part (sub-pixel shift). Full pixel shifting can be achieved by shifting the pixels in the bit box. Subpixel shifting cannot be achieved in this way, but can be done by a traversing/dithering process. The shift in the Y direction is global (ie, overall pattern shift in the Y direction) or dedicated to beamlets (eg, beam position or extinguisher timing offset correction). The transfer process should know which beamlet is written to the scan line and (subpixels) are shifted by the appropriate scan line pixels. The pixel is shifted before the transition, so it is aligned with the "strip vec ref Y" (see: enlarged display A in the figure) line, which is in the y direction for the vector format description of the feature and dose Baseline.

Since the relationship between the beamlet and the pixel X index is fixed only when scanning is started, only the sub-pixel shift can be handled by the immediate transition. Offline de-column will always assume that the sub-pixel is shifted to zero.

Channel dithering

Dithering is the second step in the rasterization process. By dithering, the specific dose rate is achieved by the switching sequence for the subchannels. Dithering is essentially the quantization of multi-order gray-scale pixels into second-order white/black pixels, and the quantization error in each pixel is propagated to adjacent pixels and locally forces a specific average dose rate. Figure 30 illustrates this process. The dithering technique is typically used to achieve grayscale or color variations when printing. Some well-known algorithms are error diffusion (2x2 matrix) and Floyd Steinberg (2x3 matrix).

The dithering is performed in one or two (spiral) directions. The dithering algorithm typically requires some pixels in preparation. Therefore, the strip width is a small margin that extends for better results.

Some improvements can be made for lithography purposes. One improvement is that the error propagation is preferably a pixel that does not propagate to a zero value. The error value should be propagated or discarded in the other direction. Propagating the quantization error to a pixel where a zero dose is needed is useless. This is also understood in view of the reasonable value for CD and spacing. This guarantee will follow multiple zero pixels if a transition from gray to zero occurs.

The dithering process converts grayscale pixels into black/white pixels. Since the dithering process must propagate the quantization error to its neighboring pixels, the sub-pixel shift of each scan line is also processed. Figure 30 illustrates this process. In order to propagate the quantization error in an accurate manner, the error propagation to the other scan line is not unimportant because the scan lines are not aligned. The quantization error may be propagated based on the amount of overlap between adjacent pixels such that pixels with larger overlap receive a larger portion of the propagation quantization error. An alternative and simpler strategy is to propagate only the error to its neighbors with the greatest overlap.

The dose used for the dithering process is preferably due to the dose rate from the transposition process, the dose factor for each beamlet, and the scaling factor for the channel. The dose factor is preferably set for each beamlet. Therefore, the dithering module should also know that the scan line pair is bundled ("Bundle idx" in Figure 30).

The dithering process will result in an on/off state for all pixels of the strip. Remove the selected margin pixels before proceeding further. If a soft edge occurs, there is no need for a margin pixel because there is already a smooth fade in and fade out at the strip boundary.

Depending on the architectural options, the correction is known or unknown during the dithering process. For offline dithering, subpixel shifting is not possible and the pixels will be aligned in the Y direction.

For the dithering process, the threshold is preferably half of the "white value" because the white value will deviate from the preset value due to the small beam dose correction.

Channel framing and multiplexing

This process performs various tasks after dithering. The dithered pixel bit is projected into the scan line bit box. In this assignment, a small beam-specific full pixel shift can be performed. For a single deflection scan, the appropriate bits are then combined.

As described earlier for the hopping process, full pixel shifting in the Y direction can be done at a later stage. The pixels mapped by the b/w bit are placed in their scan line bit box. This bit box is typically wider than the bit map width because it allows for shifting space. Figure 31 illustrates this processing. The vertical arrow indicates the full pixel shift relative to the zero shift line. If the pixel begins on this line (as in the leftmost scan line of the scan line bit box in Figure 31), its full pixel shift is zero and the pixel is fully centered in the scan line bit box.

The next step in combining the deflection scan frame bits is shown in FIG. This step is necessary to accommodate the correct write strategy and to present the bits needed for the extinguisher at the right moment. By way of example, Figure 32 shows different beamlet positions for the parameters N = 4 and K = 3 on the bottom left side of the figure. The position is shown as a scan for different subsequent deflections: n, n+1, n+2, and n+3. At this step, mapping only the scan beam pair is not sufficient. For this step, both the beamlet index and the deflection scan index should be known. All bits for a particular deflection scan index are packaged as a single deflection scan bit box. In Figure 32, the two bottom columns are filled with symbols to find the pixel location of the deflection scan bit box.

Channel coding

As a last (optional) step, the deflection scan bit box will be encoded to improve data transfer.

data flow

Figure 33 is a schematic block diagram showing the main data processing and storage elements of the data path, including: offline processing & central storage unit (server), several graphics streamer nodes, and extinguisher chips (beamlet extinguisher array) .

The offline processing & central storage unit processes input layout data (eg, in GDS-II format) and produces an input file for the stripe. The stripe data must end up at the correct pattern streamer node based on the stripe allocation for each scan channel.

The graphics streamer node contains disk and RAM storage. The disk storage is used to store input data for the plan pattern, and the RAM stores the data required by the processing unit that is streaming the current pattern.

Depending on the architecture options, the input data from the server is the same as the input data for the processing unit. This is for offline and instant rasterization. For offline rasterization, the bit map is received from the server and forwarded to the processing unit. For instant rasterization, input data in vector format is received from the server and forwarded to the processing unit. The processing unit converts the vector format to a bit map. For the option of inline architecture, input data in vector format is converted to a bit map for processing units.

Schema options

The functional units of the data pathway are shown in Figure 28: (1) pre-processing; (2) channel partitioning; (3) channel transposition; (4) channel dithering; (5) sub-channel mapping; and (6) multi-channel Work and coding.

Pre-processing and channel partitioning are preferably performed offline, and sub-channel mapping and channel multiplexing and coding are preferably performed on-the-fly. However, rasterization (including channel routing and channel dithering) can be performed offline, inline, or in real time. The following architectural options are: (A) offline rasterization; (B) inline rasterization and field offset; (C) inline rasterization and alignment field; (D) instant rasterization .

In one embodiment of the lithography system, the following requirements of the lithography system are defined (which affect the data path architecture): the maximum field size is 26 mm x 33 mm (y, x) and the write time per field is 2.5 seconds. , plus another 2.5 seconds for the second time; 13,000 fibers/channels/strips with 637,000 electron beamlets (13,000 x 49 small beams per channel); strip width 2 μm and overscan width (one side) is 1.15 μm (including 0.2 offset range (+/-200 nm) + 0.2 calibration range (10% of strip width) + 0.5 soft edge (0.5 μm one side) + 0.25 write strategy (hypothesis) W _proj =420 nm: one-sided W _proj /2=210 nm)); maximum deflection width is 4.3 μm (deflection frequency depends on the write strategy and drive speed); typical pixel size is 3.5 nm, and pixel size range 2 nm-6 nm (1/3 to 3x (typical pixel size) ² ); dose grid resolution is 10-15 nm; minimum spacing is 64 nm, minimum CD for line is 22 nm, and for holes The minimum CD is 32 nm; the input resolution is 0.25 nm and the rasterization resolution is 0.1 nm.

The data pattern storage size on the pattern streamer is >10 patterns; the time to update the new correction parameters and prepare to start writing new wafers is 36 seconds; from the server to the graphics streamer Upload time <60 minutes; imaging from local storage to fast memory <60 seconds (separate processing steps) and <6 minutes (during writing); and processing nodes of 12 channels of 7 processing units.

The lithography system is preferably capable of processing both positive and negative resists. The characteristics of the resist are preferably processed in off-line processing of the data path and the remainder of the data path should not be known to this. In order to write a single wafer, two times can be used, namely: first time and second time or redundancy. A combination of the two will write all 13,000 strips on the wafer.

Option A: Offline rasterization

Figure 59 shows an embodiment using offline rasterization. GDS-II format data is processed offline, including: proximity effect correction and resist heating correction. If a smart boundary is used, the boundary is calculated at this stage. Rasterization (transfer and dithering) is performed to convert vector pattern data into a second-order black/white bit map, which is used in this embodiment (ie, for data format transmission to the lithography system) The tool inputs the data format. This off-line processing is performed once for one or more batches of wafers for a given pattern design.

Second, in-line processing of the tool input data is performed to generate a pattern system streaming (PSS) format, which is also a B/W bit mapping format. Inline processing is typically implemented in software. The pattern streamer then processes the PSS format data to produce extinction format data ready for transmission to the beamlet blanker array. This processing is typically performed in hardware and may include corrections relating to full pixel shifting in the X and/or Y direction for beam position calibration, field size adjustment, and/or field position adjustment. This process can be performed in accordance with the field. The extinguisher format pattern data is then transferred to a lithography system for wafer exposure.

In this architectural option, much of the work is done offline. Rasterization will be performed offline and each design will be executed once. For this option, the input data for the lithography system is described in a strip pattern of the black/white (B/W, black/white) bit map format. The bit map is processed on the fly. Therefore, only the corrections provided by Phase 5 (channel framing and multiplexing, see: Figure 34) are available. The correction of stage 5 is a full pixel shift correction, which may include: overall pattern shift in each of the X and Y directions, extinguisher timing offset (Y direction), and extinguisher hole offset (Y direction).

The X offset has an effect on the beamlet versus column mapping (extinguator hole offset and extinguisher timing offset). The appropriate Y offset will be appended and rounded to the nearest full pixel.

Since only full pixel correction is made, a relatively small pixel size (~2 nm) is desirable to meet the accuracy specifications. The disadvantage of using small pixels is that they are required to be larger than the available bandwidth for the channel, which may result in lower throughput or the need to use multiple fibers per channel.

In Figure 35, the process flow for this architectural option is shown. The focus is on the moment of changing the batch. The process flow can be analyzed to find the intervals in the lithography system that can be used to load the pattern data so that the processes can be processed in parallel to maximize throughput. In the central bar, the batch changes from pattern A to pattern B. For this figure, it is assumed that there is no reason (because of the failed bundle) to reconfigure the bundle with the strip. Loading the main part of the new pattern (for the strip written by the main scan of pattern B) can begin immediately after the last major scan is completed. This figure also shows that the second scan/redundant scan portion of the loaded new pattern can start quite late and should be done when the second scan/redundant scan for the new pattern should begin.

The duration of scanning G and F is typically 2.5 minutes. The total duration for parallel treatments H and D can be about 1 minute. Therefore, the time available for loading the total pattern is equal to the time for two scans and wafer exchanges (about 6 minutes), assuming no strip data recombination between nodes is required. When the new failure channel is found by process D, strip data reorganization may be necessary.

Figure 36 is a block diagram of the main components of a graphics streamer node for an offline rasterization architecture (option A). In Figure 36, each node contains several components. The node CPU coordinates the processing on the node and moves the data around. The network device communicates with the server (offline processing & central processing unit) and receives layout data to the stream.

The disk storage unit stores a bit map for the processing unit. There may be several versions of the bitmap mapped to be available on the disk. Reliability and read performance can be improved by using disk arrays in certain RAID modes. The read speed of the drive is increased by striping (RAID 0, distributing data across the disk array). Reliability can be improved by storing data in a redundant manner (RAID 5, N disks: storage size = N-1x disk size).

Processing unit memory (PU-RAM) stores pattern data. When scanning, the processing unit reads its graphics data from this RAM. The CPU loads the pattern data into the RAM before scanning. The processing unit streams the pattern data and produces an optical signal for transmission to the extinguisher.

A typical data flow for this configuration is shown in Figure 37. The pattern data is received by the node CPU from the network device (1) and stored on the disk (2). Whenever the pattern data is required for scanning, the node CPU reads data from the disk (3) and stores it in the PU-RAM (4). When scanning, the processing unit reads its pattern data (5) from the PU-RAM.

Important features of this architecture are PU-RAM size, PU-RAM load time, disk load time, and disk size. The PU-RAM load time (the time it takes to load all stripe data into the PU-RAM) will depend primarily on the performance of the disk storage unit. Regarding the disk load time, the bit map for the new scan must be downloaded from the server, and the server may be the bottleneck for communication. The disk load time can be improved by increasing the bandwidth from the server to the node or compressing the bit map data on the server. For disk size, it is assumed that in order to overcome the distribution bottleneck (server bandwidth), multiple (eg, 10) patterns can be stored in the disk storage unit. Depending on the requirements for availability or read speed, the disk can be constructed for a particular RAID hierarchy.

With the concept of off-line and in-line, the reordering and mapping of pre-processed pixels can be performed by their processing unit containing a field programmable gate array (FPGA). This processing unit will allow full pixel shifting and the data from the memory can be reordered for multiplexer transmission towards the extinguisher.

Compression can also be used for architectural option A. Possible configurations include: uncompressed, compressed dithered images, or compressed grayscale images.

For no compression, the graphics streamer node stores the (uncompressed) dithered image on the disk. It is also possible to compress this image on the server before distribution. In this case, the graphics streamer should decompress the image after it has been received, but this does not seem to be a bottleneck because there is a reasonable amount of time for this processing.

For compressed dithered images, compression reduces the amount of distributed work (communication time) and reduces RAM size requirements. For this solution, offline processing should compress the dithered image, and the FPGA should internally decompress the image and process it. Therefore, the image in RAM is much smaller. As far as the functional unit of Fig. 34 is concerned, the compression and decompression functions are inserted after the dithering, as shown in Fig. 39.

Compression may be less effective for dithered images because dithered images contain many zero values, and non-zero regions may be difficult to compress due to changes in dose values. Figure 40 shows a dithered test image using a single color (one bit per pixel) image. The image (Fig. 40) is 8 times the dithered version of Fig. 42 that changes the dose level each time it is repeated. Since the dose is changed each time it is repeated, the compression tool cannot utilize the repeat and is less efficient. GZIP and Optipng are possible compression methods. The compression of the dithered image is not easy and will pass approximately a compression ratio of 1:4 scale (mainly a sequence of compressed zeros). With a compression ratio of 1:4, the size of a typical strip image using 2 nm pixels will result in 4352 MB uncompressed and 1088 MB compression per strip, and 61 GB uncompressed and 15.2 GB compressed per streamer (ie: 14x). In this scenario, compressing the dithered image will reduce the RAM size to 16G bytes, providing a load time (for a single disk, disk -> RAM is about 2 minutes) and distribution time (server -> The advantage of the disk is about 1.5 hours). The 2 minute load time is suitable for processing the time window of loading in the process. The downside is that the FPGA is enhanced with decompression for each channel, which keeps up with the instantaneous data rate of about 5 Gbit/s. In addition, the server preferably compresses all data initially.

For compressed grayscale images, as far as the functional units of Figure 34 are concerned, the compression and decompression functions should be inserted after the transition, as shown in Figure 41. After the transition, the offline process should compress the grayscale image and the FPGA decompresses, dithers, and processes the image.

Figure 42 shows an example of a truncated bit map for a cell (64x1000 nm @ 2 nm pixels). For compression, use GZIP and optipng (both are open source compression tools). Both methods are lossless. GZIP is a universal compression tool, while optipng is dedicated to compressing 2D images. PNG compression consists of two phases, namely: 2D predictive filter and GZIP compressor, which makes optipng provide excellent compression ratio. Depending on the pattern found in the actual design, there may be more repetitions in larger images.

Using a compression ratio of 1:40 (PNG) and 2 nm pixels, the compression ratio shrinks the image to a size comparable to the vector format. However, using this approach requires PNG decompression integration in the processing unit FPGA. When the bit map size grows by a factor of four, the compressed image is only a factor of 1.3 for GZIP and a factor of 2 for PNG. Compression combined with small pixels is quite effective.

An interesting observation of this approach to using grayscale pixels is that it is potentially allowed to shift and form larger pixels for streaming to the extinguisher. The value of a larger pixel can be calculated from a smaller pixel by using a linear combination of values of smaller pixels. The input image can be viewed as oversampling. Figure 43 shows this concept of small grid input pixels and large output pixels. An example is proposed in which the ratio of pixel sizes is 1:2, however, other ratios are also possible. The FPGA maps the uncompressed bits and combines several small pixels into a large pixel for streaming to the extinguisher. The advantage is that this approach will be limited to the bandwidth of the fiber (large output pixel) even when using small input pixels. The bandwidth of the fiber is considered a bottleneck, and each channel may require two fibers to stream 2 nm pixels to the extinguisher.

Notes on this architecture:

‧ The dose mapping is preferably still attached to the input bit map and used by the FPGA.

‧ Dose correction is possible because of the dithering in the FPGA.

‧ When X and Y are shifted from the input pixel to form the extinguisher array, the accuracy depends on the actual pixel size.

‧ Decompression and dithering in the FPGA is necessary.

‧ Compression is attached to the offline process. It is expected that compression will significantly increase the processing effort.

The RAM size is reduced with a compression ratio of 1:40. For this scenario, the FPGA is equipped with instant decompression logic that keeps up with the rate at which grayscales are extended (>>5 Gbit/s).

Options B and C: In-line rasterization

Figure 60 shows an embodiment using in-line rasterization. The GDS-II format pattern data is accepted as offline processing for the offline embodiment of Figure 59, including: proximity effect correction, resist heating correction, and (if used) smart boundaries. The modified vector pattern data and dose map are the tool input data formats used in this embodiment. This off-line processing is performed once for one or more batches of wafers for a given pattern design.

Second, in-line processing of the vector tool input data is performed to rasterize the vector data to produce B/W bit map data, which in this embodiment is a graphics system stream (PSS) format. This processing is typically performed in software and can be performed when a new dose setting is set. As in the embodiment of FIG. 59, the pattern streamer then processes the PSS format data to produce extinction format data, including that it relates to beam position calibration, field size adjustment, and/or field as previously mapped in the bit map data. The correction of the full pixel shift in the X and/or Y direction of the domain position adjustment. This process can be performed in accordance with the field. The extinguisher format pattern data is then transferred to a lithography system for wafer exposure.

Figure 61 shows a second embodiment using in-line rasterization. This is an embodiment similar to that of Figure 60 except that the corrections for beam position calibration, field size adjustment, and/or field position adjustment are made on vector tool input data. Since these corrections are made in vector data, full pixel shifts and sub-pixel shifts in the X and Y directions can be made. These corrections are typically implemented in software and can be performed on a wafer basis. After the correction has been made, rasterization is performed to generate PSS format data for input to the graphics streamer.

Figure 44 shows the inline rasterization functional unit that it is assigned to the processing step. For this architecture, functional units 3 and 4 (rasterized) are performed inline. For this option, the input data for the lithography system will be described in a stripe pattern in vector format. Rasterization will be performed according to requirements (by wafer, by wafer, by series of wafers). In-line rasterization can be triggered by an overall offset or a change in overall dose.

The appropriate dose is set by changing the pixel area. The pixel area can be changed by changing both the X and Y pixel sizes. However, only the X size can be changed to some value (as discussed with respect to Figure 10). For fine tuning of the overall dose, a change to the Y size can be used. Assuming a fixed bit rate, the Y pixel size is set by changing the deflection frequency and using different pattern scaling factors.

Because the rasterization results will be used for all fields, the sub-pixel offset for a particular field cannot be considered. The offset of each field is preferably rounded to the full pixel, which is immediately considered by stage 5 (channel framing and multiplexing).

Fixes can include:

‧ Field pattern shifts in X and Y (only full pixel shift). The parameter is that each field is updated once.

‧ The overall pattern shift in X and Y (in sub-pixel resolution). The parameter is that each wafer scan is updated one or more times.

‧ The overall dose change through the calibration of the pattern. The parameter is that each wafer scan is updated one or more times.

The dose correction and sub-pixel shift of each beamlet are unprocessable. The root cause is the ability to shift in the X direction, which controls the mapping of columns to beamlets. To limit the error, this option will typically result in the use of a fairly small pixel size (approximately 2 nm). This option is a special case compared to architecture option B in the sense that the beamlet will be written to the same line for each field. In other words, the columns for the beamlet map are fixed and the same for each field. Therefore, the beamlet specific correction can be compensated. Since the sub-pixel correction is properly performed, the beamlet will write the pattern with greater accuracy. Therefore, the pixel size is large (~3.5 nm), which does not cause a higher optical channel count towards the extinguisher.

All corrections are supported, however, the field is in the ideal position and therefore does not have an offset between X and Y between the fields. The processing flow may be different from architecture option A. For architectural options B and C, new bit maps must be generated frequently from vector input files on each wafer or wafers.

(F) Main scan. If the new pattern bit map is reproduced, it may have a dependency on wafer measurement (E1). Figure 45 shows the processing flow if dependency occurs. When there is no such dependency, the processing flow will be similar to the processing flow of FIG. There is also no dependency when effectively estimating the information needed for regeneration (slowly changing processing parameters). Therefore, regeneration can begin early, but must be confirmed after actual measurement. If an unexpected mismatch occurs, regeneration will resume and some production will be lost. Finally, the consideration is that if enough RAM is available, processing can begin as soon as possible after the main scan. This will increase the time frame for processing by another 2.5 minutes. Solutions that support inline processing will require extremely powerful processing units to meet reasonable timing requirements. For the worst case condition (2.00 nm pixels, maximum stitching), the number of pixels to be rotated will be 35 G pixels per strip. The size of the vector data will be 606 Mbytes per strip. In Figure 46, the architecture for inline processing is shown. The illustrated architecture displays the square "rasterizer". This block will be the inline processing task responsible for translating the vector format into stripe B/W images. The options for implementing an inline rasterizer are:

● Offline, processing and control.

● Use FPGA logic. For instant rasterization, the FPGA logic is used for the same purpose. For instant rasterization, many resources in the FPGA must be used to meet performance requirements. For inline rasterization, using FPGA technology, the solution can be implemented with fewer resources than the instant form.

‧ Use GPU technology. A GPU (Graphical Processing Unit) is a processor typically used for video processing. These processors are found in consumer systems (desktop and laptop) for transferring 3D images (games, Vista). The GPU is using a lot of parallelism. The G80 architecture utilizes 128 thread processors, while the state of the art card GTX280 utilizes 240 thread processors. The performance of the processor is roughly one-fifth that of the Intel core CPU. The performance of a GPU is obviously dependent on the degree of parallelism in its mission. The transition is a task that is fairly easy to parallelize. The dithering task (in one direction) is parallel to a certain degree (diagonal).

‧ Multi-core CPUs using state of the art technology. Today's multi-core CPUs are extremely powerful. The example is Intel's new architecture: Core 17 technology. The FPGA solution is clearly a relatively inexpensive solution. Compared to architectural option D (in the FPGA instant rasterization), the performance requirements for this solution are much more relaxed (2.5 seconds for 7 stripes, compared to 6 minutes for 14 stripes). Therefore, FPGAs are much smaller (and cheaper). Nevertheless, the feasibility depends on the feasibility of VHDL's implementation of the transfer algorithm.

When evaluating software solutions, GPU technology will be optimal because the high parallelism available on the GPU will benefit the task of migrating. The downside is that GPU technology is rapidly evolving. This fast-developing hardware problem (at least by NVIDIA) has been addressed by providing a stable Compute Unified Device Architecture (CUDA) API. This API is suitable for a wide range of graphics card models and versions. Today, there is even a product line for high performance computing (Tesla). This product line is aimed at scientific calculations rather than drawing for games.

For this architecture, the processing is described in the following steps.

The vector format input file is transferred from the server to the hard drive. The rasterization module should process the input file to generate a new bit map before starting the initial scan or after the parameter changes. The bit map is the RAM memory stored in the processing unit. When scanning, the processing unit reads the bit map data from its RAM. This process is similar for architectural options A, B, and C. Rasterizers are implemented using FPGA technology. The logic will be similar as the one used for instant rasterization. Inline solutions are much lighter than instant solutions. Therefore, fewer logic cells will be needed. For the FPGA solution, there are two options for the data stream. In Figure 47, a data stream is shown in which the FPGA stores its output directly in the PU-RAM. This solution is appropriate if the rasterized logic is combined with the same FPGA as the processing unit. In this case, the components share the same memory controller. According to the processing diagram of Fig. 45, the processing can be performed in parallel. However, the potential interference is the reason for separating the FPGA. Another possibility is shown in Figure 48, where the node CPU will be responsible for extracting the results from the FPGA and storing them in the PU-RAM. In Figure 49, communication between the host and the GPU is shown. The host stores the program (core) and data in the GPU's DRAM and triggers the program. The multiprocessor extracts the data it needs from the DRAM and writes the result back to the DRAM. When the total job is completed, the host will extract data from the GPU's DRAM. The interface between the host and the GPU is typically a PCIe x16 bus and involves DMA in data transfer. When using standard GPU hardware, the interface between the CPU node and the GPU card is PCI-Express/16. The internal architecture of the GPU (see: Figure 51) shows that it is completely focused on parallelism. This particular GPU contains 30 multiprocessors and 8 multiprocessors per multiprocessor. This adds up to 240 processor pairs. Multiprocessors use the SIMD (Single Instruction Multiple Data) type and use crystal-loaded (fast) shared memory for their eight processor. In order to take advantage of the performance of the GPU architecture, its task is to split into multiple parallel tasks. The rasterization task consists of two subtasks: traversing and dithering.

The nature of the task of transitioning is that it is fairly easy to parallelize. Scanning lines or even pixel sub-listings can be considered as separate processing. The nature of the dithering task is relatively serial, because the quantization error propagates in two directions (on the same line in the direction of dithering movement and to the next line). However, when dithering in only one direction, the dithering is parallelized along the diagonal. The next line should be decremented by one or two squares to correctly handle the quantization error of the previous line.

Disadvantages of using a GPU include that the GPU is not cheap; considerable power consumption at execution time (eg, TDP = 200 W); and it is not a common task to generate a parallel code for balancing the GPU that uses its power.

Multi-core CPU solution: When using a powerful multi-core CPU as a node CPU, the node CPU will be able to perform rasterization tasks. Figure 52 shows a typical data flow for this configuration. The CPU reads the vector input data (3) from the hard disk. The CUP will perform the rasterization task and store the bit map to the PU-RAM (4). When scanning, the processing unit reads the bit map (5) from the PU-RAM.

Disadvantages include: processor cost; considerable power consumption (Intel Core2 Extreme quad-core processor: TDP = 130 W); and, relatively low parallelism (4 cores for Intel Core 2 quad-core processors) .

For in-line rasterization, different solutions are possible. However, in-line rasterization reveals some common features: PU-RAM size. As with offline rasterization, inline rasterization requires a bit map to be stored in the PU-RAM. Architecture option B requires a small pixel size (for example: 2.00 nm, see Appendix A.1) and therefore requires storage of approximately 61 Gbytes of (uncompressed) bit map data. For architectural option C, use a larger pixel (for example: 3.50 nm). For a 3.50 nm pixel, a 20 G byte would be appropriate. RAM load time. For this solution, assume that only vector input data is stored on the disk (total size 8.5 GB). Whenever a new bit map is needed, the vector input data is read from the disk and rasterized and stored in the PU-RAM. In this case, the disk data rate does not seem to be a bottleneck. The bottleneck for this solution will be the rasterizer. Its performance depends on many factors and cannot be easily predicted. An alternative would be to implement rasterization at an earlier stage. The bit map can be stored in PU-RAM or on a disk. Storing the intermediate bit map on a disk has the disadvantage of having a significant bottleneck for load time (see: Architecture Option A).

Disk load time: The vector input data for the new scan must be downloaded from the server. The server will obviously be the bottleneck for communication. The option for improved disk load time is to increase the bandwidth from the server to the node or to compress the bit map data on the server. Storing 10 versions of the bit map on the disk storage unit will require 85 GB of storage capacity. Improved reliability (and read performance) suggests using a mirrored configuration (RAID 1) and using two 100 GB disks.

Assuming that the main algorithms are largely parallelized, the approximate performance comparison between the CPU and the GPU is based on the following characteristics: Intel CPU core is better than the thread processor by a factor of 5; Intel CPU has 4 Core; and, the GPU contains 20 processor.

Assuming the full utilization of parallelism, the main point of performance ratio (Intel: GPU) is four cores: GPU=(4*5): 240=1:12. In fact, several factors will reduce this "ideal" ratio. The factors are: the difference in execution costs (the cost of integer division is quite high for this brand of GPU); the degree of parallelism; the extent to which parallel codes can be written; how many threads can be executed in a limited amount of local memory; The use of single instruction multiple data (SIMD) processors. There are typically 8 processor in the SIMD group. This means that the execution path is extended because the two sides of the branch are always (serial) execution.

On the other hand, multicore solutions like Intel processors use shared cache memory. Depending on several factors, when multiple cores are active, the performance of each core will be degraded. In this section, an estimate of its rasterization (transfer and dither) performance using Intel CPUs is made.

In order to estimate performance, the transfer and dither module has been implemented in C++. Use only C++'s 00 features, not any performance-critical instructions like new, delete, or any advanced data structure like a serial or queue. The 64*1000 nm grid is used as a unit for indexing and dithering. It is visually confirmed by comparing the vector format input with the bit map output that the transition and dithering are as expected. The Visual C++ 2008 compiler has been used to enable optimization of speed.

The algorithm used for the conversion is the scan line method. The active edge table is used to maintain an edge group that intersects at least one scan line (pixel line). The pixel size used is 3.5 nm (Schema Option C). Although a maximum of 64 edges are specified, 52 (81%) per division is a reasonable average.

For measurement, machines with modern CPUs have been chosen. The CPU is a Core 2 Duo (6400) running at 2.14 GHz and has 2 GB of RAM for the Windows XP operating system.

The input vector format used is the specification of a set of closed polygons in the grid. The dose grid is omitted, but the dose factor incorporating the Y-dependent is processed. The shift for the y direction is always 0, but the algorithm incorporates a job for the scan line dependent shift value.

The optimization of the code is performed by measuring the code improvement. A regular parser is not suitable because of its limited time resolution. Instead, "QueryPerformanceCounter" has been used in the Win32 API. This counter uses a CPU timestamp counter in ns resolution. The code is optimized by hand based on the results of QueryPerformanceCounter. After optimization, the load is distributed across the application in the following fractional parts: 55% for reversal, 27% for dithering, and 18% for input processing.

The single core of the machine can perform 100,000 grid rotation cycles in 8.7 seconds. This translates to 11,494 cycles per second. In addition, the implementation with dual cores is almost linearly calibrated (8.7 single core 100,000 grids -> 8.8 dual core 200,000 grids). The entire strip is made up of 2,200,000 cells.

Therefore, a core will cost 194 seconds in a strip. Assuming linear scaling, this means that when 7.5 cores are used, 14 strips are rotated within 6 minutes. The Core 2 Duo (6400) is no longer the top model of the Intel CPU. Therefore, core performance should be improved by a factor (for example: 30%). On the other hand, it is known that the use of multiple cores is never possible to scale in a linear manner. Assume that these two factors will cancel each other out.

The performance results are the sum of: the algorithm used; the scale (size to column); the integrity of the algorithm; the specific optimization used; the total time spent optimizing; compared to the prototype The actual configuration is used by the cache/memory; and, the relative performance of the CPU that will be used in the final configuration.

As discussed for option A, it is possible to compress the image that is held in the PU-RAM. The rasterizer should compress its dithered or grayscale image, and the processing unit FPGA should decompress it and selectively dither it. Architecture B will actually benefit from compression and oversampling techniques. It is no longer necessary to use 2 fibers for each channel. Architecture C has used a fairly large pixel size and will benefit only from compression. This means a smaller PU-RAM with less load time. However, the decompression logic should be attached to the processing unit FPGA. However, decompression will have a significant impact on the in-line processing workload.

Option D: Instant rasterization

Figure 62 shows an embodiment of its use of instant rasterization. This is an embodiment similar to that of Figure 61, except that rasterization is carried out further during the process, typically during hardware-implemented on-the-fly processing. Corrections for beam position calibration, field size adjustment, and/or field position adjustment are made on vector format PSS format data, and then rasterized to convert this to a B/W bit map. Since the correction is made on the vector data, the full pixel shift and the sub-pixel shift in the X and Y directions can be created.

Figure 53 shows the functional blocks for this architecture. For this option, functional units 3 and 4 (rasterized) are executed on-the-fly during execution.

The amendments include:

● Correction of pixel shifts (full pixels and sub-pixels) in X and Y. The parameters are updated once per field.

● Dose correction for each subchannel. The parameters are updated once per field.

● Calibration correction for each channel for Y. The parameters are updated once per field.

● Extinguished timing offset correction. The parameters are updated once per wafer scan.

The offline preprocessing system will prepare the vector format for all stripes. The graphics streamer will use this data as input. The pattern streamer generates a B/W bit map by instant indexing and dithering. All kinds of corrections are implemented during the transition and dithering. From the BAA/bit map, the pattern streamer generates a small bundle of bits, multiplexes all of its beamlets of data for the channel and transmits the data to the extinguisher wafer through the fiber.

Resources are needed to stream data to the laser.

Processing consists of two steps: getting the data from the memory and routing it to the pixels in a logical order, reordering the logically ordered pixels to the box due to the sub-beam ordering. The first step may consist of the actual transfer of the vector data, or only the pixel data of the transferred data from the memory.

To subdivide vector data into pixels, each strip is divided into sub-strips of 62.5 nm in vector format. For a (maximum) 500 nm soft edge, the number of sub-bands to be processed is 2000 + 500 + 500 / 62.5 = 42.8 sub-strips. Each sub-strip is indexed in a sub-strip pipe. Each pipe will operate at approximately 100 MHz and 48 pipes will result in a near-needed 5 Gbit/s.

At the top of the pipeline, a FIFO is used to cross the clock domain boundary from the memory clock domain to the processing clock domain. This FIFO also acts as an intermediate storage buffer, since the memory bandwidth must be shared across multiple stripes. The FIFO contains both angular data and dose mapping data. The transition application can be randomly addressed in the bottom of the FIFO. The FIFO must contain data for at least three blocks to allow some slack to the memory arbitrator. The data for each block contains 272 bytes. Data for 3 blocks = 816 bytes. The standard block random access memory contains 18 Kbits of data = 2 Kbytes of data. This means that, from the viewpoint of data size, each block random access memory (blockram) can be applied to three sub-strip pipes. However, from the perspective of data availability, each pipe should use its own block of random access memory at the top.

Each sub-strip pipe requires some internal FF and LUT for processing. Assume that the number of available FFs and LUTs and the number of required BLOCKRAMS are more than necessary.

Rearrange the pixels for multiple exposures.

At the bottom of the sub-strip pipe, or if the data is mapped to the bits in the memory directly under the memory, the data is stored in another FIFO. This FIFO must contain at least 245 lines of data, which is required to write pixels with 49 small bundles with K=5. Each line will (maximally) contain 3000 nm/2 nm = 15000 pixels. 15,000 pixels * 245 lines = 367,500 bits. This is equal to 20 block random access memories, which are rounded into 32 block random access memories to facilitate processing.

The framing/multiplexer reads from these 32 block random access memories and forms a frame suitable for transmission to the laser. These blocks are stored in another FIFO block random access memory, which is necessary as a non-synchronous boundary between the MGT clock domains and as a flexible storage unit.

Lattice-based input format

Vector notation is typically used to generate graphical data, such as: GDS-II or OASIS formats. As mentioned above, different modes of operation may be used for charged particle lithography systems. One of the above modes is an instant rasterization mode in which graphics data in a vector-based input format is used and processed by a processing unit (such as an FPGA) (ie, for a set of fields of the wafer) The pattern data is at least partially processed when a scan of the group of fields occurs.

A grid-based input format can be used in this instant rasterization mode. One embodiment of the input format describes two aspects: feature layout and dose rate. The feature layout is described using a grid-based approach that is suitable and optimized for instant FPGA routing and dithering. The dose rate is described by a fixed size grid that covers all feature areas (eg, field).

A grid-based format for pattern data can produce a data set having a more predictable size, facilitating the streaming of pattern data to the lithography system for immediate and/or hardware processing. Pattern data in vector format provides a more unpredictable size per cell. Pattern data in a bitmap mapping format can be used, but will need to be compressed for transfer from the preprocessing system to the lithography system. The amount of compression of the bit map data may vary appreciably per cell, depending on the features in the cell. Streaming such compressed data to a lithography machine and then decompressing the data results in an unpredictable transmission rate of uncompressed data.

It is advantageous to know in advance how much data (bits) are contained per cell and what compression factors are achieved if the pattern data is compressed (eg, when compared to the total size encoded in the bit map format). The grid-based format is designed with these features. This is desirable because it provides a guarantee that the grid-based pattern data always fits a certain size of memory (the size of the memory selected at design time), which is substantially smaller than the size of the uncompressed bit map data. This guarantee cannot be provided for a bit map compressed using a general compression algorithm such as: ZIP. It is also desirable because it provides that the grid-based pattern data can be converted to a bit map for a certain maximum amount of time, which is important if instant rasterization occurs.

Moreover, if a particular cell covering a certain area of the bit map field must be read from a "compressed file" encoded in a grid-based format, it is immediately known where the cell is encoded in the file (no need to be like Look for this area if the file is in a GDSII format, for example, where the feature is randomly present in the file.

The grid-based format is also more suitable for streaming to the lithography system because it is arranged in a grid, and arranging the pattern data in the order of the cells to be scanned is quite straightforward compared to the vector format.

In the lattice-based format, there is also an additional amount of "compression" due to the only relative position encoding of the features in each cell. This relative position combines the position of the grid to provide the absolute position of the feature in the field. Relative feature locations have fewer possible values (restricted by the size of the cell) and therefore require fewer bits to define than the absolute position of the field.

The relevant parameters of this embodiment for describing the grid-based input format of the feature layout are summarized below.

For feature layout formats, the minimum feature spacing is an important parameter. The minimum feature spacing is essentially limiting feature density. It means that within a distance of the minimum feature spacing, a particular transition (eg: ON->OFF or OFF->ON) can only occur twice.

In Fig. 67, a pattern layout of an example is shown which has features (lighter colored regions) that follow the minimum feature pitch (P).

An important result of the characterization is that a transpose of 64x64 nm should describe up to 4 corners. When a feature is described in such a transition box, the index of the index provides its reference position. Features within the transition grid can be described using relative positions.

The (partial) feature within the transitional column can be described by its angularity or by a straight line. The line angle can be limited to a multiple of 45 degrees, limiting the vector orientation to only 8 possible directions, as illustrated in FIG. The eight orientation codes are assigned for each possible orientation as shown in FIG.

Figure 68 illustrates the concept of a corner. A cell is a line that appears as having an edge of the feature (on the right side) and an edge of the feature (on the left side). Both corners and straight lines are considered "angular". The corner A is defined by the position of A (for example: X _A , Y _A ) and two vectors (for example, defined by the orientation codes Edge1=2 and Edge2=4). By definition, the area in the direction of movement from Edge1 to Edge2 in a clockwise direction is the active area. In the same way, the line is described by the "virtual edge" point B (for example: X _B , Y _B ) and the two edges (for example: Edge1=4, Edge2=0). The position of this virtual corner is at any point on its defined line. Furthermore, the area in the clockwise direction of movement from Edge1 to Edge2 is the active area.

Within the grid, the edges of the same feature should be matched. Figure 70 shows a simple square feature encoded as four matching corners among the 64 nm x 64 nm cells. The table on the left side of Figure 70 shows the parameters that fully describe the features. The corners are described by their angular coordinates (X, Y) and the edge description is based on the angular orientation of the direction defined in Figure 69. From the angular coordinates and the orientation code, it can be determined that all the corners in Fig. 70 are a single feature.

For processing in an FPGA (or other type of hardware processor), it is advantageous to have a fixed size data structure. This makes it easier to address the cell description in memory and to help keep the FPGA logic simple.

Figure 71 shows an example of the more complex feature shapes described by the corners in the cell. Straight lines along the 45 degree and -45 degree orientations are also used to define the features displayed.

Feature edge with 45 degree orientation

The minimum feature spacing ensures the maximum number of corners in the grid. When considering a feature with an azimuthal edge at 45 degrees, the largest dimension of the lattice is its diagonal, the length of which is equal to the grid size multiplied by the square root of the square for the square (for example: 64 x for a 64 nm square) ). When the minimum feature spacing is less than this diagonal length, the risk is that there may be more than 4 corners per cell. This situation is shown in Figure 72. On the left side, the legend shows a regular grid of square features with a 64 nm pitch, positioned in a 64 nm grid, and 4 corners per grid (angles are indicated by small circles). On the right side, the grid of square features is rotated 45 degrees. The emphasized corners show that the six corners are on the middle of the grid.

To solve this problem, several solutions can be applied:

● For +/- 45 degree lines, specify a larger minimum feature spacing, at least equal to the length of the diagonal of the grid (for example: 64 x √ 2 nm for a 64 nm square).

● Reduce the grid size so that the grid diagonal is equal to (or less than) the minimum feature spacing (for example: the minimum feature spacing for 64 nm is √ 2x64 nm).

● Allow a larger number (for example: six) of the corners of each cell.

● Allow a variable number of corners for each cell.

In the following description, it is assumed to be the first option described above.

Proximity effect correction

Proximity effect correction is required to improve the pattern (especially the corners) after processing the wafer. Proximity effect correction can be counteracted by locally fine-tuning the geometry or dose. It is assumed that the proximity effect correction is performed by geometrical changes, using a serif that surrounds the corners, which typically has The length of the CD.

In Fig. 73, an example in which the serif is attached to some of its corners is shown. Each corner is preferably provided with an option to incorporate the serif at a particular corner. As shown in Figure 73, an important result of such techniques is that the serifs defined by the edges of a cell (for example, the feature B serif of cell 2 in the figure) can be partially rotated in adjacent cells. (For example: Feature B serif extends to grid 3). Alternatively, features having all of their edges in a grid (eg, feature A in grid 1) need to be part of their serifs in adjacent grids (eg, feature A serif in grid 2).

In order to deal with this, different ways are possible:

● Share information about the edges and edges of the serifs with adjacent partitions.

• Once the outer serif edge has the effect of arranging the grid, the extra information is encapsulated (copied) in the grid definition.

● Describe the serif as a normal corner. This solution significantly increases the number of edges per division (extremely variable).

Dose grid

In addition to the feature geometry, the dose rate is an important system parameter that is significant at the microscale. The dose information can be described by providing a dose grid containing a dose rate per division (dose information can be provided in other ways, for example by correlating a dose value for each feature). The cell size is typically equal to or less than the desired critical dimension (CD). In theory, the dose grid is irrelevant to the grid of the grid.

The two options for handling the two grids are:

● Define two grids without regard to each other.

● Align the two grids and integrate the options.

For FPGA processing, it may be advantageous to combine a dose grid with a transition grid. The dose grid size is typically less than the size of the staggered grid. This can be achieved, for example, by embedding (3 x 3) 9 dose grids within the transition grid. The gray scale value can vary between 100% and 50% in steps of 0.2%. Therefore, each dose grid requires 8 bits.

However, the result is a link between two separate concepts. Whenever the pitch value changes, it also has the inevitable result for the size of the dose grid.

Pixel grid

The pixel size and position are preferably elastic. Pixels can be non-square, but will always have the same dimensions within a strip/channel. Pixels can be indexed by (worst case) 4 transition cells. Because of the shifting of the sub-pixels, different (Y-direction) alignments can be used for each column.

Input format specification

The following specifications are provided for one embodiment. The transitional column contains blocks and additional information with 64 by 64 nm with up to 4 corners. The edge is the vector that starts in the corner, Edge1 or Edge2, and the clockwise angle from Edge1 to Edge2 defines the active side. The corners are the corners of the features in the grid. When the line is traversed without the actual angularity, the corners may have an angle of 180 degrees. Assume that each transition column has a maximum of 4 corners.

The specifications for the angular data for one embodiment are provided in the following table:

In order to calculate the size of the serif from its field value, different strategies can be used, such as lookup tables, where the field value is used as an index in a predefined table, or by calculation (eg seren size = The value is *0.5 nm, so its range is 0...15.5@0.5nm, assuming a positive serif size).

The specifications for the reticle data for one embodiment are provided in the following table:

The following table summarizes the amount of data when using the above format. The assumption for this data volume table is that there is no stitching.

There may be opportunities for data compression. For example, it is contemplated that multiple cells contain less than 4 corners and the dose rate may be the same for all dose grids.

Defining a fixed-size data structure will ease the task of FPGA design (addressing and loading), but with consequences for memory. For communication and (disk) storage, standard compression techniques can be used to compress the data. This is effective when the unused record is filled with the same value (for example, it is zero for unused edges). Compression is also valid for repeated values as similar values for dose mapping.

Some of the design issues for the above embodiments are:

● Up to 4 corners per division may not be enough;

● Finding serifs in adjacent cells is expensive at processing time and memory and should be avoided if possible;

● The serif may be different from the expected shape;

● Fixed angles per grid are desirable for hardware implementation;

● A large fixed number of corners per grid results in a huge amount of data;

● a small fixed number of corners per division results in a lack of flexibility;

● From the theoretical point of view of information, coding all angular codes is excessive information, but significantly beneficial for implementation in hardware;

● The resolution of the angular angle is preferably 0.25 nm instead of 0.5 nm;

● It may be sufficient to encode only half of the edges.

Coding large blocks together

As a compromise between a large number of large and small fixed numbers of corners, one possibility is to limit the maximum number of corners for larger data blocks, for example: about 16 times larger in the mechanical scanning direction. It is assumed that the local maximum number of corners in one region of this larger block will be compensated by the smaller number of corners in another region of the block.

An upper limit of more than 4 at the maximum number of corners is undesirable due to the increased use of memory. However, the lower limit of use will not cover all possible scenarios. As an intermediate solution, consider the following scheme: encode the data in a block larger than the current cell (for example, a block of 16 cells at a time), and limit the number of edges to the block, where the local maximum The number of corners can be higher. In this scenario, the serif is encoded as if it were an edge, which facilitates implementation.

In order to implement this embodiment, the following changes can be made to the above embodiment:

● Define a block that is 62.5 nm in the Y direction (deflection direction) and 1000 nm in the X direction (mechanical scanning direction);

● The Y size of the cell/block is reduced from 64 to 62.5 nm. This has two advantages: 16*62.5=1000 nm and 62.5/0.25=250, which can be efficiently encoded in 8-bit;

● The density map can have a resolution of 31.25 x 31.25 nm (1/32 of 1000 nm);

● The maximum number of corners is set to 64 per block (average 4 corners for each 62.5 x 62.5 nm grid);

● The serif is coded within the data, like the edges themselves.

The following specifications are provided for this embodiment:

The specifications for the angular data for this embodiment are provided in the following table:

The specifications for the reticle data for this embodiment are provided in the following table:

The following table summarizes the amount of data when using the above format. The assumption for this data volume table is that there is no stitching. This estimate does not take into account rounding, which occurs when information is stored in actual RAM.

There is a chance of compression. For example, it is contemplated that multiple blocks will contain less than 64 corners, and for adjacent dose cells, the dose rate will have similar values. However, compression also leads to more complicated implementations. The data may be compressed as it is transported through the system.

From the theoretical point of view of information, it is not necessary to encode all the corners with all coordinates. However, this dramatically reduces the amount of computational effort in implementation. It is also beneficial to cross-code block boundaries. This increases the number of corners, but reduces the computational effort in the FPGA more. In addition, it should be taken into consideration that the entire transfer process should be performed from both ends of the data. Leaving some "obvious" information in one direction may cause problems when scanning in other directions.

The block is also likely to be positioned in the deflection scan direction. There are two reasons why there should be no such. The parallelism of the implementation must process the data across several strips within the strip, and if the data is located in this way, this would not be possible. Furthermore, the grain size in the deflection scan direction will be 1000 nm, which is undesirable for stitching. In the present case, the particle size of the strip width including the stitching area is 62.5 nm.

There should be some ideas for wrapping data in memory. It may be helpful if the data for the dose mapping is stored in an individual bit path other than the angular data.

The use of the previous paragraph has the following benefits:

● Small amount of data (for example: 3.5 TB instead of 5 TB);

● High resolution (eg 0.25 nm instead of 0.5 nm);

● for the serif and for the number of corners in the local range, the elasticity is higher;

● The implementation is less complicated.

Pattern beam lithography system

Figure 74 shows a simplified schematic of an embodiment of a charged small particle lithography system 1 based on a co-crossing electron beam optical system that does not have all of the electron beamlets. This optical system is described in detail in U.S. Patent Application Serial No. 61/045,243, the entire disclosure of which is incorporated herein by reference.

Such a lithography system suitably includes: a beamlet generator that generates a plurality of beamlets; a beamlet modulator that maps the beamlets into modulated beamlets; and, a beamlet projector, Used to project the beamlets onto the target surface. The beamlet generator is typically comprised of a source and at least one array of pores. The beamlet modulator is typically a beamlet extinguisher with an extinguishing deflector array and a beam stop array. Beamlet projectors typically include a scanning deflector and a projection lens system. The wafer positioning and support structure of the present invention is not explicitly shown in FIG.

The lithography system 1 is particularly adapted to implement redundant scanning functionality in conjunction with so-called two or more scans as described herein. This improvement in scan line accuracy onto the target surface enables a second scan that fills the gap left in the first scan sequence.

In the embodiment shown in FIG. 74, the lithography system includes an electron source 3 for generating a homogenous, extended electron beam 4. The beam energy is preferably maintained relatively low in the range of about 1 to 10 keV. To achieve this, the accelerating voltage is preferably low, and the electron source is preferably maintained between about -1 and -10 kV with respect to the target at ground potential, although other settings may be used.

The electron beam 4 from the electron source 3 passes through a double octup and is subsequently a collimator lens 5 for collimating the electron beam 4. As will be appreciated, the collimator lens 5 can be any type of collimating optics. Subsequently, the electron beam 4 strikes the beam splitter, which in one suitable embodiment is the aperture array 6A. The aperture array 6A blocks a partial beam and allows a plurality of beamlets 20 to pass through the aperture array 6A. The aperture array preferably comprises a plate having a through hole. Thus, a plurality of parallel electron beamlets 20 are produced.

The second aperture array 6B produces a number of beamlets 7 from the respective beamlets. The system produces a large number of small bundles 7, preferably about 10,000 to 100,000 small bundles, although it is certainly possible to use more or fewer small bundles. Note that other known methods can also be used to generate a collimated beamlet.

This allows manipulation of the beamlets, with the result that it is beneficial for system operation, especially when the number of beamlets is increased to 5,000 or more. Such manipulation is achieved, for example, by a concentrating lens, a collimator, or a lens structure that converges the beamlets onto an optical axis (eg, in the plane of the projection lens).

A concentrating lens array 21 (or a group of concentrating lens arrays) is incorporated behind the beamlet generation aperture array 6A for focusing the beamlets 20 toward corresponding openings in the beam pupil array 10. The second aperture array 6B produces a beamlet 7 from the beamlet 20. The beamlet generation aperture array 6B is preferably incorporated into the bundle beamlet array 9; for example, the two can be assembled together to form a subassembly. In FIG. 74, aperture array 6B produces three beamlets 7 from respective beamlets 20 that impinge corresponding openings in beam stop array 10 such that the three beamlets are projected lens systems in end module 22. Projected onto the target. In fact, for each of the projection lens systems in the end module 22, a larger number of beamlets can be produced by the aperture array 6B. In one embodiment, 49 beamlets (arranged in a 7x7 array) are generated from each beamlet and directed through a single projection lens system, although the number of beamlets per beamlet can be increased to 200 or more By.

The stepwise generation of the beamlet 7 from the intermediate stage of the beam 4 through the beamlet 20 has the advantage that the main optical operation can be achieved with a rather limited beamlet 20 and located relatively far from the target. One such operation converges the beamlets to a point corresponding to a projection lens system. Preferably, the distance between the point of operation and the point of convergence is greater than the distance between the point of convergence and the target. Most suitably, an electrostatic projection lens is utilized here in combination. This convergence operation enables the system to meet the need to reduce spot size, increase current, and reduce dot unwinding to achieve reliable charged particle beam lithography at advanced nodes, especially at nodes having a critical dimension of less than 90 nm.

The beamlet 7 then passes through the modulator array 9. The modulator array 9 can include an array of small beam extinguishers having a plurality of extinguishers, each of which is capable of deflecting one or more electron beamlets 7. The extinguisher is an electrostatic deflector that is more specifically provided with first and second electrodes, and the second electrode is a ground or common electrode. The beamlet blanker array 9 and the beam stop array 10 constitute a modulation device. Based on the beamlet control data, the modulation mechanism 8 adds the pattern to the electron beamlet 7. The pattern will be projected onto the target 24 by means of components present within the end module 22.

In this embodiment, the beam stop array 10 includes an array of apertures for allowing small beam to pass. The beam stop array comprises, in its basic form, a substrate that provides through holes, typically circular holes, although other shapes may be used. In one embodiment, the substrate of the beam stop array 10 is formed from a germanium wafer having regularly spaced arrays of vias and may be coated with a surface layer of metal to prevent surface charging. In one embodiment, the metal is a type that does not form a natural oxide skin layer, such as: CrMo.

In one embodiment, the vias of the beam stop array 10 are aligned in the apertures in the beamlet blanker array 9. The beamlet extinguisher array 9 is operated with the beamlet array 10 to block the beamlets 7 or pass the beamlets 7. If the beamlet blanker array 9 deflects the beamlets, it will not pass through the corresponding apertures in the beamlet array 10, but will be blocked by the substrate of the beamlet blocking array 10. However, if the beamlet blanker array 9 does not deflect the beamlets, it will pass through the corresponding apertures in the beamlet array 10 and will then be projected as the spot on the target surface 13 of the target 24.

The lithography system further includes a data path for supplying beamlet control data to the beamlet blanker array. The fiber optic can be used to transmit the beamlet control data. The modulated beam from each fiber end is projected onto the photosensitive element of the beamlet blanker array 9. Each beam holds partial pattern data for controlling one or more modulators coupled to the photosensitive element.

Subsequently, the electron beamlet 7 enters the end module. Hereinafter, the term "small beam" refers to a small beam that has been modulated. This type of modulation beamlet is a part of the sequence that effectively contains the time mode. Some of these sequential portions may have a lower intensity and preferably have a zero intensity, i.e., stop at the portion of the beam stop. In order to allow the beamlet to be positioned to the starting position for the subsequent scan cycle, some portions will have zero intensity.

The end module 22 is preferably constructed as an insertable, replaceable unit that includes a variety of components. In this embodiment, the end module includes a beam stop array 10, a scan deflector array 11, and a projection lens configuration 12, although not all of them must be included in the end module and they may be different Mode configuration.

After passing through the beamlet array 10, the modulated beamlets 7 pass through the scanning deflector array 11, which provides the respective beamlets 7 in the X- and/or Y-direction (substantially perpendicular to the undeflected beamlets 7) Deflection. In this embodiment, the deflector array 11 scans the electrostatic deflector, which enables a relatively small drive voltage to be applied, as will be explained below.

The beamlets are then passed through the projection lens arrangement 12 and projected onto the target surface 24 of the target (typically a wafer) in the target plane. For lithography applications, the target typically includes a wafer that provides a charged particle sensitive layer or a resist layer. The projection lens arrangement 12 focuses the beamlets, preferably to a geometric spot size having a diameter of between about 10 and 30 nanometers. Projection lens configuration 12 of such design preferably provides a reduction of about 100 to 500 times. In the preferred embodiment, the projection lens arrangement 12 is advantageously positioned proximate to the target surface.

In some embodiments, the beam protector can be positioned between the target surface 24 and the focused projection lens configuration 12. The beam protector can be a foil or plate that provides the necessary porosity for the resist particles released from the wafer to be absorbed before it can reach any sensitive elements in the lithography system. Alternatively or in addition, scan deflection array 11 may be provided between projection lens configuration 12 and target surface 24.

In summary, the projection lens arrangement 12 focuses the beamlet 7 to the target surface 24. In addition, it is further ensured that the spot size of a single pixel is correct. Scanning deflector 11 deflects beamlet 7 throughout target surface 24. In addition, it must be ensured that the pixel position on the target surface 24 is correct on the micro scale. In particular, the operation of the scanning deflector 11 must ensure that the pixels are properly matched to the pixel grid, which is ultimately the pattern that is formed on the target surface 24. It will be appreciated that the micro-scale positioning of the pixels on the target surface is suitable for enabling the wafer positioning system underneath the target 24.

High quality projection of this type is related to get a lithography system that provides reproducible results. Typically, target surface 24 contains a resist film on top of the substrate. A portion of the resist film will be chemically modified by the application of a small beam of charged particles (ie, electrons). As a result, the irradiated portion of the film will be somewhat soluble in the developer, resulting in a resist pattern on the wafer. The resist pattern on the wafer can then be transferred to the underlying layer, i.e., by performing etching and/or deposition steps as is conventional in semiconductor fabrication techniques. Obviously, if the illumination is not uniform, the resist may not be developed in a uniform manner, resulting in errors in the pattern. Moreover, many such lithography systems utilize a plurality of small bundles. The deflection step should not cause any difference in the illumination.

In one embodiment of such an optical system, a space is reserved between the first and second groups of beamlets 7 from adjacent beamlets 20. Further, the system is defined to include a beam region 51 and a non-beam region 52, as shown in FIG. The division into the beam region 51 and the non-beam region 52 is present in the modulation device and in the end module (eg, the projection lens system). A non-beam region 52 can be utilized in a projection lens system for providing a mechanical support structure to minimize any vibration effects. The space corresponding to the non-beam region 52 may be filled, for example, the predetermined pattern is a space that is transferred to the target in a subsequent step of the transfer process. This subsequent step is performed after moving the target relative to the column. The specific order in which the space is filled is also referred to as the write strategy.

The invention has been described in relation to certain embodiments discussed above. It should be noted that various structures and alternatives have been described which may be used in conjunction with any of the embodiments described herein, as will be apparent to those skilled in the art. In addition, it is to be understood that the embodiments are susceptible to various modifications and alternative forms that are well known to those skilled in the art without departing from the spirit and scope of the invention. It is to be understood that the specific embodiments have been described, and are not intended to limit the scope of the invention, which is defined in the scope of the appended claims.

1. . . Photolithography system

3. . . Electronic source

4. . . Electron beam

5. . . Collimator lens

6. . . Pore array

6A. . . Pore array

6B. . . Pore array

7. . . Small bunch

9. . . Beamlet extinguisher array

10. . . Beam array

20. . . Sub bundle

twenty one. . . Concentrating lens array

twenty two. . . End module

twenty four. . . aims

51. . . Beam area

52. . . Non-beam area

100. . . Charged particle lithography system

101. . . Wafer positioning system

102. . . Electro-optical column

103. . . Data pathway

104. . . aims

110. . . Charged particle source

111. . . Pore array

112. . . Concentrating lens array

113. . . Collimator lens system

114. . . XY deflector array

115. . . Second pore array

116. . . Second concentrating lens array

117. . . Beam extinguisher array

118. . . Beam array

119. . . Beam deflector array

120. . . Projection lens array

130. . . Electron beam

131, 132, 133. . . Small bunch

140‧‧‧Pretreatment unit

143‧‧‧Electro-optical conversion device

145‧‧‧ fiber optic

146‧‧‧ Beam

147‧‧‧ lens

148‧‧‧Mirror

149‧‧‧ photoelectric conversion device

Various aspects of the invention and some examples of embodiments of the invention are illustrated in the drawings, in which:

Figure 1 is a conceptual diagram showing a maskless lithography system;

2A is a simplified schematic diagram of an embodiment of a charged particle lithography system;

Figure 2B is a simplified diagram of the elements in the data path;

Figures 3 and 4 show a portion of the beamlet blanker array;

Figure 5 is a diagram showing the writing direction on a wafer divided into fields;

Figure 6 is a diagram showing a scan line bit frame and beamlet deflection;

Figure 7 is a diagram illustrating an example of pattern offset and pattern scaling;

Figure 8 is a diagram showing an example of a possible interleaving scheme for writing a strip using four beamlets;

Figure 9 is a simplified illustration of a four beamlet extinguisher array and scan line pattern;

Figure 10 is a table for values of the factor K and the distance between scan lines;

Figure 11 is an illustration of nine small beam arrays showing beam spacing P _b , projection pitch P _proj , grid width W _proj , and tilt angle α _array ;

Figure 12 is a diagram of a frame start indicator bit;

Figure 13 is a schematic diagram of a node having X processing units;

Figure 14 is a conceptual diagram of the position of the channel for each scan;

Figures 15 and 16 are conceptual diagrams of the allocation of channels to two scanned processing units;

17 to 23 are graphs illustrating simulation experiment results of varying the data path capacity with respect to lithography machine capacity;

Figure 24 is a flow chart showing the dependence of processing in a lithography system;

25 and 26 are diagrams illustrating an example of x and y pattern shifting;

Figure 27 is a table of typical parameters and ranges for different types of corrections;

Figure 28 is a simplified functional block diagram of the data path;

Figure 29 is a diagram of a layout pattern feature superimposed on a strip;

Figure 30 is a legend of a dithering process;

Figure 31 is a legend of a bit shift in a bit box;

Figure 32 is a legend of beamlet positions for parameters N = 4 and K = 3;

Figure 33 is a schematic block diagram showing data processing and storage elements of a data path;

Figure 34 is a functional block diagram of a second embodiment of the data path;

Figure 35 is a flow chart showing the dependence of the processing of the data path of Figure 34;

Figure 36 is a block diagram of elements of a pattern streamer node;

Figure 37 is a functional diagram showing the flow of data between elements of the graph type stream node of Figure 36;

Figure 38 is a block diagram showing details of processing and transmission elements of a data path;

39 is a functional block diagram of a portion of a data path including compression and decompression functions;

Figure 40 illustrates an example of a dithered monochrome test image;

41 is a functional block diagram of a portion of a data path including compression and decompression functions after channel hopping;

Figure 42 shows an example of a truncated bit map of a cell;

43 is a conceptual diagram of a small grid input pixel and a large output pixel;

Figure 44 is a functional block diagram of another embodiment of a data path;

Figure 45 is a flow chart showing the dependence of the processing of the data path of Figure 44;

Figure 46 is a block diagram of elements of a pattern streamer node;

47 and 48 are functional diagrams showing alternative data streams between elements of the pattern streamer node of FIG. 46;

Figure 49 is a schematic diagram showing communication between elements of a data path;

Figure 50 is a functional diagram showing an alternate data flow between elements of a graphics streamer node;

51 is an illustration of an internal architecture of a GPU for a data path;

Figure 52 is a functional diagram showing an alternate data flow between elements of a graphics streamer node;

Figure 53 is a functional block diagram of another embodiment of a data path;

Figure 54 is a block diagram showing details of processing and transmission elements of a data path;

Figure 55 is a schematic illustration of a data path with interleaved/multiplexed subchannels;

Figure 56 is a schematic diagram of a demultiplexing scheme using a column selector and a row selector;

57 is a table of pixel size and grid width, depending on the number of beamlets (N _{pat_beams} ), array tilt angle (α _array ), projection pitch (P _proj ), and K factor of each pattern bundle;

Figure 58A is a diagram illustrating a smart boundary strategy;

Figure 58B is a diagram illustrating a soft edge strategy;

59 is a functional flow diagram of an embodiment of a data path using offline rasterization;

60 is a functional flow diagram of an embodiment of a data path using in-line rasterization;

61 is a functional flow diagram of another embodiment of a data path using inline rasterization;

62 is a functional flow diagram of an embodiment of a data path using instant rasterization;

Figure 63 is a diagram illustrating an array of four beamlets;

Figure 64 is a diagram illustrating a stitching scheme;

Figure 65 is a diagram illustrating a write strategy having factors K = 1 and K = 3;

Figure 66 is a legend of possible K values for a pattern bundle with 4 small bundles;

Figure 67 is a diagram illustrating an example of a pattern layout;

Figure 68 is a diagram illustrating the concept of an edge;

Figure 69 is a diagram illustrating the orientation of a vector;

Figure 70 is a diagram illustrating the encoding of a square feature;

Figure 71 is a diagram illustrating the encoding of a complex feature shape;

Figure 72 is a diagram illustrating an example of a minimum feature spacing of diagonal lengths less than one grid;

Figure 73 is a diagram illustrating an example of a feature having a serif attached to some of its edges;

74 is a simplified schematic diagram showing an embodiment of a plurality of small beam lithography systems with charged particles;

Fig. 75 is a diagram showing an example of division into a bundle region and a non-beam region.

Claims (14)

A charged particle lithography system for exposing a wafer according to pattern data, the system comprising: an electron optical column for generating a plurality of electron beamlets for exposing the wafer, the electron optical column comprising a beamlet extinguisher array for turning on or off the beamlet; a data path for transmitting beamlet control data for switching control of the beamlet; and a wafer positioning system for the wafer Moving under the electron optical column in a mechanical movement direction, supplying the wafer positioning system with a synchronization signal from the data path to align the wafer having an electron beam from the electron optical column; wherein the data path comprises One or more processing units for generating the beamlet control data and one or more transmission channels for transmitting the beamlet control data to the beamlet blanker array. The system of claim 1, wherein the transmission system comprises a plurality of transmission channels, each of the transmission channels being for transmitting data corresponding to the beamlet group. The system of claim 1 or 2, wherein the beamlets are arranged in a plurality of groups, and wherein each of the transmission channels is a beamlet control for transmitting one of the beamlet groups data. The system of claim 3, wherein the data path comprises a plurality of multiplexers, each multiplexer being small beam control data for multiplexing a small bundle group. For example, the system of claim 4, further comprising: a plurality of demultiplexers, each of which is a small bundle control data for demultiplexing a small bundle group. The system of claim 1, wherein the data path comprises an electrical to optical conversion device for converting beamlet control data generated by the processing units into an optical signal for transmission to the charged particle lithography machine . The system of claim 6 wherein the transmission channels comprise optical fibers for directing the optical signal. A system of claim 6 wherein the beamlet blanker array comprises an optical to electrical conversion device for receiving the optical signal and converting it to an electrical signal for control of the beamlets. The system of claim 1, wherein the beamlets are arranged in a plurality of groups, and wherein each processing unit is for generating beamlet control data for any one of the beamlet groups, and each of the transmission channels It is dedicated to transmitting beamlet control data for one of the beamlet groups. The system of claim 9, wherein the charged particle lithography system allocates a first subset of the beamlets for exposing the first portion of the wafer and for exposing the second portion of the wafer a second subset of the beamlets; and wherein the cross-connect switch connects the processing units to a first subset of the transmission channels corresponding to the first portion of the scan for the wafer a first subset of bundles, and the cross-connect switch connects the processing units to a second subset of the transmission channels corresponding to the wafer The second portion scans the second subset of the beamlets. The system of claim 1, wherein the lithography system is adapted to expose the wafer by two scans, wherein the first portion of the wafer is exposed according to the first pattern data and then the wafer is The two parts are exposed according to the second pattern data; and wherein the processing units comprise a memory, the memory is divided into a first memory portion for storing the first pattern data and for storing the second a second memory portion of the pattern data; and wherein the first portion of the wafer in the next batch of wafers is loaded during the second partial exposure of one of the wafers of the current batch of wafers Type data to the first memory portion. A method for exposing a wafer in a charged particle lithography system, wherein the charged particle lithography system is a system according to claim 1 of the patent application, the method comprising: actuating the charged particle lithography system The electron optical column to generate a plurality of charged particle beamlets, the beamlets being arranged in groups, each group comprising a beamlet array; the wafer positioning system controlled in the charged particle lithography system, The wafer moves under the beamlets in a mechanical movement direction at a wafer scanning speed; the beamlets are deflected at a deflection scanning speed in a deflection direction substantially perpendicular to the mechanical movement direction; and relative to the deflection scanning speed The wafer scanning speed is adjusted to adjust the dose given to the wafer by the beamlets. The method of claim 12, wherein the method comprises: wherein the beamlets are deflected such that each beamlet exposes a plurality of scan lines on the wafer; and wherein each beamlet array has an array in the array spacing between the small bundles is projected to the machine direction of the P _proj, and equal to the projection pitch P _proj distance multiplied by the number of groups of beamlets in the array; and wherein in each scan between the small bundles such The relative movement between the wafers in the direction of mechanical movement is equal to the group distance divided by the integer K. The method of claim 13, wherein K satisfies the requirement that K is the largest common denominator of the number of beamlets in each array.