TW201123254A - Cell based vector format - Google Patents

Abstract

A method for defining features for writing on a target using a lithography process. The method comprises defining an array of cells, the features occupying one or more of the cells, and describing for each cell any corners of the features that fall within the cell. The corner may be described by a corner position, a first vector, and a second vector, the two vectors originating from the position.

Description

201123254 y VI. Description of the Invention: [Technical Field] The present invention relates to maskless charged particle lithography, especially regarding data paths, methods for implementing corrections, and scanning methods for such devices β [Prior Art] The design for an integrated circuit is typically represented by a computer readable file. The GDS-II file format (the gds standard for graphic data signals) is the database broadcast format 'which is the lithography industry standard for integrated circuit or 1 (: layout of the original image data exchange. For masks A lithography machine, typically using a GDS-Π file to create a mask or a set of masks that are then used by the lithography machine. For unshaded lithography machines, the GDS_n standard is electronically processed to make it Suitable for controlling the format of lithography machines. For charged particle micro~machine GDS-II files is converted into a set of control signals for controlling the charged particle beam used in the lithography process. The preprocessing unit can be used to process GDS. - Π file to generate intermediate data for the current lithography system. Depending on the architecture options, this intermediate data is in a bitmap format or a vector 的 region description. The current lithography system is used Intermediate data uses a large number of electron beams to write patterns into the wafer. The architecture of the data path must be broadly defined to implement all the features needed to scale up to the same valley at the lowest cost. The data path characteristics required for a global high volume machine contain modifications of the different types required for tool calibration and process variation 201123254. [Invention] The present invention is described in the accompanying patent application. A method of defining a feature that uses lithography to write to a target. The method includes defining a feature that occupies one or more of .ιν „ > β, etc., and, for each cell, describing its genus; Any angularity of the feature, , belongs to. The sinuous angle can be described by the angular position, the first s1 and the second vector, and the two are from the position. The ridge is described by the rib. The coordinates and/or are described by a right-angled bit code. The square direction in which the direction of the vector can be specified::I is deprecated as being moved from the first vector in a predetermined direction to the second::: The area defined by the vector and the boundary of the grid, the predetermined direction is blocked as in the clockwise direction. The virtual edge and the gentleman. The crescent moon r belongs to a part of it without having any corners in the grid... "Characteristics of hard angles Place Definition. Virtual corners can be described by the first and second vectors whose orientation is 180 degrees to each other. The boundary quantity can be selected to have only parallel to the grid boundary or perpendicular to the grid ===/ or only have parallel to the grid boundary, vertical The grid boundary, or the direction of the grid boundary is μ degrees. The minimum feature spacing can be defined, and 哒笙, ^^, etc. can have a size equal to or less than the minimum feature spacing. The grid can have -fc- -to inches For a + square root equal to or less than 2, multiply the minimum feature spacing by one - » , ^ ^ ^ . The minimum feature spacing is the square root of the size of the size 4 or greater (four). The 201123254 bit is 45 for the grid boundary. Some features of the edge of the degree can be defined, ο 特征 的 的 的 的 或 心 心 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小 最小. The maximum number of corners can be defined for each cell. Each of the features may be one or more features and/or one or more features H 4 (4) to contain pattern data for a portion of the field of the wafer, or pattern data for the field strip of the wafer. ^ Another point of view 'The present invention includes a method for processing a graph of f for a lithography method'. The method includes: providing graph data in a vector format; changing the flanking data; , , , A iw , Generating pattern data in a grid-based format; rasterizing the 4 grid-based pattern data to generate first-order pattern data for the lithography method. The grid-based pattern data may include grid data describing features of the grid or array of grids that occupy the grid, and the grid data describes any of the corners of the features within the grid for each grid. Rasterizing the grid-based pattern data can be performed in an instant process when the lithography method is implemented. Rasterizing the grid-based pattern data can include: translating the grid-based pattern data to generate multi-level pattern data; and, dithering the multi-level pattern data to generate the first-order pattern data. In yet another aspect, the present invention provides a method for exposing a wafer based on pattern data using a charged particle lithography machine that produces a plurality of charged particle beamlets to expose the wafer, the method comprising: Providing pattern data in a vector format; transforming the vector pattern data to generate pattern data in a grid-based format; rasterizing the grid-based pattern data to generate second-order pattern data; and encoding the second-order pattern data string Flowing to the beamlet extinguisher array to turn on and off the beamlets generated by the charged particle lithography machine; and I Si 5 201123254 and, based on the second-order pattern number, turn the beamlets on and off . The lattice-based pattern number may include lattice data describing characteristics of one or more of its occupied grid arrays, the lattice data describing any angularity of the features within the grid for each of the cells. Rasterizing the grid-based pattern data can be performed with immediate processing while the lithography machine is exposing the wafer. Rasterizing the grid-based pattern data may include: translating the grid-based pattern data to generate multi-level pattern data; and, dithering the multi-level pattern data to generate the second-order pattern data . [Embodiment] Hereinafter, a charged particle lithography system of various embodiments of the present invention will be described by way of example only and with reference to the drawings. FIG. 1 is a conceptual diagram showing a charged particle lithography system, and the system 100 is divided into three. High-order subsystems: wafer positioning system 1〇, electron optical column (10), and data path 1G3. Wafer positioning (4) 1 () 1 moves the wafer below the electron optical column 102 in the x direction. The wafer positioning system 101 is supplied. The synchronization signal from data path 103 is used to align the wafer with the electron beamlets produced by electro-optical column 102. Figure 2A shows a simplified illustration of an embodiment of a charged particle lithography system showing the electron optical column 1() 2 detail. For example, such a lithography system is described in U.S. Patent No. 6,897,458, No. 7, Zheng, No. 7, No. 19,908, No. 7, No. 84, 414, and No. 7,129, No. 2, U.S. Patent The application announcement No. 2〇〇7/〇〇64213 and the joint application of the US 201123254 national patent application No. 61/03 1,573, 61/031,594, 61/045,243, 61 U.S. Patent Nos. 5,054, issued toK.S. Pat. In the embodiment illustrated in Figure 2A, the lithography system includes a charged particle source 110, such as an electron source for generating an extended electron beam 13A. The extended electron beam 130 impinges on the aperture array 丨丨丨, which blocks a portion of the beam to produce a plurality of beamlets 13 1 . The system produces a plurality of small bundles, preferably in the range of about 丨〇, 〇〇〇 to 1,000,000 small bundles. The electron beamlet 131 passes through a concentrating lens array 112 that focuses the electron beamlets 131. The beamlet 13 1 is collimated by the collimator lens system 丨13. The collimated electron beamlets pass through the XY deflector array 丨14, the second aperture array U5, and the small beam 132 caused by the second concentrating lens array 116〇, then pass through a beamer array i丨7, which includes a plurality A extinguisher to deflect one or more of the beamlets. The beamlets pass through the mirror 148 and arrive at a beam stop array 118 having a plurality of apertures. The beamlet blanker array 117 operates in conjunction with the beam stop array ι 8 to turn the beamlets on or off by blocking or passing the beamlets. The beamlet blanker array 117 can deflect the beamlets such that they will not pass through the corresponding apertures in the beam stop array 118 <RTIgt; If the beamlet extinguisher array "17 does not deflect the beamlets, it will pass through the corresponding apertures in the beam stop array 118. The undeflected beamlets pass through the beam pupil array and pass through the beam deflector array 119 and the projection lens array 12A. The beam deflector array 19 provides deflection of each beamlet 133 in the 乂 and/or gamma directions (substantially perpendicular to the direction of the undeflected beamlets) to scan the beamlets throughout the surface of the 201123254 target 104. This deflection is different from the deflection used by the beam blanker array to turn the beam off or off. Next, the small pupil 133 passes through the projection lens array 12G and is projected onto the target 1G4. The projection lens configuration preferably provides a reduction of about 100 to 500 times. The beam 133 strikes the surface of the target ι 4, and the target 104 is placed on the movable stage of the wafer positioning system. For lithography applications, the target typically includes wafers that provide a charged particle sensitive layer or a resist layer. The representative diagram shown in Fig. 2A is extremely simplified. In the preferred embodiment, a single electron beam is first split into a plurality of smaller beamlets, which are then divided into more beamlets. Such a system is described in U.S. Patent Application Serial No. 61/045,243, the entire disclosure of which is incorporated herein by reference. In this system, each sub-beam is divided into several small beams, which can be regarded as a pattern bundle. In one embodiment, each beamlet is divided into 49 beamlets arranged in a 7χ7 array. The beamlet blanker array preferably includes a hole having associated extinguisher electrodes for each beamlet to enable on/off switching of individual individual beamlets. Figures 3 and 4 show a portion of the beamlet blanker array, with each of the pattern bundles having nine beamlets, the beamlets of each group being arranged in a 3χ3 array. The beamlet arrangement and the writing strategy in the pattern bundle are described, for example, in U.S. Patent Application Serial No. 61/58,596, the entire disclosure of which is incorporated herein by reference. The beam deflector array and the projection lens array preferably comprise only one aperture and lens for each pattern bundle (e.g., a small aperture or lens for each of the 49 small bundles forming a pattern bundle). A small bundle is typically combined (interleaved/multiplexed) in a group in which it is written into a single stripe. 201123254 Data Path Architecture A simplified block diagram of one embodiment of data path 103 is shown in Figure 2B, and a portion of the data path also appears in Figure 2a. The switching of the small beam extinguisher array Π7 is controlled via the data path. Pre-processing unit 140 receives information describing the layout of the device to be fabricated by the lithography machine. This information is typically provided in the GDS-II file format. The pre-processing unit performs a series of transformations of the GDS-II file to generate an on/off control signal to control the beamletter array 11 7 . The control signal is transmitted to an electro-optical conversion device 143 (such as a laser diode) to convert the electrical control signal into an optical signal. The optical control signal is directed through fiber 145. The beam 146 at the output of the fiber is directed through the lens 147 of the array onto the apertured mirror 148. From the mirror, the beam is reflected onto the bottom side of the beam extinguisher array 117. The individual beams are directed to a plurality of photoelectric conversion devices (e.g., photodiodes) directed to the bottom side of the beam extinguisher array 117. Preferably, the beamlet extinguisher array has a photodiode "photodiode" operation for each fiber 145 to actuate individual beam extinguisher electrodes to control the deflection of the beamlets 13 2 to separate individual beamlets Switch on or off. The control signal for controlling the individual beamlet totalizer electrodes is preferably multiplexed such that each beam 146 carries a control signal for a channel that includes a plurality of small fibers that share a single fiber and photodiode. bundle. The multiplexer diaphragm is received by the photodiode and converted into an electrical signal. The beamlet blanker array 117 includes logic operations for demultiplexing the control signals received by the photodiodes to derive control signals for individually controlling the electrodes of the plurality of beamlet blankers 201123254. In a preferred embodiment, the individual control signals for the 49 beamlets used to control a pattern beam are time multiplexed for use on a single fiber as a single photodiode on the beamlet annihilator array. Receiver In addition to multiplex, the beamlet control signal can also be configured for transmission in a fume configuration and can have synchronization bits and additional coding to improve transmission, for example: using coding techniques to achieve frequent signal transitions, preventing The coupling method uses a laser diode and a photodiode. By forcing the transition, ^ is automatically distributed over the optical signal. Figure 12 shows an example of a beamlet control signal with 49 small bundles of frames (of a pattern bundle), synchronization bits, and multiplexing. Control bit. At a closer proximity to the wafer, a beam deflector array ι 9 is used to deflect the electron beam in the y-direction (and a small amount of deflection in the direction) to achieve electron beam scanning across the surface of the wafer. In the illustrated embodiment, the wafer ι 4 is mechanically tangentially oriented by the sweet circular positioning system 1 〇 1 and the electron beam is scanned throughout the wafer in a y-direction substantially perpendicular to the X-direction. When writing data, the : beam is slowly deflected in the y direction (compared to the return ship = beam is the car quickly moving back to the yr_ start position (this is called = beam deflector array 119 receives timing and synchronization from the digital signal.) The small amount == can be divided into several channels. The channel is from the pre-processing unit to the gas to the optical converter (for example: in the laser diode case, the channel contains the individual money and the optical to the t4# beam control (four) This is the channel to transmit the control signal for a single pattern bundle. The single pattern bundle contains several individual beamlets (for example, 49 small cells that make up a pattern beam). A pattern bundle can be used to write a single strip on the wafer. In this configuration, the channel represents a data path component that is dedicated to control the inclusion of multiple beamlets (eg, 49 beamlets) A pattern bundle and carrying a beamlet control signal to write a strip based on the pattern data. The subchannel represents a data path component that is dedicated to control a single beamlet within the pattern bundle. Data path 101 transforms the layout data into The on/off signal of the control electron beamlet. As described above, this transformation can be performed at the pre-processing unit 140, and the pre-geographic unit 140 performs a series of transformations on the layout data, typically in the form of a GDUJ or similar file. This processing typically includes: flattening/preprocessing, rasterization, and multiplexing steps. The flattening/preprocessing step transforms the layout data format into a dose map. The dose mapping is in vector format. The associated dose rate value is used to describe the area on the wafer. This step may include some pre-processing such as proximity effect correction. Because of the complexity of the pre-processing, this step is preferably performed offline. The thumb-up step transforms the dose mapping It becomes the control (on/off) signal of the stream. The multiplex step is to package the beamlet control signal according to the multiplex scheme. The half-field can be used to write the wafer in the lithography machine..._日日日万万沄 It can be roughly described in the order of the following steps. Wafer 1〇4 is from An Meng*曰ffi” 疋 哀 哀 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在, The J is calibrated. The wafer is mechanically aligned and calculated according to the alignment (offset) of the field. The wafer is moved by the station in the +x direction and the column is open and mad. The first % field is written. When the beamlet is extinguished, the hole in the leading column of the 201123254 array is passed through a field boundary, and the offset correction is set for the next field. Therefore, when the first field is In order to still write, the lithography system will start writing to the next field. After the force passes through the last field in a column, 'the station will be moved to locate the field below the wafer-on-row. Below the small beam extinguisher array. When the station moves in the x direction, a new run will begin. The scan deflection direction is preferably unchanged. Correcting the data processing performed by the data path provides a small beam control signal. - Some different adjustments to make corrections and compensations for various types. For example, such corrections and compensations may include proximity corrections and anti-(four) heating corrections to compensate for the effects that occur as a result of using resist properties. Data adjustments may also include modifications designed to compensate for errors or failures that occur in the lithography machine. In the preferred embodiment of the charged particle lithography machine II, the lithography machine does not have any built-in facilities for adjusting individual electron beamlets to correct for errors in beam position, size, current, or other characteristics of the beam. Missing is misalignment or failure such as small beam, low or high beam current, and incorrect deflection of beamlets. Such a deficiency may be the result of defects or tolerance changes in the manufacture of the lithographic machine, the blocking of small bundles or the turning off of dirt or dust that is charged and deflected, the failure or degradation in machine components, and the like. The lithography machine omits the correcting lens or circuit for making individual corrections to the J-beam' to avoid the additional complexity and cost involved in incorporating additional components into the electron beam to make the actual beam correction, and avoiding the inclusion of such Additional components require an increase in the size of the column. However, the modulation of the beamlet control signals and/or the additional scanning of the wafer 12 201123254 can compensate for these types of problems. Failures in the data path can also be corrected by the modulation of the control signal and with rescanning of the wafer. The various methods used to make these modifications are described below. Redundant scanning The charged particles of the work ^ 夕 ..... % 佩 个 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的It is highly probable that failures may occur in some of these components or that 2 such components will deteriorate or be affected by contaminants so that they are not implemented within specifications. In order to maximize the time between system maintenance, periodic checks can be made to identify failed or substandard beamlets or data channels. This check is performed before each wafer scan, before each first scan of the wafer, or at a convenient time. The inspection may include one or more examples of 'including the U.S. Patent Application Serial No. 61/122,591, the entire disclosure of which is incorporated herein by reference. The failure of the main target, ,, due to the replacement of the failed part in the column, 'can use redundant scanning to deal with the failure in the data path, the failed fiber or laser in the channel ^ The channel was cut during the scan and corrected using the strip of the person written by the other channel's remaining failed channel. It is written that the strip that is to be exposed by the bundle is unwritten in the small bundle that is invalid or out of specification. ‘================================================================================ In a pattern beamlet system such as that described above, the complete channel including the failed or out-of-spec beamlets can be severed and will not be written to the full strip of the wafer field to be exposed by the beamlets of the channel. band. After the first scan of the entire circle is performed, a redundant scan can then be performed to fill the missing strips (and any other missing strips for other channels with failed beamlets). For redundant scans, the wafer is returned to the starting position after the first scan and is shifted to ensure that the appropriate active channel is where it can be used to write the missing strip. The pattern data for the redundant scan is preferably prepared in the lithography system during the first scan, so that the redundant scan can begin as soon as the first scan is completed. Preferably, there is no significant delay between the end of the first scan and the beginning of the redundant scan, so that the data for the redundant scan is preferably fast available on the appropriate node. The lithography machine is preferably capable of writing a continuous in-line (m-Iine) field in one scan and writing in two directions parallel to the chirp direction of the mechanical scan (ie, -X and +χ directions). . The machine also preferably includes a spare bundle (or pattern bundle)' which is typically located at the edge of the column.曰 In order to write a missing strip during the redundant scan by the appropriate active channel, the off-four column can be shifted (offset) in the y-direction and/or the χ direction by an amount corresponding to the number until the channel with the appropriate effect beamlet To locate the position to write the missing strip. This is preferably achieved by mechanical offset of the wafer on the stage. In order to better handle the failure of one channel after all kinds of errors, it may be necessary to sneak a dream, which requires a shift for the first and second scans. Multiple scans 201123254 In multiple scans, in the examples, m, soil can also use the small beam and the small beam scanning effect in the -a & In many times...! The first scan of the _ Ap Yasuda day circle that still achieves the redundant strip is the write field rt. The second scan is the rest of the write strip, causing the scan or four scans, etc., to extend this principle to The total time and reduction of the three exposures is used to scan the circle to be 1 compared to b 4 . Therefore, the secondary scan or the two rate is = scan and redundant scan is possible because the small beam failure type is low. The beam measurement can be performed before the first scan to (4) the failure, and the small beam without the σ specification. Using this binning, you can calculate the first and second knowledge, which will cause it to be specified in the redundant scan of the wafer scanned by the small beam, preferably, when it fails or does not meet the specifications? At the time of the test, cut off the entire channel including the beamlet and use another 1 乍 = (all beamlets that meet the specifications) to write the strips that will be written by the failed channel. A variety of algorithms can be used to calculate the channels to be used for the first and second scans and the wafers (four) required for each scan, causing all strips to be written by the active channel. For the second scan, the algorithm is to find a G-segmented channel between the various scans of the (four) channel. A brute force can be used to test various channel assignments and wafer offsets to find the right combination' or a more complex matching algorithm can be used. Therefore, the total exposure current for the wafer is distributed between two (or more) scans. In multiple scans, a second scan (or a third scan) can be used

S 15 201123254 = fourth scan, etc.) to scan the strips in the first sweep channel, as in redundant scans. There is no any loss: = effect 】 When the beam is bundled, it can also be made into multiple scans. The advantage of dividing the current into two or more fields is that the instantaneous heating of the wafer = the total beam current of each scan is reduced, and each scan = is dispersed over multiple sweeps for the same 'total heat load'

Causes less local or instantaneous heat negative I ❹ more cuts to reduce the demand capacity in (four) way. The data transmission capacity of the ::circle using the secondary scan' data path is theoretically halved because each scan requires only half of the amount of small beam control data. Yes: it is significant for the inter-connected cost of the huge data transmission capacity required for the data path. For the above embodiment, each pattern bundle of one channel has 49 transmission capacities of 4 and two: Machines with about 6 people and 83,000 pattern bundles (49 bundles for each pattern bundle) will require a channel of 4 coffee/... capacity, thus 'significantly reducing the need for data paths. The current industry standard for writing strategies is 300mm wafers. Wafers are divided into fixed sizes (4) 'The largest scale is 26mm x 33mm. Each field can be processed = multiple 1Cs are generated (ie: layout for multiple wafers) Can be written to a single field) and 1C does not cross the field boundary. The maximum size of 26mmx33mm has a total of 63 fields available on a single standard wafer. The smaller field is Probably = will cause each wafer to be more than one field. 5 shows that it is divided into a field circle and the direction of the write field. The field is in the rectangular area 201123254 on the wafer, typically with a maximum of 26mmx33mtn Size. The ODS-II file describes the field. It is also possible to write a partial (incomplete) field, for example, by writing the full field as a partial field and across the wafer boundary. In a preferred embodiment of the lithography machine, the machine generates 丨3, a sub beam and each sub-beam is divided into 49 small beams, resulting in 637, a small beam (ie: 〇χ 49). The beamlet annihilator array contains 13' in the 26x26mm area光电 a photodiode with 637, _ holes. Each photodiode in the beamlet extinguisher array receives a multiplex control signal for the control of 49 (7x7) extinguisher holes/beamlets. A distance of 26 mm from 26 mm causes a strip of 2 μιη width in the y direction (perpendicular to the mechanical scan) and is as long as the field in the x direction. 49 small bundles of each subbeam are written into a single strip. The circle is preferably written by the lithography machine in the reverse and forward direction of the ( (10) light ^ by the deflection II) in the y direction of the writing direction is expected to be in the __ direction. The field size (height) is Choose to be smaller than the size of the electron · optics (E〇=r〇n_°Ptieal) crack (ie · as small as projected onto the wafer) The size of the beam's two = X is less than the maximum size of 26 mm, for example, multiple = two are placed on the wafer, but not all of the electron beamlets will be used for reduction. 9 will... Output When the machine is writing the pattern to the field extinguisher array into the next p-, and instantaneously, the small bundle J into the next % field and start writing the pattern should be able to write to both fields simultaneously If the machine is on the machine - can write to three fields at the same time. ... machine @ Μ The simplified form of the beam reducer array is shown in Figure 3 and 4 s] 17 201123254 of which only 16 Dipoles, each receiving a multiplex control signal for the control of 9 (3 χ 3) annihilation holes/beamlets. An associated extinguisher and extinguisher electrode can be used to block or pass a small beam (or electron beam). The small beam passing through the quencher hole will be written to the resist on the wafer surface. The configuration of the 'extinguilder hole' in Figure 3 is shown for the parallel projection write strategy; and in Figure 4+, this is for the vertical write strategy. In Fig. 4, the (four) apertures for the beamlets are distributed over the entire strip width: i.e., each beamlet and adjacent beamlets are equidistantly positioned in a direction perpendicular to the write (scan) direction. This is possible, but for a small number of holes, the efficiency of this configuration will be extremely low in terms of the ratio between the beam and the beam current. One measure of efficiency is the fill factor, which is the ratio of the total area of the extinguisher holes to the area of the group of holes for a pattern bundle. The fill factor is useful for estimating the efficiency of a particular grid geometry with respect to current input (beam current) and current output (total beam current). When the area of the small beam group is small, the fill factor will increase to a better value. The write strategy for a small number of holes is the "parallel projection" write strategy (see: Figure 3) 'where (in its simplest form) individual beamlets are interleaved and the entire strip width is written (as in Figure 8B) Shown). A write strategy of this type is described in U.S. Patent Application Serial No. 61/058,596, the entire disclosure of which is incorporated herein by reference. Deflection signal. The deflection signal includes a scanning phase and a kickback phase, as shown in the schematic of Figure 。. During the scan phase, the deflection signal slowly shifts the beamlet (when 18 201123254 is turned on) in the y direction and the beamlet blanker array turns the beamlet on and off according to the beamlet control signal. After the scanning phase, the kickback phase begins. In the flyback phase (4), the beamlet is cut and the deflection signal moves the beamlet quickly to the position where the next scanning phase will begin. The scan line is the beamlet path on the wafer surface during the scan phase. Without special measures, the scan line will not actually be written to the wafer along the y-direction, but will be slightly skewed to have a small chirp direction component as well, because of the continuous table movement in the X direction. This error can be corrected by adding a small chirp direction component to the deflection field to match the station shift. This correction can be handled at ε〇 = so that the data path does not need to correct this error. & The component of the χ direction is small 'because the stage movement is slower than the y-direction deflection scan speed (the typical relative speed ratio can be 1:1_. However, the effect of this χ direction component is in the pattern bundle The system is greatly improved. First, the deflection speed can be reduced in proportion to the number of beamlets per pattern bundle. Secondly, due to the tilt of the beamlet array (as in the examples of Figures 3, 4 and 9) As shown, the skew of the scan lines on the wafer will cause the distance between the scan lines made by the different beamlets to be changed. A sufficiently large skew may cause the scan lines to overlap or change the position relative to each other. The scan line (see: the right side of Figure 6) is divided into three sections: the beginning of the scan slave, the pattern segment and the end overscan segment. The beamlet is deflected along the y direction. Small: the distance in which the turn is typical It should be written wider than its strip. Space over the position of the write. Overscan: Excessive in the early side. If the strip width is 2pm and the overscan is - (or called, this results in a scan line of 3 Pm Length. The scan line bit box has passed the 201123254 scan segment holding it is not expected The bit of the human pattern (pattern segment bit). The overscan bit value is cut off, but transmitted on the fiber. The pattern segment of the scan line bit box holds the bit describing the rasterized pattern. The bits in this segment are actively turned on and off for writing features. In Figure 6 (left side), the scan line is depicted for the case where only one small beam is written to the strip. The beamlet path during the period is a b_C. AB疋 scan line movement during the scanning phase, but the secret during the beamlet is cut off. The strip boundaries are labeled D and E. On the right side of Figure 6, identification Overscan and pattern segments. The entire set of bits used to switch the beamlet beamlet control signals on the scan line is referred to as the scanline bitframe. During the entire scanline, the beamlets are controlled by the lithography system. In the overscan segment, the beamlet will be cut. In the pattern segment, the beamlet is switched according to the features that need to be written in the field of the wafer, and the scan line is for the overscan segment and the pattern segment. The & meta of the meta box is the data representing the array of small beam extinguishers to be rotated (four). The bits in the overscan segment The meta/pixel seems to be useless and consumes the bandwidth of the data path. However, the bits/pixels in the overscan segment provide space for corrections (such as pattern shifting and pattern scaling), providing stitching calculations. Two of the methods, and when the write strategy is to write the entire strip width (parallel projection) for all beamlets, provides a space for the difference in the position of the beamlets at the extinguisher hole y. The fixed bit rate of the beam control signal and a certain pixel size, the scan line can be mapped into a fixed length bit box, ie: the scan line bit box. In Figure 7, an example of pattern offset and pattern scaling is proposed. The scan line A 疋 'has again offset or scaled vertical scan lines, wherein the write beam 20 201123254 line beamlets are properly aligned and τ is flat and properly deflected to properly expose the desired exposure on the wafer. The scan line 停 and stop ' , ± ^ . The 悚 belt is not optimally aligned, for example: due to small beam misalignment. This can be corrected by ridiculing the error, adjusting the timing of the beamlet switching, and shifting the data in the control # number by one pixel. This can be achieved by shifting the control bits within the scan line bit box. 9 Scan line C is not being determined to match the deflection at the strip boundary d and inside, for example, due to its locality, which is a weaker beam that is weaker than the crucible. Therefore, m controls more than one bit of the signal, while the overscan segment uses less 疋. The pattern written to the strip requires multiple bits for the stripe width. From the viewpoint of the bit frame, the shifting and 疋 = " can be performed only by the resolution of the pixel, and the rasterization method can process the sub-pixel resolution correction (for example, : pixels). Combining the two will allow shifting, such as shifting the beamlets of (1) pixels slightly in the above-described embodiment, each of the early hits of the eight & d Λ valley sub-beams is 49 small bundles and the channel will There are 49 different bundle combinations for the write-in stripe. There are multiple different write strategies for writing strips. The small bundle write strategy is how the L7 ^ ^ ^ ^ beamlet is arranged for writing stripes. The solution can be a combination of stacking, interleaving or overlapping. Xiao 疋 f two-stage financial deflection: scanning and returning. In the sweep (four) paragraph, two bundles /. The person is deflected (when it is on) on its scan line on the wafer. The pattern segment of the Scan = Metaframe will be filled with the bit pattern to expose the desired wafer features. In the figure "Several examples show possible interleaving schemes, the basin uses four small bundles for writing strips. These examples are not instant display of how the beamlet L S. } 21 201123254 writes, but instead shows Which bundle is already written to the strip when the write has been completed. Example A shows stacking the bundles. Each bundle is written to its own sub-strip. For this configuration, the individual bundles are in it. Before the flyback, only a small amount of : yuan is written. The frequency of the deflection signal is high and its amplitude is small. This write strategy applies to the clustering of small bundles to make the group width (the number of small bundles) The technical spacing ppr〇j) is equal to the strip width (vertical projection). A series of writing strategies are applied. For the basic form of vertical projection, all small bundles are written into small sub-bands. The strip width is a small 4 knife width. The size of the quench hole grid is typically related to the strip width. In the example, the beam is interleaved over the entire strip width. Deflection signal = frequency is low Moreover, its amplitude is large. The writing of the matching interleaved scanning line ^^^ Line projection writer strategy. Especially for the "small bundles" in the group - this strategy allows for smaller group sizes and improvements because of the small number of small bundles, the group size on the wafer is because A reasonable fill factor can be calculated to calculate i is oblique to force _ for this write strategy (parallel projection), the beam door distance is two; - a specific number of small bundles in a group and a pair of small π The pixel size + pixel size is not an extra bit in any of the π 兮栺 line positions 以 to compensate for the worst case offset between the beam blanking Μ and the center of the strip. The small bundle is based on the writing strategy of the π series. For parallel projection, all strips have a bandwidth of I. The way to write the entire strip width. The annihilator hole mesh is irrelevant. Example C is a combination of interleaving and stacking. For Example D, the continuous interleaving 22 201123254 layer is a better average like a brick wall. Small bunch. overlapping. Compared to example c, this configuration will provide an example of how the beam will be filled in the strip, with the determination that the strip will be written over 35 strips. One of the advantages of the write strategy is that the slave write strategy is effective = use an electron beam to make the beamlets. The efficiency depends on the hole μ: area (small beam output current) compared to the hole group area (beam input current). For a relatively small number of holes (49) 'beam (small beam group) area It must be small for acceptable efficiency. For "parallel projection," the bundle (group) size is smaller than the strip width. Pixel size is an important system parameter. The correlation between the grid of the extinguisher (hole) and the pixel size is explained below. Figure 9 shows a simplified beamlet blanker array. For each beamlet, there is one corresponding hole in the beamlet extinguisher array and the extinguisher electrode in each hole. The extinguisher includes an electronic circuit that turns the beam off or on by causing the extinguisher electrode to be powered or de-energized. An array with only four holes is shown as a simple example, and the pattern bundle is composed of four small bundles. The scan line pattern according to the grid 'five columns is similar to the pattern of Fig. 8'. The five columns are plotted for a particular κ value in the range of 1 to 5. K is a factor about the distance between the scan lines (for example, caused by the movement of the table between scans). A different K factor can be achieved by adjusting the relative speed of the table movement in the χ direction and the yaw rate in the 丫 direction (scan phase and flyback phase).

23 201123254 In the column for κ=1 in Fig. 9, the pattern is displayed when the distance of the group moving group width is displayed. The distance between the scan lines is equal to the distance between the extinguisher holes projected for this, i.e., the projection pitch (Ρμ.). In fact, the pitch of the projection will be much larger than the pixel size and a constant (design parameters of the lithography machine). The other columns in Fig. 9 show what happens when the station only moves the integer fraction of the group size and the scan line distance in the x direction. κ is this score. Some devaluation will cause the previous scan line to be overwritten. These kappa values should not be used. The κ value to avoid this is defined by the equation GCD(NK)=1, where GCD indicates the maximum common denominator and N is the number of holes in a beamlet extinguisher for one channel (ie: in each pattern bundle) The number of small bundles, and 艮 is the score of the mobile to group size. The κ value is acceptable if the number of holes in the grid and the maximum common denominator of the κ value are equal to one. When a value of κ = 5 is used, the distance between the scan lines will also decrease with the same factor. Use Parallel Projection and select the appropriate value to determine the pixel size (at least in the other direction). However, one limitation is that this results in only a fixed set of pixel sizes. The factor κ links the deflection frequency to the table speed. Figure 65 illustrates a write strategy with a factor K = 1 at the top and K: 3 at the bottom. Figure 66 illustrates the possible threshold for a pattern bundle with 4 small bundles. An example of a grid of 49 holes (eg, a 7χ7 array) is provided in the table of Figure 1〇, which describes the pixel size (in nanometers) in the χ direction for several valid κ values, assuming beam spacing It is 61 nm (25 〇 / fill ratio for a given blood type pore size). For these parameters, the projection pitch p 24 201123254 will be 8.6 nm. The grid width for this geometry is WprQj=414 nm. Therefore, the bit box is capable of controlling the write strategy shift of +/_2〇7 nm. Figure 11 is a legend of an array of nine small bundles showing some definitions of terms used, including: beam spacing Pb, projection pitch Ppr <) j, grid width and tilt angle 〇 {array. Figure 63 is another example showing an array of four beamlets. Figure 57 shows a table of pixel size and grid width, depending on the number of beamlets (Npat_beains), array tilt angle (aarray), projected pitch (Pproj), and K factor for each pattern bundle. In order to reduce the amount of control data that needs to be generated and transmitted through the data path and increase throughput, large pixel sizes are desirable. However, the pixel size is limited by the desired CD and resist properties. In the table, it is assumed that the optimum pixel size (I-X) in the X direction is 3.5 nm, and the fourth row from the left side shows the calculated value of κ based on the projection pitch and the optimum pixel size. Given the number of beamlets per bundle, the closest acceptable K value is shown in the fifth row from the left. The sixth and seventh lines show

...the number of beamlets, the tilt angle of the array, the pitch of the projections, and the K-factor to be the pixel size in nanometers and the width of the grid. A higher Κ indicates a faster deflection scan speed (relative to the table movement) and k is a smaller pixel in the X direction. At a fixed data rate, the pixels will become larger in the y direction, causing the pixel shape to change from approximately square to rectangular. Small _ bundle write strategy chrome, τ: Tian Xiao Shu 疋 orientation can be written to non-overlapping lines at a certain angle of 9 Ε〇 I seam. The Ε0 crack is related to the tilt of the yaw direction causing the gap in the 乂 direction as shown in Fig. i i . This location gap can be corrected. For each, the value of the shift is a multiple of the projected pitch. In Figure η, S. 25 201123254 The difference between the top hole and the center hole is equal to Wproj/2. This value will result in a full pixel shift component and a subpixel shift component. The full pixel shift component is preferably compensated for, but the subpixel component can only be compensated for using instant rasterization. Multiple Framing, Coding, and Synchronization To reduce system cost, you can use one fiber to control multiple (for example, 7x7 = 49) extinguisher holes. In one embodiment, the continuous control bits transmitted through the respective fibers are continuous extinguisher holes for controlling the beam blanker array (ie, for controlling a series of beamlets in an embodiment, each fiber comprises Channel transfer control information for 49 subchannels for 49 beamlet control on a single pattern bundle. This control information can be buffered before being applied to the extinguisher electrodes for each beamlet, or Control information can be applied directly without buffering. For this purpose, a buffer can be provided on the beamlet blanker array. The data path with interleaved/multiplexed subchannels is not intended to be shown in Figure 55. And the schematic diagram of the demultiplexing scheme is shown in Figure 56's array selector and row selector to decode the multiple = subchannels to separate the individual control bits for each beamlet. To synchronize and indicate the control information string Which bit in the stream belongs to which bundle 'is better to use some kind of ^ box, as shown in the example of item 12. In this example, use the box start indicator bit (in this example ^ 7 Bit The framing device on the beamlet extinguisher will be synchronized to its cycle pattern. When the DC balance sequence requires AC for the photodiode side to engage the optical ejector and automatic threshold adjustment, preferably Use some kind of encoding. - An example, such as 8b/10b. Mom, however, this will result in a higher bit rate, and the encoding of 26 201123254 will increase the bit rate by 2 $%. The signal is framed and coded. The group is marked with the beginning of the box. For example, use a specific code: a paste contains a number of individual beamlets (for example: 49 beamlets). The video will be transmitted in tandem from the data path to the extinguisher. The solution on the extinguisher is ''multiple'' with synchronous implementation and 胄 'may need to compensate for the extinguisher timing offset', Gan & m ^ ^, resulting from the annihilator due to serial data transmission at different times Receive the control information of Dong + according to the m * η * bundle. There are several small beam synchronization options for the month b. The threshold palladium is mainly determined by the possibility of implementation on the extinguisher. The way to implement d, pot η 本仃J bundle step, for example: synchronize all the small bundles to A synchronization signal, which will synchronize all the small beams in one column, synchronize all the small beams in one column or not small & t, 。. For each pattern bundle with arrays arranged in 7x7 For the 49 small beam embodiments, in order to synchronize all the small beams with =: one (four)' for 49 small bundles, the four (four) data can be buffered and applied to each of the 49 extinguisher electrodes for beamlet switching. Will: all the small bundles of one line are synchronized, for the control number in each line...the buffer is buffered and applied synchronously to the 7 annihilation two for the line beamlet: two will synchronize all the small beams in one column, for each The 7 passes of the column:: The control data can be buffered and applied synchronously to the 7...t synchronizations for the column beamlets, all 49 small beam control electrodes. 4 Debt received and applied directly to the extinguisher For line sync, column sync, or no sync, the individual beamlet pixel timing will be different for 27 201123254. It is compensated when there is a timing difference shift between the beamlets. This shift shifts the view depending on the beamlet combination, which is possible to make the difference in y constant in the sub-pixel range. Since the compensation is only when performing rasterization and stitching because the field is written by multiple beams, it is preferable to use stitching between the fields of the field written by the different beams. The stitching error (the pattern of the person written by the beam (4) shifting the pattern written by the adjacent beam) causes two types of lithography errors. The critical dimension (CD) error (the line at the seam boundary) Too thick or too thin to read overlap, difference _ overlap error, typically 5 nm allowed. The stitching method is to eliminate the CD error, CD error is caused by the stitching error. You can use the stitching strategy of not =. Other strategies are, for example, seamless splicing, irregular edge edges and intelligent boundaries. For a seamless 辍 strategy, it is expected that no specific means are required other than the good alignment of the bundle. If there is a misalignment, the line will appear at a dose that is too low or too high. The beam spot will average this effect to some extent. However, seamless splicing is not preferred. It is described in U.S. Patent Publication No. 2008/0073, the entire disclosure of which is incorporated herein by reference. At the two ends of the two-beam write (Before dithering) Fade out this strategy with the effect that its error is spread over a region, as shown in the soft edge of 丨μιη in the figure. The side effect of this strategy is that some pixels may be doubled (ie: Use a 2% dose). Because the beam size of the 201123254 is quite large, the dose will spread between several pixels. The smart boundary strategy defines the overlapping write range, but only writes a bundle to this area. 58A shows it A legend illustrating a smart boundary strategy. In the example of a circle, a 100 nm overlap write range is used, for example: 25 pixels with pixels. The boundary between two strips or fields is close to this boundary. The critical portion of the pattern data feature will be identified and placed in a strip or the other. This pod, the _ gamma / owed book has τ this & into the actual write boundary between a strip To move to avoid crossing the critical part of the feature, the critical feature will be weird to be written by a single bundle. The soft edge stitching strategy is to smooth out the two borders to the area of the next strip. For the soft edge stitching strategy Can make The maximum overscan length of 0 5 μηι. If a 5 nm stitching error occurs, this causes a 1% dose error in the area of the 5 fine line width. If the seam overlap is i (four), this ι dose is wrong, less To 1〇〇%χ 5 — 5%. The total dose error can be set to 3%' and the 5% 5% dose error is a reasonable budget for the error of the stitching from this dose error budget. Soft edge or smart border) and overscan length can be chosen for each description. Lowering the scan length will result in higher machine yield. Users are better able to choose soft edge or smart border stitching strategy and edge The size of the required data path is reduced. The use of multiple scans with two scans causes the lithography machine to write a master/, eight, and a flat with the maximum capacity of the basin. This reduction in write capacity allows the amount of hardware required for the data path to be significantly reduced.

29 201123254 - A channel is a unit of work in the data path. One channel is capable of writing a person-strip during the scan. The components of the data path involved in real-time processing are: fast memory, processing unit, laser, fiber optic and annihilator. Since only the #50% channel is now used for call time, the number of processing units may be reduced by approximately the same factor. At the same time, the processing unit that contends for fewer channels has the following advantages: fewer logical cells required per channel (,, each channel node requires a hard limit on the fast memory bandwidth and the required The possibility of fast memory storage size is reduced. Reducing the number of processing units also has the disadvantage that there must be a way to connect the processing unit to the thunder for the appropriate s channel, and new restrictions may invalidate the scan, especially if a large number of successors (cluster) occur. Channel error. In the following description, the concept of a node is used. A node has one (optical) channel connected and has one processing unit available. Figure 13 shows a model for such a node. Commercially available electrical to An optical (Ε/0) converter typically contains 12 channels (ie, γ = 12). A Ε/0 converter (eg, a laser diode) converts electrical control data from the processing unit into an optical fiber. Optical data transmitted to the extinguisher of the lithography machine. The processing unit driven by the Ε/〇 converter (eg, field programmable gate array (Fp (3A, field programmable gate arr) Ay)) contains one channel. You can use χ*γ intersection to switch any processing unit to any Ε/〇 converter. χ*γ intersection is a separate device or integrated in the processing unit. Routing any of the processing unit outputs (X) to any of the data path outputs (γ). In case some optical channels fail, the probability of shifting between the first and second scans must first be determined, Where all strip positions 30 201123254 are covered by at least one properly working channel. When the possible shift position is known 'determine whether the available processing unit is allocated between scans and covers 100% of the strips. Let's show the position of each scan channel in a conceptual diagram. The strip (basket) shown in Figure 14 is written with the channel error of this particular combination and two individual shift values. The difference overlaps and non-overlaps. The channel position is important for strips that will be correctly written at overlapping channel locations where they must be available for a scanned working channel. For non-overlapping channel positions, first and second The wafer shift between scans will result in two regions where only one specific scan can be used to write the strip. The failed channel in this region will interrupt the sequence of good channels. The leftmost channel error (see: The red arrow pointing to it in the figure) forces the strip to start on its right side. On the left side, the channel cannot be used. Typically, the shift is used so that the overlap field becomes error-free (using two scans) and can be used for overlap Some of the channels in the area to reach the required number of stripes to be written. Compared to the possibility of not being able to write to locations in the overlapping area, the possibility of not:: the position of the non-overlapping area is relatively High. Therefore, = in terms of 'non-overlapping areas... good channel, the sequence is short. Therefore, making Shaw 12870 channels covered in two scan orders (10) would be difficult because it depends too much on non-heavy strips The availability of a fairly large sequence. It is much easier to use _ strips to cover _ strips, because: m scans are in non-overlapping areas. In fact, it is very important to rely on the complete sequence. This 找到 finds a strip in the overlap area 31: 31 201123254 When the processing unit is 铋, the singer introduces a new constraint when the number is reduced. In addition to finding a suitable shift, a successful assignment of the unit to the channel must be performed for the processing of the second and second scans. In Figure 15, an example of this is shown.

For this example, assume that the mussels 1 J are white, and the nodes of the Steward Road and the three processing units are stored. The white point is the sunrise channel, and the black point indicates that it is the channel used for processing and the processing unit is assigned. Red A 4* Today & s has a channel error. It is verifiable that there is no limit to the specific processing unit. Having a maximum of three acting on a node Figure 16 does not appear to be the result of using fewer processing units for channels in non-overlapping regions. This ~ _ π 艮 艮 通道 通道 通道 通道 通道 通道 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大 最大The maximum length is equal to twice the number of processing units per node. For other shift values (the shift in Figure 16 is ideal), the useful sequence in the non-re-ink region will be substantially smaller (the one that occurs when the cut-off is increased). Therefore, the channels in the non-overlapping regions are even less useful than previously (without considering reducing the amount of processing units). In addition to the poor utilization of channels in non-overlapping regions, another weakness based on the same constraints occurs in overlapping regions. In the overlap region, reducing the number of processing units of the parent node is a change to sensitivity to the error sequence (error cluster). For each of the 12 channel nodes, the number of processing units of the 7 processing units plus twice the number of processing units will result in a failure. If the cluster is mapped on a single node, the allocation will fail for processing the cluster with a single 7L size plus one. Whenever the cluster is controlled as the actual bottleneck ^ There is still the possibility of scaling up the lang point size (for example: 24 channels with 14 32 201123254 processing units). This will reduce the sensitivity to large clusters. What's important is that the system is strong for a certain level of channel error. In addition, if a reduction processing unit occurs, the robustness to the channel error is maintained at a reasonable level. The key parameters for the redundant scanning concept are the number of stripes, the number of channels, the expected number of error channels, the expected size of the error cluster, the number of channels per node, and the number of processing units per node. After identifying the channel error, the system will find a possible shift combination that results in a "good" sequence of length equal to or greater than the number of required strips. A "good" sequence is formed by "good," in a non-overlapping region, or at a location in which at least one of the channels is "good," in the overlapping region. This process will result in a list of shifts with "good, start and size of the region. If a one-to-one relationship between the channel and the processing unit occurs (ie: no reduction in the data path valley), successful The wafer shifting unit is less than the channel, and the successful assignment is the attached force: one of the ® Λ d channels and the two scans of the Lai Ketian I. Temple, the assignment is successful. According to the scan, the nodes cannot be assigned There are many processing units available. Generally speaking, f can be assigned to the position in the overlapping area of the scan which must be written to some strip positions, and t is set at - position. False K壬^τ... The error in his scan is that if any of the points need to be tried, it will fail. The 勹 妁 妁 早 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , !:= will be assigned as the earliest node leaving the range. If such a king knife is equipped with 'other nodes from other scans, the processing unit should be assigned to: i. If any point needs more processing units than the available ones, the allocation attempt Will fail. You can use 苴^ to make With other scrolling, it gives a better knot to find the probability of allocation when it is rejected before A. The typical reason for the failure of the knife-matching scheme is the limitation of failure in the non-overlapping region, and there is no standby virtual singer _ $ Alternate processing early, and large error clusters. The specific shift value combined with the set error channel often results in a failed allocation. For two scans, the 'alternative processing unit is a processing order that exceeds half the number of channels that the node should supply. %, for example: each node is configured with 2 channels and 6 processing units without any spare processing units. The large error cluster will eventually exhaust the number of processing units at a particular node. The impact of the cluster is heavily dependent Its position, because it is determined whether one or two nodes should allocate processing units to write the error position. For each 12 channel nodes, there are 7 processing units, one node can absorb up to 7 errors, and the two nodes can Absorb 14 errors. ... Figures 17 to 23 are curve circles' which illustrate the simulation of the effect of changing the data path capacity in order to determine the lithography machine order. The result is a graph showing the number of successes from 5G experiments. Success means that a successful shift and assignment has been found. Because many simulations are about changing a single parameter, unless otherwise referred to as the sun and the moon, define it as The preset parameter set used: : the number of bands = 13000; the number of channels = 1331〇; the number of processing units per node = 7' and the number of channels per node = 12. 12 channels use 7 The node of the processing unit is called the configuration. 34 201123254 In Figure 17 'shows the effect of each node as a different number of processing units, assuming no large error clusters (only small natural clustering situations, gossip 2/6 groups) The state is considered to be the lower limit of the reduction' because the configuration of 5 processing units per 12 channels will fail. The 12/12 configuration is actually a configuration without any processing nodes being reduced; its success is only dependent on finding A successful shift (no allocation limit). The simulation results show that the robustness for the 12/6 and 12/7 configurations will be slightly reduced compared to the 12/12 configuration. Figure 18 is the effect of the error cluster for the same configuration as in Figure 17. . The 12/6 configuration is particularly sensitive to error clusters of size 5, and the error cluster of size 5 is due to the lack of spare processing units in the nodes. An error at a critical location will cause an execution failure. The 12/7 and 1 2/12 configurations do not show the special sensitivity for clusters of size 5. The effect of changing the number of channels is shown in Figure 19. Non-overlapping areas are almost useless if there is a reduction in the number of processing units. This explanation is a poor result for using 13,000 channels. Configurations with more channels will give more opportunities for shifts with a good "sequence", mainly because of the wider overlap area. Simulation experiments show that 1313 channels with 2 errors will result in an average of 26 A successful shift, while 13260 channels will result in an average of 41 successful shifts for the same number of errors. Using 13 channels is only for an average of 14 successful shifts. For a typical 1 2 / 7 group State, increasing the number of channels increases the robustness. Figure 20 shows the results of the previous simulation with the effect of an error cluster of 5. No significant effects of combining the number of changed channels were observed. As mentioned earlier, robust Degree when reducing the number of processing units from 12

35 201123254 Reduces to 7 and increases the number of channels to improve robustness. Figure η presents the result of a reduction in robustness due to reduced processing units due to the use of more channels. As can be seen, the loss of robustness when changing the configuration from i2/i2 to 12:7 can be achieved by increasing the number of channels by only about 1% (for example: increasing the number of channels from 1313 to 1328). make up. Note that the clusters used in the simulation are the feature size @ | clusters that appear to be the worst condition. Other clustering strategies tend to provide more positive results. Ffl 22 shows a comparison of the three strategies: only injecting a single cluster; injecting as many similar clusters as possible at a fixed distance (65 from the starting position to the starting position); and, injecting as many as possible at random locations A similar cluster (however maintains 2 (M is the minimum distance for a good channel). Note that the fixed distance between the error clusters produces a lot of correlation and will cause a large number of successful shifts. When reducing the number of processing units, the size is greater than The cluster of 5 will have a severe impact on robustness. This can be seen in Figure 23, where 12/07 (12/07@5) with cluster size 5 and ^ with cluster size 8 (12) The difference in robustness between /07@8) is obvious. If error clusters greater than 5 occur more frequently, alternative methods can be used in combination to reduce the number of processing units to reduce cluster sensitivity. Increase node size and use comparable The ratio (such as 24/14 configuration) is one such alternative. The effect of this can be seen in Figure 23, which shows the use of 24/14@ compared to the 12/〇7@8 configuration. 8 The greater robustness of the configuration. Other alternatives The channel is randomly arranged throughout the node, or the channel system is widely distributed among the nodes. These will result in an error cluster, 36 201123254 which corresponds to multiple different nodes instead of being concentrated in one or two nodes. In this configuration, all mirrored positions written to the cluster error will not be 丨 or 2 nodes but the task of many of them. However, randomly arranging or spreading the channels may have other negative side effects because The concept of neighbors (and potentially shared information) disappears. Allocation strategy optimization: In addition to checking allocation constraints, an important task of assigning functionality may be to minimize the number of stitches between scans. The conclusion is as follows. Reducing the number of processing units per node can significantly reduce the amount of hardware. Decreasing the number of processing units per node will slightly reduce the robustness. For two scans, 5q% (for example: 12/ 6 configuration) is the lower limit for reducing the number of processing units per node. Nearly 50% of the configuration is particularly sensitive to small cluster errors (size = 5). 12/6 configuration is therefore not 12/7 configuration is preferred, 12/7 configuration does not show this. The 12/7 configuration seems to be a reasonable lower limit for the number of processing units per 12 channels. For good robustness, the number of channels is preferably greater than The number of bands (+1%). Increasing the number of channels is an obvious measure of H. Because the number of 7Gs for processing each node is reduced, the loss can be easily achieved by using an additional 1% channel. The error cluster (>5) will dramatically reduce the robust production. The data path is to be built & the flow chart in Figure 24 is an overview of its dependence. Γ The processing involved understands the dependence (allows) It is time to recognize and reveal for parallel execution to increase production.: To be processed while scanning and/or to cut to read. Hold one

37 201123254 Different dependencies and their different probabilities or limitations may occur in different configurations. For example, the dependency between processing E1 (wafer measurement and positioning) and ci (in-line = rational and / or loading data for initial scanning to _). Broader than architecture option A (offline processing), this dependency does not exist. For options, this dependency may be a problem. 'However, for immediate rasterization, this dependency will exist (the instant combination of Xiaodong and the scan line ^. Typical performance requirements for processing: downloading a new pattern from the feeder to 2 The local storage of the node is <6G minutes; the number of patterns to be stored in the streamer node: 2); (1); the machine is attributed to loading a new image: offline time < 60 seconds; Each wafer will be rasterized—the maximum time between the update of the two positive parameters and the ready to write is 36 seconds (10% of 6 knives); and, during the scan exposure, < 3 minutes. Timing and Synchronous Clock and Synchronization Signals can be distributed through fiber to other subsystems (also from the wafer table). This has the advantage of current isolation between subsystems and insensitivity to electromagnetic effects. Clock changes can be used to change the agent = however 'because the dose variation can be compensated by changing the pixel size, rather than: avoiding clock changes to simplify the implementation of the actual part of the number responsible for transferring data to the quencher and eliminating Be heavy after the clock frequency changes The time required for synchronization: The advantage of using a fixed clock rate is that the clock no longer needs to be distributed between different components of the = path. Use (in the FPG "side" standard phase 2 loop), in local time Variations in pulse frequency can be compensated for. When a change in ( (such as fiber) is required, special preparation is required to enable synchronization of data 38 201123254. The data path is preferably operated as a clock master for the entire lithography system. And providing timing and synchronization signals to other subsystems, such as: an electronic optical column (deflector) and a wafer positioning system. Corrected in the embodiment of the charged particle lithography machine described above, there is no built-in to lithography machine Any facility to adjust individual electron beamlets to correct errors in beam position, size, current, or other beam characteristics. The lithography machine omits modified lenses or circuits to make individual corrections for beamlets to avoid Component to the electro-optical column to create additional complexity and cost involved in actual beam correction, and avoid the need to incorporate such additional components The size of the column is large. = Therefore, in order to correct the change in the beam position, size, current, etc., the adjustment is made by the correction of the control signal provided by the (4) route. For various reasons, it is necessary to create Several types of corrections. These corrections include corrections to compensate for: ^ • changes in beamlet position. Due to variations in the manufacture of the column, such as holes in the array of pores or beamlet extinguishers The exact positioning and variation, or by the condenser lens or projection lens or deflection electrode:: field: degree difference, small beam may be misaligned. Such misalignment can be corrected by "pattern shift. M soil (4) These may cause the entire wafer field to shift in the / and / or y directions. This type is fixed. Domain shifts can also be used with "® shifts,"

39 201123254 • Delay error in the data path (eg due to differences in fiber length in the data path). This error can be corrected by shifting in the y direction. • Off and off timing offset. Due to the multiplexed control of the beamlet control signal, multiple beamlets are controlled through one channel and the beamlet control signals are in-line reception, ie: the control signals for different beamlets are by the beamlet extinguisher array at different times Received. Depending on the design of the extinguisher, it will be subject to different offsets for turning the beam on and off (for example, the beamlets can be switched in units of columns or rows) or individual beamlets. Depending on the strategy for implementing the control bits (the beamlets are switched), this may cause the particular beamlet to switch between later (four) than the other beamlet. The effect of this error is in the subpixel range +. The result is the offset of each beamlet. • Changes in the hole position of the small beam quencher array. Each beamlet passes through the aperture in the beam annihilator array and is switched by the extinguisher electrode at the aperture. Variations in the manufacture of the beamlet blanker array may result in mechanical offsets in both the 乂 and y directions of the hole and thus the position of the corresponding beamlets, as compared to the reference position. The effect of this error is typically multiple pixels, and the result is the offset of each beamlet. The full pixel (integer) portion of this error will typically be compensated for during execution. The remaining fraction (fractional) portion can be compensated by instant rasterization. • Changes in deflection strength. These may be due to the spatial variation of the beam deflection (4) electrical deflection field strength, which must be corrected for "SCaling", "dose correction," or it may have a small difference in deflection; The beam offset component, which can be corrected by "pattern shifting." For use in extinguishing the beamlets, the effective dose rate will vary during the control signal pulse. Different timing behaviors due to the turn-on and turn-off of the array electrodes 40 201123254 is different between J bundles. This effect is significant when the control signal is not multiplexed (for example: 1G%). As far as the control signals of 49 small beams in one channel are transmitted, the significance is reduced because the transition effects are the same, but the minimum pulse width is larger than that of the unmultiplexed transmission case. Times (assuming 10%/49=0.2%). Moreover, this error is dependent on the dose rate. The error will be written to be small for the 100% dose rate, and the error is written at the highest dose rate at 5 〇%. The overall pattern is paid. When writing a pattern on a wafer, the beamlet of the written pattern is unlikely to be a sentence for Van Wang. In order to correct this misalignment and cause the beamlet to be able to write to the alignment strip' adjustment pattern data to compensate for the misalignment error. This adjustment can be done using software or hardware and can be done at different stages during the processing of pattern (4). For example, the correction may be made in (4) vector format, # in a multi-level gray scale format, or in a pattern data of a first-order B/W bit το bitmap. The offset may occur in the X direction (stage movement direction) or the y direction (small beam scan deflection direction) or both. The offset may occur with full pixel shifting and/or sub-pixel shifting. Full pixel shifting can be achieved by shifting several pixels after rasterization. Subpixel shifting can be achieved as part of the rasterization process. The overall pattern shift (ie, the shift of all beamlets in a channel) can be used for strip position correction (in the X and y directions) and field position correction (in the \ and y directions). The example of the χ and y pattern shifts for strip position correction is not as shown in Fig. 25. On the left side of the figure, the strip is displayed with the desired pattern with its overlap at the intended position. On the right side of the figure, the strip is a pattern that has overlaps that will be written if no corrections have been made. As can be seen, the overall pattern shift 41 201123254 is required to cause all of the beamlets of the channel to be written to the position shifted up and to the left. Typically done frequently after calibration (per wafer or field-to-beam shift. It can be assumed that the beamlets are fully aligned with respect to their = beamlets in the same channel, so that all beamlets in the channel are made The same pattern offset is obtained. His typical requirement for pattern shift is the individual X-Shaft shift setting for each head of the overall shift, and the 纟 parameter is for each field _ is updated - times = typical The maximum shift range can be from +2〇〇nm to _2〇〇, and the displacement accuracy of 八·υ·1 nm. This correction is for each channel of the overall shift, and is expected to be 'in the pattern bundle All beamlets in the same offset value are used. For the overall pattern shift, the channel pattern is shifted regardless of the beam interleaving strategy. 煻, 灭 灭 庠 _ _ Τ Τ For multiple subchannels The beamlet control signal is preferably multiplexed on a single channel. Depending on the design of the extinguisher, this will cause individual beamlets to switch to the next pixel at different times. The totalizer timing offset correction needs to be corrected. = channel correction in Υ, typically with a maximum margin of less than one pixel, and (M nm shift accuracy. The shift parameter is static, since the extinguisher timing offset is dependent on the extinguisher design. The gunner hole is a child. Because of the extinguisher geometry, different holes have a certain The different offsets of the reference points use the offset of the X of the hole to produce the interpolated pattern (see: Figure 9). The predictable timing delay will be considered immediately and is not considered part of this correction. The offset of γ of the reference (eg, the middle strip) is compensated by the alpha error. The knives are full-pixel and sub-pixel components. The full-pixel shift should always be compensated, while only the instant rasterization can process the sub-pixels. Component. Quencher 42 201123254 Hole offset correction requires correction of γ for sub-pixel components according to sub-channels, typically with a maximum shift range of +/- Wproj/2 or +/_210 called: )) 0_1 nm displacement accuracy. The correction parameters are static, because the extinction hole offset is based on the extinction geometry. Dose Correction Because the manufacturing tolerances in the lithography machine vary, the effective dose varies according to the beamlet Small beam scanning deflection intensity change It can also cause a change in dose intensity. The dose rate can also be corrected using a dose factor: causing a dose rate = dose rate map * dose factor. This formula is modified mathematically, but the dose correction is preferably by adjusting the pixel white value. And/or the threshold is implemented during the dithering process. For example, when the small beam is calibrated with a 9G% dose factor, the intensity is 100%/90% = Ul.1%e. Therefore, if 1小 is The white value of the preset value for dithering will be Ul.1; and if the preset value is 5〇, the dithering threshold will be 55,6 〇 The dose correction is performed according to the small bundle, and the correction parameter is The wafer is updated once. For the typical requirement of dose correction, the pattern dosage accuracy of 0.2/〇 step size, -(10)% beam dose factor, and the map agent in the model of 5〇%_1〇〇% are mapped. Beam dose accuracy of 0.2% step size. The resulting dose rate should be rounded to the nearest value. The item is scaled and deflected in the y direction during each scan and the pattern is written from one side of the strip to the other. The deflection distance is preferably two times the width of the strip and the overscan distance. If the deflection is not exactly the same, one beam is deflected stronger than the others and therefore the deflection distance will be different. Due to the difference across 43 201123254, the difference is the beam that occurs in the weaker deflection field at the far end of the scan column, and the electrons that occur in the array are dropped. The surface of the deflection array that scans the deflection intensity is “intelligible”. The deflection field is deflected and the deflection distance is shorter for a weaker experience. This is the use of the model; I® & I e g 261 M ® to the standard example is shown in Figure 26. In the left part of the figure, the strip _ stick material is covered by the icon of the figure with the pattern feature between the dotted lines, and the right side is taken from the mountain to the right of the figure, the strip is displayed public, and the right is not made. The calibration pattern will be written to the covered pattern. For example, ^: Graphic calibration correction is required to reduce the correct calibration of all beamlets of the channel to write features. The calibration can be achieved by adjusting the bit rate of the data signal transmitted to the extinguisher, and the pattern of light is spread over a different number of pixels. Due to the synchronization of the test, changing the bit rate is not preferable. To avoid this, scaling is performed by spreading the pattern over a different number of bits/pixel. The assumed two = the same group of beamlets have the same deflection strength. This is because it is deflected by a deflector that is identical. Therefore, the pattern scaling factor is the same for a group. ^Graphic calibration requires correction for each channel. The correction parameter is preferably updated once for each redundant scan recombination. The maximum range is typically i to "" (for example: 2 _ becomes 2.2 (four), and the accuracy 〇" nm / 1 Mm = 1 / 1 〇, _. Assume that the deflection strength 疋 is the same for all the small 朿 in the channel, Since the beamlets share the same deflection array and are approximately the same position in the deflector. Figure 27 is a table summarizing the various types of corrections and typical parameters and ranges. Note that when using the first scan and the second time (or redundant) scanning, 44 201123254 Dose correction is better to perform the dynamic pattern shift before the dynamic map 袒 付 paid a scan can also be used to compensate for wafer heating. This can be used The channel's X and γ are low - the table 'has a time-dependent value. It can be used every 1 ms for the 1 nm field's attack slope (equal to X -10 μηι at X), and every 3 00 mm (wafer The size α horse has an offset table of 30,000 items. The forced size (Si7ir>Mf is the difference in the deflection strength of the beamlet scanning across the surface of the scanning deflection array'. The deflection distance of the beamlet will change. This can be used (above) ) Figure calibration or Figure 3L sizing correction for compensation. The requirement for pattern sizing correction is summarized as being the same as the pattern sizing. The data path architecture data control receives the layout data of the specified format and processes this data so that it can be written on the wafer using the electron beam. The data path also implements adjustments to the pattern data to compensate for errors in the lithography machine and provides synchronization signals to other subsystems. Figure 28 shows a functional block diagram of the data path showing the GDs_n pattern data file to The flow of the bit stream transmitted through the fiber. This figure also shows the corrections that occur in the appropriate function block. Depending on the architecture option, it can be modified at different points within the data path processing. The input to the datapath subsystem will be in a preprocessed format (usually from an industry standard file format such as GDS-II or MEBES) containing layout information that will be "written" onto the wafer. This industrial standard building case

45 201123254 Format, pre-defined season After processing, the data will be applied to =: for offline processing. It is stored offline in the next stage of the second:= for subsequent processing. The number is a file. Fields, storage, for example: number of dose mappings per individual channel 剂量 The dose mapping is typically the area of use. The dose rate is the radiant intensity of the indium b area of each of the graphs. It is necessary to write the pattern with the appropriate dose hand, otherwise the written pattern will not appear on the resist. For example, the range of dose rates may be 50-1 GG% in steps of 〇. 2%, and the spatial resolution of the dose mapping may be (7). η · The regions are non-overlapping, so the description of the regions The line of the polygon is not the parent. The material area can be used at angles 〇, 45. , or 90. The line is defined by the vector. The immediate process is broken down. The offline process can decompose the complex polygon into a simpler one. For example, the polygon can be simplified so that the scan line only intersects the boundary at most twice. In 匕 simplify the transfer in the hardware. Pretreatment Pretreatment is typically performed once for each design. This step requires a lot of computing power. The following functionality is usually included in the pre-processing: (Sentence reads the GDS.II wafer design and takes the information needed for the specific steps in the wafer process. This typically results in a polygonal map of the features required in this step. b) applying a resist heating correction to the dose mapping. This correction typically proceeds to adjust the feature position. (c) Apply a proximity correction to the polygon. This correction will result in a dose mapping for more polygons with different dose rates attached. (d) The dose mapping for each field in the vector format will be output. 46 201123254 Channel division (splitting) is used as a unit for further virtual & οβ 'processing. To make this possible, The field dose mapping is divided into dose maps for each & 'channel. The polygon is reduced to the strip region written by one channel. The strip region is preferably extended beyond the boundary of the strip to consider The stitching of the New Chu & t 1 is slightly related to the initial color of the dithering. If the "smart border, the stitching strategy, the pot, the critical features are assigned to a single For the track/strip, the critical feature polygon on the strip boundary is assigned to the specific channel when the dose map is divided. Channel rendering The transition is the first... of the rasterization process. The information is circulated in the pixels. Figure 29 shows the layout pattern features superimposed on the strips to illustrate the transition process. (4) Information and Agent # Information is described in vector format in (4) (iv), and is usually based on the field The pixel boundary value at χ is fixed by the starting point of the machine (also assuming that the first column will be written by the beamlet). This will determine all pixel X coordinates (deben ν · 1豕 IX idx in Figure 29) The relationship between the corresponding beamlets (in Figure 29, ^4 ldx) of the scan line. The scan line is a column of pixels in the gamma direction. Typical X position from the field on the wafer And the X-offset determined by the routine metrology process, the first-order scan line (the first field-pixel column) of the specific field can be determined. The pixel in this example is misaligned with the field origin. "sub pix offs X" defines the left pixel X boundary from the origin of the field (as a reference for the vector format) offset. ' 1 pixel size, strip width, overscan and pattern scaling in Y will cause it to be an integer number of pixels needed. An extra pixel may be added to allow 201123254 = Bit. The scaling factor for all beamlets will be the same and therefore all pixels will be the same gamma size. And the shift can always be divided into integer parts (full pixel shift). Bit) and the fractional part (sub-bit. The shift in the η method η box to achieve full-pixel shift..., the method achieves sub-pixel shifting in this way, but can be performed by arranging /: :: in the Υ direction Shift to the whole (ie: the total in the direction of the ¥: repair: Γ): dedicated to the small bundle (for example: beam position or extinguisher timing offset). The transfer process should know which small beam is written to the scan line and (sub-image: suitable:: the sweep line is like the h pixel is shifted before the transition, so it is the f-strip strip VecrefY) (see: in the figure) The magnified display shows the A) line, which is the baseline in the y direction for the vector format description of the feature and dose. Because the relationship between the beamlet and the pixel X index is only when the scan is started, the set is only available. Instant sub-column to handle sub-pixel shifts. Offline sub-columns will always assume that the sub-pixels are shifted to zero. Virtual_message Mitherinp;) Dithering is the second step of the rasterization process. By dithering, The specific dose rate is achieved by a switching sequence for the sub-channels. The dithering is to substantially quantize the multi-T gray-scale pixels into second-order white/black pixels, and propagate the quantization error in each pixel to the adjacent pixels and Locally forcing a specific average dose rate. This process is illustrated in Figure 30. The dithering technique is typically used to achieve grayscale or color variations when printing. Some well known algorithms are error diffusion (2χ2 matrix) with Freudstein Grid (F1〇yd steinberg) (2x3 matrix It is implemented in one or two (spiral) directions. The dithering algorithm typically requires some pixels to be prepared. Because &, the strip is extended to a small margin for better results of 2011 201123254. For lithography purposes, some improvements can be made. One improvement is that the error propagation is preferably a pixel that does not propagate to zero. The error value should propagate or discard in the other direction. Propagating the quantization error to a pixel that requires a zero dose is useless. This is also understood in view of the reasonable value for CD and spacing. This guarantee will follow multiple zero pixels if a transition from gray to zero occurs. Dithering transforms grayscale pixels into black/white pixels. Since the dithering process must propagate the decimation error to its neighboring pixels, the sub-pixel shift of the $ scan line is also processed. Figure 30 illustrates this process. In order to propagate the quantization error in an accurate manner, the error to the other scan line Propagation is not unimportant because the scan lines are not aligned. The quantization error can be propagated based on the amount of overlap between adjacent pixels' such that the pixels with larger overlap receive propagation quantization error The larger part. The alternative and simpler strategy is to propagate the error only to its neighbors with the greatest overlap. v... Once the eight-powered squid, due to the rate of the transfer, the dose factor of each beamlet And the calibration factor for the channel, the age of the county, Heshe, the soil, the μ. The agent, the 哎, the 疋 know; the factor: the factor is better for each beam, m, 胄 color module It should also be known that the scan line pair is bundled (in the “Subbeam Μχ” in Figure 3). The dithering county causes the on/off state of all pixels of the strip. Before the step is processed, the selected edge is removed. Limit pixels. If a soft edge occurs, ^ be bound to the pixel, because the strip boundary already has a smooth interval is known or the pixel will be in the γ view architecture option ^, the correction is unknown during the dithering process. For offline dithering, subpixel shifting is not possible, 49 201123254 Alignment. For the dithering process, the threshold is always always "white value," - half because the white value will deviate from the preset value due to the small beam dose correction. Channel, frame and multiplex this process is performed in the dither Subsequent tasks. The dithered pixel bit is projected into the scan line bit box. In this operation, a small beam-specific full pixel shift can be performed. For a single deflection scan, then the appropriate bit is combined. Earlier for the column processing, the full pixel shift in the gamma direction can be performed at a later stage by ❶b/w bit mapping of the pixels placed in its scan, in the bit box. This bit box is typically compared The bit map width is wide because = allows for shifting space. Figure 31 illustrates this process. The vertical arrow indicates the full pixel shift relative to the zero shift line. If the pixel is on this line (as in scan line in Figure 31 = The leftmost scan line of the meta box begins with 'the full pixel shift is zero and the pixel is fully centered in the scan line bit box. The next step in combining the deflection scan frame bits is shown in FIG. Out::: necessary to adapt to the positive handle write strategy and present at the right moment The heart is different for the small beam position of the bottom side of the bottom side of the parameter Ν=4 and Κ-3μπ Λ. The position is displayed as a good fortune and is not enough. For this step, you should know There are:: deflection scan index. For the particular deflection scan index, the column = material is a single deflection scan bit box. In Figure 32, the two bottoms are filled with symbols to find the deflection sweep # ' The pixel position of the bit-box is deflected. 50 201123254 As the last (optional) step to improve data transmission. The digital deflection scan bit box will be coded as shown in Figure 33. The main data from the non-data path is returned to the block diagram of the data processing and storage component, including: offline processing & m _ pattern The streamer node and the extinguisher wafer are early), and several months (the beamlet extinguisher array). Offline processing & central storage; θ + to rn, ... process input layout data (for example: in GDS-II format) and generate input slots for strips '. According to the channel for each known channel, the winter band data must be terminated at the correct pattern stream node. The graphics streamer node contains disk and RAM storage. The disk storage is used to store the input data for the metering pattern, and the ram stores the data required by the processing unit that is processing the current pattern stream. Depending on the configuration option, the input data from the server is the same as the input data for the processing list 7C. This is for offline and instant rasterization. Pair: Offline rasterization, the bit map is received from the server and forwarded to the process. For instant rasterization, the input data in vector format is received from the word benefit and forwarded to the processing unit to convert the vector format to a ^-mapping. For the option of inline architecture, input data in vector format is converted to a bit map for processing units. The functional units of the Ji data path are shown in Figure 28: (1) pre-processing; (2) channel partitioning; (3) channel transposition; (4) channel dithering; (5) sub-channel mapping; 6) Channel multiplexing and coding. 51 201123254 Pre-processing and channel division are preferably performed offline, and sub-channel mapping and channel Xigong and U-code are better for immediate execution. However, bookkeeping (including channel routing and channel dithering) can be performed offline or in-line. The following architectural options are: (A) offline rasterization; (8) inline rasterization and field offset; (C) inline rasterization and alignment field; (D) instant rasterization. In one embodiment of the lithography system, the following requirements of the lithography system are defined (which affect the data path architecture): the maximum field size is 26 mm χ 33 匪 (y, X) and the write time per field is 2.5. Seconds, plus another 2.5 seconds for the second time; 13,000 fibers/channels/strips and (4) side electron beamlets 03'OOOx 49 small beams per channel); strip width is - and overscan Width (one side) is 1.1 5 _ (including 〇2 offset range 卜 / 鸠 _ + 〇 2 scaling range ((10) of strip width) + () · 5 soft edges (() 5 _ one side) + 〇 ·25 write strategy (assuming Wpr. corpse 42〇nm: one-sided Wpr〇j/2=2 ι 〇; maximum deflection width is 4.3 _ (deflection frequency depends on the write strategy and drive speed); typical pixel size Is 3.5nm, and the pixel size range is 2,6诣 (1/3 to 3x (typical pixel size) 2); the dose grid resolution is (7)^(4); the minimum spacing is 64 for the line with a minimum CD of 22 nm, And for the smallest CD of CD $ 32 nm; the input resolution is 〇25 _ and the resolution of the thumb is 0.1 nm. The data pattern storage size on the pattern streamer > 10 patterns; The new and new correction parameters are ready to start writing new wafers for 36 seconds; the upload time from the server to the graphics stream is <6〇 minutes; from local storage to fast-distance reading <60 seconds (single processing step) and <6 minutes (in writing period)'· and processing nodes of 12 channels of 7 processing units. '·', 52 201123254 The lithography system is preferably capable of Processing positive and negative anti-surname agents. The characteristics of the anti-money agent are preferably processed in the off-line processing of the data path and the rest of the data path should not be known for this. , ie: first and second or redundant times. The combination of the two will be written on all 13 strips on the wafer. Yan Guang A: Offline Rasterization Figure 59 shows the use of offline grid The embodiment of the grid. The GDs n format data is processed offline, including: proximity effect correction and anti-(four) heating correction. If a smart boundary is used, the boundary is calculated at this stage. Rasterization (transition and dithering) ) is implemented to convert the Shaw pattern data into second-order black/white bits Shot, which is the tool input data format used in this embodiment (ie, the data format used for transmission to the lithography system). This offline processing is for a given pattern design, for one or more batches of crystal The circle is implemented once. Secondly, the in-line processing of the tool input data is implemented to generate a pattern system streaming (PSS) format, which is also a B/w bit mapping format. Inline processing is typically implemented in software. The pattern streamer then processes the PSS format data to produce extinction format data, ready for transmission to the beamlet blanker array. "This process is typically implemented in hardware and may include it involving beam position calibration, field Correction of full-pixel shift in the X and/or Y direction for domain size adjustment and/or field position adjustment. This process can be performed by field. The extinguisher format pattern data is then transferred to a lithography system for wafer exposure. In this architecture option, 'many jobs are heterogeneous; good

On the eve of the evening, I will leave the color. Rasterization will; I

Offline and the mother is set to perform a beta cake in the 丨, strong TS J for this option, for lithography 53 201123254 input data is black / white (Qing, w μ mapping = graphic description The bit map is instant processing. Therefore, only the correction provided by stage 5 (channel framing and accommodating. Phase 5 mod...: Fig. 34) is available for 疋王 pixel shift correction 'which may include: Overall pattern shift in each pass and Υ direction, extinator timing offset (γ direction) and extinction hole offset (Υ direction). ', there is in, bundle versus column mapping (quenchor hole deviation) The effect of shifting and extinguishing the portrait. The appropriate ¥ offset will be appended and rounded to the nearest due to only the full pixel correction, the relatively small pixel size (a) (four) is to meet the accuracy specification. The disadvantage of using small pixels is that : Requires a larger bandwidth than the available channels, which may result in lower yields; the parent channel requires multiple fibers. Figure 5 shows the processing flow for this architectural option. The focus is on changing The instant of the batch. The virtual 4] processing machine can be analyzed to The entire process of the shadow system finds the interval it can use to load the pattern data, so that these processes can be processed to maximize the yield. In the central block, the batch ^ changes to the graph @ B. For this graph, Assume that there is no reason (because of the failure bundle) to reconfigure the bundle with the strip. Loading the main part of the new pattern (for the strip written by the main scan of pattern B) can be done at the end of the main scan Start immediately. This figure also shows that the second scan/redundant scan portion of the new pattern can be started quite late and should be when the second scan/redundant scan for the new pattern should start. The 0 field scan 0 and F durations are typically in minutes. For Ping 54 201123254 lines, the total duration of processing Η and D can be about i minutes. Therefore, it can be used to load total (four) (four) equal to two The time between scanning and wafer exchange (about 6 minutes), assuming that there is no need to reorganize the strip data between nodes. It may be necessary to reorganize the stripe data when the new failed channel is found by processing D. Figure 36 is for Offline rasterization architecture (option Α) A block diagram of the main components of a graphics streamer node. In Figure 36, each node contains several components. The node, the point CPU coordinates the processing on the node and moves the data around. The network device and the server ( Offline processing & central processing unit communication and receiving office data to the stream. The disk storage unit stores the bit map for the processing unit. It is possible to have several versions of the bit map mapped to be available on the disk. Improves reliability and read performance with disk arrays in some RAID modes. The drive's read speed is improved by striping (RAID 0, distributing data across the disk array). The data is stored redundantly (RAID 5, N disks: storage size = N-lx disk size) to improve reliability. The processing unit memory (PU-RAM) stores pattern data. When scanning, the processing unit 7L reads its pattern data from this RAM. The CPU loads the pattern data into the RAM before scanning. The processing unit streams the pattern data and produces an optical signal for transmission to the extinguisher. A typical data flow for this configuration is shown in Figure 37. The pattern data is received by the node cpu from the network device (1) and stored on the disk (2). Whenever the pattern data is required for scanning, the node CPU reads data from the disk (3) and stores it in the PU-RAM (4). When scanning, the processing unit reads its pattern data (5) from the PU-RAM. 55 201123254 An important feature of this architecture is the size of PU_RAM, PU RAM load %, disk load time and disk size. The pu_RAM load time (the time it takes to load all stripe data into the PU-RAM) will depend primarily on the performance of the disk storage unit. Regarding the disk load time, the bitmap for the new scan must be downloaded from the feed service. The illusion device may be the neck for communication. The disk load time can be improved by increasing the bandwidth from the server to the node or compressing the bit map data on the server. For the disk size, it is assumed to overcome the distribution bottleneck (server bandwidth), and multiple (for example, 10) patterns can be stored in the disk storage unit. Depending on the availability or read speed requirements, the disk can be constructed for a particular RAID hierarchy. With the concept of off-line and in-line, the reordering and mapping of pre-processed pixels can be performed by a processing unit that includes a field programmable gate array (FpGA). This processing unit will allow full pixel shift # and the data from the memory can be reordered for multiplexer transmission towards the extinguisher. Compression can also be used for architectural option A. Possible configurations include: uncompressed, compressed dithered images, or compressed grayscale images. For no compression, the graphics streamer node stores the (uncompressed) dithered image on the disk. It is also possible to compress this image on the server before distribution. In this case, the graphics streamer should decompress the image after it has been received, but this does not seem to be a bottleneck because there is a reasonable amount of time for this processing. For compressed dithered images, compression reduces the amount of distributed work (communication time) and reduces RAM size requirements. For this solution, off-line processing should compress the dithered image. @FPGA should image the image internally and process it. Because 56 201123254 this 'image in RAM is much smaller. As far as the functional unit of Fig. 34 is concerned, the compression and decompression functions are inserted after the dithering, as shown in Fig. 39. Compression may be less effective for dithered images because the dithered image contains many zero values and the non-zero region may be difficult to compress due to changes in dose values. Figure 40 shows a dithered test image using a single color (one bit per pixel) image. The image (Fig. 40) is 8 times the dithered version of Fig. 42 that changes the dose level each time it is repeated. Since the dose is changed each time it is repeated, the compression tool cannot be reused and is less efficient. GZIp and 〇ptipng are possible compression methods. The compression of the dithered image is not easy and will pass approximately: a compression ratio of 4 scale (mainly a sequence of compressed zeros) ^ using a compression ratio of i: 4, the size of a typical strip image using 2 nm pixels will result in each The strip is 4352 MB uncompressed and 1088 MB compressed, and each streamer is 6i gb uncompressed and 15.2 GB compressed (ie: 14x). In this scenario, compressing the dithered image will reduce the RAM size to 16 Gbytes, providing the load time (for a single disk, the disk_>RAM is about 2 minutes) and the distribution time (server)优点 The advantage of the disk is about 1,5 hours). The 2 minute load time is suitable for processing the time window of loading in the process. The expectation is that FPGA A enhances the decompression of each channel, which keeps up with the instantaneous data rate of approximately 5 Gbit/s. In addition, the server preferably compresses all data initially. For compressed grayscale images, as far as the functional units of Figure 34 are concerned, the compression and decompression functions should be inserted after the transition, as shown in Figure 41. After the transition, the offline process should compress the grayscale image and FPga decompresses, dithers, and processes the image. ~ Figure 42 shows the transition bit of the grid (64χ1〇〇〇 nm@2 nm pixels)

57 201123254 Example of shooting. In order to compress 'use GZIP and 〇ptipng (both are open source compression tools). The two boxes of ancient m, and methods are no loss. GZIP is a universal compression tool, and 〇Ptipng is dedicated to compressing 2D images. pNG compression is composed of - orders, ie. 2D predictive filters and compressors, so that 0PUPng provides excellent (four) scaling. Depending on the pattern found in the actual design, there may be more repetitions in larger images. Using a compression ratio of 1:40 (PNG) and 2 nm pixels, the compression ratio shrinks the image to a size comparable to the vector format. In this way, png decompression is integrated into the processing unit FpGA. When the bit map size grows by a factor of four, the compressed image is for σ ζ ιρ and for a factor of two. Compression combined with small pixels is quite effective. 有趣3 An interesting observation of this approach to using grayscale pixels is that it potentially allows shifting and constituting larger pixels for streaming to the extinguisher. The value of a larger pixel can be calculated from a smaller pixel, #by a linear combination of values using smaller pixels. The input image can be viewed as oversampling. Figure 43 shows this concept of small grid input pixels and large output pixels. An example is proposed in which the ratio of pixel sizes is 1:2, however, other ratios are also possible. The FpGA maps the uncompressed bits and combines several small pixels to form a large pixel for streaming to the extinguisher. The advantage is that this approach will be limited to the bandwidth of the fiber (large output pixel), even when using small input pixels. The bandwidth of the fiber is considered a bottleneck, and each channel can use two fibers to stream 2 nm pixels to the extinguisher. Remarks about this architecture: • The dose mapping is preferably still attached to the input bit map and used by the FPGA. 58 201123254 • Dose correction is possible because of the dithering in the FPGA. • When X and γ are shifted from the input pixel to form the extinguisher array, the accuracy depends on the actual pixel size. • Decompression and dithering in the FPGA is necessary. • Compression is attached to the offline process. It is expected that compression will significantly increase the processing effort. The RAM size is reduced with a compression ratio of 1:4〇. For this scenario, the FPGA is equipped with instant decompression logic that keeps up with the rate at which the grayscale is extended ("5 Gbit/s). Options B and C: Initiation Figure 60 shows an embodiment using inline rasterization. The gds-II format pattern data is accepted as offline processing for the offline embodiment of Figure 59, including: proximity effect correction, resist heating correction, and (if used) smart boundaries. The corrected vector pattern data and dose map are the tool input data formats used in this embodiment. This off-line processing is performed once for a given pattern design for one or more batches of wafers. Next, the in-line processing of the vector tool input data is performed to rasterize the vector data to produce B/W bit map data, which in this embodiment is a graphics system stream (PSS) format. This process is typically implemented in software and can be performed when new dose settings are set. As in the embodiment of FIG. 59, the pattern streamer then processes the PSS format data to produce extinction format data, including that it relates to beam position calibration, field size adjustment, and/or field as previously mapped in the bit map data. The correction of the full pixel shift in the X and/or γ directions of the domain position adjustment. This process can be performed in accordance with the field. Extinguisher format pattern 59 201123254 Data is then transferred to the lithography system for wafer exposure. Figure 61 shows a second embodiment using in-line rasterization. This is an embodiment similar to that of Figure 60 except that the correction for beam position calibration, field size adjustment, and/or field position adjustment is made on the vector tool input data. Since these corrections are made in vector data, both full pixel shift and sub-pixel shift in the gamma direction can be made. These corrections are typically implemented in software, and can be performed on a wafer basis. After the correction has been made, rasterization is performed to generate pss format data for input to the graphics streamer. Figure 44 shows the inline rasterization functional unit that it is assigned to the processing step. For this architecture, functional units 3 and 4 (rasterized) are performed inline. For this option, the input data for the lithography system will be described in a strip chart in vector format. Rasterization will be performed according to requirements (by wafer, by several wafers, by system (4)). In-line rasterization can be triggered by an overall offset or a change in overall dose. The agent of the field is set by changing the pixel area. The pixel area can be changed by changing both the X and Y pixel sizes. However, only X size = can be changed to some value (as discussed with respect to Figure 1G). For the fine tuning of the overall dose, a change in the size of the gamma size can be used. Assuming a fixed bit rate, the gamma pixel size is determined by changing the deflection frequency, Befeng, and using different pattern scaling factors. Because the rasterization results will be used for all % fields, you cannot consider a particular field. The sub-pixel offset of the field. Each Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ The corrections may include: 201123254 • Field mode shifts in χ and γ (only full pixel shifts). The parameter is that each field is updated once. • The overall pattern shift in X and ( (in sub-pixel resolution). The parameter is that each wafer scan is updated one or more times. • The overall dose change through the graphic target. The parameter is that each wafer scan is updated one or more times. The dose correction and sub-pixel shift of each beamlet are unprocessable. The root cause is the ability to shift in the X direction, its (4) (4) small beam mapping. To limit the error' this option will typically result in the use of a fairly small pixel size (approximately 2 nm). This option is a special case compared to architecture option B in the sense that a small bundle will write the same line for each field. In other words, the columns for the beamlet map are fixed and the same for each field. Due to &, the small beam specific correction can be compensated. S is a sub-pixel correction that is appropriate, and the beamlet will be written to the pattern with greater accuracy. Therefore, like the larger size (~3 5 nm), it does not cause a higher optical channel count towards the quencher. All corrections are supported, however, the field is in the ideal position, and therefore there is no offset between X 盥 /, Y between the fields. The processing flow may be different from architecture option A. For architecture option 7 L, the new bitmap must be generated frequently on each wafer or on several wafers from the input file. (F) Main scan. If the new map is regenerated, there may be a dependency on the wafer measurement (E1). Figure 45 /, 棰$ & ^ ” Should not be dependent on the processing flow. When there is no such dependency, the processing flow will be similar to the processing & process of Figure 35. When the effective estimate is for re-physiological + ^ The required tribute (slowly changing place > number) 'is not dependent. Therefore, the bamboo king starts early, but must be 61 201123254 must be confirmed after the actual measurement. If unexpected unexpected occurs Matching, heavy weight starts to regenerate and some production will be lost. Finally, the consideration is: If enough ram is available, the processing can be started as soon as possible after the main scan. This will increase the processing time frame by another 25 minutes. Support inline processing The solution is to treat the sheep element extremely powerfully to meet reasonable timing requirements. For the worst case condition (2.00 nm pixels, maximum stitching), the number of pixels to be rotated will be 35 G pixels per strip. The size of the vector data will be 606 每个 bytes per strip. In Figure 46, the architecture for inline processing is shown. The illustrated architecture shows a rasterizer, which will be Responsible for translating vector formats into inline processing tasks for stripe B/w images. The options for implementing inline rasterizers are: • Offline, processing, and control • Using FPGA logic “For instant rasterization, FpGA logic is used for the same purpose. For instant rasterization, many resources in FpGA must be used to meet performance requirements. For inline rasterization, use Fp (5A technology, available less than instant form) Resources to implement solutions. • Use GPU technology. The Graphic Processing Unit (Gpu) is a typical processor for video processing. These processing hacks are used to steer 3D images (games, Vista). The consumer system (desktop and laptop) is seen. The GPU is using a lot of parallelism. The G8 architecture utilizes 128 thread processors, while the current state of the art card GTX28 uses 240 threads. The performance of the processor is roughly one-fifth that of the core CPU. The performance of the GPU is obviously dependent on the degree of parallelism in its tasks. The rotation is a task that is fairly easy to parallelize. The dithering task of direction 62 201123254 is a certain degree (diagonal) parallel. • Multi-core CPU using the current state of the art. Today's multi-core cpu is extremely powerful. The example is Intel's new architecture: ~i 7 technology. The fpga solution is _ a relatively inexpensive solution. Compared to the architectural option d (in fpga instant rasterization), the performance requirements for this solution are much more relaxed (2.5 seconds for 7 stripes) This is 6 minutes longer than for a solid strip. So the 'FPGA is much smaller (and cheaper). However, the feasibility S depends on the feasibility of the VHDL's implementation of the algorithm. When evaluating software solutions, GPU technology will be optimal because the high parallelism available on the GPU will benefit the task of migrating. The downside is that GPU technology is rapidly evolving. This rapidly evolving hardware problem (at least by NVImA) has been addressed by providing a stable Compute Unified Dev1Ce Architecture (CUDA) API. This API is suitable for a wide range of graphics card models and versions. Today, there is even a product line for high performance computing (Tesla). This product line is for scientific computing and not for game mapping. For this architecture, the processing is described in the following steps. Entering the file in the format is transferred from the server to the hard drive. The rasterization module should process the input file to generate a new bit map before starting the initial scan or after the parameter changes. When the bit map is stored in the RAM memory 1 of the processing unit, the processing unit reads the bit map from its ram. This process is similar for architectural options A, B, and C. Rasterizer 疋 is implemented using FPGA #术. The logic will be similar to #for the instant thumbtization option. Inline solutions are lighter than instant solutions.

63 201123254 More. Therefore, fewer logic cells will be needed. For the FPGA solution, there are two options for the data stream. In Figure 47, a data stream is shown in which the FPGA stores its output directly in the PU-RAM. This solution is appropriate if the rasterized logic is combined with the same FPGA as the processing unit. In this case, the components share the same memory controller. According to the processing diagram of Fig. 45, the processing can be performed in parallel. However, the potential interference is the reason for separating the FPGA. Another possibility is shown in Figure 48, where the node CPU will take the negative results from the FPGA and store it in the PU-RAM. In Figure 49, the communication between the host and the GPU is shown. The host stores the program (core) and data in the GPU's DRAM and triggers the program. The multiprocessor extracts the data it needs from the DRAM and writes the result back to the DRAM. When the total job is completed, the host will extract data from the GPU's DRAM. The interface between the host and the GPU is typically a PCIe xl6 bus and involves DMA in the data transfer. When using standard GPU hardware, the interface between the CPU node and the GPU card is PCI-Express/16. The internal architecture of the GPU (see: Figure 51) shows that it is completely focused on parallelism. This particular GPU contains 30 multiprocessors and 8 multiprocessors per multiprocessor. This adds up to 240 processor pairs. Multiprocessors use the Single Instruction Multiple Data (SIMD) type and use crystal-loaded (fast) shared memory for their eight processor. To take advantage of the performance of the GPU architecture, its task is to split into multiple parallel tasks. The peachization task consists of two subtasks: transition and dithering. The nature of the task of transitioning is that it is fairly easy to parallelize. Scanning lines or even pixel-forwarding can be treated as separate processing. The nature of the dithering task is more than 64 201123254 serial 'because the quantization error propagates in two directions (on the same line in the direction of dithering and to the next line). However, when dithering in only one direction, the dithering is parallelized along the diagonal. The next line should be decremented by one or two squares to correctly handle the quantization error of the previous line. Disadvantages of using GPUs include: Gpu is not cheap; considerable power consumption at execution time (e.g., TDP = 2()() w); and it is not a common task to generate parallel codes for GPUs that use their power. Budu core CPU solution: When using a powerful multi-core CPU as the node CPU, the node CPU will be able to perform rasterization tasks. Figure 52 shows a typical data flow for this configuration. The CPU reads the vector input data (7) from the hard disk. The CUP will perform the rasterization task and store the bit map # pu_RAM(4). When scanning, the processing unit reads the bit map from the PU_RAM (5 disadvantages include: processor cost; considerable power consumption (Intel Core2 Ex^eme quad core processor: TDp=13() w); and, quite Low parallel spit (for 4 cores of the lntel c〇re2 quad core processor.) For inline rasterization, different solutions are possible. However, inline rasterization reveals some common features: pu_RAM size. As for offline flickering, inline rasterization requires bit maps to be stored in PU-RAM. Architecture option B requires a small pixel size (eg 2 〇〇 nm, see appendix ai). The number of (uncompressed) bit maps of the g-bytes, ten is less than the architectural option c, using larger pixels (eg, 3 5 〇 nm). For 3.5 〇rnn pixels, 20 G bytes will be appropriate. RAM load time. 1 ; This solution 'assumes that only vector input data is stored on the disk 8.5 GB. Whenever a new bit map is required, the vector input data is 65 201123254 read from the disk and rasterized and stored in pu_ram. In this case: the disk data rate does not seem to be a bottleneck. The bottleneck for this solution will be the rasterizer. Its performance depends on many factors and cannot be easily predicted. An alternative would be to implement rasterization at an earlier stage. The bit map can be misplaced in PU-RAM or on a disk. Storing the bit map between t on a disk has the disadvantage of having a significant bottleneck for load time (see: Architecture Option A). Disk load time. The vector input data for the new scan must be downloaded from the vocabulary. The server will obviously be the bottleneck for communication. The option for improved disk load time is to increase the bandwidth from the feeder to the node or to compress the bit map data on the server. Storing 10 versions of the bit map on the disk storage unit will require 85 GB of storage capacity. Improved reliability (and read performance) prompted the use of a mirrored configuration (RAID 1} and the use of two 100 GB disks. Suppose the main algorithm is largely parallelized, between the cup and the outline. Performance The comparison is based on the following characteristics: the intel cpu core outperforms the thread processor by a factor of 5; "the cpu cpu contains 4 cores; and the GPU contains 20 distinct processors. Again assume parallelism. The full use, performance ratio (Intel: Gpu) is the four core: GPU = (4 * 5): 240 = 1: 12. In fact, several factors will reduce this ''ideal' ratio" factor: execution cost The difference (for this brand of GPU, the cost of integer division is quite high); the degree of parallelism; the degree to which parallel codes can be written; how many threads can be executed in a limited amount of local memory; SIMD) processor usage. In the SIMD group 66 201123254 typically has 8 processor. This means that the execution path is extended because it always (serial) executes the two sides of the branch. On the other hand, like Intel Multi-core solution for processors Shared cache memory. Depending on several factors, when multiple cores are active, the performance of each core will be degraded. In this section, make use of it - CPU rasterization (transfer and dither) Estimation of performance. In order to estimate performance, the transfer and dither module has been implemented in C++. Only use the C++ 00 feature instead of any performance critical instructions like: new, delete or like serial or 伫Any advanced data structure of the column. The 64*1000 nm grid is used as a unit for indexing and dithering. By comparing the vector format input with the bit map output, it is visually confirmed that the transition and dithering are as As expected, the Visual C++ 2008 compiler has been used to enable speed optimization. The algorithm used for the conversion is the scan line method. Use the current edge table to maintain its intersection with at least one scan line (pixel line). Edge group. The pixel size is 3.5nm (Architecture Option C). Although up to 64 edges are specified, 52 (81%) per cell is a reasonable average. For measurement, a machine with a modern CPU has been selected. cpu At 2.14 GHz The Core 2 Du〇 (64〇〇) line has 2GB of RAM for executing the Windows operating system. The input vector format used is the specification of a set of closed polygons in the grid. The dose grid is omitted 'but the processing is included in γ Dependent dose factor. For the shift in the y direction is always G, but the algorithm is based on the operation of the line dependent shift value. 'Hetian 67 201123254 code optimization is carried out by measuring the horse improvement. The regular parser is not applicable because of its limited temporal resolution. & However, it has been used in the Wni 32 API "QueryPerf〇rmanceC〇unter". This counter uses a CPU timestamp counter in ns resolution. The code is already based

The result of QueryPerformanceCounter is optimized by humans. After optimization, the load is distributed across the application in the following fractional parts: 55% for reversal, 27% for dithering, and 18% for input processing. The single core of the machine can perform a job_frame transition cycle in 8.7 seconds. This translates to U, 494 cycles per second. The execution with dual cores is scaled by a few m linear methods (87 single core, (10) coffee grid - > 8.8 dual core 200, _ grid). The whole strip is composed of 22 〇〇, _ 格. Therefore, one core will take 194 seconds in i strips. Assuming linear scaling, this means that when 7.5 cores are used, 14 strips are converted to J within 6 minutes. The Core2 Duo (6400) is no longer the top model of the Intel cpu. Therefore, core performance should be improved by a factor (for example: 3〇%). Another aspect] knows that using multiple cores is never possible to scale in a linear manner. Assume that these two factors will cancel each other out. The performance results are the sum of: the algorithm used; the scale (size to column); the integrity of the algorithm; the specific optimization used; the total time spent optimizing; compared to the prototype And in the actual configuration used by the cache /. The memory, and the relative performance of the CPU that will be used in the final configuration. As discussed for option A, it is possible to compress the image that is held in pu_RAM. The rasterizer should compress its dithered or grayscale image, 68 201123254 and the processing unit FPGA should decompress it and select the dither. Architecture B will actually benefit from compression and oversampling techniques. It is no longer necessary to use 2 fibers for each channel. Architecture C has used a fairly large pixel size and will benefit only from compression. This means a smaller PU_RAM with less load time. However, the decompression logic should be attached to the processing unit FPGA. However, decompression will have a significant impact on the in-line processing workload. Option D: Instant grid servant. Figure 62 shows an embodiment of its use of instant rasterization. This is an embodiment similar to that of Figure 61, except that rasterization is performed further in the process during immediate processing, typically performed by hardware. Corrections for beam position calibration, field size grading, and/or field position adjustment are made in vector format pss format data, and then rasterized to convert this to a B/w bit map. Since the correction is made on the vector data, the 像素 and γ-direction full-pixel shift and sub-pixel shift can be made. ... Figure 53 shows the functional blocks of this architecture. For this option, function sheets 7L 3 and 4 (rasterized) are executed for immediate execution during execution. The corrections include: θ • Pixel shifting (full pixel and subpixel) corrections in χ and γ. Parameters 更新 Each field is updated once. • Dose correction for each subchannel. The parameters are updated once per field. Each channel is corrected for the calibration of ¥. The parameter is the update of each field. • The annihilator timing offset correction. Moxibustion age θ > plus ~. I positive parameter 疋 mother wafer scan update one 69 201123254 type streamer will use this data as input. Fly chart The graphic streamer covers the Β/W bit map. In t instant transfer and dithering, sister mapping. All kinds of corrections during the transition and dithering. From the BAA/bit mapping, the pattern string box will multiplex the data for all of its small bundles of channels and = the fiber will transfer the data to the extinguisher wafer. ° Two resources to be used to stream data to the laser. :: consists of two steps: getting the data from the memory and logically: eight-column to the pixel, due to the sub-beam ordering (4) to the box. The first step can be composed of the actual data of the vector data = 疋 from the memory data of the recalled column. In order to transfer vector data to pixels 'each strip is divided into sub strips with vector 001. For a soft edge of (maximum) 500 nm, the number of prince strips is 2000 + 5 〇〇 + 5 〇〇 / 62.5 = 42.8 sub-strips. Each child is a bad sorcerer ^ /, - Hz operation, strips ^ road transfer column. Each pipe will have about 8 pipes and will therefore produce nearly 5

Cjbit/s 〇 In the pipeline's 7§ @.., only the FIFO is used to cross the clock from the memory clock domain to the processing clock domain. . The boundary of the pulse. This FIFO also acts as an intermediate storage buffer, since the record & ^ 'member width must be shared across multiple stripes. The FIFO contains both the borrowing angle data and the dose mapping and town data. The transition application can be randomly addressed within the FIFO base. The FIFO must have data containing at least three blocks to allow for a 穸 对于 ‘ 对于 对于 。 。 。 。. The data for each block contains 272 bytes. The number of three blocks is like ~816 bytes. Standard block random access memory 70 201123254 Volume 3 has 1 8 K bits of data = 2 κ bytes of data. This means: From the data size point of view, each block of random access memory (bI〇ckram) can be applied to three sub-strip pipes 'however' from the point of view of data availability, each pipe should be used at the top (4) Block random access memory. Each sub-strip pipe requires some internal FF and Ιυτ for processing. The number of available FF and LUTs and the number of blOCKRAMS required are more than necessary. Rearrange the pixels for multiple exposures. At the bottom end of the sub-strip pipe, or if the data is mapped directly in the memory of the bit in the memory, the data is stored in another fif. This FIFO must have at least 245 lines of data, which is required to write pixels in small bundles. Each line will (maximally) contain nm/2 (10): 15000 pixels. 15,000 pixels * 245 lines = 367, 5 〇〇 bits. This is equal to 20 block random access memories, which are rounded into 32 block random access memories for processing. The framing/multiplexer reads from these 32 block random access memories and forms a frame suitable for transmission to the laser. These blocks are stored in another FIFO block random access memory, which is necessary as a non-synchronous boundary between the clock regions and as a flexible storage unit. Lattice-based input format The vector U method is typically used to generate graphical data, such as the m or 〇ASIS format. As mentioned above, different modes of operation may be used for the charged pull lithography system. The above-mentioned mode is an instant rasterization mode, in which the pattern data of the vector-based input format is (4) and is processed by the processing unit.

71 201123254 (such as: FPGA) is processed on the fly (ie: the pattern data for the wafer-group field) is at least partially processed when the scan of the group field occurs. The grid-based input format can be used This instant rasterization mode. One embodiment of the input format describes two aspects: feature layout and dose rate. The feature layout is described in a grid-based manner and is suitable and optimized for instant fpga transitions and dithering. The dose rate is described by a fixed size grid covering all feature areas (eg, field). A grid-based format for pattern data can produce a data set having a more predictable size, facilitating the streaming of pattern data to the lithography system for immediate and/or hardware processing. Pattern data in vector format provides a relatively unpredictable size per cell. Pattern data in a bitmap mapping format can be used, but will be compressed for transfer from the preprocessing system to the lithography system. The amount of compression of the number of bit maps may vary appreciably per cell, depending on the features in the cell. Streaming such compressed data to a lithography machine and then decompressing the data results in an unpredictable transmission rate of uncompressed data. It is advantageous to know in advance how much data (bits) are contained in each cell and what compression factor is achieved if the pattern number is compressed (e.g., when compared to the total size encoded in the bit map format). The grid-based format is a design tool

Sit:. This is desirable because it provides a guaranteed size-based pattern data ~D memory of a certain size (the size of the memory selected at the time of design)' which is substantially smaller than the size of the uncompressed bit map data. For the pass: compression bitmap algorithm (such as: ZIP) compressed bit map can not provide this U ° is also expected 'because the guarantee of grid-based graph data can provide maximum time, the system converts to bit Mapping, which is important if instant grid 72 201123254 occurs. Even if 'something from the bit map field is encoded from the cell-based format, the '1 rights-restriction=specific cell must be coded in the slot case (no need to know the GDSII format as if The special inspection case, for example, in this area), the feature 疋 randomly exists in the slot case, finds the grid-based format because it is arranged according to the grid, to the lithography system, and the pattern data is waiting The smoothness of the scan is quite straightforward compared to the vector format. The order of the lattices of ^ is the formula of the = lattice, and there is an additional amount of "(four)" because only the special code in each cell is a code. This < sets the absolute position of the feature provided in the field. (4) The feature ^ = ^ is limited to the size of the cell) and therefore defines fewer bits than the field. : in the grid-based input format describing the feature layout

0.2% step size LSI. 73 201123254 For the feature layout format, the minimum feature-to-feature spacing is essentially within the distance of the distance between the P && It means that only a minimum of two can occur in the minimum feature. (4) Change (for example: grab > coffee or 〇 ff-> ON) In Fig. 67, gg - , .. shoulders are not an example of a pattern layout, which has a small feature spacing 〇 >) (lighter) The color (four) domain ^ Μ (four) from the most characteristic description of the important result is that 64 χ 6 should describe up to 4 ribs 6 wood, 褥 褥 i i grid index provides its reference position ... row proud position to describe. Within the transition grid The features can be used relative to the _ cell (the partial w sign can be described by its angular or by a straight line. The line angle can be limited to a multiple of 45 degrees, and the vector can only be tamped in the possible direction, as in Figure 69. The eight orientation codes are pairs: the assignment of each possible orientation as shown in Figure 69. Figure 68 illustrates the concept of the angle (c〇rner). The grid (ceU) is shown as containing the edges of the feature (on the right) A straight line at the edge of the feature (on the left). Both the corner and the line are treated as "edges." The corner A is defined by the position of a (for example: ^, γΑ) and (for example, using the orientation code Edge 2 and Edge 2 = 4). Defined by two or eight vectors. By definition, in the direction of movement from Edgel to Ehd in a clockwise direction The area is the active area. In the same way, the line is described by the 'virtual edge' point B (for example: χΒ ' γΒ) and the two edges (for example: Edgel=4, Edge2=0). The position of this virtual corner is Any point on the line defined by it. Furthermore, the area in the clockwise direction of movement from Edgel to Edge2 is the active area. 201123254 Within the grid, the corners of the same feature should be square, 1 踽 helmet ^. , Bedin's morning husband... 4 yards for the four matching corners in the 64nm x 64nm grid. The table on the left side of Figure 70 shows the parameters that fully describe the features. The corners are defined by their angular coordinates (X, γ). Description, and the edge description is based on the angular orientation of the direction defined in Figure 69. From the angular coordinates and the azimuth code, it can be determined that all the corners in Figure 70 are described as a single feature. ... for FPGAs (or other types of hardware) Processing of the processor, it is advantageous to have a fixed-size data structure. This makes it easier to address the cell description in memory and to help keep the FPGA logic simpler. Figure 71 shows the corners in the cell. Description of the complex An example of a miscellaneous feature shape. A straight line along the 45-degree and _45-degree azimuth is also used to define the characteristic feature of the displayed feature. The minimum feature spacing ensures the maximum number of corners in the cell. The characteristic of the azimuthal edge, the largest dimension of the lattice is its diagonal: its length is equal to the grid size multiplied by the square root of the square lattice $ 2 (for example: 64 * ^ for 64 nm * lattice). The feature spacing is less than this $angle length, the risk is that there may be more than 4 corners per cell. This is shown in Figure 72. On the left, the legend shows a regular grid of square features with a square feature with a 64 nm pitch Positioned in a 64nm grid, and each grid has 4 corners (the corners are indicated by small circles). On the right side, the grid of = shaped features is rotated 45 degrees. The emphasized corners show that the six corners are in the middle of the grid. To solve this problem, several solutions can be applied:

L S 75 201123254 • Specify a larger minimum feature spacing for the 仏45 degree line, at least equal to the length of the diagonal of the grid (for example: Μ X V^nm for a 64 nm square). • Reduce the grid size so that the grid diagonal is equal to (or less than) the minimum feature spacing (for example: the minimum feature spacing for 64 nm is ^(10)(10)). • Allow a larger number (eg, six) of corners per cell. • Allow a variable number of corners for each cell. In the following description, 'the first option is assumed above. Adjacent effect deer chrome requires proximity effect correction to improve the pattern (especially the corners) after processing the wafer. Proximity effect correction can be counteracted by locally fine-tuning the geometry or dose. It is assumed that the proximity effect correction is performed by geometrical variations, using a serif that surrounds the corners, which typically has a length of (iv). In Fig. 73, an example in which the serif is attached to some of its corners is shown. Each corner is preferably provided with an option to incorporate the serif at a particular corner. As shown in Fig. 73, an important result of such a technique is that the serif defined in the corner of the lattice (for example, the characteristic B serif of the lattice 2 in the figure) can be partially rotated in the adjacent lattice. (For example: Feature B serif extends to grid 3). Alternatively, a feature having all of its edges in a cell (e.g., feature A in cell 1) requires a portion of its serif to be indexed in the adjacent cell (e.g., feature A serif in cell 2). In order to deal with this, different ways are possible: • Share information about the edges of the serifs with adjacent partitions. • Once the external serif edge has the effect of shifting the grid, the additional information is encapsulated (copied) in the grid definition. • Describe the serif as a normal corner. This solution significantly increases the number of edges (extremely variable) per division. The IL quantity grid (grid, in addition to the characteristic geometry, the dose rate is an important system parameter, which is significant on the micro scale. The dose information can be described by providing a dose grid, the dose grid containing one per grid Dose rate (dose information may be provided in other ways, for example by correlating a dose value for each feature with a dose size 疋 typically equal to or less than a desired critical dimension (CD). In theory, the dose grid is irrelevant The grid grid. The two options for working with the two grids are: • Define the two grids without regard to each other. • Align the two grids and select the integration. For FPGA processing, the dose is It may be advantageous to combine a grid with a reticle grid. The dose grid size is typically smaller than the size of the reticle grid. ^ can be done, for example, by embedding (3x3) 9 dose grids within the transition grid. The grayscale value can vary between 1% and 5〇% in 0.2% steps. Therefore, each dose cell requires 8 bits. However, the result is to link two separate concepts. The pitch value changes, also has The inevitable result of the size of the dose grid. The pixel grid size and position are preferably elastic. The pixels can be non-square, but will always have the same scale in one strip/channel. The pixel can be (the worst) Case) Four sub-columns are rotated. Because of the sub-pixel shift, each column can be used with different (Y-direction) alignments. 2011-11254 The following specifications are provided for one embodiment. Contains blocks and additional information with up to 4 corners of 64 by 64 nm. Edges are vectors starting in the corners, Edge丨 or Edge2, and the clockwise angle from Edge 1 to Edge2 defines the active side. The corners are the corners of the features in the grid. When a line is crossed and there is no actual corner, the corners can have an angle of 18 degrees. Assuming that each of the transitions has a maximum of 4 corners, the specification of the angular data is楛下下+ : Name Number of Bits Basic Principle X Position 8 64 nm®〇.5 nm Y Position 8 64 nm®0.5 nm Edgel Direction 3 8 Directions Edge2 Direction 3 7 Directions Possible, Equal to Edge 1 is a Special Case: Project No serif size used 5 0 means cutoff (〇ff) total 27 In order to calculate the size of the serif from its field value, different strategies can be used, for example: look up the table '丨, the field value is used as an index in a predefined table, Or by calculation (for example, serif size = value * 0.5 nm, therefore, the range is 〇. 15 5@G 5nm, assuming a positive serif size). Specifications for the reticle data of one embodiment Is provided in the following table: 78 201123254 Name of the number of bit cells per cell Total bit angle 27 4 108 Dose mapping 3x3 8 9 72 Total 180 The following table summarizes the amount of data when using the above format. For this number, the assumption is that there is no stitching. -- - --•m ,~ f ^ Name formula result number of bytes per cell 180 bits / 8 23 bytes Number of cells per strip 3 3 mm / 64 nm * 2jLtm 16E6 grid / 64 nm ^ The number of cells is 13000*16E6 209E9 The number of bytes in the field of Gezhi 209E9*23 The number of bytes in the band of 5T bytes is 16E6*23 3 The number of bytes in the 70-bit byte may exist. For example, it is expected that multiple grids contain less than 4 corners, and for all dose grids, the dose rate = month t* is the same value. 0 The fixed-size data structure will alleviate the FpGA design (addressing and loading) Into the task, but with consequences for the memory. For communication to (disk) storage, the standard ink reduction technique can be used to transfer the data _. This ^ usage record is filled with the same value (example (6): is valid for unused edges). Compression is also valid for repeated values, as for agent Dan: zero). Some of the design problems for the above embodiments are: 79 201123254 ♦ Up to 4 corners per cell may not be sufficient; * Finding serifs in adjacent cells is expensive in processing time and memory and if possible Avoid; *The serifs may be different from the expected shape; • Fixed angles per grid are desirable for hardware implementation; • A fixed number of corners per grid creates a large amount of data; • Each grid is small A fixed number of corners creates a lack of flexibility; • From the theoretical point of view of the information, encoding all the corners is over-information, but significantly beneficial for implementation in hardware; • The resolution of the corners is preferably 0.25 nm instead of 0.5 Nm; • Encoding only half of the edges may be sufficient. The larger block co-chops i as a compromise between a large number of large and small fixed number of corners, one possibility is to limit the maximum number of edges for larger data blocks, for example: in the mechanical scanning direction is about Big 16 times. It is assumed that the local maximum number of corners in a region of this larger block will be compensated for by the smaller number of corners in another region of the block. An upper limit of more than 4 at the maximum number of corners is undesirable due to the use of a memory. However, the lower limit of use will not cover all possible situations. As an intermediate solution, consider the following scheme: encode the data in a block larger than the current cell (for example, a block of i 6 cells at a time), and limit the number of edges to the 'where' part of the block. The maximum number of corners can be higher. In this scenario, the serif is coded as if it were an edge, which is helpful. 80 201123254 In order to implement this embodiment, the following changes can be made to the above embodiment: • Define a block having a γ direction (deflection direction) of 62 5 nm and an X direction (mechanical scanning direction) of nm; The Y size of the block is reduced from 64 to 62 5 ηηι. This has two advantages. 16*62.5 = 1000 nm and 62.5/0.25=250, which can be efficiently encoded in 8-bit; • The fee map can have a resolution of 3 1 25 X 31 25 nm (1〇 • 1/32 of 〇〇nm); • The maximum number of corners is set to 64 per block (average of 4, 62, 6 x 62.5 nm for 4 corners); • The serif is encoded within the data, Like the edges and corners themselves. The g lower specification is provided for this embodiment: Name — 丨 1 Value Transfer block 62.5 by 1 〇〇〇 nm block containing 64 angular and dose information. Edge The vector at the beginning of the corner. Edgel or Edge2. The clockwise angle from Edgei to Edge2 defines the active side. Angular angle of a feature in a lattice. If the line is traversed without the actual angularity, it may also be an angle with an angle of 180 degrees. Assume that each transition column has a maximum of 4 corners. The specifications for the angular data for this embodiment are provided in the following table:

81 201123254 Name Number of Bits Basic Principle X Position 12 1 〇〇0 nm (Sy〇.25 nm Y Position 8 • --- 62.5 nm (®y〇.25 nm Edgel Direction 3 - One 8 Directions Edge2 Direction 3 7 The direction is possible, equal to Edgel is a special case: the project is not used for a total of 26 ~ - one --- ^ gig: the specification of the transfer column data of this embodiment is the total number of bit units provided in each unit of the table below name Angle 26 64 1664 Dose Mapping 3x3 8 64 512 Total 1 2176 The following table summarizes the amount of data when using the above format. The assumption for this table is that there is no stitching. This estimate does not consider rounding, which will The information is stored in the actual RAM. Name formula result The number of bytes per block 2176 bits / 8 272 bytes The number of blocks per strip 3 3mm / l 000nm * 2 / tm / 62.5nm 1056000 Number of blocks per field 13000*1E6 Number of bytes per field in 13.7E9 block 13E9*272 3.4T bytes Number of bytes per strip 1E6*272 274M bytes exist The opportunity to compress", for example, 'expected: multiple blocks are 82 201123254 contains less than 64 corners, and the dose rate will have similar values for adjacent dose grids. However, compression also leads to more complex implementations. Data may be compressed as it is transported through the system. Theoretically, it would be unnecessary to have all the angular bats with all the coordinates. However, this dramatically reduces the computational effort in the implementation. Also coding the block boundaries is the number of added edges that can be beneficial, but The computational effort in the FPGA will be reduced more. In addition, it should be taken into consideration that the entire transfer process should be performed from the second end of the data. In one direction, it will be "obvious" and be careful. , —Bebe, it may cause problems when scanning in other directions. The block is also likely to be positioned in the direction of the deflection scan. There are two reasons why this should not be the case. The parallelism of the implementation must be within the strip. Several strips process the data' and this would be impossible if the data is in this way. In addition, the granularity in the deflection scan direction will be 1GG() nm, and (4) the stitching is undesired.纟 The current situation 'the granularity of the strip width including the stitching area is 62.5 nm °. The data should be encapsulated in the memory should get some ideas. If the data for the dose mapping is stored in an individual bit path different from the angular data, there may be The benefits of using the previous paragraphs are as follows: • Small amount of data (eg 3.5 TB instead of 5 TB); • Feature resolution is better (eg 〇2 5 nm and dt Λ c \ m nm) Instead of 0.5 nm); • For the serif and for the local number of the corners of the target, the elasticity is higher; • The implementation is less complicated. 83 201123254 圊-beam lithography system FIG. 74 shows a simplified schematic diagram of an embodiment of a charged beam multi-beam lithography system 1 based on electron beam optics that does not have all electron beamlets system. The optical system is described in detail in U.S. Patent Application Serial No. 61/045,243, the entire disclosure of which is incorporated herein by reference. Such a lithography system suitably includes: a beamlet generator that generates a plurality of beamlets; a beamlet modulator that maps the beamlets into modulated beamlets; and, a beamlet projector Used to project the beamlets onto the target surface. The beamlet generator is typically comprised of a source and at least one array of pores. The beamlet modulator is typically a beamlet extinguisher with an extinguishing deflector array and a beam stop array. Beamlet projectors typically include a scanning deflector and a projection lens system. The wafer positioning and support structure of the present invention is not explicitly shown in FIG. The lithography system 1 is particularly adapted to perform several scan functions in combination with so-called two-time or singularity & This improved accuracy of the scan line to the target surface enables a second scan that fills the gap left in the first scan sequence. In the embodiment shown in FIG. 74, the lithography system includes an electron source '3' for generating a homogenous, extended electron beam 10 kev that maintains a relatively low temperature, preferably low, and the electron source is preferably correlated. Between 1 and -l〇kV, although the electron beam 4 from the electron source 3 also collimates the collimator lens 4 of the electron beam 4. The beam energy is preferably at about 1 to achieve this, the accelerating voltage is maintained at the target of the ground potential and other settings can be used. Pass double octet and subsequently for 5. As will be appreciated, the collimator lens 5 84 201123254 can be any type of collimating optics, and then the 'electron beam 4 strikes the beam splitter, which in one suitable embodiment is the aperture array 6A. The aperture array 6A blocks a partial beam and allows a plurality of beamlets 2 to pass through the aperture array 6A. The aperture array preferably comprises a plate having a through hole. Thus, a plurality of parallel electron beamlets 20 are produced. The second aperture array 6B produces a number of beamlets 7 from the respective beamlets. The system produces a large beam 7 ', preferably about 1 〇, and loo ooo, although it is certainly possible to use more or less beamlets. Note that other known methods can also be used to generate a collimated beamlet. This allows manipulation of the beamlets, which results in a benefit to system operation, especially when the number of beamlets is increased to 5,0 or more. Such manipulation is achieved, for example, by a concentrating lens, a collimator, or a lens structure that converges the beamlets onto an optical axis (e.g., in the plane of the projection lens). A concentrating lens array 21 (or a group of concentrating lens arrays) is incorporated behind the beamlet generation aperture array 6A for focusing the beamlets 2 朝向 toward corresponding openings in the beam pupil array 10. The second aperture array 6B produces a beamlet 7 from the beamlet 2〇. The beamlet generation aperture array 6B is preferably incorporated into the beamlet extinguisher array 9; for example, the two can be assembled together to form a subassembly. In Fig. 74, the lash array 6B generates three small bundles 7 from the respective sub-beams 2 , which impinge on corresponding openings of the beam aperture array 10 such that three small pupils are projected by the end module 22 t The projection of the lens system to the target produces a greater amount of beamlets for each of the projection lens systems 6B in the end module 22. In one embodiment, 49 small bundles (arranged in a 7x7 array) are indexed. In fact, ' can be generated from each sub-beam by a pore array through a single projection

85 201123254 Lens system 'Although the number of beamlets per sub-beam can be increased to 2 or more. The stepwise generation of the beamlet 7 from the intermediate stage of the beam 4 through the beamlet 20 has the advantage that a relatively limited beamlet 20 can be used and positioned relatively far from the target to achieve the primary optical operation. One such operation concentrates the beamlets to a point corresponding to a projection lens system. Preferably, the distance between the operation and the convergence point is greater than the distance between the convergence point and the target. Most suitably, an electrostatic projection lens is used in combination here. This convergence operation enables the system to meet the need to reduce spot size, increase current, and reduce dot unwinding to achieve reliable charged particle beam lithography at advanced nodes, especially at nodes with critical dimensions less than 90 nm. The beamlet 7 then passes through the modulator array 9. The modulator array 9 can include an array of small east extinguishers having a plurality of extinguishers, each of which is capable of deflecting one or more electron beamlets 7. The quencher is an electrostatic deflector that is more specifically providing first and second electrodes, and the second electrode is a ground or common electrode. The beamlet extinguisher array 9 and the east beam array 1 are constituting a modulation device. Based on the beamlet control data, the modulation mechanism 8 adds the pattern to the electron beamlet 7. The ^ type will be projected onto the target 24 by means of components present within the end module 22. In this embodiment, the beam stop array 1G includes an array of apertures for allowing the beamlets to pass. The I pupil array comprises, in its basic form, a substrate that provides a via, typically a circular aperture, although other shapes may be used. In one embodiment, the substrate of the beam stop array H) is formed by a stone wafer of regularly spaced via arrays and can be coated with a metal surface layer to prevent surface charging. In one embodiment, the metal is a type that does not form a natural oxide 86 201123254 skin layer, such as: CrM〇. In the example, the path of the beam stop array 10 is aligned to the square of the beamlet extinguisher array 9, ^ ^ D ^ β , the hole. The beamlet quencher array 9 and the beamlet array 10 operate to block the beamlets 7 or pass the beamlets 7. If the small beam J 9 deflects the beam, it will not pass through the corresponding aperture in the beamlet array 1/, but will be blocked by the beamlet blocking array 1@@ substrate. But to the right, the beamlet extinguisher array 9 does not deflect the beamlets, which will pass through the corresponding apertures in the beamlet array 1G and will then be projected as the spot on the target surface 13 of the target 24. The 2-shadow system step-by-step includes a data path for supplying beamlet control data to the small bundle of de-emphasis arrays. The fiber optic can be used to transmit the beamlet control data. The modulated beam from each fiber end is projected onto the photosensor of the beamlet extinguisher array. Each beam holds partial pattern data for controlling one or more modulators that are coupled to the photosensitive element. Subsequently, the electron beamlet 7 enters the end module. Hereinafter, the term "small beam" 疋 refers to the small beam that has been modulated. This type of modulation beamlet is effectively included in a sequential part of the time mode. Some of these sequential portions may have a lower intensity and preferably have a zero intensity, i.e., stop at the portion of the beam stop. In order to allow the beamlet to be positioned to the beginning of the subsequent scan cycle, some portions will have zero intensity. The end module 22 is preferably constructed as an insertable, replaceable unit that includes a variety of components. In this embodiment, the end module includes a beam aperture array i 〇, a scanning deflector array 11 , and a projection lens arrangement 丨 2, although not all of them are included in the end module and In different ways, 87 201123254 is placed. After passing through the beamlet 1G, the modulated beamlets 7 pass through the bail deflector array U, which provides the respective beamlets 7 in the X- and/or Y-direction (solid ^ two straight; undeflected beamlets) Deflection of the direction of 7). In this embodiment, the deflector array 11 scans the electrostatic deflector, which enables a relatively small drive voltage to be applied, as will be explained below. The beamlets are then passed through the projection lens arrangement 12 and projected onto the target surface 24 of the target ' (typically wafer) in the target plane. For lithography applications, it is intended to include wafers that provide a charged particle sensitive layer or resist layer. The projection lens arrangement 12 focuses the beamlets, preferably to a geometric spot size having a diameter of about 10 to 3 nanometers. Projection lens configuration ι2 of this type preferably provides a reduction of about 100 to 500 times. In the preferred embodiment, the projection lens arrangement 12 is advantageously positioned proximate to the target surface. In some embodiments, the beam protector can be positioned between the target surface 24 and the focused projection lens configuration 12. The beam protector can be a foil or plate that provides the necessary porosity for the resist particles released from the wafer to be absorbed before it can reach any sensitive elements in the lithography system. Alternatively or in addition, the scan deflection array 11 can be provided between the projection lens arrangement 12 and the target surface 24. In summary, the projection lens arrangement 12 focuses the beamlet 7 to the target surface 24^ In addition, it is further ensured that the spot size of a single pixel is correct. Scanning deflector 11 deflects beamlet 7 throughout target surface 24. In addition, it must be ensured that the pixel position on the target surface 24 is correct on the micro scale. In particular, the operation of the broom deflector 11 must ensure that the pixels are properly matched to the pixel grid, which is followed by the pattern formed on the target surface 24. It will be appreciated that the micro-scale positioning of the pixels on the target surface is suitable for enabling the wafer positioning system underneath the target 24. High quality projection of this type is related to get a lithography system that provides reproducible results. Typically, target surface 24 contains a resist film on top of the substrate. A portion of the resist film will be chemically modified by the application of a small beam of charged particles (i.e., electrons). As a result, the irradiated portion of the film will be somewhat soluble in the developer, resulting in a resist pattern on the wafer. The resist pattern on the wafer can then be transferred to the lower layer, i.e., by performing etching and/or deposition steps as is conventional in semiconductor fabrication techniques. Obviously, if the illumination is not uniform, the anti-synthesis agent may not be developed in a uniform manner, resulting in errors in the pattern. "Our many such lithography systems utilize a plurality of small beams. The deflection step should not cause any difference in the illumination. In one embodiment of such an optical system, space is reserved between the first and second groups of beamlets 7 from adjacent beamlets 2A. Further, the system is defined to include a beam region 51 and a non-beam region 52, as shown in FIG. The division into the beam region 51 and the non-beam region 52 is in the presence of the modulation device ♦ and the end module (e.g., projection lens system). A non-beam region 52 can be utilized in the lenticular lens system for providing a mechanical support structure to minimize any vibration. The space corresponding to the non-beam region 52 can be filled, for example: = The pattern is the space that is transferred to the target in a subsequent step of the transfer process. This subsequent step is performed after moving the target relative to the column. The specific order in which the commands are filled is also known as the write strategy. The present invention has been described in relation to certain embodiments discussed above. It is to be noted that various structures and alternatives have been described which may be used in conjunction with any of the embodiments described herein, as will be apparent to those skilled in the art. Furthermore, the embodiments are susceptible to various modifications and alternative forms that are well known to those skilled in the art without departing from the spirit and scope of the invention. The present invention is intended to be illustrative only and not limiting of the invention, which is defined in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Various aspects of the present invention and some examples of embodiments of the present invention are illustrated in the drawings, in which: FIG. 1 is a conceptual diagram showing a maskless lithography system; FIG. 2A is a charged particle micro A simplified schematic of an embodiment of a shadow system; FIG. 2B is a simplified diagram of elements in a data path; FIGS. 3 and 4 show a portion of a beamlet blanker array; FIG. 5 is a diagram showing writes on a wafer that is divided into fields Fig. 6 is a diagram showing a scanning line bit frame and beam deflection; Fig. 7 is a diagram illustrating an example of pattern offset and pattern scaling; Fig. 8 is a diagram showing the use of four beamlets for writing Figure for an example of a possible interleaving scheme for strips; Figure 9 is a simplified illustration of a four beamlet extinguisher array and scan line pattern; Figure 1 表格 Table for the value of the factor κ and the distance between scan lines Array Figure 1 is an illustration of nine small beam arrays showing beam spacing pb, projection pitch Pproj, grid width Wpr〇j and tilt angle 90 201123254 Figure 12 is an illustration of the box start indicator bit; Figure 13 Schematic diagram of a node with X processing units Figure 14 is a conceptual diagram of the channel position of each scan; Figures 15 and 16 are conceptual diagrams of the allocation of channels for two scanned processing units; Figures 17 to 23 are graphs, showing the results of simulation experiments of data path capacity 5 shows a change in the lithography machine capacity. FIG. 24 is a flow chart showing the dependence of the processing in the lithography system. FIGS. 25 and 26 are diagrams illustrating an example of the \ and 丫 pattern shift; FIG.

Figure 2 is a simplified functional block diagram of the data path; Figure 29 is an illustration of the layout pattern features overlaid on the strip; Figure 30 is a legend of the dithering process; Figure 31 is a bit in the bit box Figure for the meta-shift; Figure 32 is a graphical representation of the beamlet position for the parameters N=4 and κ=3; Figure 33 is a schematic flow diagram of the data processing and storage elements of the data-only path;

Figure 36 is a block diagram of the components of Figure 33. Figure 37 is a block diagram of the elements of Figure 36; the functional diagram of the stream; the number of elements between the graphs of the streamer node

ISI 91 201123254 Figure 38 is a block diagram showing details of the processing and transport elements of the data path, Figure 39 is a functional block diagram of a portion of the data path including compression and decompression functions; Figure 4 is a diagram illustrating a dithered monochrome An example of a test image; Figure 41 is a functional block diagram of a portion of the data path including compression and decompression functions after channel tracing; Figure 42 shows an example of a truncated bit map of a cell; A conceptual diagram of input pixels and large output pixels; Figure 44 is a functional block diagram of another embodiment of the data path; Figure 45 is a flow chart showing the dependency of the processing of the data path of Figure 44; Figure 46 is a diagram Block diagram of elements of a type of streamer node; Figures 47 and 48 are functional diagrams of the alternate data stream shown in Figure 46; Figure 49 of the diagram of the streamer node is shown in Figure 49. A functional diagram of a stream of graphics; a schematic diagram of communication between components; an alternative data flow between components of a node; Figure 51 is an illustration of the internal architecture of a coffee channel for data access; Figure 2 is a graphical representation of the graphics flow Figure 5 shows the function block diagram of the θ θ back-through example; Figure 54 shows the details of the data path Block 92 201123254 Figure 55 is a schematic diagram of a data path with interleaved/multiplexed subchannels; Figure 56 is a schematic diagram of a demultiplexing scheme using column selectors and row selectors, and Figure 57 is a pixel size and grid width The table depends on the number of beamlets (Npat beams), the array tilt angle (aarray), the projected pitch (Pproj), and the K factor for each of the pattern bundles; Fig. 58A is a diagram illustrating the smart boundary strategy; Fig. 58B is An illustration of a soft edge strategy is illustrated; Figure 59 is a functional flow diagram of an embodiment of a data path using offline rasterization; Figure 60 is a functional flow diagram of an embodiment of a data path using inline rasterization; Figure 61 is a Functional flow diagram of another embodiment of an in-line rasterized data path; Figure 62 is a functional flow diagram of an embodiment of a data path using instant rasterization; Figure 63 is an illustration of four small beam arrays Legend; Figure 64 A legend illustrating a stitching scheme; Fig. 65 is a diagram illustrating a writing strategy having a factor of K = 1 and κ = 3; Fig. 66 is a diagram of a possible & value of the bundle of Fig. 35 having 4 small bundles; Fig. 6 is a diagram illustrating an example of an angular layout; Fig. 69 is a diagram illustrating a vector orientation; Fig. 70 is a diagram illustrating encoding of a square feature; 93 201123254 Fig. 71 f illustrates a complex feature shape Encoded legend, Fig. 72A illustrates an example of an example of a minimum feature spacing of diagonal lengths less than one L, and lattice; a real graph 73 of features of the angular serrations is illustrated with an example attached to an example thereof; Figure 74 is a simplified schematic diagram showing one; and an embodiment of a plurality of small beam lithography systems with charged particles. Figure 75 is a diagram showing the division of the beam region and the non-beam region. [Main component symbol description 1 lithography electron source electron beam collimator lens pore array pore array pore array small beam small beam extinguisher array beam 阑 array sub-beam concentrating lens array end module target 3 4 5 6

6A

6B 7 9 10 20 21 22 24 94 201123254 51 52 100 101 102 103 104 110 111 112 113 114 115 116 117 118 119 120 130 131 ' 140 143 145 146 Beam area non-beam area charged particle lithography system wafer positioning system Electro-optical column data path target charged particle source aperture array concentrating lens array collimator lens system XY deflector array second aperture array second concentrating lens array beam extinguisher array beam 阑 array beam deflector array projection lens array electron Beam 132 ' 133 small beam pre-processing unit electro-optical conversion device fiber beam 95 201123254 147 lens 148 mirror 149 photoelectric conversion device 96

Claims (1)

201123254 VII. Scope of application for patents · · A method for defining features that use lithography to write on a target, the method comprising: defining a grid array, the features occupying one or more cells; Individual cells, describing any corners that belong to the features within the cell. 2. The method of claim 2, wherein each of the corners is described by a ridge and a second vector, the two vectors being from a position of 5 s. The method of claim 1 & 2, wherein the angular position is described by a coordinate. 4. If the scope of patent application is 2 or ¥ ^ Λ * Λ ^, the party of the flying item goes, where the angular position is described by a rectangular coordinate. 5. For example, the scope of the patent application is specified in the direction of the vector, where each vector is described by its position code. 6. If the scope of the patent application is 2, the region from the first vector is defined by the predetermined square =, 4 features 与 with the edge S; ° "The vector in the case of two vectors. 7. For example, the scope of the patent application is 6 o'clock. The method of the item, wherein the predetermined direction is shun. 8. If the patent application scope is the first part, the part belongs to a cell without a The angular angle is for the definition. The characteristics of any of the corners in the grid are as follows: 9. In the eighth item of the patent application, the first fish is oriented at 180 degrees to each other, and the virtual corner is described by the second vector. 97 201123254 10. The method of claim 2, wherein the vectors may only have directions parallel to the lattice boundary or perpendicular to the lattice boundary. 8. The method of claim 2, wherein the vectors may have only a direction parallel to the lattice boundary, perpendicular to the lattice boundary, or 45 degrees to the lattice boundary. Pitch "12", as in the scope of claim 1, and wherein the cell has a size, wherein the minimum feature is defined to be equal to or less than the minimum feature, wherein the minimum feature is less than 2 square root multiplied by 13. The method spacing of item 1 of the range, and wherein the element has a size equal to or half of the minimum feature spacing. Door distance, the method of claim 1 of the patent scope, wherein the minimum feature is defined as 0 having a size equal to or greater than the size of the cell multiplied by the square root of 2. The method of claim 1G, wherein for a feature or a partial feature having an edge having an azimuth two = lattice boundary of 45 degrees, a minimum is defined: the micro-spacing to have a size having a size equal to or greater than the size of the element... The method wherein each of the cells is 16. The maximum number of corners is defined as defined in the scope of the patent application. Each of the cells may contain a pair of methods, such as the method of claim 1, wherein one or more features and/or one or more features are recited. 18. The method of claim 1, wherein the pattern data of a portion of the field of the wafer. 98 201123254. For the method of claim 18 of the patent scope, the pattern data of the field strips of the various days of the box is added. 20. A method of processing pattern data for lithography, the method comprising: providing the pattern data in a vector format; transforming the vector pattern data to produce a grid-based format; and The grid-based pattern data is rasterized to produce data for the second-order pattern. 21. The method of claim 20, wherein the grid-based pattern data includes lattice data describing characteristics of one or more of its occupied grid arrays. The angularity of the features within the grid. 22. The method of claim 2, wherein the grid-based pattern data is rasterized in an instant processing when the lithography method is implemented. 23. The method of claim 2, wherein the rasterizing the grid-based pattern data comprises: translating the pattern data of the grid based on the grid to generate multi-level graph data; The meta-pattern data is dithered to produce the second-order graph data. 24. A method of using a charged particle lithography machine to expose a wafer based on pattern data, the charged particle lithography machine generating a plurality of charged particle beamlets to expose the wafer, the method comprising: Providing the graphic data; 99 201123254 transforming the data to the Dong pattern to generate the pattern data of the grid-based format; rasterizing the grid-based pattern data to generate the second-order pattern data; The data stream is streamed to the beamlet extinguisher array to turn the beamlets generated by the charged particle lithography machine on and off; and the beamlets are turned on and off based on the second order pattern data. 25. The method of claim 24, wherein the grid-based pattern data includes lattice data describing features of one or more of its occupied grid arrays, the grid data describing each of the grids belonging to the grid Any angular feature of the feature. 26. The method of claim 24, wherein the rasterizing the pattern data of the grid is performed by immediate processing when the lithography machine is exposing the wafer. W. The method of claim 24, wherein the grid-based pattern data rasterization comprises: translating the grid-based pattern data to generate multi-level pattern data; The data is dithered to produce the second order pattern data. Eight, the pattern: (such as the next page) 100