TWI514742B - Power controllers and related control methods - Google Patents

Description

Power controller and related control methods

Embodiments of the invention are related to a switched mode power supply.

Switched power supplies typically employ a power switch to control the flow of current through an inductive component. Compared with other general power supplies, the switch power supply has a small product volume and superior conversion efficiency, so it is widely welcomed and adopted by the industry.

Among the many switch-mode power supplies, one operates in a quasi-resonance (QR) mode called a QR switching power supply. The QR switching power supply can make a power switch to change from a closed state to a conducting state when its voltage across the bridge is substantially at a minimum, so theoretically, the switching loss of the power switch can be reduced. Therefore, the conversion efficiency of the QR switching power supply, especially at heavy loads, is generally quite excellent.

1 shows a conventional QR switching power supply 10 in which the transformer is an inductive component having a phase inductively coupled primary side winding PRM, a secondary side winding SEC, and an auxiliary winding AUX. The QR switching power supply 10 is powered by the input voltage V _IN , providing a load 24 - an output voltage V _OUT and an output current I _OUT . The QR controller 26 generates a pulse width modulation (PWM) signal V _GATE that periodically switches the power switch 34 through the drive terminal GATE. Through the voltage dividing resistors 28 and 30, the QR controller 26 detects the voltage across the auxiliary winding AUX V _AUX . Figure 2 shows the PWM signal V _GATE and the voltage across V _{AUX in} Figure 1. In Fig. 2, there is a switching period between the two rising edges of the PWM signal V _GATE , and the time in between is called the cycle time T _CYC , which is composed of an on time T _ON and a off time T _OFF . The turn-on time T _ON is the length of time that the power switch 34 remains on for a period of time T _CYC and is also the pulse width in the PWM signal V _GATE . As shown in FIG. 2, the off time T _OFF of the rear half, as the inductance element discharged, cross voltage V _AUX signals begin to oscillate while two trough VL ₁ and VL _2. The QR controller 26 can cause the cycle time T _{CYC to} end approximately when the signal valley VL ₂ occurs. Thus, the control method that ends the cycle time T _CYC when the signal trough occurs is generally referred to as valley switching.

In the QR switching power supply 10, at the compensation terminal COMP, there is a compensation signal V _COMP controlled by the operational amplifier 20, and the operational amplifier 20 compares the difference between the output voltage V _OUT and the target voltage V _TAR . In the conventional QR controller 26, the compensation signal V _COMP substantially simultaneously determines the on time T _ON and the mask time T _BLOCK . After the end of the masking time T _BLOCK , the QR controller 26 allows the end of the cycle time T _CYC to avoid premature valley switching, resulting in a switching frequency f _CYC (=1/T _CYC ) that is too high and reduces conversion efficiency. Therefore, the masking time T _BLOCK is equal to the defined maximum switching frequency f _CYC-MAX (=1/T _BLOCK ).

The conventional QR switching power supply 10 has two possible problems.

1. Electromagnetic wave interference is difficult to solve. At a fixed load 24, the compensation signal V _COMP may be a fixed value, and the power switch 34 ends at a fixed signal valley for a cycle time T _CYC , which means a fixed switching frequency f _CYC and a fairly strong Electromagnetic interference. One conventional solution is to make small interference to the compensation signal V _COMP , but the negative feedback mechanism provided by the operational amplifier 20 tends to automatically offset the provided interference, so the effect is not obvious.

2. The appearance of audible noise. At a fixed load 24, the compensation signal V _COMP may oscillate such that the QR controller 26 performs valley switching in one signal valley at a time and valley switching in another adjacent signal valley at another. As a result of such unstable valley switching, the QR switching power supply 10 may cause disturbing abnormal sound. A power supply that produces an abnormal sound is generally difficult for the market to accept.

The embodiment discloses a power supply controller suitable for a switching power supply. The switched power supply includes an inductive component and a power switch connected in series. One of the inductive elements can be oscillated across the voltage to produce at least one signal valley. The power switch is controlled by a pulse width modulation signal. The pulse width modulation signal has an on time and a off time. The power controller includes a valley detector, a masking time generator, and a shutdown time controller. The valley detector is coupled to the inductive component for generating a valley indication signal to indicate a time at which the at least one signal trough occurs. The masking time generator provides a masking time. The shutdown time controller records a oscillating time record, which represents a front oscillating time, associated with a front switching period; the closing time is terminated according to the oscillating time record, the occlusion time, and the trough indication signal; and, according to The shock time is updated to update the shock time record. The oscillating time begins with one of the starting points after the sway begins to oscillate, and ends with the closing time.

The embodiment discloses a control method suitable for a power supply comprising an inductive component and a power switch. The power switch is controlled by a pulse width modulation signal. The pulse width modulation signal has several switching periods. Cycle time per switching cycle There is an open time and a close time. One of the inductive elements can be oscillated across the voltage to have an oscillation period and generate at least one signal valley. The control method includes: providing an oscillating time record, which represents a front oscillating time, associated with a front switching period; and controlling the power switch to end the closing time according to the previous oscillating time during a switching period; According to a shock time, the shock time record is updated. The oscillating time and the previous oscillating time start from a starting point after the sway of the cross-pressure, and the oscillating time ends at the same time as the closing time. The difference between the oscillating time and the previous oscillating time is less than the oscillating period, so that one of the front switching period and the switching period operates in a valley switching, and the other operates in a non-valley switching.

10‧‧‧QR Switching Power Supply

20‧‧‧Operational Amplifier

24‧‧‧load

26‧‧‧QR controller

28, 30‧‧ ‧ voltage divider resistor

34‧‧‧Power switch

36‧‧‧resistance

80‧‧‧QR controller

82‧‧‧ Valley Detector

84‧‧‧Discharge time detector

86‧‧‧Output current estimator

88‧‧‧ and gate

90‧‧‧Shading time generator

92‧‧‧ Frequency Jitter

94‧‧‧ Pulse width modulator

100‧‧‧CS peak voltage detector

102‧‧‧Voltage Control Current Source

104‧‧‧ switch

190‧‧‧Transducer

192‧‧‧potentiometer

196‧‧‧Update circuit

198‧‧‧ collecting capacitor

199‧‧‧ Capacitance

200‧‧‧Power Controller

300‧‧‧QR controller

302‧‧‧Close time controller

304, 305, 306, 308, 310, 312, 314, 315, 316, 318, 320, 322, 324 ‧ ‧ steps

ACC‧‧‧ Collector

AUX‧‧‧Auxiliary winding

COMP‧‧‧Compensation end

CS‧‧‧current detection terminal

f _CYC ‧‧‧Switching frequency

f _CYC-MAX ‧‧‧Maximum switching frequency

GATE‧‧‧ drive side

I _CHARGE ‧‧‧Charging current

I _CS ‧‧‧current

I _DIS ‧‧‧discharge current

I _L ‧‧‧Preset current

I _H ‧‧‧Preset current

I _OUT ‧‧‧Output current

I _PRM ‧‧‧current

PRM‧‧‧ primary side winding

PT _S-VL ‧‧‧ before shock time

QRD‧‧‧Detector

S _BLOCK ‧‧‧shadow signal

SEC‧‧‧secondary winding

S _JITTER ‧‧‧Jitter control signal

S _LOCK ‧‧‧Lock signal

S _TDIS ‧‧‧discharge time signal

S _UPDATE ‧‧‧Update signal

S _VD ‧‧‧ trough indication signal

t _STR , t ₁ , t ₂ , t ₃ , t ₄ , t _RELEASE , t _END , t _AB-1ST , t _WS , t _WE ‧‧‧

T _BLOCK ‧‧‧Shading time

T _CYC ‧‧‧ cycle time

T _AUX-CYC ‧‧‧ oscillation period

T _DIS ‧‧‧Discharge time

T _OFF ‧‧‧Closed time

T _ON ‧‧‧Opening time

T _S-VL ‧‧‧ shock time

TW‧‧‧ hour window

V _ACC ‧‧‧ feedback voltage

V _AUX ‧‧‧cross pressure

V _COMP ‧‧‧compensation signal

V _{COMP-SCALED ‧‧‧Proportional} compensation signal

V _CS ‧‧‧ current detection signal

V _CS-PEAK ‧‧‧ voltage

V _GATE ‧‧‧PWM signal

V _IN ‧‧‧ input voltage

VL ₁ , VL ₂ , VL ₃ ‧‧‧Signal troughs

V _L-EST ‧‧‧Load representative signal

V _M ‧‧‧ voltage

V _OUT ‧‧‧ output voltage

V _QRD ‧‧‧Detection voltage

V _REF ‧‧‧Preset reference voltage

V _TAR ‧‧‧target voltage

Figure 1 shows a conventional QR switching power supply.

Figure 2 shows the PWM signal V _GATE and the voltage across the V _{AUX in} Figure 1; Figure 3 shows a QR controller implemented in accordance with the present invention; and Figure 4 shows a QR switched power supply implemented in accordance with the present invention. Some signal waveforms in the device; Figure 5 shows an output current estimator; Figure 6 shows the relationship between the load representative signal V _L-EST and the output current I _OUT ; Figure 7 shows the load representative signal V _L-EST and a maximum Relationship between switching frequency f _CYC-MAX (=1/T _BLOCK ); FIG. 8 shows a power supply controller implemented in accordance with the present invention; and FIG. 9 shows a QR controller that can implement conversion; FIG. Some signal waveforms in the circuit after the QR controller 300 replaces the QR controller 26 of FIG. 1; FIG. 11 is a control method used by the shutdown time controller 302 in an embodiment; The crossover voltage V _AUX in some continuous switching cycles, and the timing of some signals when re-turning light; Figure 13 shows the crossover voltage V _AUX in some continuous switching cycles when the load is lightly weighted, and some signals Timing; Figure 14 shows the oscillating time T in the prior art One possible variation of _S-VL ; and Figure 15 shows one possible variation of the oscillating time T _S-VL in one embodiment of the invention.

In a power controller as exemplified in an embodiment of the present invention, a compensation signal V _COMP only determines an on time T _ON . The power controller detects a discharge time T _{DIS of the} auxiliary winding AUX, and then uses the current detection signal V _CS and the discharge time T _DIS to derive a load representative signal V _L-EST . The load representative signal V _L-EST can represent approximately the current supply I _OUT provided to a load by the current power supply. The power controller determines a masking time T _BLOCK according to the load representative signal V _L-EST . After the occlusion time T _BLOCK has elapsed, the power controller allows the end cycle time T _CYC to be ended.

Briefly, in an embodiment of the invention, the turn-on time T _ON is determined by the compensation signal V _COMP , and the mask time T _BLOCK is determined by the load representative signal V _L-EST representing the output current I _OUT .

Under such a design, the output current I _OUT is a fixed constant under a steady state condition in which the load is constant, and the corresponding masking time T _BLOCK is approximately a constant value. At this time, the compensation signal V _COMP is automatically adjusted to produce a suitable turn-on time T _ON . The result is that the power switch of the power supply can perform valley switching in a fixed signal valley, and there is no longer a problem of unstable valley switching in the prior art. So it is possible to eliminate the abnormal sound.

In an embodiment of the invention, in order to eliminate electromagnetic interference caused by fixed valley switching, a power controller performs jittering on the masking time T _BLOCK . The jitter result of the masking time T _BLOCK will of course affect the compensation signal V _COMP . However, in this embodiment, the compensation signal V _COMP does not affect the occlusion time T _BLOCK because the occlusion time T _BLOCK is substantially only affected by the output current I _OUT and the jitter, and when the electromagnetic wave interference is measured, the output The current I _OUT is constant. Accordingly, jitter may be determined that the masking time T _BLOCK results in substantially faithfully also effective, and the masking time T _BLOCK changes within a certain small range, it may be possible to change the switching frequency f _CYC in a corresponding small scale To solve the problem of electromagnetic interference.

Figure 3 shows a QR controller 80 implemented in accordance with the present invention, which in one embodiment replaces the QR controller 26 of Figure 1. As shown in FIG. 3, the QR controller 80 includes a valley detector 82, a discharge time detector 84, an output current estimator 86, and a gate 88, a masking time generator 90, a frequency jitterer 92, and a pulse wave. Width modulator 94. Figure 4 shows some of the signal waveforms in the circuit after the QR controller 80 replaces the QR controller 26 of Figure 1. For the following description, please refer to the figures 1, 3 and 4.

The discharge time detector 84 is coupled to the auxiliary winding AUX through the detection terminal QRD and the voltage dividing resistors 30 and 28. Discharge time detector 84 based on the voltage across the auxiliary winding V _AUX AUX, the discharge time to generate a signal S _TDIS, which may indicate AUX auxiliary winding of a discharge time T _DIS. For example, as shown by the waveform of the discharge time signal S _TDIS in FIG. 4, the discharge time T _{DIS is} approximately the first rising edge of the cross voltage V _AUX after the end of the _ON time T _ON (at time point t ₁ ) to the time between the first falling edge (at time point t ₂ ).

The valley detector 82 detects the signal trough appearing across the voltage V _AUX after the discharge time T _DIS through the detection terminal QRD. There is a detection voltage V _QRD on the detection terminal _QRD . The valley detector 82 produces a valley indication signal S _VD having a plurality of pulses, each representing the time at which a corresponding signal trough occurs. For example, the valley indication signal S _VD has a pulse when the voltage across the voltage V _AUX drops past 0V for a fixed time. As exemplified by the waveforms of the voltage across the V _AUX and the valley indication signal S _VD in FIG. 4 , the voltage across the voltage V _AUX after the first drop in the off time T _OFF crosses 0V (time point t ₃ ), indicating a signal valley VL ₁ appears, so that at time point t ₄ , the valley indication signal S _VD has one pulse. Similarly, a fixed time after the occurrence of the signal valley VL ₂ , the valley indication signal S _VD has another pulse.

As shown in FIG. 3, the output current estimator 86 receives the current detection signal V _CS and the discharge time signal S _TDIS to generate a load representative signal V _L-EST . The current detection signal V _CS is located at the current detection terminal CS, which represents the current I _CS flowing through the resistor 36, which is also the current I _PRM flowing through the primary side winding _PRM . Although the load representative signal V _L-EST is an estimated result, it can roughly represent the output current I _OUT supplied to the load 24. The output current estimator 86 will be described in detail later by way of example.

The masking time generator 90 generates a masking signal S _BLOCK according to the load representative signal V _L-EST to provide a masking time T _BLOCK . For example, when the load representative signal VL _-EST is larger, the occlusion time T _BLOCK is larger. As exemplified by the waveform of the masking signal S _BLOCK of FIG. 4, the masking time T _BLOCK starts substantially synchronously with the cycle time T _CYC (at the time point t _STR ), and the masking time T _BLOCK ends at the time point t _RELEASE .

A frequency ditherer 92, coupled to the masking time generator 90, provides a dithering control signal S _JITTER for a slight change in masking time T _BLOCK . For example, in a steady state where the load 24 is constant, the jitter control signal S _JITTER is a periodic signal whose frequency of change is 400 Hz, and the jitter control signal S _JITTER can change the masking time T _BLOCK to 1/(27.5). Between kHz)~1/(25kHz), so the switching frequency f _CYC will probably vary between 25kHz and 27.5kHz. In other words, at this time, the period of change of the jitter control signal S _JITTER (=1/400) is much larger than the cycle time T _CYC (between 1/(27.5 kHz) and 1/(25 kHz)).

The two inputs of the AND gate 88 are coupled to the masking time generator 90 and the valley detector 82, respectively. Only after the end of the masking time T _BLOCK , the gate 88 transmits the valley indication signal S _VD , and the pulse in the valley indication signal S _VD sets the pulse width modulator 94. As exemplified by the waveforms of the valley indication signal S _VD and the mask signal S _BLOCK of FIG. 4, at the time point t _END after the end of the masking time T _BLOCK (t _RELEASE ), a trough indication signal S _VD exhibits a pulse, and this The pulse width modulator 94 is pulsed such that the PWM signal V _GATE is set to a logical "1". The gate 88 causes the cycle time T _{CYC to} end when the first signal valley after the masking time T _BLOCK appears (time point t _END ). The time point t _{END of} this switching cycle is equal to the time point t _{STR of the} next switching cycle.

As exemplified by the time points t _STR and t _END in FIG. 4, when the PWM signal V _GATE is set to a logical "1", the power switch 34 is turned on, starting a cycle time T _CYC and an opening time. T _ON . The pulse width modulator 94 determines the length of the turn-on time T _ON based on the compensation signal V _COMP and the current detection signal V _CS . For example, Figure 4 shows a proportional compensation signal V _COMP-SCALED that is roughly proportional to the compensation signal V _COMP . As shown by the waveform of the current detecting signal V _CS in FIG. 4, when the current detecting signal V _CS exceeds the proportional compensation signal V _COMP-SCALED (time point t ₁ ), the PWM signal V _GATE is changed to logical "0", the on time T _{ON is} ended, and the off time T _{OFF is} started.

Figure 5 illustrates an output current estimator 86 having a transducer 190, a level shifter 192, an update circuit 196, a collection capacitor 198, a switch 104, and a voltage-controlled current source. Source) 102, and a CS peak voltage detector 100.

The CS peak voltage detector 100 generates a voltage V _CS-PEAK that represents a peak of the current detection signal V _CS . An example of a CS peak voltage detector 100 is provided, for example, in FIG. 10 of U.S. Patent Application Publication No. US20100321956A1. In some embodiments, the CS peak voltage detector 100 can be replaced with an average current detector as exemplified in FIG. 17 or FIG. 18 of US Patent Application Publication No. US20100321956A1. The voltage controlled current source 102 converts the voltage V _CS-PEAK into a discharge current I _DIS which discharges the collector terminal ACC only when the discharge time signal S _TDIS is logically "1". In other words, the discharge time of the discharge current I _DIS to the collector terminal ACC is equivalently approximately equal to the discharge time T _DIS . In some embodiments, the switch 104 in FIG. 5 can be omitted. Instead, the discharge time signal S _{TDIS is} used to activate or deactivate the voltage controlled current source 102. The voltage V _M on the capacitor 199 is shifted and converted into a load representative signal V _L-EST , which is supplied to the transducer 190 for comparison with a predetermined reference voltage V _REF . The transducer 190 outputs a charging current I _CHARGE according to the comparison result, and continuously charges the collecting terminal ACC. The update circuit 196 is triggered by the update signal S _UPDATE and samples the feedback voltage V _ACC on the collector ACC to update the voltage V _M , which can be updated once every cycle time T _CYC . The update signal S _UPDATE does not necessarily _require the update circuit 196 to perform an update once per cycle time T _CYC , for example, it may be performed once every two cycle times T _CYC . In an embodiment, the update signal S _UPDATE may be equivalent to the pulse width modulation signal V _GATE , meaning that the updated action is performed at the beginning of the off time T _OFF . The voltage V _M is always maintained at a constant value until the update circuit 196 updates it to become another constant value. From the above description, it can be found that when the voltage V _{M is} constant, the charging current I _CHARGE will remain unchanged.

During a cycle time T _CYC , the collection capacitor 198 records and collects a charge integration result of the charge current I _CHARGE at the cycle time T _CYC , and a discharge integration result of the discharge current I _DIS at the discharge time T _DIS , two integration results The difference.

Similar to the analysis in U.S. Patent Application Publication No. US20100321956A1, when the charging current I _CHARGE is a fixed value and the value of the feedback voltage V _ACC when being sampled is equal to the value of the previous sampling, the charging current I _CHARGE will be It is proportional to the output current I _OUT output to the load 24. In order to make the charging current I _CHARGE proportional to the output current I _OUT , the value of the feedback voltage V _ACC every time it is sampled must be the same or stable. The update circuit 196, the potential converter 192, and the transducer 190 together form a loop having a negative loop gain, and this loop can finally stabilize the value of the feedback voltage V _ACC each time it is sampled. A value. For example, if the charging current I _{CHARGE is} greater than a desired value proportional to the output current I _OUT , the feedback voltage V _ACC will become larger at the next sampling, causing the updated voltage V _{M to} become larger as well. Therefore, the charging current I _CHARGE becomes small. vice versa. Therefore, at a steady state where the load 24 is constant, the voltage V _M can be stopped at a relatively fixed value, and the charging current I _CHARGE can eventually become approximately proportional to the output current I _OUT .

Figure 6 shows, in one embodiment, the load representative signal VL _-EST versus output current _IOUT . As shown in FIG. 6, the load representative signal V _L-EST is approximately in a one-to-one relationship with the output current I _OUT , so the load representative signal V _L-EST can roughly represent the output current I _OUT .

The load representative signal V _L-EST roughly determines a masking time T _BLOCK , so the output current I _OUT roughly determines the masking time T _BLOCK , that is, the maximum switching frequency f _CYC-MAX (=1/T _BLOCK ). Figure 7 shows the relationship between the output current I _OUT and a maximum switching frequency f _CYC-MAX (=1/T _BLOCK ) in one embodiment. When the output current I _{OUT is} too large, for example, greater than the preset current I _H , the load 24 is a heavy load, and the maximum switching frequency f _CYC-MAX is changed by the frequency of the jitter control signal S _JITTER , and the modulation is changed to 60 kHz. Between 66kHz. When the output current I _{OUT is} small, for example, less than the preset current I _L , indicating that the load 24 is a light load, and the maximum switching frequency f _CYC-MAX is changed by the variation frequency of the jitter control signal S _JITTER to 25 kHz~ Between 27.5kHz.

It can be seen from FIGS. 3 and 4 that the turn-on time T _ON is determined by the compensation signal V _COMP , and the mask time T _BLOCK is determined by the load representative signal V _L-EST representing the output current I _OUT .

As previously stated, in such a design, as long as the load 24 is constant, the output current I _OUT is a fixed constant, and the corresponding masking time T _BLOCK is approximately a fixed value. It is changed as the compensation signal V _COMP changes. The result is that the power switch 34 of the power supply can perform valley switching in a fixed signal valley, and there is no longer a problem of unstable valley switching in the prior art. So it is possible to eliminate the abnormal sound.

Moreover, as exemplified in FIGS. 3 and 7, the masking time T _BLOCK is substantially only affected by the output current I _OUT and the jitter control signal S _JITTER , and when the electromagnetic wave interference is measured, the output current I _OUT is a constant value. Therefore, it can be determined that the jitter control signal S _JITTER can substantially faithfully and effectively change the masking time T _BLOCK within a certain small range, that is, the switching frequency f _CYC will vary within a corresponding small range. In this way, it is possible to solve the problem of electromagnetic interference.

The above examples are all QR switching power supplies, but the invention is not limited thereto. Figure 8 shows a power supply controller 200 implemented in accordance with the present invention. The power controller 200 is not operating in the QR mode, but in an embodiment, the QR controller 26 in Figure 1 can be replaced. The power controller 200 does not have the valley detector 82 and the AND gate 88 in FIG. 3, and the reverse of the mask signal S _BLOCK is directly connected to the set terminal of the pulse width modulator 94. When the masking time T _BLOCK ends, the pulse width modulator 94 is set immediately, and the cycle time T _CYC and the opening time T _{ON in the} next switching cycle are immediately started. In other words, under the control of the power supply controller 200, the cycle time T _{CYC is} approximately equal to the occlusion time T _BLOCK .

In another embodiment of the invention, the power supply is operated for valley switching most of the time, except that during switching from valley switching of one signal valley to valley switching of another signal valley, some switching cycles are not operational. Switch to the valley. For example, the power supply initially operates in a valley shift of the third signal valley, and then may be due to a larger load or other possible causes, and the switching time of the subsequent switching cycle is progressively forward. (that is, the second signal trough) is close, and after a few switching cycles, the valley switching of the second signal trough is performed. Such a conversion process, referred to herein as soft transition for valley switching, means that two operations are between switching cycles located in valley switching of different signal valleys, and at least one or a number can be tolerated. The switching period of non-valley switching.

Fig. 9 shows a QR controller 300 in which conversion can be implemented, which can be substituted for the QR controller 26 in Fig. 1, as an embodiment of the present invention. The QR controller 300 in Fig. 9 and the QR controller 80 in Fig. 3 are similar or identical to each other, and can be known from the prior teachings, and will not be described here. The QR controller 300 replaces the AND gate 88 in the QR controller 80 with a shutdown time controller 302. The shutdown time controller 302 can cause a power supply to end a turn-off time _TOFF and perform a valley shift when the first signal trough after the end of the masking time T _BLOCK occurs. However, under some conditions, the off-time controller 302 may also not perform valley switching, as will be described in detail later.

Figure 10 shows some of the signal waveforms in the circuit after the QR controller 300 replaces the QR controller 26 of Figure 1. The same parts of Fig. 10 and Fig. 4 can be referred to with reference to Fig. 4 and its description, and will not be described again.

The oscillating time T _S-VL is the length of time between a fixed time point after the end of the discharge time T _{DIS and the} end of the closing time T _OFF (t _END ) in one switching cycle. In the example of the tenth, the oscillation time T _S-VL is from the time point t ₂ to t _END . In another embodiment, it may be from time point t ₃ to t _END or from time point t ₄ to t _END . In a preferred example, the start time of the oscillating time T _S-VL must be no later than the time point t ₄ , that is, the time at which the trough indication signal S _VD appears after the end of the discharge time T _DIS . The oscillating time T _S-VL can be roughly regarded as how long the voltage V _AUX oscillates, and the current cycle time T _CYC or the closing time T _OFF ends.

In some cases, the front oscillating time PT _S-VL is the oscillating time T _S-VL in the previous switching cycle. For example, the oscillation time T _S-VL in the current switching cycle is the pre-oscillation time PT _S-VL in the next switching cycle. In other cases, the front oscillating time PT _S-VL is an oscillating time T _S-VL before several switching cycles.

The time window TW is the time between the time points t _WS and t _WE and is generated according to the front oscillation time PT _S-VL . For example, the time point t _WS is the previous predetermined time at the end of the front oscillating time PT _S-VL , and the time point t _WE is located at another predetermined time after the end of the front oscillating time PT _S-VL . These two predetermined times can be the same or different. The length of the time window TW is preferably less than an oscillation period T _AUX-CYC across the voltage V _AUX . An oscillating period T _{AUX-CYC is} approximately the time between the bottoms of the two signal troughs, and is also approximately equal to the time between the two falling edges of the cross-voltage V _AUX falling through 0V.

The time point t _AB-1ST is the time point at which the first pulse generated by the valley indication signal S _VD appears after the time point t _RELEASE (the end of the masking time T _BLOCK ). In other words, it is also the time point at which the first signal trough appears after the end of the masking time T _BLOCK . The time point t _AB-1ST and the time point t _END do not necessarily appear simultaneously as shown in FIG. That is, the next switching cycle does not necessarily start at time point t _AB-1ST .

Figure 11 is a diagram showing the control method employed by the off-time controller 302 in one embodiment. The close time controller 302 has a recorder that records and provides a digital lock signal S _LOCK . When the lock signal S _LOCK is logically "1" (determined in step 305), indicating that the valley is locked, means that the valley switching is locked in the same signal valley; otherwise, the lock signal S _LOCK is logically "0". , indicating that the valley is not locked, meaning that the signal valley of the valley shift can be changed.

The off time controller 302 records an oscillating time record RT, which may represent the front oscillating time PT _S-VL . Step 306 provides time window TW according to the previous oscillation time PT _S-VL , that is, determines time points t _WS and t _WE . In other words, step 306 determines the time points t _WS and t _WE based on the oscillating time record RT.

In the absence of trough lock, step 308 causes time point t _END to occur only within time window TW, that is, not earlier than time point t _WS , and not later than time point t _WE . As for the exact time point t _END, it depends on the relative position of the time point t _AB-1ST . If the time point t _AB-1ST occurs before the window TW, that is, the time point t _AB-1ST appears earlier than the time point t _WS , the time point t _END is the time point t _WS . If the time point t _AB-1ST appears within the window TW, the time point t _END is the time point t _AB-1ST . If the time point t _{WE is} earlier than the time point t _AB-1ST , the cycle time T _CYC and the closing time T _{OFF are} immediately ended, and the time point t _END is equal to the time point t _WE . At time t _END , the PWM signal V _GATE has a rising edge to end the cycle time T _CYC and the off time T _OFF . The oscillating time record RT, when the closing time T _OFF ends, will be updated, and the signal of the oscillating time T _S-VL of the switching cycle is brought to the next switching cycle to become the pre-oscillation time PT _{S- of the} next cycle. _VL . In this embodiment, the off time T _OFF time point of the end, depending on the point of time windows TW t _AB-1ST, the TW window record time RT is determined by the shock, the time point _AB-1ST masking time T _BLOCK and trough t The indication signal S _VD is determined.

When the valley is locked, step 316 causes the time point t _{END to be the end} of the front oscillation time PT _S-VL . The signal valley at which the current switching period ends and the closing time T _OFF is the same as the signal valley where the closing time T _OFF is ended at the end of the previous switching cycle, and the trough locking is achieved.

The shutdown time controller 302 also has a counter that provides a count value that is generally used to calculate the number of trough locks, as shown in step 320. The counter can also be thought of as a timer that calculates the total time of the valley lock. Step 322 shows that when the number of valley locks reaches a predetermined value N, the lock signal S _LOCK will change from a logical "1" to a logical "0" to cancel the valley lock. In other words, the lock signal S _LOCK is "1" for at least N cycle times. After the valley lock is released, when the time point t _AB-1ST is not in the time window TW at all, it indicates that it is not a valley shift, so step 315 returns the count value to zero. When the time point t _AB-1ST enters the time window TW again, it indicates that the valley lock should be entered, so step 314 makes the lock signal S _LOCK logically "1", increments the count value by 1, and the counter starts counting.

Please also refer to Figure 1, Figure 9, Figure 11, and Figure 12. Figure 12 shows the cross-over voltage V _AUX in some successive switching cycles, as well as the timing of some of the signals, when the load is lightly re-turned.

As shown by the voltage across the voltage V _AUX in the _Xth switching period in FIG. 12, it is assumed that before the Xth switching period, it is in a steady state, and the off time controller 302 is stable to cause the valley switching to occur when the second signal trough occurs. . In the Xth switching period, the time point t _AB-1ST is also the time point t _END (the end of the cycle time T _CYC ), the oscillation time T _S-VL will be the same as the front oscillation time PT _S-VL , and the lock signal S _LOCK is "0", the count value is N. In Fig. 11, the closing time of the X switching period T _OFF is following the steps 304,305,306,308,310,312 and 324, the step of the process is determined.

At the beginning of the X+1th switching period in Fig. 12, the time point t _{RELEASE is} suddenly delayed because the load is lightly re-rotated, so that the time point t _AB-1ST still does not appear when the time window TW ends. The off time T _OFF in the X+1th switching cycle is determined in accordance with the flow of steps 304, 305, 306, 308, 310, 315 and 324. Therefore, as shown in Fig. 12, the time point t _{END of} the X+1th switching period is approximately the same as the time point t _WE , the lock signal S _LOCK is "0", and the count value is 0. The oscillating time T _S-VL will be a predetermined time longer than the previous oscillating time PT _S-VL , as shown in Figure 12. This predetermined time is only one part of the oscillating period T _AUX-CYC across the voltage V _AUX , and in FIG. 12 , this predetermined time is less than one-half of the oscillating period T _AUX-CYC across the voltage V _AUX . Therefore, as clearly shown in Fig. 12, the X+1th switching period is not a valley switching.

In the X+2 switching cycle in Fig. 12, when the time window TW ends, the time point t _AB-1ST still does not appear. Therefore, the off time T _OFF in the X+2 switching cycle follows steps 304, 305, 306, 308, 310, 315, and 324. The time point t _{END of} the X+2 switching cycle is approximately the same as the time point t _WE , the lock signal S _LOCK is “0”, and the count value is 0. The X+2 switching cycle is also not a valley switch.

In the X+3 switching cycle in Fig. 12, the time point t _AB-1ST appears in the time window TW. Therefore, the off time T _OFF in the X+3 switching cycle follows steps 304, 305, 306, 308, 310, 312, and 314. As shown in Fig. 12, the time point t _{END of} the X+3 switching cycle is approximately the same as the time point t _AB-1ST , the lock signal S _LOCK becomes "1", and the count value is 1. The X+3 switching cycle is a valley switching.

In the X+4 switching cycle in Fig. 12, since the lock signal S _LOCK is "1", the time point t _END appears at the end of the front oscillation time PT _S-VL . The off time T _OFF in the X+4 switching cycle follows steps 304, 305, 316, 318 and 320. The front oscillating time PT _S-VL will not be updated, and the oscillating time T _S-VL will be the same as the previous oscillating time PT _S-VL . The lock signal S _LOCK remains "1" and the count value becomes 2. The X+4 switching cycle is a valley switching.

During the period from the Xth switching period to the X+4 switching period, it can be found that the oscillating time T _S-VL is increased with the switching period. The end time of the oscillating time T _S-VL is gradually increased from the time point when the second signal trough occurs, and finally stops at the time point when the third signal trough appears, as shown in Fig. 12. The closing time controller 302 forces the difference between the oscillating time T _S-VL and the front oscillating time PT _{S-VL to} be less than the oscillating period T _AUX-CYC across the voltage V _AUX .

After the X+4 switching cycle in Figure 12, the front oscillating time PT _S-VL and the oscillating time T _S-VL remain unchanged and approximately equal, and each closing time T _OFF follows the steps in Figure 11 304, 305, 316, 318 and 320 are determined. As shown in Fig. 12, the count value increases by 1 with each switching cycle until the count value becomes N, and the lock signal S _LOCK is changed to "0", thereby canceling the valley lock.

Please also refer to Figure 1, Figure 9, Figure 11, and Figure 13. Figure 13 shows the crossover voltage V _AUX in some successive switching cycles, as well as the timing of some of the signals when the load is lightly weighted.

As shown by the voltage across the voltage V _AUX in the Y-th switching period in Fig. 13, assuming that the state is in a steady state before the Y-th switching period, the off-time controller 302 stably causes the valley switching to occur in the third signal valley VL _{3 .} When it appears. In the Yth switching cycle, the time point t _AB - _1ST is also the time point t _END (the end of the cycle time T _CYC ), the oscillation time T _S-VL will be the same as the front oscillation time PT _S-VL , and the lock signal S _LOCK is "0", the count value is N. In Fig. 11, the first Y switch off time T _OFF is a period following the steps 304,305,306,308,310,312 and 324, the step of the process is determined.

In the Y+1 switching cycle in Fig. 13, it may be due to light load to heavy load, so the time point t _{RELEASE is} suddenly advanced to the vicinity of the signal valley VL ₁ , resulting in the time window TW when the time point t _AB-1ST appears. Not yet appearing. The off time T _OFF in the Y+1th switching cycle is determined by the step flow following steps 304, 305, 306, 308, 310, 315 and 324. Therefore, the time point t _{END of} the Y+1th switching period is approximately the same as the time point t _WS , the lock signal S _LOCK is “0”, and the count value is 0. The oscillating time T _S-VL will be less than the previous oscillating time PT _S-VL , as shown in Figure 12. This predetermined time is only a part of the oscillating period T _AUX-CYC across the voltage V _AUX , and in FIG. 13 , this predetermined time is less than one-half of the oscillating period T _AUX-CYC of the voltage across the voltage V _AUX . Figure 13 clearly shows that the Y+1 switching period is not a valley switching.

In the Y+2 switching cycle in Fig. 13, when the time point t _AB-1ST occurs, the end of the time window TW still does not appear. Therefore, the off time T _OFF in the Y+2 switching cycle follows steps 304, 305, 306, 308, 310, 315, and 324. The time point t _{END of} the Y+2 switching cycle is approximately the same as the time point t _WS , the lock signal S _LOCK is “0”, and the count value is 0. The Y+2 switching cycle is also not a valley switch.

In the Y+3 switching cycle in Fig. 13, the time point t _AB-1ST appears in the time window TW. Therefore, the off time T _OFF in the Y+3 switching cycle follows steps 304, 305, 306, 308, 310, 312, and 314. Y + 3 of the switching cycle will be the time point t _END time point t _AB-1ST about the same time, the lock signal S _LOCK becomes "1", the count value is 1. The Y+3 switching cycle is a valley switching.

In the Y+4 switching cycle in Fig. 13, since the lock signal S _LOCK is "1", the time point t _END appears at the end of the front oscillation time PT _S-VL . The off time T _OFF in the Y+4 switching cycle is determined in accordance with steps 304, 305, 316, 318 and 320. The front oscillating time PT _S-VL will not be updated, and the oscillating time T _S-VL will be the same as the previous oscillating time PT _S-VL . The lock signal S _LOCK remains "1" and the count value becomes 2.

From the Yth switching period to the Y+4 switching period, it can be found that the oscillation time T _S-VL is reduced with the switching period. The end time of the oscillating time T _S-VL is gradually decreased from the time point when the third signal trough occurs, and finally stops at the time point when the second signal trough appears.

After the Y+4 switching cycle in Figure 13, the front oscillating time PT _S-VL and the oscillating time T _S-VL remain unchanged, and each closing time T _OFF follows steps 304 and 305 in FIG. 11 . 316, 318 and 320 are decided. As shown in Fig. 13, the count value increases by 1 with each switching cycle until the count value becomes a predetermined N, and the lock signal S _LOCK is changed to "0" to cancel the valley lock.

As can be seen from Fig. 11, Fig. 12, and Fig. 13, in one embodiment of the present invention, trough lock occurs upon switching of a valley that enters a certain signal trough. That is, the valley switching of this signal valley will last for at least N switching cycles before the valley switching of another signal valley can be allowed to occur. Moreover, the soft transition of the valley switching is also provided in the embodiment, that is, between two switching periods of valley switching in different signal valleys, there is at least one switching period that is not operating in valley switching.

Figure 14 shows a possible variation of the oscillating time T _{S-VL in the prior} art. Prior art does not convert the so-called soft handover valley, therefore an oscillation of the switching period T _S-VL, and another switching cycle oscillation time T _S-VL, is an integer of oscillation cycle must cross voltage V _AUX of the T _AUX-CYC Times, as shown in Figure 14. The oscillating period T _{AUX-CYC is} approximately the time difference between the bottoms of two consecutive signal troughs. Such a large oscillation time T _S-VL changes easily causes instability of the entire system, and also causes a large jitter of the output voltage V _OUT .

Moreover, prior art power supplies do not have so-called valley locks. Therefore, as in the case shown in Fig. 14, it may happen that as the switching period advances, the valley switching jumps and jumps rapidly in the two signal valleys.

Figure 15 shows a possible variation of the oscillating time T _S-VL in one embodiment of the invention. Fig. 15 shows the soft transition, so during the valley switching of the fourth signal valley VL ₄ and the transition to the valley of the third signal valley VL ₃ , three switching periods of non-valley switching are experienced. Figure 15 also shows the effect of valley lock. The valley switching of the third signal valley VL ₃ must go through at least 8 switching cycles before it can switch to the valley of another signal valley. Comparing Fig. 14 with Fig. 15, it can be seen that the oscillating time T _S-VL in Fig. 15 is relatively smooth, and the system instability is not produced.

The QR controller 300 in FIG. 9 has 1) the masking time T _{BLOCK is} determined by the load representative signal V _L-EST ; 2) the soft transition of the valley switching; and 3) the trough locking, the three technical features, but the present invention Not limited to this. These three technical features can be implemented independently or in combination. For example, an embodiment of the present invention may implement 1) the masking time T _{BLOCK is} determined by the load representative signal V _L-EST ; and 2) the soft transition of the valley switching, both technical features, but no trough locking is implemented. Another embodiment implements a soft transition of valley switching and valley lock, but the masking time T _{BLOCK is} determined by the compensation signal V _COMP , rather than the load representative signal V _L-EST .

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

304, 305, 306, 308, 310, 312, 314, 315, 316, 318, 320, 322, 324 ‧ ‧ steps

PT _S-VL ‧‧‧ before shock time

S _LOCK ‧‧‧Lock signal

t _AB-1ST ‧‧‧ time

T _CYC ‧‧‧ cycle time

T _OFF ‧‧‧Closed time

T _S-VL ‧‧‧ shock time

TW‧‧‧ hour window

Claims (11)

A power controller is provided for a switching power supply, the switch power supply includes an inductance component connected in series and a power switch, and one of the inductance components can be oscillated across the voltage to generate at least one signal valley. The power switch is controlled by a pulse width modulation signal having an on time and a off time. The power controller includes: a valley detector coupled to the inductive component, Generating a trough indication signal to indicate the time at which the at least one signal trough occurs; a masking time generator providing an obscuration time; and an OFF-time controller recording an oscillating time record, Representing a front oscillating time associated with a front switching period; ending the closing time according to the oscillating time record, the occlusion time, and the trough indication signal; and updating the oscillating time record according to an oscillating time; wherein The oscillating time begins with one of the starting points after the sway begins to oscillate, and ends with the closing time. The power controller of claim 1, wherein the off time controller can provide a time window according to the oscillating time record, and the front oscillating time ends within the time window. The power controller of claim 2, wherein the shutdown time controller limits the closing time to end in the time window. The power controller of claim 2, wherein: the shielding time starts substantially together with the opening time; the first unmasked signal trough after the shielding time ends appears at a first time point; When the first time point is earlier than the time window, the closing time ends at a starting point of the time window; when the first time point is later than the time window, the closing time ends at an end of the time window a point; and when the first time point is within the time window, the closing time ends at the first time point. The power controller of claim 2, wherein a length of the time window is less than one of the span voltages. The power controller of claim 1, wherein the off-time controller forces the difference between the oscillating time and the previous oscillating time to be less than one of the cross-pressure oscillating periods. The power controller of claim 6, wherein the off-time controller has a timer for recording a time when the valley switching lock occurs in a same signal trough. A control method is applicable to a power supply comprising an inductive component and a power switch, the power switch being controlled by a pulse width modulation signal having a plurality of switching cycles, each The cycle time of the switching cycle has an on time and a turn-off time. One of the inductive components can be oscillated across the voltage to have an oscillation period and generate at least one signal valley. The control method includes: providing an oscillation time record, which represents a front oscillating time associated with a front switching cycle; controlling the power switch to end the closing time according to the previous oscillating time during a switching cycle; and updating the oscillating time record according to an oscillating time, wherein The oscillating time and the previous oscillating time start from a starting point after the swaying of the sag, and the oscillating time ends at the same time as the closing time; wherein the difference between the oscillating time and the previous oscillating time is less than the oscillating period, Make the front open One of the off period and the switching period operates on a valley switch, and the other operates on a non-valley switch. For example, in the control method of claim 8, the method further includes: providing a time window according to the front oscillating time, wherein the front oscillating time ends in the time window; and ending the closing time in the time window. The control method of claim 9 further includes: providing a masking time, which starts substantially together with the opening time; after the masking time ends, indicating that a first unmasked signal trough occurs at a first time Point; the first unmasked signal trough after the end of the masking time occurs at a first time point; when the first time point is earlier than the time window, the closing time ends at a starting point of the time window; When the first time point is later than the time window, the closing time ends at an end point of the time window; and when the first time point is located in the time window, the closing time ends at the first time point. The control method of claim 8 further includes: providing a lock signal to cause the power supply to continue at the end of the previous oscillating time, ending the closing time; and maintaining the lock signal for at least one duration, The lock signal is released; wherein the duration is a predetermined number of switching cycles.