TWI514401B - Serial interface nand flash memory and embedded changeable block management method thereof - Google Patents

Description

Management of tandem reverse flash memory and its built-in variable bad area method

The invention relates to a management method of a serial-reverse flash memory, and in particular to an in-line reversible flash memory built in an erasable rewrite error block lookup table (Bad Block) Management look up table, BBM LUT) management method.

With the popularization of electronic products, providing non-volatile memory with fast and large capacity for reading and writing has become an important feature of electronic products. Among them, the anti-flash memory is a popular choice.

In a reverse flash memory, such as a Serial Peripheral Interface (SPI) reverse flash memory, a Bad Block Management (BBM) lookup table is provided. The damaged block management lookup table is used to correspond to a plurality of logical addresses to a plurality of physical locations. Damaged area The block management lookup table records the information of the physical address of the damaged memory block in the flash memory, and manages the lookup table through the damaged block when the flash memory is accessed, according to the memory area to be accessed. The logical address of the block to find the physical address of the normal memory block.

The invention provides a serial reverse sync type flash memory and a flash memory management method, which can modify the address correspondence table (error block lookup table) therein.

The method for managing a flash memory of the present invention includes: setting an address correspondence table, wherein the address correspondence table has an initial correspondence record to record a correspondence between a plurality of logical addresses and a plurality of physical locations; and receiving a lock Release the command to erase at least a portion of the initial corresponding record according to the lock release command to receive the erase signal; in addition, receiving the update data and writing the update data to the portion of the erased initial corresponding record to obtain the updated corresponding record .

The flash memory of the present invention includes a plurality of flash memory cells, an initialization circuit, and an address correspondence table. The flash memory cells are arranged into a flash memory cell array, the initialization circuit is coupled to the flash memory cell array, and the address correspondence table is coupled to the initialization circuit. The address correspondence table has an initial correspondence record to record a correspondence between a plurality of logical addresses and a plurality of physical locations. The initialization circuit receives and follows the lock release command to receive the erase signal to erase at least a portion of the initial corresponding record. Initializing the circuit and receiving the update data and writing the update data to the portion of the initial corresponding record that is erased Get updated corresponding records.

Based on the above, the present invention provides an erasable and updated address correspondence table, and through such a setting, when the flash memory is damaged in use, the existing address correspondence table can be updated by updating the existing address correspondence table. Avoid access to damaged memory blocks. In addition, by updating the address correspondence table, the frequency of access of a particular good block in the flash memory can also be reduced, and the lifetime of the flash memory can be maintained.

The above described features and advantages of the invention will be apparent from the following description.

S110~S140‧‧‧Flash memory management steps

210‧‧‧ Address correspondence table

211~212‧‧‧ initial correspondence record

PBA1, PBA2‧‧‧ physical address

LBA1‧‧‧ logical address

230‧‧‧Lock release flag

UPD‧‧‧Updated information

400‧‧‧Flash memory

410‧‧‧Flash memory cell array

420‧‧‧Initialization circuit

430‧‧‧ Address correspondence table

440‧‧‧ 存存器

450‧‧‧Backup memory block

FIG. 1 is a flow chart of a method for managing a flash memory according to an embodiment of the present invention.

FIG. 2 and FIG. 3 are schematic diagrams showing a method for managing a flash memory according to an embodiment of the present invention.

4 is a schematic diagram of a flash memory according to an embodiment of the invention.

Please refer to FIG. 1. FIG. 1 is a flow chart of a method for managing a flash memory according to an embodiment of the present invention. The flash memory can be an SPI interface NAND flash memory. In step S110 of the management method, a built-in address correspondence table is set. This address correspondence table has an initial corresponding record to record multiple logical addresses and multiple Correspondence between physical locations. The address correspondence table can be constructed by using a plurality of memory cells in the flash memory, and the address correspondence table is used as a damaged block management lookup table. In step S120, a lock release command is received, and the lock release command is used to cancel the write-protection operation of the address correspondence table. In the embodiment, the content of the address correspondence table cannot be changed in the initial state ( That is to prevent writing). In step S130, the anti-write operation of the address correspondence table is released according to the received lock release command, and the erase signal is received to first erase the portion to be updated in the address correspondence table. The above erase operation may be erased for all the address correspondence tables, or may be erased for a part of the address correspondence table.

On the other hand, the lock release command may be provided according to the state of the lock release flag. For example, when the lock release flag is set and set (for example, set to a high logic level), the write-protected state of the address correspondence table is correspondingly Lifted. In contrast, when the lock is de-flagged and reset (for example, reset to a low logic level), the anti-write state of the address correspondence table is activated. In other words, the lock release flag is reset to the low logic level state in the initial state.

Next, in step S140, the update data is received, and the received update data is written to the erased portion of the initial corresponding record, and the updated corresponding record is obtained.

After the step S140 is completed, when the flash memory performs the access operation, the corresponding operation of the memory block logical address and the physical address may be performed according to the update corresponding record in the address correspondence table.

The following is an example for the steps of Figure 1, for a more detailed explanation. Referring to FIG. 2 and FIG. 3, FIG. 2 and FIG. 3 are schematic diagrams showing a method for managing a flash memory according to an embodiment of the present invention. In FIG. 2, in the initial state, the initial correspondence records 211 to 212 are stored in the address correspondence table 210, wherein the initial corresponding records 211 to 212 are respectively used to correspond to logical addresses of the plurality of memory blocks to a plurality of good memories. The physical address of the block. In the present embodiment, the initial corresponding record 211 corresponds to the logical address LBA1 of the memory block to the physical address PBA1 of the good memory block. Moreover, when the user of the flash memory accesses the logical address LBA1, the flash memory can provide the physical address in the memory cell array 220 through the initial corresponding record 211 in the address correspondence table 210. The memory block 221 of PBA1 is accessed.

Incidentally, the lock release flag 230 at this time is equal to the low logic level "0", that is, the address correspondence table 210 is in a write-protected state.

In FIG. 3, when the initial correspondence record 211 stored in the address correspondence table 210 is to be changed, the lock release flag 230 is first set to be equal to the high logic level "1", that is, the address correspondence table 210 is in the erasable state. In addition to the rewritten state, the initial correspondence record 211 to be updated is deleted, and the update material UPD is written in the field stored in the original initial correspondence record 211, and the change operation of the address correspondence table 210 is completed. The update data UPD is used to correspond to the logical address LBA1 of the memory block to the physical address PBA2 of the memory block. In this way, when the user of the flash memory accesses the logical address LBA1, the flash memory can be provided in the memory cell array 220 through the update data UPD in the address correspondence table 210. The memory block 222 of the physical address PBA2 is accessed.

More notably, in an embodiment of the invention, when flash memory When the change operation of the address correspondence table 210 is to be performed, after the lock release flag 230 is set, the flash memory may first back up the initial corresponding record stored in the address correspondence table 210 in the backup memory block. The backup memory block can be configured by using multiple memory cells in the flash memory. In addition, the backed up initial correspondence record can be rewritten back into the address correspondence table 210 according to the user's needs.

Regarding the implementation details of writing the initial corresponding record of the backup back to the address correspondence table 210, it is similar to the manner of writing the updated data to the address correspondence table, wherein when the initial corresponding record is completely backed up in the backup memory block When the initial correspondence record of the backup is written back to the address correspondence table 210, the update corresponding record in the address correspondence table 210 needs to be completely erased, and then the write operation of the initial corresponding record is performed.

Through the above-mentioned backup operation, the flash memory of the embodiment of the present invention will not be caused by the incomplete update of the address correspondence table caused by the phenomenon of similar power-off in the process of data change in the address correspondence table. Unable to work.

Please refer to FIG. 4, which is a schematic diagram of a flash memory according to an embodiment of the invention. The flash memory 400 includes a flash memory cell array 410, an initialization circuit 420, an address correspondence table 430, and a register 440. The flash memory cell array 410 is composed of a plurality of flash memory cells. The register 440 is coupled to the initialization circuit 420 and stores a lock release flag, wherein the lock release flag is used to provide a lock release command to the initialization circuit 420.

The initialization circuit 420 is further coupled to the address correspondence table 430, and is used to perform the management action on the address correspondence table 430, and the address pair is The update and backup operations should be performed on the table 430. For details of the implementation of the management operation performed by the initialization circuit 420, please refer to the foregoing embodiments and embodiments of the present invention.

On the other hand, the flash memory cell array 410 may further include a backup memory block 450. The backup memory block 450 is coupled to the initialization circuit 420 and provided as an initial correspondence in the address correspondence table 430 as the initialization circuit 420. Record the storage space when backing up.

In summary, the present invention provides an address address correspondence table of the built-in built-in inverse flash memory that can be erased and updated as a damaged block management lookup table. In this way, the content in the damaged block management lookup table can update the corresponding record according to the actual working state and requirements of the flash memory. When the flash memory generates a new damaged memory block, the normal operation of the flash memory can be maintained by updating the address correspondence table, and the same normal memory block can also be reduced by updating the address correspondence table. The frequency is accessed to increase the life cycle of the flash memory.

S110~S140‧‧‧Flash memory management steps

Claims (8)

A management method for a built-in variable bad area of a built-in inverse flash memory, comprising: setting an address correspondence table, the address correspondence table having an initial corresponding record to record a plurality of logical addresses and a majority Corresponding relationship between physical locations; receiving a lock release command; receiving an erase signal according to the lock release command to erase at least a portion of the initial corresponding record; and receiving an update data and writing the update data to the erased The portion of the initial corresponding record is divided to obtain an updated corresponding record. The method for managing a built-in variable bad area of the built-in inverse flash memory according to claim 1, wherein the method further comprises: providing the lock release command by setting a lock release flag. The method for managing a built-in variable bad area of the built-in inverse flash memory according to claim 1, wherein the method further comprises: backing up the at least part of the initial corresponding record before erasing the at least part of the initial corresponding record The initial corresponding record is recorded in a backup memory block. The method for managing a built-in variable bad area of the built-in inverse flash memory according to the second aspect of the patent application, further comprising: erasing the address correspondence table according to the lock release command The update corresponds to a record; the initial corresponding record is read by the backup memory block; The initial corresponding record is written into the address correspondence table. A built-in inverse flash memory, comprising: a plurality of flash memory cells arranged in a flash memory cell array; an initializing circuit coupled to the flash memory cell array; and an address correspondence table coupled The initialization circuit, wherein the address correspondence table has an initial corresponding record to record a correspondence between a plurality of logical addresses and a plurality of physical locations, and the initialization circuit receives and according to a lock release command to receive an erase signal to wipe In addition to at least a portion of the initial corresponding record, the initialization circuit receives an update data and writes the update data to the portion of the initial corresponding record that was erased to obtain an updated corresponding record. The built-in anti-flash memory according to claim 5, further comprising: a temporary register coupled to the initialization circuit, the temporary storage device storing a lock release flag, the lock release flag Used to provide the lock release command. The built-in inverse flash memory according to claim 5, further comprising: a backup memory block coupled to the initialization circuit, wherein the initialization circuit erases at least the initial corresponding record Before part of the backup, the initial corresponding record is backed up to the backup memory block. The built-in anti-flash memory according to the seventh aspect of the invention, wherein the backup memory block is configured to erase the update corresponding record in the address correspondence table according to the lock release command, and the backup is performed by the backup The memory block reads the initial corresponding record and writes the initial corresponding record into the address correspondence table.