TWI513484B - Multi-channel electronic stimulator for spinal cord stimulation - Google Patents
Multi-channel electronic stimulator for spinal cord stimulation Download PDFInfo
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Description
本發明是關於一種脊髓電刺激產生器,特別是關於一種可調整刺激電波之振幅及頻率的多通道之脊髓電刺激產生器。The present invention relates to a spinal cord electrical stimulation generator, and more particularly to a multi-channel spinal cord electrical stimulation generator that can adjust the amplitude and frequency of a stimulation wave.
一般可植入式的微刺激器廣泛地應用於治療各種生理疼痛和神經疼痛,利用電刺激的方式阻斷身體疼痛訊號通過脊髓向大腦傳遞,以大幅度減緩疼痛。Generally, implantable micro stimulators are widely used to treat various physiological pains and neuropathic pains, and electrical stimulation is used to block the transmission of body pain signals through the spinal cord to the brain to greatly reduce pain.
請參閱第8圖,一種習知電刺激產生器200具有一電源供應單元210、一電壓轉換單元220、一控制單元230、一保護元件240、一儲能元件250、一電流方向控制開關260及一輸出線圈270,該電源供應單元210用以提供一電流,該電壓轉換元件220電性連接該電源供應單元210以將該電流轉換為該電刺激產生器200的一額定電壓,該控制單元230及該保護元件240電性連接該電壓轉換單元220,該儲能單元250電性連接該保護元件240,該電流方向控制開關260電性連接該控制單元230並受該控制單元230所控制,且該電流方向控制開關260接收該額定電壓,以輸出一刺激電流至該輸出線圈270,由於習知電刺激產生器200中僅藉由控制單元230控制該電流方向控制開關260以調整該刺激電流的極性方向,但無法調整該刺激電流的振幅、頻率及脈衝波寬,且由於該電刺激產生器200是由離散元件所組成,使得該電刺激產生器200的體積較大,因此,若將該電刺激產生器200使用於植入式的治療,則易造成使用者的不適。Referring to FIG. 8 , a conventional electrical stimulation generator 200 has a power supply unit 210 , a voltage conversion unit 220 , a control unit 230 , a protection component 240 , an energy storage component 250 , a current direction control switch 260 , and An output coil 270 is configured to provide a current. The voltage conversion component 220 is electrically connected to the power supply unit 210 to convert the current into a rated voltage of the electrical stimulation generator 200. The control unit 230 The protection component 240 is electrically connected to the voltage conversion unit 220, and the energy storage unit 250 is electrically connected to the control unit 230 and is controlled by the control unit 230, and The current direction control switch 260 receives the rated voltage to output a stimulation current to the output coil 270. Since the current direction control switch 260 is controlled by the control unit 230 only in the conventional electrical stimulation generator 200 to adjust the stimulation current. Polarity direction, but the amplitude, frequency and pulse width of the stimulation current cannot be adjusted, and since the electrical stimulation generator 200 is composed of discrete components Therefore, the volume of the electrical stimulation generator 200 is large, and therefore, if the electrical stimulation generator 200 is used for implantable treatment, it is liable to cause discomfort to the user.
本發明的主要目的在於藉由控制電路分別提供振幅控制訊號、通道選擇訊號及刺激類型訊號至數位類比轉換電路、取樣電路及刺激波形產生器,使數位類比轉換電路根據振幅控制訊號輸出振幅訊號至取樣電路,取樣電路接收通道選擇訊號及振幅訊號後可輸出穩定之電壓訊號至刺激波形產生器,並藉由通道選擇訊號的控制,可決定欲輸出電壓訊號之通道,刺激波形產生器接收刺激類型訊號及電壓訊號後輸出刺激波形以進行電刺激之治療,其中刺激波形產生器可藉由電壓訊號調整刺激波形之振幅,並藉由刺激類型訊號調整刺激波形之頻率、極性及脈衝波寬,使多通道之脊髓電刺激產生器之應用更加廣泛,且由於本發明之各個電子元件整合於一積體電路,因此大幅降低多通道之脊髓電刺激產生器之體積,以避免使用者於使用時產生不適。The main purpose of the present invention is to provide an amplitude control signal, a channel selection signal and a stimulus type signal to a digital analog conversion circuit, a sampling circuit and a stimulus waveform generator by a control circuit, so that the digital analog conversion circuit outputs an amplitude signal according to the amplitude control signal to The sampling circuit, the sampling circuit receives the channel selection signal and the amplitude signal, and then outputs a stable voltage signal to the stimulation waveform generator, and through the control of the channel selection signal, the channel for outputting the voltage signal is determined, and the stimulation waveform generator receives the stimulation type. After the signal and the voltage signal, the stimulation waveform is output for the treatment of the electrical stimulation, wherein the stimulation waveform generator can adjust the amplitude of the stimulation waveform by the voltage signal, and adjust the frequency, polarity and pulse width of the stimulation waveform by the stimulation type signal. The multi-channel spinal cord electrical stimulation generator is more widely used, and since the electronic components of the present invention are integrated into an integrated circuit, the volume of the multi-channel spinal cord electrical stimulation generator is greatly reduced to prevent the user from using it during use. Discomfort.
一種多通道之脊髓電刺激產生器包含一控制電路、一數位類比轉換電路、一取樣電路及複數個刺激波形產生器,該控制電路輸出一振幅控制訊號、一通道選擇訊號及複數個刺激類型訊號,該數位類比轉換電路電性連接該控制電路以接收該振幅控制訊號,且該數位類比轉換電路輸出一振幅訊號,其中該振幅控制訊號用以決定該振幅訊號的大小,該取樣電路具有一多工器及複數個取樣元件,該多工器電性連接該控制電路以接收該通道選擇訊號,且該多工器輸出複數個選擇訊號,各該取樣元件電性連接該數位類比轉換電路及該多工器,以接收該振幅訊號及各該選擇訊號,且各該取樣元件輸出一電壓訊號,其中各該選擇訊號用以決定各該取樣元件為導通或截止,該振幅訊號用以決定該些電壓訊號之大小,各該刺激波形產生器具有一運算放大器及一類比開關,各該運算放大器電性連接各該取樣元件以接收各該電壓訊號,且各該運算放大器輸出一放大電壓訊號,各該類比開關電性連接各該運算放大器及該控制電路,以接收各該放大電壓訊號及該刺激類型訊號,且各該類比開關輸出一刺激電波,其中各該放大電壓訊號用以決定各該刺激電波的大小,各該刺激類型訊號用以決定各該刺激電波的頻率。A multi-channel spinal cord electrical stimulation generator comprises a control circuit, a digital analog conversion circuit, a sampling circuit and a plurality of stimulation waveform generators, wherein the control circuit outputs an amplitude control signal, a channel selection signal and a plurality of stimulation type signals The digital analog conversion circuit is electrically connected to the control circuit to receive the amplitude control signal, and the digital analog conversion circuit outputs an amplitude signal, wherein the amplitude control signal is used to determine the magnitude of the amplitude signal, and the sampling circuit has a plurality of And the plurality of sampling components, the multiplexer is electrically connected to the control circuit to receive the channel selection signal, and the multiplexer outputs a plurality of selection signals, each of the sampling components being electrically connected to the digital analog conversion circuit and the a multiplexer for receiving the amplitude signal and each of the selection signals, and each of the sampling elements outputs a voltage signal, wherein each of the selection signals is used to determine whether each of the sampling elements is turned on or off, and the amplitude signal is used to determine the The magnitude of the voltage signal, each of the stimulation waveform generators has an operational amplifier and an analog switch Each of the operational amplifiers is electrically connected to each of the sampling elements to receive each of the voltage signals, and each of the operational amplifiers outputs an amplified voltage signal, and each of the analog switches is electrically connected to each of the operational amplifiers and the control circuit to receive each of the amplification signals. The voltage signal and the stimulus type signal, and each of the analog switches outputs a stimulation wave, wherein each of the amplified voltage signals is used to determine the magnitude of each of the stimulation waves, and each of the stimulation type signals is used to determine the frequency of each of the stimulation waves.
本發明藉由該多通道之脊髓電刺激產生器輸出複數個可調整振幅、頻率、極性及脈衝波寬之該刺激電波以進行不同類型之電刺激治療,且由於本發明之各個元件整合於一積體電路中,以縮小該多通道之脊髓電刺激產生器之體積,並可降低該多通道之脊髓電刺激產生器之功耗,以減低使用者對於植入式之裝置的不適。The multi-channel spinal cord electrical stimulation generator outputs a plurality of the stimulation waves capable of adjusting amplitude, frequency, polarity and pulse width to perform different types of electrical stimulation treatment, and since the components of the present invention are integrated into one In the integrated circuit, the volume of the multi-channel spinal cord electrical stimulation generator is reduced, and the power consumption of the multi-channel spinal cord electrical stimulation generator can be reduced to reduce the user's discomfort to the implanted device.
請參閱第1圖,為本發明之一實施例,一種多通道之脊髓電刺激產生器100包含一控制電路110、一數位類比轉換電路120、一取樣電路130、複數個刺激波形產生器140、一升壓電路150及複數個電極160。Referring to FIG. 1 , a multi-channel spinal cord electrical stimulation generator 100 includes a control circuit 110 , a digital analog conversion circuit 120 , a sampling circuit 130 , and a plurality of stimulation waveform generators 140 . A booster circuit 150 and a plurality of electrodes 160.
請參閱第1及2圖,該數位類比轉換電路120電性連接該控制電路110,且該數位類比轉換電路120接收該控制電路110輸出的一振幅控制訊號ACS,該數位類比轉換電路120根據該振幅控制訊號ACS輸出一振幅訊號DAC_out,該振幅控制訊號ACS用以決定該振幅訊號DAC_out的大小,請參閱第2圖,在本實施例中,該數位類比轉換電路120為一8位元電流導向數位類比轉換器(8-bit current-steering DAC),該數位類比轉換電路120具有8組電流開關組121、一緩衝器122及一接地電阻123,各該電流開關組121具有一電流源121a及一電流開關121b,各該電流開關121b電性連接於各該電流源121a及該緩衝器122之間,以使各該電流源121a及該緩衝器122之間為導通或截止,各該電流源121a及各該電流開關121b為P型電晶體,各該電流源121a之閘極端接收一1.8 V之直流偏壓dac_vbias,各該電流源121a之源極端接收一2.5 V之電壓源VDD,各該電流源121a之汲極端電性連接各該電流開關121b之源極端,各該電流開關121b之閘極端接收該反相之該振幅控制訊號ACS,各該電流開關121b之汲極端電性連接該緩衝器122,較佳的,該8組電流源121a之尺寸依照二進位權重設計,由右至左之電流源121a的尺寸分別設計為1、2、4、8、16、32、64及128個單位,該振幅控制訊號ACS為8位元之訊號(ACS0至ACS7),各該電流開關121b電性連接該控制電路100並接收該振幅控制訊號(ACS0至ACS7),該振幅控制訊號之各訊號位元分別控制各該電流開關121b以決定各該電流開關121b為導通或截止,若該振幅控制訊號ACS僅導通最右側之該電流開關121b,最右側之該電流源121a則輸出1單位之電流至該緩衝器122,另外,若該振幅控制訊號ACS同時導通右側3個電流開關121b,則右側之3個電流源121a則分別輸出1單位、2單位及4單位之電流至該緩衝器122,而該緩衝器122則接收7單位之電流,以此類推,該些電流源121a藉此提供一線性變化且受該振幅控制訊號ACS控制之電流至該緩衝器122,此外,該接地電阻123電性連接該些電流開關121b及該緩衝器122,且該緩衝器122之反相輸入端連接該緩衝器122之輸出端形成負回授以增強電流,該緩衝器122藉由該線性變化之電流輸出線性變化之該振幅訊號DAC_out。Referring to FIGS. 1 and 2 , the digital analog conversion circuit 120 is electrically connected to the control circuit 110 , and the digital analog conversion circuit 120 receives an amplitude control signal ACS output by the control circuit 110 , and the digital analog conversion circuit 120 The amplitude control signal ACS outputs an amplitude signal DAC_out, and the amplitude control signal ACS is used to determine the size of the amplitude signal DAC_out. Referring to FIG. 2, in the embodiment, the digital analog conversion circuit 120 is an 8-bit current steering. An 8-bit current-steering DAC, the digital-to-analog converter circuit 120 has eight sets of current switch groups 121, a buffer 122, and a grounding resistor 123. Each of the current switch groups 121 has a current source 121a and a current switch 121b, each of the current switch 121b is electrically connected between each of the current source 121a and the buffer 122, so that the current source 121a and the buffer 122 are turned on or off, and the current source is 121a and each of the current switches 121b are P-type transistors, and the gate terminals of the current sources 121a receive a 1.8 V DC bias dac_vbias, and the source terminals of the current sources 121a receive a voltage of 2.5 V. a source VDD, each of the current sources 121a is electrically connected to a source terminal of each of the current switches 121b, and a gate terminal of each of the current switches 121b receives the inverted amplitude control signal ACS, and the current terminal of each of the current switches 121b The buffers 122 are electrically connected. Preferably, the size of the eight sets of current sources 121a are designed according to binary weights, and the sizes of the right-to-left current sources 121a are designed as 1, 2, 4, 8, 16, 32, respectively. And 64 and 128 units, the amplitude control signal ACS is an 8-bit signal (ACS0 to ACS7), and each of the current switches 121b is electrically connected to the control circuit 100 and receives the amplitude control signal (ACS0 to ACS7). Each of the signal bits of the control signal controls each of the current switches 121b to determine whether each of the current switches 121b is turned on or off. If the amplitude control signal ACS only turns on the rightmost current switch 121b, the rightmost current source 121a is Output 1 unit of current to the buffer 122. If the amplitude control signal ACS simultaneously turns on the right three current switches 121b, the three current sources 121a on the right side output currents of 1 unit, 2 units, and 4 units, respectively. The buffer 1 22, and the buffer 122 receives 7 units of current, and so on, the current sources 121a thereby providing a linearly varying current controlled by the amplitude control signal ACS to the buffer 122. In addition, the grounding resistor The current switch 121b and the buffer 122 are electrically connected to the current switch 121b and the buffer 122, and the inverting input end of the buffer 122 is connected to the output end of the buffer 122 to form a negative feedback to enhance the current. The buffer 122 is linearly changed. The amplitude output of the current is linearly changed by the amplitude signal DAC_out.
請參閱第1及3圖,該取樣電路130具有一多工器131及複數個取樣元件132,該多工器131電性連接該控制電路110以接收該通道選擇訊號CSS,且該多工器131輸出複數個選擇訊號SS,請參閱第3圖,在本實施例中,該多工器131為一4對16解碼器(4-to-16 decoder),該多工器131接收4位元之該通道選擇訊號(CSS[0]至CSS[3])並輸出16位元之該選擇訊號(SS0至SS15)至16組之該取樣元件132,分別以各位元之該選擇訊號(SS0至SS15)控制各該取樣元件132,各該取樣元件132電性連接該數位類比轉換電路120及該多工器131,以接收該振幅訊號DAC_out及各該選擇訊號(SS0至SS15),且各該取樣元件132分別輸出一電壓訊號(SH_out_0至SH_out_15),其中各該選擇訊號(SS0至SS15)用以決定各該取樣元件132為導通或截止,該振幅訊號DAC_out用以決定該些電壓訊號SH_out之大小,請參閱第3圖,在本實施例中,該取樣電路130之各該取樣元件132具有一電壓開關132a、一電容132b及一增益緩衝器132c,各該電壓開關132a電性連接於該數位類比轉換電路120及各該增益緩衝器132c之間以使該數位類比轉換電路120及各該增益緩衝器132c之間為導通或截止,各該電容132b耦接於該數位類比轉換電路120,當各該選擇訊號(SS0至SS15)為高電位使各該電壓開關132a導通時,各該增益緩衝器132c及該數位類比轉換電路120為導通,且各該電容132b接收該振幅訊號DAC_out以儲存該振幅訊號DAC_out之大小,因此,當各該電壓開關132a截止時,則由各該電容提供與該振幅訊號DAC_out大小相同之電壓於各該增益緩衝器132c。Referring to FIGS. 1 and 3, the sampling circuit 130 has a multiplexer 131 and a plurality of sampling elements 132. The multiplexer 131 is electrically connected to the control circuit 110 to receive the channel selection signal CSS, and the multiplexer 131 outputs a plurality of selection signals SS. Referring to FIG. 3, in the embodiment, the multiplexer 131 is a 4-to-16 decoder, and the multiplexer 131 receives 4-bits. The channel selects signals (CSS[0] to CSS[3]) and outputs the selection signals (SS0 to SS15) of 16 bits to the sampling elements 132 of the 16 groups, respectively, by selecting the signals of the bits (SS0 to SS15) controlling each of the sampling elements 132, each of the sampling elements 132 is electrically connected to the digital analog conversion circuit 120 and the multiplexer 131 to receive the amplitude signal DAC_out and each of the selection signals (SS0 to SS15), and each of the The sampling component 132 outputs a voltage signal (SH_out_0 to SH_out_15), wherein each of the selection signals (SS0 to SS15) is used to determine whether each sampling component 132 is turned on or off. The amplitude signal DAC_out is used to determine the voltage signals SH_out. For the size, please refer to FIG. 3. In this embodiment, each of the sampling circuits 130 The sample element 132 has a voltage switch 132a, a capacitor 132b and a gain buffer 132c. The voltage switch 132a is electrically connected between the digital analog conversion circuit 120 and each of the gain buffers 132c to enable the digital analog conversion circuit. 120 and each of the gain buffers 132c are turned on or off. Each of the capacitors 132b is coupled to the digital analog conversion circuit 120. When each of the selection signals (SS0 to SS15) is high, the voltage switches 132a are turned on. Each of the gain buffers 132c and the digital analog conversion circuit 120 is turned on, and each of the capacitors 132b receives the amplitude signal DAC_out to store the magnitude of the amplitude signal DAC_out. Therefore, when each of the voltage switches 132a is turned off, each of the voltage switches 132a is turned off. The capacitor provides a voltage of the same magnitude as the amplitude signal DAC_out in each of the gain buffers 132c.
請參閱第3圖,較佳的,各該取樣電路另具有一反相器132d、一冗餘開關132e及一重置開關132f,各該反相器132d電性連接於該多工器131及各該冗餘開關132e之間,該反相器132d接收該多工器131之各該選擇訊號(SS0至SS15)並提供一反相之該選擇訊號至該冗餘開關132e,該冗餘開關132e電性連接各該電壓開關132a,由於各該冗餘開關132e是接收反相之該選擇訊號,因此,當各該電壓開關132a截止時,各該冗餘開關132e為導通,以避免電荷注入效應(charge injection)影響後端之各該增益放大器132c之輸出,各該重置開關132f之閘極端接收一重置訊號rst,各該重置開關132f之汲極端電性連接各該電容132b,各該重置開關132f之源極端為接地,當各該重置開關132f接收之該重置訊號rst為高電位時,則各該重置開關132f為導通,以使各該電容132b放電至低電位,避免各該重置開關132f再次導通時,各該電容132b無法儲存振幅訊號DAC_out之大小。Referring to FIG. 3, each of the sampling circuits further has an inverter 132d, a redundant switch 132e and a reset switch 132f. Each of the inverters 132d is electrically connected to the multiplexer 131 and Between each of the redundant switches 132e, the inverter 132d receives the selection signals (SS0 to SS15) of the multiplexer 131 and provides an inverted reference signal to the redundant switch 132e. The redundant switch Each of the voltage switches 132a is electrically connected to the voltage switch 132a. Since each of the redundant switches 132e receives the selection signal for inversion, when the voltage switches 132a are turned off, the redundant switches 132e are turned on to avoid charge injection. The charge injection affects the output of each of the gain amplifiers 132c of the back end, and the gate terminals of the reset switches 132f receive a reset signal rst, and the reset switches 132f are electrically connected to the capacitors 132b. The source terminals of the reset switches 132f are grounded. When the reset signals rst received by the reset switches 132f are high, the reset switches 132f are turned on, so that the capacitors 132b are discharged to a low level. Potential, to prevent each of the reset switches 132f from being turned on again, Each of the capacitors 132b cannot store the magnitude of the amplitude signal DAC_out.
請參閱第1及4圖,由於該多通道之脊髓電刺激產生器100所接收之電壓來源通常為低壓之電壓(2.5 V),但低壓之電壓(2.5 V)並無法供後端之該些刺激波形產生器140使用,在本實施例中,藉由該升壓電路150進行升壓,該升壓電路150接收一直流電壓Vcp_in,且該升壓電路150電性連接各該刺激波形產生器140,藉由該升壓電路150將低壓之該直流電壓(2.5 V)升壓至高壓(大於14.7 V)並提供一升壓電壓Vcp_out(大於14.7 V)至各該刺激波形產生器140,或在其他實施例中,可直接提供該多通道之脊髓電刺激產生器100兩組不同振幅電壓之電壓源,請參閱第4圖,在本實施例中,藉由一5級之電荷泵電路(charge pump circuit)進行升壓,該升壓電路150具有5個升壓元件151及一反相器152,各該升壓元件151具有一第一電容151a、一第二電容151b、一第一電晶體151c、一第二電晶體151d、一第三電晶體151e、一第四電晶體151f、一第一節點n1、一第二節點n2、一第三節點n3及一第四節點n4,該第一電容151a電性連接該第三節點n3,且該第一電容151a接收一時脈訊號clk,該第二電容151b電性連接於該反相器152及該第二節點n2之間,且該第二電容151b接收反相之該時脈訊號,該第一電晶體151c之汲極端電性連接該第一節點n1,該第一電晶體151c之閘極端電性連接該第二節點n2,該第一電晶體151c之源極端電性連接該第三節點n3,該第二電晶體151d之源極端電性連接該第三節點n3,該第二電晶體151d之閘極端電性連接該第二節點n2,該第二電晶體151d之汲極端電性連接該第四節點n4,該第三電晶體151e之汲極端電性連接第一節點n1,該第三電晶體151e之閘極端電性連接第三節點n3,該第三電晶體151e之源極端電性連接第二節點n2,該第四電晶體151f之源極端電性連接該第二節點n2,該第四電晶體151f之閘極端電性連接該第三節點n3,該第四電晶體151f之汲極端電性連接該第四節點n4,藉由各該升壓元件151,該直流電壓Vcp_in在通過各該升壓元件150後,該直流電壓Vcp_in皆會疊加一個時脈訊號clk之電壓大小,較佳的,將該時脈訊號clk之電壓大小設定與該直流電壓Vcp_in大小(2.5 V)相同,因此,該直流電壓Vcp_in通過5個升壓元件151後電壓會升壓至15V(2.5 V+2.5 V*5),藉此提供電壓大於14.7 V之該升壓電壓Vcp_out供各該刺激波形產生器140使用。Referring to Figures 1 and 4, since the multi-channel spinal cord stimulation generator 100 receives a voltage source of low voltage (2.5 V), the voltage of the low voltage (2.5 V) is not available for the back end. The stimulation waveform generator 140 is used. In the embodiment, the boosting circuit 150 performs boosting, the boosting circuit 150 receives the DC voltage Vcp_in, and the boosting circuit 150 is electrically connected to each of the stimulation waveform generators. 140, the boost circuit 150 boosts the low voltage DC voltage (2.5 V) to a high voltage (greater than 14.7 V) and provides a boost voltage Vcp_out (greater than 14.7 V) to each of the stimulation waveform generators 140, or In other embodiments, the multi-channel spinal cord electrical stimulation generator 100 can directly provide voltage sources of different amplitude voltages. Referring to FIG. 4, in the embodiment, a 5-level charge pump circuit is used ( The boosting circuit 150 has five boosting elements 151 and an inverter 152. Each of the boosting elements 151 has a first capacitor 151a, a second capacitor 151b, and a first capacitor. a crystal 151c, a second transistor 151d, a third transistor 151e, and a a fourth transistor 151f, a first node n1, a second node n2, a third node n3, and a fourth node n4. The first capacitor 151a is electrically connected to the third node n3, and the first capacitor 151a receives a clock signal clk, the second capacitor 151b is electrically connected between the inverter 152 and the second node n2, and the second capacitor 151b receives the inverted clock signal, the first transistor 151c The first node n1 is electrically connected to the first node n1. The gate of the first transistor 151c is electrically connected to the second node n2. The source of the first transistor 151c is electrically connected to the third node n3. The source of the transistor 151d is electrically connected to the third node n3. The gate of the second transistor 151d is electrically connected to the second node n2. The second transistor 151d is electrically connected to the fourth node n4. The third transistor 151e is electrically connected to the first node n1, and the gate of the third transistor 151e is electrically connected to the third node n3. The source of the third transistor 151e is electrically connected to the second node. N2, the source of the fourth transistor 151f is electrically connected to the second node n2, the fourth transistor The gate of the body 151f is electrically connected to the third node n3, and the fourth transistor 151f is electrically connected to the fourth node n4. The DC voltage Vcp_in passes through each of the boosting elements 151. After the voltage component 150, the DC voltage Vcp_in is superimposed with the voltage of a clock signal clk. Preferably, the voltage of the clock signal clk is set to be the same as the DC voltage Vcp_in (2.5 V). After the DC voltage Vcp_in passes through the five boosting elements 151, the voltage is boosted to 15V (2.5 V+2.5 V*5), thereby providing the boosting voltage Vcp_out having a voltage greater than 14.7 V for use by each of the stimulation waveform generators 140.
請參閱第1及5圖,各該刺激波形產生器140具有一運算放大器141及一類比開關142,各該運算放大器141電性連接各該取樣元件132以接收各該電壓訊號SH_out,且各該運算放大器141輸出一放大電壓訊號HV_out,在本實施例中,各該運算放大器141電性連接該升壓電路150,並以該升壓電路150之該升壓電壓Vcp_out作為各該運算放大器141之電源以放大各該電壓訊號SH_out,各該類比開關142電性連接各該運算放大器141及該控制電路110,以接收各該放大電壓訊號HV_out及該刺激類型訊號STS,且各該類比開關142輸出一刺激電波o_sti,其中各該放大電壓訊號HV_out用以決定該刺激電波o_sti的振幅,而該刺激類型訊號STS用以決定該刺激電波o_sti的頻率、極性及脈衝波寬。Referring to FIGS. 1 and 5, each of the stimulation waveform generators 140 has an operational amplifier 141 and an analog switch 142. Each of the operational amplifiers 141 is electrically connected to each of the sampling elements 132 to receive each of the voltage signals SH_out. The operational amplifier 141 outputs an amplified voltage signal HV_out. In the embodiment, each of the operational amplifiers 141 is electrically connected to the boosting circuit 150, and the boosting voltage Vcp_out of the boosting circuit 150 is used as the operational amplifier 141. The power source amplifies each of the voltage signals SH_out, and each of the analog switches 142 is electrically connected to each of the operational amplifiers 141 and the control circuit 110 to receive the amplified voltage signals HV_out and the stimulation type signals STS, and the analog switches 142 output A stimulating electric wave o_sti, wherein each of the amplified voltage signals HV_out is used to determine the amplitude of the stimulating electric wave o_sti, and the stimulation type signal STS is used to determine the frequency, polarity and pulse width of the stimulating electric wave o_sti.
請參閱第6圖,該運算放大器141具有一低壓端LV及一高壓端HV,該低壓端LV具有一偏壓電路141a及一輸入級電路141b,該輸入級電路141b電性連接該偏壓電路141a,且該偏壓電路141a及該輸入級電路141b皆接收2.5 V之該電壓源VDD,該高壓端HV具有一輸出級電路141c,該輸出級電路141c電性連接該輸入級電路141b,且該輸出級電路141c以該升壓電壓Vcp_out(電壓大於14.7 V)為電壓源,並輸出各該放大電壓訊號HV_out。Referring to FIG. 6, the operational amplifier 141 has a low voltage terminal LV and a high voltage terminal HV. The low voltage terminal LV has a bias circuit 141a and an input stage circuit 141b. The input stage circuit 141b is electrically connected to the bias voltage. The circuit 141a, and the bias circuit 141a and the input stage circuit 141b receive the voltage source VDD of 2.5 V. The high voltage terminal HV has an output stage circuit 141c, and the output stage circuit 141c is electrically connected to the input stage circuit. 141b, and the output stage circuit 141c uses the boosted voltage Vcp_out (voltage greater than 14.7 V) as a voltage source, and outputs each of the amplified voltage signals HV_out.
請參閱第7圖,各該類比開關142以各該運算放大器141之該放大電壓訊號HV_out做為電壓源,且各該類比開關142具有一第一端143、一第二端144,各該電極160電性連接於該第一端143及該第二端144之間,該第一端143具有一第一低壓開關143a、一第一分壓電阻組143b、一第一高壓開關143c及一第一接地開關143d,各該第一低壓開關143a電性連接該控制電路110,該第一分壓電阻組143b電性連接於該第一低壓開關143a及各該運算放大器141之間,該第一高壓開關143c電性連接該第一分壓電阻組143b、各該運算放大器141及各該第一接地開關143d,各該第一接地開關143d電性連接該控制電路110,該第二端144具有一第二低壓開關144a、一第二分壓電阻組144b、一第二高壓開關144c及一第二接地開關144d,各該第二低壓開關144a電性連接該控制電路110,該第二分壓電阻組144b電性連接於該第二低壓開關144a及各該運算放大器141之間,該第二高壓開關144c電性連接該第二分壓電阻組144b、各該運算放大器141及各該第二接地開關144d,各該第二接地開關144d電性連接該控制電路110。Referring to FIG. 7, each of the analog switches 142 uses the amplified voltage signal HV_out of each of the operational amplifiers 141 as a voltage source, and each of the analog switches 142 has a first end 143 and a second end 144. The first end 143 is electrically connected to the first end 143 and the second end 144. The first end 143 has a first low voltage switch 143a, a first voltage dividing resistor group 143b, a first high voltage switch 143c and a first a grounding switch 143d, each of the first low-voltage switch 143a is electrically connected to the control circuit 110, the first voltage-dividing resistor group 143b is electrically connected between the first low-voltage switch 143a and each of the operational amplifiers 141, the first The high voltage switch 143c is electrically connected to the first voltage dividing resistor group 143b, the operational amplifier 141 and the first grounding switch 143d. Each of the first grounding switches 143d is electrically connected to the control circuit 110. The second terminal 144 has a second low voltage switch 144a, a second voltage dividing resistor group 144b, a second high voltage switch 144c and a second grounding switch 144d, each of the second low voltage switch 144a is electrically connected to the control circuit 110, the second voltage dividing The resistor group 144b is electrically connected to the second low voltage switch Between the 144a and each of the operational amplifiers 141, the second high voltage switch 144c is electrically connected to the second voltage dividing resistor group 144b, the operational amplifier 141 and each of the second grounding switches 144d, and each of the second grounding switches 144d is electrically connected. The control circuit 110 is connected sexually.
請參閱第1及7圖,在本實施例中,該控制電路110傳送16組之該刺激類型訊號STS至各該類比電路142,且各該刺激類型訊號STS具有一第一類型訊號STS1及一第二類型訊號STS2,各該第一端143之該第一低壓開關143a及各該第二端144之該第二接地開關144d接收各該第一類型訊號STS1,各該第一類型訊號STS用以決定各該第一低壓開關143a及各該第二接地開關144d導通或截止,因此各該第一低壓開關143a及各該第二接地開關144d同時導通或截止,當各該第一低壓開關143a導通時,該第一分壓電阻組143b接收各該放大電壓訊號HV_out,且各該第一分壓電阻組143b具有一第一電阻143e及一第二電阻143f,各該第一電阻143e及各該第二電阻143f將各該放大電壓訊號HV_out進行分壓以導通各該第一高壓開關143c,因此,當該第一低壓開關143a導通時,該第一高壓開關143c及該第二接地開關144d亦導通而與各該電極160形成一第一迴路L1而產生各該刺激電波o_sti,並藉由各該第一類型訊號STS1的控制,可調整各該刺激電波o_sti的頻率及脈衝波寬。Referring to FIGS. 1 and 7, in the embodiment, the control circuit 110 transmits 16 sets of the stimulation type signal STS to each of the analog circuits 142, and each of the stimulation type signals STS has a first type signal STS1 and a The second type of signal STS2, the first low voltage switch 143a of the first end 143 and the second grounding switch 144d of the second end 144 receive the first type signal STS1, and the first type signal STS In order to determine that each of the first low voltage switch 143a and each of the second grounding switches 144d is turned on or off, each of the first low voltage switch 143a and each of the second grounding switches 144d are simultaneously turned on or off, and each of the first low voltage switches 143a The first voltage dividing resistor group 143b receives each of the amplified voltage signals HV_out, and each of the first voltage dividing resistor groups 143b has a first resistor 143e and a second resistor 143f, each of the first resistors 143e and each The second resistor 143f divides each of the amplified voltage signals HV_out to turn on the first high voltage switch 143c. Therefore, when the first low voltage switch 143a is turned on, the first high voltage switch 143c and the second ground switch 144d Also conductive and The first electrode 160 forms a loop to stimulate each of the L1 wave generating o_sti, and by controlling each STS1 signal of the first type, each of the adjusted stimulation o_sti radio frequency and pulse width.
請參閱第7圖,各該第二端144之該第二低壓開關144a及各該第一端143之該第一接地開關143d接收各該第二類型訊號STS2,各該第二類型訊號STS2用以決定各該第二低壓開關144a及各該第一接地開關143d導通或截止,因此各該第二低壓開關144a及各該第一接地開關143d同時導通或截止,當各該第二低壓開關144a導通時,各該第二分壓電阻組144b接收各該放大電壓訊號HV_out,且各該第二分壓電阻組144b具有一第三電阻144e及一第四電阻144f,各該第三電阻144e及各該第四電阻144f將各該放大電壓訊號HV_out進行分壓以導通各該第二高壓開關144c,因此,當各該第二低壓開關144a導通時,該第二高壓開關144c及該第一接地開關143d亦導通而與各該電極160形成一第二迴路L2而產生各該刺激電波o_sti,並藉由各該第二類型訊號STS2的控制,可調整各該刺激電波o_sti的頻率及脈衝波寬。藉由各該刺激類型訊號STS之該第一類型訊號STS1及該第二類型訊號STS2,可使該第一迴路L1或該第二迴路L2導通或截止,藉此輸出各該刺激電波o_sti於各該電極160上以進行電刺激治療,且由於該第一迴路及該第二迴路之電流方向不同,可藉此改變各該刺激電波o_sti的極性,且各該刺激電波o_sti之振幅與各該放大電壓訊號HV_out相同,因此可藉由各該放大電壓訊號HV_out調整各該刺激電波o_sti的振幅,而各該刺激電波o_sti之頻率、及脈衝波寬則可藉由各該刺激類型訊號STS進行調整,以使該多通道之脊髓電刺激產生器100的應用範圍更加廣泛,可適用於不同類型之電刺激治療。Referring to FIG. 7, the second low-voltage switch 144a of the second end 144 and the first grounding switch 143d of the first end 143 receive the second type signal STS2, and the second type signal STS2 is used. In order to determine that each of the second low voltage switch 144a and each of the first grounding switches 143d is turned on or off, each of the second low voltage switch 144a and each of the first grounding switches 143d are simultaneously turned on or off, and each of the second low voltage switches 144a The second voltage dividing resistor group 144b receives each of the amplified voltage signals HV_out, and each of the second voltage dividing resistor groups 144b has a third resistor 144e and a fourth resistor 144f, each of the third resistors 144e and Each of the fourth resistors 144f divides each of the amplified voltage signals HV_out to turn on the second high voltage switches 144c. Therefore, when the second low voltage switches 144a are turned on, the second high voltage switch 144c and the first ground. The switch 143d is also turned on to form a second loop L2 with each of the electrodes 160 to generate each of the stimulating waves o_sti, and the frequency and pulse width of each of the stimulating waves o_sti can be adjusted by the control of each of the second type signals STS2. . The first loop L1 or the second loop L2 can be turned on or off by the first type signal STS1 and the second type signal STS2 of the stimulus type signal STS, thereby outputting each of the stimulation waves o_sti The electrode 160 is electrically stimulated, and because the current directions of the first loop and the second loop are different, the polarity of each of the stimulation waves o_sti can be changed, and the amplitude of each of the stimulation waves o_sti and each of the amplifications The voltage signals HV_out are the same. Therefore, the amplitude of each of the stimulation waves o_sti can be adjusted by each of the amplified voltage signals HV_out, and the frequency of each of the stimulation waves o_sti and the pulse width can be adjusted by each of the stimulation type signals STS. In order to make the multi-channel spinal cord electrical stimulation generator 100 more widely applicable, it can be applied to different types of electrical stimulation treatment.
本發明藉由該多通道之脊髓電刺激產生器100輸出複數個可調整振幅、頻率、極性及脈衝波寬之該刺激電波o_sti以進行不同類型之電刺激治療,且由於本發明之各個元件整合於一積體電路中,以縮小該多通道之脊髓電刺激產生器100之體積,並可降低該多通道之脊髓電刺激產生器100之功耗,以減低使用者對於植入式之裝置的不適。The multi-channel spinal cord electrical stimulation generator 100 outputs a plurality of the stimulation waves o_sti of adjustable amplitude, frequency, polarity and pulse width to perform different types of electrical stimulation therapy, and is integrated by the various components of the present invention. In an integrated circuit, the volume of the multi-channel spinal cord electrical stimulation generator 100 is reduced, and the power consumption of the multi-channel spinal cord electrical stimulation generator 100 can be reduced to reduce the user's use of the implantable device. Discomfort.
本發明之保護範圍當視後附之申請專利範圍所界定者為準,任何熟知此項技藝者,在不脫離本發明之精神和範圍內所作之任何變化與修改,均屬於本發明之保護範圍。The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
100...多通道之脊髓電刺激產生器100. . . Multi-channel spinal cord stimulation generator
110...控制電路110. . . Control circuit
120...數位類比轉換電路120. . . Digital analog conversion circuit
121...電流開關組121. . . Current switch group
121a...電流源121a. . . Battery
121b...電流開關121b. . . Current switch
122...緩衝器122. . . buffer
123...接地電阻123. . . Grounding resistance
130...取樣電路130. . . Sampling circuit
131...多工器131. . . Multiplexer
132...取樣元件132. . . Sampling component
132a...電壓開關132a. . . Voltage switch
132b...電容132b. . . capacitance
132c...增益緩衝器132c. . . Gain buffer
132d...反相器132d. . . inverter
132e...冗餘開關132e. . . Redundant switch
132f...重置開關132f. . . Reset switch
140...刺激波形產生器140. . . Stimulus waveform generator
141...運算放大器141. . . Operational Amplifier
141a...偏壓電路141a. . . Bias circuit
141b...輸入級電路141b. . . Input stage circuit
141c...輸出級電路141c. . . Output stage circuit
142...類比開關142. . . Analog switch
143...第一端143. . . First end
143a...第一低壓開關143a. . . First low voltage switch
143b...第一分壓電阻組143b. . . First voltage dividing resistor group
143c...第一高壓開關143c. . . First high voltage switch
143d...第一接地開關143d. . . First grounding switch
143e...第一電阻143e. . . First resistance
143f...第二電阻143f. . . Second resistance
144...第二端144. . . Second end
144a...第二低壓開關144a. . . Second low voltage switch
144b...第二分壓電阻組144b. . . Second voltage dividing resistor
144c...第二高壓開關144c. . . Second high voltage switch
144d...第二接地開關144d. . . Second grounding switch
144e...第三電阻144e. . . Third resistance
144f...第四電阻144f. . . Fourth resistor
150...升壓電路150. . . Boost circuit
151...升壓元件151. . . Boost element
151a...第一電容151a. . . First capacitor
151b...第二電容151b. . . Second capacitor
151c...第一電晶體151c. . . First transistor
151d...第二電晶體151d. . . Second transistor
151e...第三電晶體151e. . . Third transistor
151f...第四電晶體151f. . . Fourth transistor
152...反相器152. . . inverter
160...電極160. . . electrode
200...電刺激產生器200. . . Electrical stimulation generator
210...電源供應單元210. . . Power supply unit
220...電壓轉換單元220. . . Voltage conversion unit
230...控制單元230. . . control unit
240...保護元件240. . . Protective component
250...儲能元件250. . . Energy storage component
260...電流方向控制開關260. . . Current direction control switch
270...輸出線圈270. . . Output coil
ACS...振幅控制訊號ACS. . . Amplitude control signal
CSS...通道選擇訊號CSS. . . Channel selection signal
STS...刺激類型訊號STS. . . Stimulus type signal
STS1...第一類型訊號STS1. . . First type signal
STS2...第二類型訊號STS2. . . Second type signal
DAC_out...振幅訊號DAC_out. . . Amplitude signal
SS...選擇訊號SS. . . Select signal
SH_out...電壓訊號SH_out. . . Voltage signal
HV_out...放大電壓訊號HV_out. . . Amplified voltage signal
o_sti...剌激電波O_sti. . . Shock wave
Vcp_in...直流電壓Vcp_in. . . DC voltage
clk...時脈訊號Clk. . . Clock signal
Vcp_out...升壓電壓Vcp_out. . . Boost voltage
L1...第一迴路L1. . . First loop
L2...第二迴路L2. . . Second loop
dac_vbias...直流偏壓Dac_vbias. . . DC bias
VDD...電壓源VDD. . . power source
n1...第一節點N1. . . First node
n2...第二節點N2. . . Second node
n3...第三節點N3. . . Third node
n4...第四節點N4. . . Fourth node
rst...重置訊號Rst. . . Reset signal
LV...低壓端LV. . . Low pressure end
HV...高壓端HV. . . High pressure end
第1圖:依據本發明之一實施例,一種多通道之脊髓電刺激產生器的方塊圖。第2圖:依據本發明之一實施例,一數位類比轉換電路的電路圖。第3圖:依據本發明之一實施例,一取樣電路的電路圖。第4圖:依據本發明之一實施例,一升壓電路的電路圖。第5圖:依據本發明之一實施例,一刺激波形產生器的電路示意圖。第6圖:依據本發明之一實施例,該刺激波形產生器之一運算放大器的電路圖。第7圖:依據本發明之一實施例,該刺激波形產生器之一類比開關的電路圖。第8圖:一種習知電刺激產生器的方塊圖。1 is a block diagram of a multi-channel spinal cord electrical stimulation generator in accordance with an embodiment of the present invention. 2 is a circuit diagram of a digital analog conversion circuit in accordance with an embodiment of the present invention. Figure 3 is a circuit diagram of a sampling circuit in accordance with an embodiment of the present invention. Figure 4 is a circuit diagram of a booster circuit in accordance with an embodiment of the present invention. Figure 5 is a circuit diagram of a stimulus waveform generator in accordance with an embodiment of the present invention. Figure 6 is a circuit diagram of an operational amplifier of one of the stimulation waveform generators in accordance with an embodiment of the present invention. Figure 7 is a circuit diagram of an analog switch of one of the stimulation waveform generators in accordance with an embodiment of the present invention. Figure 8: A block diagram of a conventional electrical stimulation generator.
100...多通道之脊髓電刺激產生器100. . . Multi-channel spinal cord stimulation generator
110...控制電路110. . . Control circuit
120...數位類比轉換電路120. . . Digital analog conversion circuit
130...取樣電路130. . . Sampling circuit
140...刺激波形產生器140. . . Stimulus waveform generator
150...升壓電路150. . . Boost circuit
160...電極160. . . electrode
ACS...振幅控制訊號ACS. . . Amplitude control signal
CSS...通道選擇訊號CSS. . . Channel selection signal
STS...刺激類型訊號STS. . . Stimulus type signal
DAC_out...振幅訊號DAC_out. . . Amplitude signal
SH_out...電壓訊號SH_out. . . Voltage signal
Vcp_in...直流電壓Vcp_in. . . DC voltage
clk...時脈訊號Clk. . . Clock signal
Vcp_out...升壓電壓Vcp_out. . . Boost voltage
dac_vbias...直流偏壓Dac_vbias. . . DC bias
rst...重置訊號Rst. . . Reset signal
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