TWI512952B - Memory device and method of fabricating the same - Google Patents

Description

Memory element and method of manufacturing same

The present invention relates to a memory element and a method of fabricating the same.

Non-volatile memory allows multiple data stylization, reading and erasing operations, and even saves the data stored in the memory after the power is interrupted. Because of these advantages, non-volatile memory has become a widely used memory in personal computers and electronic devices.

Well-known electrically programmable and erasable non-volatile memory technologies such as electronic erasable programmable read-only memory (EEPROM) and flash memory using charge storage structures Memory (flash memory) has been used in a variety of modern applications. A typical flash memory cell stores charge in a floating gate. Another type of flash memory uses a charge-trapping structure of a non-conducting material, such as tantalum nitride, to replace the conductive material of the floating gate. When the charge trapping memory cell is programmed, the charge is captured and does not move through the non-conductor charge trapping structure. When the power supply is not continuously supplied, the charge remains in the charge trapping layer, maintaining its data state until the memory cells are erased. The charge trapping memory cell can be manipulated as a two-sided cell. That is, since the charge does not move through the non-conductor charge trapping layer, the charge can be located at a different charge trap. In other words, in the flash memory structure of the charge trapping structure type, information of more than one bit can be stored in each memory cell.

Operating margin (memory operation window). In other words, the memory operation margin is defined by the difference between the programmed level and the erase level. Since memory cell operation requires good level separation between various states, a large memory operation margin is required. However, the performance of a two-dimensional memory cell generally decreases with the so-called "second bit effect." Under the second bit effect, the charges localized in the charge trapping structure interact with each other. For example, during a reverse read, a read bias is applied to the drain terminal and a charge stored near the source region (ie, the first bit) is detected. However, the bit (i.e., the second bit) that is then near the drain region produces a potential barrier that reads the first bit near the source region. This energy barrier can be overcome by applying an appropriate bias voltage, using the drain-induced energy barrier reduction (DIBL) effect to suppress the effect of the second bit near the drain region, and allowing the storage state of the first bit to be detected. However, when the second bit near the drain region is programmed to a high start voltage state and the first bit near the source region is in an unprogrammed state, the second bit substantially increases the energy barrier. Therefore, as the starting voltage with respect to the second bit increases, the read bias of the first bit is not sufficient to overcome the potential barrier generated by the second bit. Therefore, since the starting voltage of the second bit increases, the starting voltage of the first bit increases, thereby reducing the memory operating margin. The second bit effect reduces the operating margin of the 2-bit memory.

In addition, the stylization of memory cells can utilize channel hot electron injection to generate hot electrons in the channel region. When the memory cells on the drain side are programmed, the thermal electrons drifting from the programmed memory cells can also cause the memory cells on the adjacent source side to be stylized at the same time.

Therefore, there is a need for a memory device that can suppress the second bit effect and avoid stylized interference, and a method of fabricating the same.

The present invention provides a memory element that can provide a positioned charge storage region to allow charge to be fully localized, reduce second bit effects, and reduce stylized interference behavior.

The invention provides a method for manufacturing a memory element, which can make a memory storage component can provide a positioned charge storage area through a simple process, so that the charge can be completely positioned and stored, thereby obtaining a better second bit and reducing the program. The act of disrupting.

Embodiments of the present invention provide a memory device including a substrate, a plurality of first insulating structures, a plurality of bit lines, a plurality of dielectric layers, a plurality of pairs of charge storage structures, and a plurality of word lines. There are a plurality of trenches in the substrate, and the trenches are arranged in the first direction. The first insulating structure is located in the trench. The bit line is located in the substrate below the first insulating structure. Each dielectric layer is on the substrate between adjacent two first insulating structures. Each charge storage structure is located on the substrate between the adjacent first insulating structure and the dielectric layer. Each of the word lines is arranged in a second direction to cover the first insulating structure, the charge storage structure, the dielectric layer, and a portion of the substrate.

According to an embodiment of the invention, each word line is composed of a single conductor layer, and the single conductor layer is filled in a first gap between the two adjacent pairs of charge storage structures and each pair of charges A second gap between the storage structures.

According to an embodiment of the invention, the memory element further includes a plurality of second insulating structures, and each of the second insulating structures is located on the corresponding first insulating structure and is filled in two adjacent pairs. A first gap between the charge storage structures. Each word line includes a patterned first conductor layer and a patterned second conductor layer. Wherein each patterned first conductor layer is located between two adjacent second insulating structures, is filled in a second gap between each pair of charge storage structures, and covers the charge storage structure and the a dielectric layer; and the patterned second conductor layer overlying the patterned first conductor layer and the insulating structure.

Embodiments of the present invention also provide a memory device including: a substrate, a plurality of first insulating structures, a plurality of bit lines, a plurality of dielectric layers, a plurality of pairs of charge storage structures, and a plurality of word lines. There are a plurality of trenches in the substrate, and the trenches are arranged in the first direction. The first insulating structure is located in the trench. The bit line is located in the substrate below the first insulating structure. Each dielectric layer is on the substrate between adjacent two first insulating structures. Each charge storage structure is located on the substrate between the adjacent first insulating structure and the dielectric layer. Each word line is arranged in a second direction, the word line is composed of a single conductor layer, and the conductor layer is filled in a first gap between two adjacent pairs of charge storage structures and each pair of charge stores a second gap between the structures and in contact with the first insulating structure, the charge storage structure, the dielectric layer, and a portion of the substrate.

According to an embodiment of the invention, the charge storage structure comprises a dielectric charge storage layer.

The embodiment of the invention further provides a method for manufacturing a memory device, comprising: forming a plurality of trenches in the substrate, each of the trenches being arranged in a first direction. A plurality of first insulating structures are formed in the trench. A plurality of bit lines are formed, the bit lines being located in the substrate below the first insulating structure. A plurality of dielectric layers are formed, each dielectric layer being on the substrate between adjacent two first insulating structures. A plurality of pairs of charge storage structures are formed, each charge storage structure being located on the substrate between the adjacent first insulating structures and the dielectric layer. A plurality of word line lines are formed, each of the word lines being aligned in a second direction to cover the first insulating structure, the charge storage structure, the dielectric layer, and a portion of the substrate.

According to an embodiment of the invention, the step of forming the word line includes: forming a single conductor layer; and patterning the single conductor layer to form the word line, the word line filling a first gap between two adjacent pairs of charge storage structures and a second gap between each pair of charge storage structures, and with the first insulating structure, the charge storage structure, the dielectric layer, and a portion Said substrate contact.

According to an embodiment of the invention, the method of forming the charge storage structure, the dielectric layer, the bit line, and the word line includes forming a charge storage stack layer on the substrate. The charge storage stack layer is patterned to form a plurality of patterned charge storage stack layers having the second gap between the patterned charge storage stack layers. The dielectric layer is formed in the second gap. A mask layer is formed overlying the patterned charge storage stack layer, the dielectric layer, and the substrate, and is filled in the second gap. Patterning the mask layer and the patterned charge storage stack layer to form a plurality of patterned mask layers and the charge storage structure, and forming the first gap to expose the first An insulating structure. The ion masking process is performed by using the patterned mask layer as a mask, and the bit line is formed in the substrate under the first isolation structure. The patterned mask layer is removed to expose the second gap and the first gap. The word line is formed.

According to an embodiment of the invention, the step of forming the word line includes: forming a plurality of patterned first conductor layers, the patterned first conductor layer being located between each pair of charge storage structures And a second gap covering the charge storage structure to expose the first insulating structure. A plurality of second insulating structures are formed, the second insulating structures being positioned in a first gap between adjacent pairs of charge storage structures and covering the first insulating structures. A plurality of patterned second conductor layers are formed, and the patterned second conductor layer covers the patterned first conductor layer and the insulating structure.

According to an embodiment of the invention, the method for forming the charge storage structure, the dielectric layer, the bit line, the patterned first conductor layer, and the second insulating structure includes: A charge storage stack layer is formed on the substrate. The charge storage stack layer is patterned to form a plurality of patterned charge storage stack layers having the second gap between the patterned charge storage stack layers. The dielectric layer is formed in the second gap. A first conductor layer is formed covering the patterned charge storage stack layer, the dielectric layer, and the substrate, and is filled in the second gap. Patterning the first conductor layer and the patterned charge storage stack layer to form the patterned first conductor layer and the charge storage structure, and forming the first gap to expose the first An insulating structure. And performing the ion implantation process by using the patterned first patterned first conductor layer as a mask, and forming the bit line in the substrate under the first isolation structure. The second insulating structure is formed in the first gap.

Based on the above, the memory element of the present invention can provide a positioned charge storage area to allow charge to be fully localized, reduce second bit effects, and reduce stylized interference behavior.

In addition, the manufacturing method of the memory element of the present invention can make the fabricated memory element provide a positioned charge storage area through a simple process, so that the charge can be completely positioned and stored, thereby obtaining a better second bit and reducing Stylized interference behavior.

The above described features and advantages of the invention will be apparent from the following description.

1A is a top view of a memory element in accordance with a second embodiment of the present invention. 1B is a cross-sectional view taken along line I-I of FIG. 1A. 1C is a cross-sectional view taken along line II-II of FIG. 1A.

1A, FIG. 1B and FIG. 1C, a memory device according to a first embodiment of the present invention includes a substrate 10, a plurality of bit lines 50, a plurality of word lines 44, a plurality of pairs of charge storage structures 30, and a plurality of dielectric layers. Layer 34, a plurality of insulating structures 18, and a plurality of insulating structures 40. Each memory cell includes a word line 44, two bit lines 50, two charge storage structures 30, and a dielectric layer 34. The two charge storage structures 30 are physically separated by a dielectric layer 34 and a word line 44.

There is a well 20 in the substrate 10. The well region 20 has a plurality of trenches 12 extending in a first direction and arranged in a parallel or substantially parallel manner. The insulating structure 18 is located in the trench 12. The bit line 50 is located in the well region 20 below the insulating structure 18. Each dielectric layer 34 is located on the well region 20 between adjacent two insulating structures 18. Each of the charge storage structures 30 is located on the substrate 10 between the adjacent insulating structures 18 and the dielectric layer 34. The insulating structure 40 is located on the corresponding insulating structure 18 and is filled in the gap 38 between the adjacent two pairs of charge storage structures 30. A plurality of word lines 44, extending in the second direction, are arranged in a parallel or substantially parallel manner, covering the insulating structure 18, the charge storage structure 30, the dielectric layer 34, and portions of the well region 20. Each word line 44 includes a patterned conductor layer 36a and a patterned conductor layer 42. Each patterned conductor layer 36a is located between two adjacent insulating structures 40, filling a gap 32 between each pair of charge storage structures 30, and covering the charge storage structure 30, the dielectric layer 34, and the well region 20 The cross section is, for example, T-shaped. Each patterned conductor layer 42 extends in a second direction, covering the patterned conductor layer 36a and the insulating structure 40. The second extending direction and the first extending direction may be perpendicular to each other or substantially perpendicular to each other.

2A to 2E illustrate a method of fabricating a memory device in accordance with a second embodiment of the present invention.

Referring to FIG. 2A, a plurality of trenches 12 are formed in the substrate 10, and the trenches 12 extend in the first direction and are arranged in a parallel or substantially parallel manner. Substrate 10 can be a semiconductor substrate, such as a germanium substrate, or a semiconductor compound substrate, such as a gallium arsenide substrate. The trench 12 can be formed by forming a patterned pad oxide layer 14 and a mask layer 16 on the substrate 10 and then forming the process by etching the substrate 10. The depth of the trench 12 is, for example, 300 to 1500 angstroms.

The pad oxide layer 14 can be formed by thermal oxidation or chemical vapor deposition. The material of the mask layer 16 may be tantalum nitride, and the formation method thereof is, for example, chemical vapor deposition.

An insulating structure 18 is formed in the trench 12. The insulating structure 18 is formed by, for example, forming an insulating layer on the substrate 10, the insulating layer covering the mask layer 16 and filling the trench 12, and then performing a chemical mechanical polishing process or an etching process to remove the insulating layer other than the trench 12. . The material of the insulating layer is, for example, cerium oxide or other dielectric material, and the method of forming it is, for example, chemical vapor deposition.

Referring to FIG. 2B, the mask layer 16 and the pad oxide layer 14 are removed. A well region 20 is then formed in the substrate 10. The well region 20 can be formed by ion implantation. The well region 20 has a dopant of a first conductivity type, such as a P-type dopant, such as boron or boron difluoride ions.

Thereafter, a charge storage stack layer 28 is formed on the substrate 10. The charge storage stack layer 28 includes a dielectric charge storage layer, such as tantalum nitride. In an embodiment, the charge storage structure 30 includes a hafnium oxide layer 22, a tantalum nitride layer 24, and a hafnium oxide layer 26. The method of forming the ruthenium oxide layer 22 and the ruthenium oxide layer 26 is, for example, a thermal oxidation method, a chemical vapor deposition method, or an in-situ steam generation. The tantalum nitride layer 24 can be formed by furnace tube nitridation or chemical vapor deposition. The thickness of the hafnium oxide layer 22, the tantalum nitride layer 24, and the hafnium oxide layer 26 may be, for example, 25 to 45 angstroms, 45 to 65 angstroms, and 80 to 120 angstroms, respectively.

Referring to FIG. 1C, the charge storage stack layer 28 is patterned to form a patterned charge storage stack layer 29. The patterned charge storage stack layer 29 is over the insulating structure 18 and extends over the well region 20 on either side of the insulating structure 18. There is a gap 32 between adjacent two patterned charge storage stack layers 29.

Next, a dielectric layer 34 is formed in the gap 32 between the adjacent two patterned charge storage stack layers 29. The material of the dielectric layer 34 is, for example, ruthenium oxide, and the method of formation is, for example, a thermal oxidation method. The thickness of the dielectric layer 34 is, for example, 25 to 70 angstroms.

Thereafter, a conductor layer 36 is formed on the substrate 10. The conductor layer 36 covers the patterned charge storage stack layer 29 and fills the gap 32 to cover the dielectric layer 34. The material of the conductor layer 36 is, for example, doped polysilicon, and the method of forming it is, for example, a chemical vapor deposition method or a sputtering method. The material of the conductor layer 36 is, for example, doped polysilicon, and the method of formation is, for example, a chemical vapor deposition method. The thickness of the conductor layer 36 is, for example, 300 to 500 angstroms.

Thereafter, referring to FIG. 2D, the conductor layer 36 and the patterned charge storage stack layer 29 are patterned to form a patterned conductor layer 36a and a charge storage structure 30 and a gap 38. A pair of charge storage structures 30 are disposed on the substrate 10 between the adjacent two insulating structures 18, and a gap 32 is formed between each pair of charge storage structures 30, and a dielectric layer 34 is filled in the gap 32; The conductor layer 36a covers the charge storage structure 30 and is filled in the gap 32 to cover the dielectric layer 34. The gap 38 is located between two adjacent pairs of charge storage structures 30, exposing the insulating structure 18.

Thereafter, a bit line 50 (also referred to as a source and drain region) is formed in the well region 20 below the insulating structure 18. The formation method of the bit line 50 is performed by, for example, using the patterned conductor layer 36a as a mask to perform an ion implantation process to implant a dopant having a second conductivity type into the well region 20. The dopant of the second conductivity type is an N-type dopant such as phosphorus or arsenic.

Thereafter, referring to FIG. 2E, an insulating structure 40 is formed in the gap 38. The material of the insulating layer 40 is, for example, yttrium oxide or other dielectric material. The method of forming the insulating structure 40 is, for example, forming an insulating layer (not shown) on the substrate 10. The insulating layer covers the patterned conductor layer 36a and is filled in the gap 38. Then, a chemical mechanical polishing process or an etching process is performed to remove the insulating layer other than the gap 38.

Thereafter, a patterned conductor layer 42 is formed on the substrate 10. The patterned conductor layers 42 extend in a second direction and are arranged in a parallel or substantially parallel manner, covering the insulating structure 40 and the charge storage structure 30. The method of forming the patterned conductor layer 42 is, for example, forming a layer of a conductor material and then patterning by lithography. The material of the conductor material layer as the patterned conductor layer 42 is, for example, doped polysilicon, which is formed by, for example, chemical vapor deposition or sputtering, and has a thickness of, for example, 200 to 700 Å. An etching process may be performed to remove the native oxide layer formed on the surface of the patterned conductor layer 36a prior to forming the conductive material layer. The patterned conductor layer 42 and the patterned conductor layer 36a serve as word lines 44.

3A is a top view of a memory element in accordance with a second embodiment of the present invention. 3B is a cross-sectional view taken along line IV-IV of FIG. 3A. 3C is a cross-sectional view taken along line V-V of FIG. 3A.

Referring to FIG. 3A, FIG. 3B and FIG. 3C, a memory element according to a second embodiment of the present invention includes a substrate 10, a plurality of bit lines 50, a plurality of word lines 54, a plurality of pairs of charge storage structures 30, and a plurality of dielectrics. Layer 34 and a plurality of insulating structures 18. Each memory cell includes a word line 54, two bit lines 50, two charge storage structures 30, and a dielectric layer 34. The two charge storage structures 30 are physically separated by a dielectric layer 34 and a word line 54.

There is a well 20 in the substrate 10. The well region 20 has a plurality of trenches 12 extending in a first direction and arranged in a parallel or substantially parallel manner. The insulating structure 18 is located in the trench 12. The bit line 50 is located in the well region 20 below the insulating structure 18. Each dielectric layer 34 is located on the well region 20 between adjacent two insulating structures 18. Each of the charge storage structures 30 is located on the substrate 10 between the adjacent insulating structures 18 and the dielectric layer 34. A plurality of word lines 54, extending in the second direction, are arranged in a parallel or substantially parallel manner. Each word line 54 is formed by a single patterned conductor layer that fills a gap 38 between two adjacent pairs of charge storage structures 30, covers the insulating structure 18, and is filled between each pair of charge storage structures 30. The gap 32 covers the dielectric layer 34, the charge storage structure 30, and the well region 20. In other words, the word line 54 composed of a single patterned conductor layer extends in the second direction, and its shape is, for example, a comb shape.

4A to 4D illustrate a method of fabricating a memory device in accordance with a second embodiment of the present invention.

Referring to FIG. 4A, a plurality of trenches 12 extending in a first direction and arranged in a parallel or substantially parallel manner are formed in the substrate 10 in accordance with the method of the first embodiment described above, and an insulating structure 18 is formed in the trenches 12. A well region 20 is then formed in the substrate 10. Thereafter, a patterned charge storage stack layer 29 is formed on the substrate 10. Next, a dielectric layer 34 is formed in the gap 32 between the adjacent two patterned charge storage stack layers 29.

Thereafter, a hard mask layer 46 is formed on the substrate 10. The hard mask layer 46 covers the patterned charge storage stack layer 29 and fills the gap 32 to cover the dielectric layer 34. The material of the hard mask layer 46 is, for example, tantalum nitride, and the method of forming it is, for example, a chemical vapor deposition method or a furnace tube nitride method. The thickness of the hard mask layer 46 is, for example, 500 to 1000 angstroms.

Thereafter, referring to FIG. 4B, the hard mask layer 46 and the patterned charge storage stack layer 29 are patterned to form a patterned hard mask layer 46a and charge storage structure 30 and gaps 38. A pair of charge storage structures 30 are disposed on the substrate 10 between the adjacent two insulating structures 18, and a gap 32 is formed between each pair of charge storage structures 30, and a dielectric layer 34 is filled in the gap 32; The hard mask layer 46a covers the charge storage structure 30 and is filled in the gap 32 to cover the dielectric layer 34. The gap 38 is located between two adjacent pairs of charge storage structures 30b, exposing the insulating structure 18.

Thereafter, a bit line 50 is formed in the well region 20 below the insulating structure 18. The formation method of the bit line 50 is performed by, for example, using a patterned hard mask layer 46a as a mask to perform an ion implantation process to implant a dopant having a second conductivity type into the well region 20. The dopant of the second conductivity type is an N-type dopant such as phosphorus or arsenic.

Thereafter, referring to FIG. 4C, the patterned hard mask layer 46a is removed, exposing the charge storage structure 30, the dielectric layer 34, and the insulating structure 18.

Thereafter, referring to FIG. 4D, a patterned conductor layer is formed on the substrate 10 as the word line 54. The word lines 54 extend in the second direction and are arranged in a parallel or substantially parallel manner. More specifically, each word line 54 is formed of a single patterned conductor layer that is filled in a gap 38 between two adjacent pairs of charge storage structures 30, overlying the insulating structure 18, and filled in pairs of charges. A gap 32 between the structures 30 is stored and covers the dielectric layer 34, the charge storage structure 30, and the well region 20 (Fig. 3C). In other words, the word line 54 composed of a single patterned conductor layer extends in the second direction, and a portion extends toward the surface (downward) of the substrate 10, and is shaped, for example, in a comb shape. The formation method of the word line 54 is, for example, forming a layer of a conductor material and then patterning by lithography. The material of the conductor material layer as the patterned conductor layer 54 is, for example, doped polysilicon, which is formed by, for example, chemical vapor deposition or sputtering, and has a thickness of, for example, 300 to 700 Å.

The word line of the second embodiment of the present invention is composed of a single conductor layer, which avoids the problem of using a two-layer conductor layer to form a native oxide layer between the conductor layers, and therefore, an additional step of removing the native oxide layer may not be required. Improve process steps and improve component reliability.

Referring to FIG. 1C and FIG. 3C, in the above embodiment of the present invention, each memory cell includes one word line 44/54, two bit lines 50, two charge storage structures 30, and a dielectric layer 34. The two charge storage structures 30 are physically separated by a dielectric layer 34 and word lines 44/54. According to the following formula, the embodiment of the present invention can narrow the width of the distribution of the starting voltage and avoid the second bit effect.

Where gm is the transfer conductance (transconductance). The ID is the bungee current. VG is the gate voltage. W is the width of the gate (word line). Mn is the electron/hole mobility. L is the gate length. Kox is the dielectric constant of the oxide. Tox is the oxide thickness. VD is the drain voltage. VT is the threshold voltage.

FIG. 5 is a diagram showing a starting voltage distribution curve of a conventional memory element and a memory element of a second embodiment of the present invention.

Referring to FIG. 5, the width of the starting voltage distribution curve 100 of the memory element of the second embodiment of the present invention is narrower than the starting voltage distribution curve 200 of the conventional memory element.

Referring to FIG. 1C and FIG. 3C, in the above embodiment of the present invention, the two charge storage structures 30 of two adjacent memory cells are separated by an insulating structure 18 in the well region 20 and an insulating structure 40 on the substrate 10. (First Embodiment) or separated by an insulating structure 18 in the well region 20 and a word line 54 on the substrate 10 (second embodiment), since the insulating structure 18 is located in the trench 12 having a sufficient depth, When the memory cells on the bungee side are stylized, it is possible to avoid the problem that the thermal electrons drifting of the stylized memory cells causes the memory cells on the adjacent source side to be stylized at the same time.

In summary, the two charge storage structures of the memory cell of the present invention are physically separated, so that the second bit effect can be avoided. The adjacent two memory cells are separated by an insulating structure located in the trench of the substrate and an insulating structure on the substrate, or are separated by an insulating structure in the trench of the substrate and a word line on the substrate, thereby avoiding stylization Interference (PDX) issue.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Base

12. . . ditch

14. . . Pad oxide

16. . . Mask layer

18, 40. . . Insulation structure

20. . . Well area

22, 26. . . Cerium oxide layer

twenty four. . . Tantalum nitride layer

28. . . Charge storage stack

29. . . Patterned charge storage stack

30. . . Charge storage structure

32, 38. . . gap

34. . . Dielectric layer

36. . . Conductor layer

36a, 42. . . Patterned conductor layer

44, 54. . . Word line

50. . . Bit line

100, 200. . . curve

I-I, II-II, IV-IV, V-V. . . Section line

1A is a top view of a memory element in accordance with a first embodiment of the present invention. 1B is a cross-sectional view taken along line I-I of FIG. 1A. 1C is a cross-sectional view taken along line II-II of FIG. 1A. 2A to 2E illustrate a method of fabricating a memory device in accordance with a second embodiment of the present invention. 3A is a top view of a memory element in accordance with a second embodiment of the present invention. 3B is a cross-sectional view taken along line IV-IV of FIG. 3A. 3C is a cross-sectional view taken along line V-V of FIG. 3A. 4A to 4D illustrate a method of fabricating a memory device in accordance with a second embodiment of the present invention. FIG. 5 is a diagram showing a starting voltage distribution diagram of a conventional memory device according to a second embodiment of the present invention.

10. . . Base

12. . . ditch

18. . . Insulation structure

20. . . Well area

22, 26. . . Cerium oxide layer

twenty four. . . Tantalum nitride layer

30. . . Charge storage structure

32, 38. . . gap

34. . . Dielectric layer

50. . . Bit line

54. . . Word line

Claims (10)

A memory element comprising: a substrate having a plurality of trenches therein, each trench being arranged along a first direction; a plurality of first insulating structures being located in the trench; a plurality of bit lines located at the In the substrate under an insulating structure; a plurality of dielectric layers, each dielectric layer being located on the substrate between two adjacent first insulating structures; and a plurality of charge storage structures, each charge storage structure being located And adjacent to the substrate between the first insulating structure and the dielectric layer; and a plurality of word line lines, each word line is arranged along a second direction to cover the first insulating structure, A charge storage structure, the dielectric layer, and a portion of the substrate. The memory device of claim 1, wherein each word line is composed of a single conductor layer, and the single conductor layer is filled in between the two adjacent pairs of charge storage structures. a gap and a second gap between each pair of charge storage structures. The memory device of claim 1, further comprising a plurality of second insulating structures, wherein each of the second insulating structures is located on the corresponding first insulating structure and is filled in two adjacent pairs. a first gap between the charge storage structures; and each word line includes a patterned first conductor layer and a patterned second conductor layer, wherein: each patterned first conductor layer is adjacent Between the two second insulating structures, filling a second gap between each pair of charge storage structures, and covering the charge storage structure and the dielectric layer; and the patterned second conductor layer, Covering the patterned first conductor layer and the insulating structure. A memory element comprising: a substrate having a plurality of trenches therein, each trench being arranged along a first direction; a plurality of first insulating structures being located in the trench; a plurality of bit lines located at the In the substrate under an insulating structure; a plurality of dielectric layers, each dielectric layer being located on the substrate between two adjacent first insulating structures; and a plurality of charge storage structures, each charge storage structure being located Adjacent to the substrate between the first insulating structure and the dielectric layer; and a plurality of word lines, each word line is arranged in a second direction, the word line being a single conductor The layer is composed of, and the conductor layer is filled in a first gap between two adjacent pairs of charge storage structures and a second gap between each pair of charge storage structures, and the first insulation structure, the charge The storage structure, the dielectric layer, and a portion of the substrate are in contact. The memory device of claim 4, wherein the charge storage structure comprises a dielectric charge storage layer. A method for manufacturing a memory device, comprising: forming a plurality of trenches in a substrate, each of the trenches being arranged along a first direction; forming a plurality of first insulating structures in the trench; forming a plurality of bit lines, Each of the bit lines is located in the substrate under the first insulating structure; a plurality of dielectric layers are formed, each dielectric layer being located on the substrate between adjacent two first insulating structures; forming a majority of pairs of charges a storage structure, each charge storage structure is located on the substrate between the adjacent first insulating structure and the dielectric layer; and a plurality of word line lines are formed, each of the word lines along a second direction Arranging, covering the first insulating structure, the charge storage structure, the dielectric layer, and a portion of the substrate. The method of manufacturing the memory device of claim 6, wherein the forming the word line comprises: forming a single conductor layer; and patterning the single conductor layer to form the word line, The word line is filled in a first gap between two adjacent pairs of charge storage structures and a second gap between each pair of charge storage structures, and the first insulation structure, the charge storage structure, The dielectric layer and a portion of the substrate are in contact. The method of manufacturing a memory device according to claim 7, wherein the charge storage structure, the dielectric layer, the bit line, and the method of forming the word line include: on the substrate Forming a charge storage stack layer; patterning the charge storage stack layer to form a plurality of patterned charge storage stack layers, wherein the patterned charge storage stack layers have the second gap therebetween; Forming the dielectric layer in the second gap; forming a mask layer covering the patterned charge storage stack layer, the dielectric layer, and the substrate, and filling in the Forming the mask layer and the patterned charge storage stack layer to form a plurality of patterned mask layers and the charge storage structure, and forming the first gap, exposed Forming the first insulating structure; performing the ion implantation process with the patterned mask layer as a mask, forming the bit line in the substrate under the first isolation structure; Patterned mask layer, bare And forming the second gap and the first gap; and forming the word line. The method of manufacturing a memory device according to claim 6, wherein the forming the word line comprises: forming a plurality of patterned first conductor layers, wherein the patterned first conductor layer is located in each pair a second gap between the charge storage structures, and covering the charge storage structure, exposing the first insulating structure; forming a plurality of second insulating structures, the second insulating structures being located in adjacent pairs of charge storage a first gap between the structures, and covering the first insulating structure; and forming a plurality of patterned second conductor layers, the patterned second conductor layer covering the patterned first conductor layer and The insulating structure. The method of manufacturing a memory device according to claim 9, wherein the charge storage structure, the dielectric layer, the bit line, the patterned first conductor layer, and the second insulation The method of forming a structure includes: forming a charge storage stack layer on the substrate; patterning the charge storage stack layer to form a plurality of patterned charge storage stack layers, the patterned charge storage layer Having the second gap between the stacked layers; forming the dielectric layer in the second gap; forming a first conductor layer covering the patterned charge storage stack layer, the dielectric layer And the substrate and filling in the second gap; patterning the first conductor layer and the patterned charge storage stack layer to form the patterned first conductor layer and the charge Storing the structure, and forming the first gap, exposing the first insulating structure; performing the ion implantation process with the patterned first patterned first conductor layer as a mask, in the first Under the isolation structure Forming the bit line in the substrate; and forming the second insulating structure in the first gap.