TWI512853B - Method for manufacturing semiconductor packaging - Google Patents
Method for manufacturing semiconductor packaging Download PDFInfo
- Publication number
- TWI512853B TWI512853B TW102131766A TW102131766A TWI512853B TW I512853 B TWI512853 B TW I512853B TW 102131766 A TW102131766 A TW 102131766A TW 102131766 A TW102131766 A TW 102131766A TW I512853 B TWI512853 B TW I512853B
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- Prior art keywords
- substrate
- semiconductor wafer
- semiconductor package
- magnet
- semiconductor
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 title claims description 7
- 238000004806 packaging method and process Methods 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims description 57
- 239000000463 material Substances 0.000 claims description 13
- 239000008393 encapsulating agent Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 description 21
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000084 colloidal system Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000576 coating method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
本發明係有關於一種半導體封裝件之製法，尤指一種運用磁力的半導體封裝件之製法。The present invention relates to a method of fabricating a semiconductor package, and more particularly to a method of fabricating a semiconductor package using magnetic force.
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能與高性能的趨勢，且半導體封裝件之尺寸亦趨於輕薄短小，而為了滿足半導體封裝件微型化(miniaturization)的封裝需求，遂發展出晶圓級封裝(Wafer Level Packaging，WLP)的技術。With the booming of the electronics industry, electronic products are gradually moving toward versatility and high performance, and the size of semiconductor packages is also tending to be thin and light, and in order to meet the packaging requirements of semiconductor package miniaturization, Developed Wafer Level Packaging (WLP) technology.
第1A至1E圖所示者，係習知之晶圓級半導體封裝件之製法的剖面圖。1A to 1E are cross-sectional views showing the fabrication of a conventional wafer level semiconductor package.
如第1A圖所示，首先，形成一剝離層11於一第一承載件10上，形成該第一承載件10之材質係為玻璃或金屬，且該剝離層11係做為離型層之用，而形成該剝離層11之材質可為光阻或乾膜，並利用壓膜方式(當該剝離層11之材質為乾膜時)或塗佈方式(當該剝離層11之材質為光阻時)形成於該第一承載件10上，該剝離層11之材質係較佳選用正型光阻。As shown in FIG. 1A, first, a peeling layer 11 is formed on a first carrier 10, and the material of the first carrier 10 is made of glass or metal, and the peeling layer 11 is used as a release layer. The material for forming the peeling layer 11 may be a photoresist or a dry film, and may be formed by a lamination method (when the material of the peeling layer 11 is a dry film) or a coating method (when the material of the peeling layer 11 is light) The resistive layer is formed on the first carrier 10, and the material of the peeling layer 11 is preferably a positive photoresist.
如第1B圖所示，接著，形成一結合層12於該剝離層11上，該結合層12係做為黏著之用，該結合層12可例如為膠材。As shown in FIG. 1B, a bonding layer 12 is then formed on the release layer 11, which is used for adhesion, and the bonding layer 12 can be, for example, a glue.
如第1C圖所示，設置複數半導體晶片13於該結合層12上，再形成一絕緣層14於該結合層12上，以包覆該等半導體晶片13。As shown in FIG. 1C, a plurality of semiconductor wafers 13 are disposed on the bonding layer 12, and an insulating layer 14 is formed on the bonding layer 12 to cover the semiconductor wafers 13.
如第1D圖所示，設置一第二承載件15於該絕緣層14上。於另一實施例中，可藉由壓合製程，令該第二承載件15壓合該絕緣層14，以形成該絕緣層14。As shown in FIG. 1D, a second carrier 15 is disposed on the insulating layer 14. In another embodiment, the second carrier 15 can be pressed against the insulating layer 14 by a pressing process to form the insulating layer 14.
如第1E圖所示，藉由剝離液(stripper)(未圖示)移除該剝離層11，以移除該第一承載件10。As shown in FIG. 1E, the peeling layer 11 is removed by a stripper (not shown) to remove the first carrier 10.
惟，由於藉由剝離液移除該剝離層11時，該剝離液僅能從該剝離層11外露之狹窄側邊進行移除，故往往難以順利移除該剝離層11，進而無法順利移除該第一承載件10，因而造成產品良率過低及可靠度不佳等問題。However, since the peeling layer 11 can be removed only from the narrow side exposed by the peeling layer 11 when the peeling layer 11 is removed by the stripping liquid, it is often difficult to smoothly remove the peeling layer 11 and thus cannot be smoothly removed. The first carrier 10 thus causes problems such as low product yield and poor reliability.
因此，如何避免上述習知技術中之種種問題，實已成為目前亟欲解決的課題。Therefore, how to avoid various problems in the above-mentioned prior art has become a problem that is currently being solved.
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件之製法，係包括：將一第一基板以磁性相吸之方式結合至一第二基板；於該第二基板上設置半導體晶片；於該第二基板上形成包覆該半導體晶片的封裝膠體；加熱去除該第一基板與第二基板間的磁性相吸力；移除該第一基板；以及移除該第二基板，以外露該半導體晶片。In view of the above-mentioned deficiencies of the prior art, the present invention provides a method for fabricating a semiconductor package, comprising: bonding a first substrate to a second substrate by magnetic attraction; and disposing a semiconductor wafer on the second substrate; Forming an encapsulant covering the semiconductor wafer on the second substrate; heating to remove magnetic attraction between the first substrate and the second substrate; removing the first substrate; and removing the second substrate, exposing the Semiconductor wafer.
於一具體實施例中，形成該第一基板之材質係為磁鐵，且形成該第二基板之材質係為磁性物質；或者，形成該第一基板之材質係為磁性物質，且形成該第二基板之材質係為磁鐵；或者，形成該第一基板之材質係為磁鐵，且形成該第二基板之材質係為磁鐵。In one embodiment, the material forming the first substrate is a magnet, and the material forming the second substrate is a magnetic substance; or the material forming the first substrate is a magnetic substance, and the second is formed The material of the substrate is a magnet; or the material forming the first substrate is a magnet, and the material forming the second substrate is a magnet.
於前述之半導體封裝件之製法中，於移除該第二基板後，復包括於該封裝膠體外露該半導體晶片之表面上形成電性連接該半導體晶片的線路重佈層，且復包括於該線路重佈層上形成導電元件。In the above method for fabricating a semiconductor package, after the second substrate is removed, a surface redistribution layer electrically connected to the semiconductor wafer is formed on the surface of the semiconductor wafer, and is included in the package. A conductive element is formed on the line redistribution layer.
依上所述之半導體封裝件之製法，於移除該第二基板後，復包括進行切單步驟，且該第二基板接觸該半導體晶片之表面係具有黏性。According to the manufacturing method of the semiconductor package, after the second substrate is removed, the singulation step is performed, and the surface of the second substrate contacting the semiconductor wafer is viscous.
於本發明之半導體封裝件之製法中，該半導體晶片係以其具有複數電極墊之表面接置於該第二基板上，且於移除該第二基板後，該半導體晶片具有該等電極墊之表面係外露於該封裝膠體。In the method of fabricating a semiconductor package of the present invention, the semiconductor wafer is mounted on the second substrate with a surface having a plurality of electrode pads, and the semiconductor wafer has the electrode pads after the second substrate is removed. The surface is exposed to the encapsulant.
由上可知，因為本發明係以磁力方式結合第一基板，故僅需加熱即可順利移除該第一基板，因此相較於習知技術，本發明移除承載板的步驟顯然較為方便與簡單，進而能有效增進產品良率與可靠度。It can be seen from the above that since the present invention magnetically combines the first substrate, the first substrate can be smoothly removed only by heating, so that the step of removing the carrier plate of the present invention is obviously more convenient than the prior art. Simple, which can effectively improve product yield and reliability.
10‧‧‧第一承載件10‧‧‧First carrier
11‧‧‧剝離層11‧‧‧ peeling layer
12‧‧‧結合層12‧‧‧Combination layer
13、22‧‧‧半導體晶片13, 22‧‧‧ semiconductor wafer
14‧‧‧絕緣層14‧‧‧Insulation
15‧‧‧第二承載件15‧‧‧Second carrier
20‧‧‧第一基板20‧‧‧First substrate
21‧‧‧第二基板21‧‧‧second substrate
221‧‧‧電極墊221‧‧‧electrode pads
23‧‧‧封裝膠體23‧‧‧Package colloid
24‧‧‧線路重佈層24‧‧‧Line redistribution
25‧‧‧導電元件25‧‧‧Conductive components
第1A至1E圖所示者係習知之晶圓級半導體封裝件之製法的剖面圖；以及第2A至2H圖所示者係本發明之半導體封裝件之製法 的剖視圖。1A to 1E are cross-sectional views showing a method of fabricating a conventional wafer-level semiconductor package; and FIGS. 2A to 2H are diagrams showing a method of fabricating the semiconductor package of the present invention. Cutaway view.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.
第2A至2H圖所示者，係本發明之半導體封裝件之製法的剖視圖。2A to 2H are cross-sectional views showing a method of fabricating the semiconductor package of the present invention.
如第2A圖所示，提供一第一基板20，其主要係做為承載之用。As shown in FIG. 2A, a first substrate 20 is provided which is primarily used for carrying.
如第2B圖所示，於該第一基板20上設置第二基板21，該第一基板20與第二基板21係彼此磁性相吸而結合在一起，為了產生彼此磁性相吸之力，形成該第一基板20與第二基板21之材質可有如下三種組合，分別是磁鐵與磁性物質、磁性物質與磁鐵、或磁鐵與磁鐵。As shown in FIG. 2B, a second substrate 21 is disposed on the first substrate 20, and the first substrate 20 and the second substrate 21 are magnetically attracted to each other and bonded together, in order to generate magnetic attraction force to each other. The material of the first substrate 20 and the second substrate 21 may be the following three combinations: a magnet and a magnetic substance, a magnetic substance and a magnet, or a magnet and a magnet.
如第2C圖所示，於該第二基板21上設置複數半導體晶片22，該半導體晶片22係以其具有複數電極墊221之表面接置於該第二基板21上，該第二基板21之頂面係具有黏性，以接合該半導體晶片22。As shown in FIG. 2C, a plurality of semiconductor wafers 22 are disposed on the second substrate 21, and the surface of the semiconductor wafer 22 having the plurality of electrode pads 221 is placed on the second substrate 21, and the second substrate 21 is The top surface is viscous to bond the semiconductor wafer 22.
如第2D圖所示，於該第二基板21上形成包覆該半導體晶片22的封裝膠體23。As shown in FIG. 2D, an encapsulant 23 covering the semiconductor wafer 22 is formed on the second substrate 21.
如第2E圖所示，加熱以消除磁鐵的磁性，進而去除該第一基板20與第二基板21間的磁性相吸力，並移除該第一基板20。As shown in FIG. 2E, heating is performed to eliminate the magnetic properties of the magnet, thereby removing the magnetic attraction between the first substrate 20 and the second substrate 21, and removing the first substrate 20.
如第2F圖所示，移除該第二基板21，以外露該半導體晶片22具有該等電極墊221之表面。As shown in FIG. 2F, the second substrate 21 is removed, and the semiconductor wafer 22 is exposed to have the surface of the electrode pads 221.
如第2G圖所示，於該封裝膠體23外露該半導體晶片22之表面上形成電性連接該半導體晶片22的線路重佈層(RDL)24，且於該線路重佈層24上形成導電元件25。As shown in FIG. 2G, a circuit redistribution layer (RDL) 24 electrically connected to the semiconductor wafer 22 is formed on the surface of the semiconductor wafer 22 exposed on the encapsulant 23, and conductive elements are formed on the circuit redistribution layer 24. 25.
如第2H圖所示，進行切單步驟。As shown in Fig. 2H, a singulation step is performed.
綜上所述，由於本發明係先藉由磁力吸住第一基板，接著於該第一基板上完成封裝製程，再加熱去除磁力，以順利移除該第一基板，因此相較於習知技術，本發明移除承載板的步驟顯然較為方便與簡單，進而能有效增進產品良率與可靠度。In summary, the present invention firstly absorbs the first substrate by magnetic force, then completes the packaging process on the first substrate, and then heats and removes the magnetic force to smoothly remove the first substrate, so that compared with the conventional In the technology, the step of removing the carrier board of the present invention is obviously convenient and simple, and the product yield and reliability can be effectively improved.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as follows. Listed around.
21‧‧‧第二基板21‧‧‧second substrate
22‧‧‧半導體晶片22‧‧‧Semiconductor wafer
221‧‧‧電極墊221‧‧‧electrode pads
23‧‧‧封裝膠體23‧‧‧Package colloid
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102131766A TWI512853B (en) | 2013-09-04 | 2013-09-04 | Method for manufacturing semiconductor packaging |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102131766A TWI512853B (en) | 2013-09-04 | 2013-09-04 | Method for manufacturing semiconductor packaging |
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| TW201511143A TW201511143A (en) | 2015-03-16 |
| TWI512853B true TWI512853B (en) | 2015-12-11 |
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| TW102131766A TWI512853B (en) | 2013-09-04 | 2013-09-04 | Method for manufacturing semiconductor packaging |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7202107B2 (en) * | 2003-07-28 | 2007-04-10 | Infineon Technologies Ag | Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method |
| CN101989005A (en) * | 2009-07-30 | 2011-03-23 | 北京京东方光电科技有限公司 | Structural substrate, conveying device and box pairing device |
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2013
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7202107B2 (en) * | 2003-07-28 | 2007-04-10 | Infineon Technologies Ag | Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method |
| CN101989005A (en) * | 2009-07-30 | 2011-03-23 | 北京京东方光电科技有限公司 | Structural substrate, conveying device and box pairing device |
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| TW201511143A (en) | 2015-03-16 |
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