TWI510908B - Power management system and power management method - Google Patents

Description

Power management system and power management method

The present invention relates to power management, and more particularly to a power management system and method for a panel self refresh.

In the traditional display technology, using the processor to support the screen presentation often consumes a lot of power, because the traditional display panel still reads the display from the system memory or graphics processor (such as GPU) when the display is not updated. The picture and an interrupt signal is sent to the graphics processor. However, with the advancement of technology, Intel has developed the Panel Self Refresh technology in the embedded DisplayPort (eDP) version 1.3, which means that when users browse websites or read e-books, Because the content of the picture is usually static. Therefore, when the screen is not updated, the display device panel only uses the data in the built-in memory of the display device panel and automatically limits the refresh rate, and does not read the display of the system memory or the graphics processor. And reduce the interrupt signal to 30 times per second (depending on the screen update rate), thereby reducing power consumption.

Figure 1 shows a simplified functional block diagram of a conventional power management system that complies with the eDP 1.3 standard and automatically updates the control panel. As shown in FIG. 1 , the power management system 10 includes a graphics processor 20 and a display device panel 30 . The display device panel 30 further includes a timing controller (T-CON) 40 , a display device 50 , and a backlight . Module 60. The processor 20 includes a transmitting end 21 for transmitting the display generated by the graphics processor 20. The screen is to the timing controller 40. The graphics processor 20 can be a graphics processing unit (GPU) located on a separate display card or a central processing unit (CPU) (eg, an Intel i5, i7 CPU) located on a main board. A graphics processor. The timing controller 40 includes at least a receiving end 41, a pixel array unit 42, a display device interface (LCD interface) 43, a video frame buffer 44, and a backlight control unit (45). .

Briefly, the timing controller 40 receives the display image from the graphics processor 20 through the receiving end 41, and rearranges the pixels of the received picture via the pixel arrangement unit 42 and stores the rearranged pixels in the video frame buffer. 44. The display device interface 43 reads the picture data from the video frame buffer 44 through the pixel arrangement unit 42, and controls the column driver 51 and the line driver 52 in the display device 50 to display the read picture. The backlight control unit 45 is used to control the switch of the backlight module 60.

It should be noted that in the conventional timing controller 40, the size of the video frame buffer 44 is often only one picture size. For example, a full-resolution high-definition picture (Full HD) can be 1920*1080*3=6220800 bytes (about 6 Mbytes). The timing controller 40 further optionally includes an image encoder and a video decoder (not shown), wherein the image encoder encodes the display image received by the receiving end 41, and then the encoded display screen The pixel arrangement unit 42 is stored in the video frame buffer 44. For details, refer to "An LCD Driver with on-chip frame buffer and 3 times image compression" SPIE-IS&T 2008, Vol. 6807, 68070H-1.

Automatic update of the panel at the timing controller 40 (eg, in still painting) In the case of time, the stored picture data is directly taken out by the video frame buffer 44 and played directly on the display device 50. At this time, the graphic processor 20 can be in a low power consumption state, thereby saving power. In addition, when the graphics processor 20 detects new image data (for example, from a keyboard key or a moving mouse), the graphics processor 20 evokes the transmitting terminal 21 and transmits a new image data to Video frame buffer 44 in timing controller 40.

In the conventional power management system 10, since the graphics processor 20 often receives an interrupt signal from the timing controller 40 or receives an interrupt signal from an external device, the graphics processor 20 must be constantly woken up to be in an active state (for example, C0). status). In other words, the graphics processor 20 is often in a high power consumption state and cannot effectively reduce the power consumption of the power management system 10. Therefore, there is a need for a power management system to reduce power consumption more effectively, thereby achieving longer usage time.

The present invention provides a power management system. The system includes: a display device; a graphics processor; a memory unit for storing image data from the graphics processor; a timing controller; and a monitoring control unit for monitoring the location of the graphics processor a plurality of bus processing activities of a bus, and filtering, by the bus activities, a plurality of graphics processing activities corresponding to the graphics processor, wherein the monitoring control unit further estimates that one of the graphics processors is idle according to the graphics processing activities a time period; wherein the graphics processor further includes a memory controller, the memory unit is divided into a first memory space and a second memory space; wherein the monitoring control unit further controls the graphics processor burst Write multiple images to the memory The first memory space in the body unit; wherein when the timing controller performs panel automatic update and the graphics processor is in the low power state, the memory controller reads the first memory space The image is written by the graphics processor, and one of the images is sequentially written to a video frame buffer in the timing controller, so that the timing controller is sufficient for the idle time period The images written by the graphics processor are played on the display device for automatic panel update.

The invention further provides a power management method for a power management system, the power management system comprising a graphics processor, a memory unit, a monitoring control unit, a timing controller and a display device. The method includes: monitoring, by the monitoring control unit, a plurality of bus bar activities of one of the bus bars of the graphics processor, and filtering, by the bus bar activities, a plurality of graphics processing activities corresponding to the graphics processor; using the monitoring control The unit estimates an idle time period of the graphics processor according to the graphics processing activities; dividing the memory unit into a first memory space and a second memory space; and controlling the graphics processor burst by using the monitoring control unit Writing a plurality of images to the first memory space in the memory unit; and reading the first memory space when the timing controller performs panel automatic update and the graphics processor is in the low power state The images written by the graphics processor are sequentially written to one of the images to a video frame buffer of the timing controller, so that the timing controller is sufficient for the idle time The images written by the graphics processor are played on the display device during the cycle for automatic panel update.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

2A is a block diagram showing a brief function of the power management system 200 in accordance with an embodiment of the present invention. As shown in FIG. 2A, the power management system 200 includes a graphics processor 220, a memory unit 270, and a display device panel 230. The display device panel 230 further includes a timing controller (T-CON) 240, The display device 250 and a backlight module 260. The graphics processor 220 includes a transmitting end 221 and a memory controller 223. The transmitting end 221 is configured to transmit the display screen generated by the graphics processor 220 to the timing controller 240. The memory controller 223 is configured to process the access operation of the graphics processor 220 to the memory unit 270.

The timing controller 240 includes at least a receiving end 241, a pixel array unit 242, a display device interface (LCD interface) 243, a video frame buffer 244, and a backlight control unit 245. .

Briefly, the timing controller 240 receives a single image from the graphics processor 220 through the receiving end 241, and rearranges the pixels of the received plurality of images through the pixel arrangement unit 242 and rearranges the single image after the rearrangement. The pixels are stored in the video frame buffer 244. The display device interface 243 sequentially reads the pixel data of the images from the video frame buffer 244 through the pixel arrangement unit 242, and controls the column driver 251 and the row driver 252 in the display device 250 to sequentially display the read data. Multiple images. The backlight control unit 245 is configured to control the switch of the backlight module 260.

In one embodiment, the graphics processor 220 can be a graphics processing unit (GPU) located on a separate display card. In this case, the memory unit 270 is a display memory (Video RAM) dedicated to the graphics processor 220. . For example, the memory unit 270 can be a dynamic random access memory, such as SRAM or DRAM. In another embodiment, graphics processor 220 can be a graphics processor located in a central processing unit (CPU) (eg, an Intel i5, i7 CPU) on a mainboard. At this time, the central processing unit and the graphics processor 220 use a unified memory architecture, that is, the memory unit 270 is a system memory, and the central processing unit and the graphics processor 220 are equally memory-oriented. The body unit 270 performs an access operation. The memory controller 223 in the graphics processor 220 can divide the memory unit 270 into a first memory area 271 and a second memory area, wherein the first memory area is stored from the graphics processor 220. A plurality of images are used for the timing controller 240 to automatically update the panel. The second memory area 272 is used as a display memory (Video Memory) to store display data for the graphics processor 220 to perform graphics operations or decoding operations.

Please refer to both Figure 1 and Figure 2A. It should be noted that the video frame buffer 44 of the timing controller 40 in the conventional power management system 10 has only one image size. Therefore, in the case where the picture update rate of the display device 250 is 60 Hz, the timing controller 40 needs to transmit an interrupt signal to the graphics processor 20 every 1/30 second, so that the graphics processor 20 transmits a picture to the timing control. Video frame buffer 44 in unit 40. In this case, the graphics processor 20 cannot be in a low power state for a long time (for example, Runtime D3 status). The graphics processor 220 of the present invention can write a plurality of images into the memory unit 270 at a time through the memory controller 223, and the images written at one time are sufficient to provide the timing controller 240 for a period of time. Automatic panel updates are performed within. Therefore, the graphics processor 220 of the present invention can be in a low power state for a longer period of time, and can save more power than the graphics processor 20 in the conventional power management system 10.

2B is a block diagram showing a brief function of the power management system 200 in accordance with another embodiment of the present invention. In an embodiment, the power management system 200 further includes a monitoring control unit 222 for monitoring the bus activity of the bus (eg, PCI-E bus) in which the graphics processor 220 is located. In an embodiment, the monitoring control unit 222 can be a microcontroller unit external to the graphics processor 220, as shown in FIG. 2A. In another embodiment, the monitoring control unit 222 can also be built into the graphics processor 220, as shown in FIG. 2B. In an embodiment, the monitoring control unit 222 may also be a software plug-in supported by a specific hardware, but the invention is not limited thereto.

The timing controller 240 periodically sends an interrupt signal to the graphics processor 220 when performing panel automatic update (PSR). The monitoring control unit 222 can further display the graphics processor 220 from different devices on the bus (for example, from PCI-E, USB). The interrupt signals of the SATA and SDIO interface devices are rearranged, and the rearranged interrupt signals are grouped and distributed to the interrupt signals that are periodically transmitted by the timing controller 240. For example, the graphics processor 220 has its original bus active state, that is, the various interrupt signals before the rearrangement are as shown in FIG. 3A. Taking the picture update rate as 60 pictures per second as an example, the timing controller 240 needs 30 complete pictures per second. In the face, each complete picture can be split into a top field and a bottom field, and then the timing controller 240 sequentially deinterlaces the upper field and the lower field of each complete picture. (de-interlacing) to cause the display device 250 to have a picture update rate of 60 pictures per second. In other words, the timing controller 240 needs to take a complete picture from the graphics processor 220 every 1/30 of a second, meaning that an interrupt signal is sent to obtain the picture.

Figure 3A is a diagram showing interrupt signals from respective devices to the busbar in which the graphics processor is located, in accordance with an embodiment of the present invention. Fig. 3B is a diagram showing the interrupt signals rearranged and grouped in Fig. 3A. Figure 3C is a diagram showing the wake-up signal emitted by the monitoring control unit 222 in accordance with an embodiment of the present invention. As can be seen from FIG. 3A, the time interval between the interrupt signals 310 and 320 issued by the timing controller 240 to the graphics processor 220 is 1/30 second (ie, the time unit is about the millisecond level), and Interrupt signals 311~313 of other devices may have been distributed between these 1/30 second intervals. The interrupt signal after being rearranged by the monitoring control unit 222 is as shown in FIG. 3B, wherein the time interval from the timing controller 240 to the graphics processor 220 interrupt signals 330 and 340 is also 1/30 second, which is noted. The interrupt signals of the same symbols in Figure 3B are all from the same device, and the rearranged interrupt signals are for illustrative purposes only, and the bus activity independent of the graphics processor is filtered out (for example, interrupt signals 311, 312). Only interrupt signals (e.g., interrupt signals 310, 320, 313) associated with graphics processor 220 are retained. As shown in FIG. 3C, the monitoring control unit 222 transmits a wake-up signal to the graphics processor 220, thereby causing the graphics processor 220 to be in an active state when the wake-up signal is at a high logic level, wherein the graphics processor 220 In working condition The voltage is, for example, 1W. When the wake-up signal is a low logic level, the graphics processor 220 is placed in a low power state (eg, a sleep state), wherein the voltage of the graphics processor 220 in the low power state is, for example, 0.001 w. In more detail, since the interrupt signals from the respective devices to the graphics processor 220 are rearranged and grouped by the monitoring control unit 222, and distributed to the interrupt signals that are periodically transmitted from the timing controller 240, Collectively, during the period of having a plurality of interrupt signals (e.g., pulse signals 350 and 360), graphics processor 220 can be placed in an operational state to centrally perform operational control of the various devices. While the wake-up signal is in a low logic state, graphics processor 220 enters a low power state. When the wake-up signal is in the high logic state, in addition to causing the graphics processor 220 to enter the active state, it can be used as a burst control signal to increase the operating frequency of the graphics processor 220. Further, if the preset operating frequency of the graphics processor 220 is 1 GHz, when the wake-up signal is in the high logic state, the monitoring control unit 222 increases the operating frequency of the graphics processor 220 to 1.3 GHz, thereby bursting (burst) The graphics processor 220 writes a plurality of consecutive images (for example, 10 or 30 images) into the first memory space 271 in the memory unit 270 in a short time.

Taking the PCI Express×4 bus as an example, the bandwidth can reach 800 MBytes/sec, and when the operating frequency of the graphics processor 220 is 1 GHz, the graphics processor 220 executes the burst write image to the video frame buffer 244. The time is only about tens of microseconds, and the interrupt signal sent by the timing controller 240 to the graphics processor 220 is approximately 33 milliseconds (1/30 second). In terms of time ratio, the graphics processor 220 performs a burst write operation The proportion of time taken is very small, so the graphics processor 220 can be in a low power state for most of the time, thereby saving power.

Continuing the foregoing embodiments, the main functions of the monitoring control unit 222 of the present invention can be summarized: (1) monitoring all activities of the bus bar (PCI-E bus bar) in which the graphics processor 220 is located and screening about the graphics processor. The activity of 220 reorders the interrupt signals sent to the graphics processor 220 on the PCI-E bus; (2) the control graphics processor 220 bursts the complex image into the memory unit 270 through the memory controller 223. Therefore, the written images can be provided by the timing controller 240 for automatic panel update (for example, through direct memory access (Direct Memory Access); (3) controlling the graphics processor 220 to enter a low power state, such as ACPI. The Runtime D3 (RTD3) state specified by the standard.

In general, the capacity of the memory unit 270 can often exceed 2 GB. In other words, the video memory dedicated to the graphics processor 220 can have a capacity of 2 GB. Take the full-resolution high-definition picture (Full HD) as an example, the size can be 1920*1080*3=6220800bytes (about 6Mbytes). If you use the video compression technology described in the prior art, the size can be compressed. Up to 2MB. It takes only 20 MB of space to store 10 full-resolution high-definition images in the memory unit 270, and only accounts for 1% of the 2 GB capacity. More specifically, the first memory space 271 and the second memory space 272 for automatically updating the panel in the memory unit 270 use different power supplies. Since the portion of the memory unit 270 for automatically updating the panel must be in an active state when the panel is automatically updated, the memory controller 223 can access the first memory space 271 for automatic panel update.

It should be noted that the memory controller 223 and the transmitting end 221 of the present invention are required. The operation of the first memory space 271 can be independent of the graphics processor 220. In more detail, the memory controller 223, the transmitting end 221, and the first memory space are supplied by an independent power source. When the graphics processor 220 and the second memory space 272 are in a low power consumption state, the memory controller 223 and the first memory space 271 do not enter the low power consumption state because the memory controller 223 is in the graphics processing. When the controller 220 is in the low power consumption state and the timing controller 240 performs the panel automatic update, the image previously written by the graphics processor 220 needs to be taken out from the first memory space 271 in the memory unit 270, and transmitted through the transmitting end. 221 The image data of one image is sequentially transmitted by the eDP bus to the video frame buffer 244 in the timing controller 240, so as to automatically update the panel.

Further, when the user browses a website for more than 4 seconds, the central processing unit (not shown) in the power management system 200 can enter the C10 or S0ix state, turn off the power of the system memory, and turn off the graphics processor ( In addition to the power of the memory controller 223 and the transmitting terminal 221), the power of the second memory space in the memory unit 270 is turned off.

In one embodiment, the monitoring control unit 222 continuously monitors the activity of the bus bar and determines whether the number of images stored in the video frame buffer 244 for automatic panel update is insufficient. In simple terms, the principle of automatic panel update is that the user cannot feel the delay of the screen. Take the example of the Microsoft "Always On Always Connected" standard as an example, when the graphics processor 220 is in a low power state and the graphics processor 220 is returned from a low power state to a wakeup time (wakeup) Time) The upper limit is 300 milliseconds. In fact, the wakeup time of graphics processor 220 may be faster, such as 100 milliseconds.

For example, the monitoring control unit 222 controls the graphics processor 220 to burst write 30 images to the video frame buffer 244, and the display device 250 has a picture update rate of 60 images per second, that is, the timing controller 240 30 complete pictures are required in seconds, and each complete picture can be split into a top field and a bottom field, and then the timing controller 240 sequentially clicks on the upper field of each complete picture. The lower field is de-interlaced to allow the display device 250 to have a picture update rate of 60 frames per second. Therefore, it takes about 1 second for the display device to read the stored 30 frames, and the average interval between reading each frame is 33 milliseconds. If the bus bar in which the graphics processor 220 is located is still not active after 20 images (or 660 milliseconds), since the 660 milliseconds plus the wakeup time of the graphics processor 220 is 300 milliseconds, the panel is automatically updated, and the display data is insufficient. The time monitoring control unit 222 needs to forcibly wake the graphics processor 220 to write the display screen to the video frame buffer 244 to avoid the situation that the panel automatic update has insufficient display data.

In brief, the monitoring control unit 222 needs to determine early whether the display screen is insufficient before the next full wake-up of the graphics processor 220. If so, the monitoring control unit 222 directly wakes up the graphics processor 220 to write the display screen to the video. Block buffer 244. If not, the monitoring control unit 222 wakes up the graphics processor 220 to execute instructions from the application or operating system. For the user, in either case it is felt that the graphics processor 220 is always on.

Figure 4 is a diagram showing the state of the state machine of the monitoring control unit 222 in accordance with an embodiment of the present invention. In state 410, monitoring control unit 222 monitors the activity of the busbar (e.g., PCI-Express bus) in which graphics processor 220 is located and filters activity regarding graphics processor 220. If the associated activity is not displayed, then return to state 410 and the monitoring control unit 222 continues to monitor the activity of the busbar in which the graphics processor 220 is located. In state 420, monitoring control unit 222 can perform the following functions: (a) estimating idling time period T _{idle of} graphics processor 220; (b) controlling graphics processor 220 to burst write a sufficient number of displays The data is transferred to the first memory space 271 in the memory unit 270, so that the written display data is sufficient to automatically update the panel between the estimated idle time periods; (c) the control power management system 200 enters the specification of the ACPI standard. The S0i3 state, and most of the subsystems in the power management system 200 (such as PCI-E, USB, SATA, and other peripherals) enter the RTD3 state. When the wake-up signal sent by the monitoring control unit 222 is in a low logic state, the graphics processor 220 is brought into a low power state (eg, RTD3 state) and the power of the associated component is turned off.

In state 430, monitoring control unit 222 monitors: (d) displays a run-out-of-display event and (e) a GPU activity, such as by an application or operating system. The graphics processing activity that is started. When no events are detected, returning to state 430, the monitoring control unit 222 continuously monitors the display of insufficient data events and the activity events of the graphics processor 220. When an event is detected, the state 440 is entered, and the monitoring control unit 222 sets the wake-up signal to a high logic state, thereby causing the graphics processor 220 to enter the active state from the low power state. If the graphics processor 220 is brought into an active state due to (d) displaying a data shortage event, then return to state 420. If the graphics processor 220 is brought into an active state due to (e) an activity event of the graphics processor 220, then state 450 is entered. In state 450. The graphics processor 220 can begin processing graphics processing activities initiated by the application or operating system within a wake-up time (eg, 300 milliseconds).

Figure 5 is a flow chart showing a power management method in accordance with an embodiment of the present invention. In step S500, the monitoring control unit 222 monitors the plurality of bus bar activities of one of the bus bars in which the graphics processor 220 is located, and filters the plurality of graphics processing activities corresponding to the graphics processor 220 from the bus bar activity. In step S510, the monitoring control unit 222 estimates one of the idle time periods of the graphics processor 220 in accordance with the graphics processing activities. In step S520, the memory controller 223 divides the memory unit 270 into a first memory space 271 and a second memory space 272. In step S530, the monitoring control unit 222 controls the graphics processor 220 to burst write a plurality of images to the first memory space 271 in the memory unit 270. In step S540, when the timing controller 240 performs panel automatic update and the graphics processor 220 is in a low power consumption state, the memory controller 223 reads the first memory space 271 written by the graphics processor 220. The images are sequentially written to one of the images to a video frame buffer 244 in the timing controller 240, thereby allowing the timing controller 240 to play graphics processing on the display device 250 during the idle time period. The images written by the device 220 are automatically updated by the panel.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

10, 200‧‧‧ Power Management System

270‧‧‧ memory unit

20, 220‧‧‧ graphics processor

271‧‧‧First memory space

21, 221‧‧‧ transmit end

272‧‧‧Second memory space

30, 230‧‧‧ display device panel

222‧‧‧Monitoring Control Unit

40, 240‧‧‧ timing controller

223‧‧‧ memory controller

41, 241‧‧‧ receiving end

410-450‧‧‧ Status

42, 242‧‧‧ pixel arrangement unit

43, 243‧‧‧ display device interface

44, 244‧‧•Video frame buffer

45, 245‧‧‧ Backlight Control Unit

50, 250‧‧‧ display devices

51, 251‧‧ ‧ column driver

52, 252‧‧ lines driver

60, 260‧‧‧ backlight module

310-313, 320, 330, 340‧‧‧ interrupt signal

350, 360‧‧‧ pulse signal

Figure 1 shows a simplified functional block diagram of a conventional power management system that complies with the eDP 1.3 standard and automatically updates the control panel.

2A is a block diagram showing a brief function of the power management system 200 in accordance with an embodiment of the present invention.

2B is a block diagram showing a brief function of the power management system 200 in accordance with another embodiment of the present invention.

Figure 3A is a diagram showing interrupt signals from respective devices to the busbar in which the graphics processor is located, in accordance with an embodiment of the present invention.

Fig. 3B is a diagram showing the interrupt signals rearranged and grouped in Fig. 3A.

Figure 3C is a diagram showing the wake-up signal emitted by the monitoring control unit 222 in accordance with an embodiment of the present invention.

Figure 4 is a diagram showing the state of the state machine of the monitoring control unit 222 in accordance with an embodiment of the present invention.

Figure 5 is a flow chart showing a power management method in accordance with an embodiment of the present invention.

200‧‧‧Power Management System

220‧‧‧graphic processor

221‧‧‧Transport

222‧‧‧Monitoring Control Unit

223‧‧‧ memory controller

230‧‧‧Display panel

240‧‧‧Sequence Controller

241‧‧‧ receiving end

242‧‧‧Pixel Arrangement Unit

243‧‧‧Display device interface

244‧‧•Video frame buffer

245‧‧‧Backlight control unit

250‧‧‧ display device

251‧‧‧ column driver

252‧‧‧ line driver

260‧‧‧Backlight module

270‧‧‧ memory unit

271‧‧‧First memory space

272‧‧‧Second memory space

Claims (10)

A power management system includes: a display device; a graphics processor; a memory unit for storing image data from the graphics processor; a timing controller; and a monitoring control unit for monitoring the graphics processing a plurality of bus processing activities of one of the bus bars, and filtering, by the bus bar activities, a plurality of graphics processing activities corresponding to the graphics processor; wherein the monitoring control unit further estimates the graphics processing according to the graphics processing activities One of the idle time periods, and controls the graphics processor to be in a low power state during the idle time period; wherein the graphics processor further includes a memory controller, dividing the memory unit into a first memory a space and a second memory space; wherein the monitoring control unit further groups and rearranges the graphics processing activities after an interrupt signal is sent from the timing controller, and controls the graphics processor to be in the Burst writing a plurality of images to the memory unit during one of the first periods of the interrupt signal The first memory space, and controlling the graphics processor to process the graphics processing activities in the wake-up time; wherein when the timing controller performs panel automatic update and the graphics processor is in the low power state, The memory controller reads the images written by the graphics processor in the first memory space, and sequentially writes one of the images to a video frame buffer in the timing controller. So that the timing controller is sufficient to play the images written by the graphics processor on the display device for automatic updating of the panel during the idle time period, wherein the first period includes the idle time period and the wakeup Time, and the wake-up time is less than the idle time period. The power management system of claim 1, wherein the monitoring control unit sends a wake-up signal to the graphics processor according to the graphics processing activities, so that the graphics processor enters a working state to write bursts. Inserting the images into the first memory space in the memory unit; wherein when the graphics processor enters the working state, the monitoring control unit further controls the graphics processor to perform the working state at a first operating frequency The operation, wherein the first operating frequency is higher than a predetermined operating frequency of the operating state. The power management system of claim 2, wherein the monitoring control unit further determines whether the images stored in the video frame buffer are sufficient for the timing controller to automatically update the panel during the idle time period. Wherein, when the images stored in the video frame buffer are insufficient for the timing controller to automatically update the panel during the idle time period, the monitoring control unit forcibly transmits the wake-up signal to the graphics processor, thereby Let the graphics processor enter a working state. The power management system of claim 2, wherein the monitoring control unit further determines whether the graphics processing activities are initiated by an application or an operating system; wherein the graphics processing activities are performed by the application Or the operating system is activated, the monitoring control unit forcibly transmits the wake-up signal to the map. A processor that allows the graphics processor to enter a working state. The power management system of claim 1, wherein the first memory space and the memory controller are supplied by a first independent power source, and the graphics processor and the second memory space system are Provided by a second independent power source; and when the graphics processor and the second memory space are in the low power consumption state and the timing controller performs automatic panel update, the first memory space and the memory control The device is in an active state by the first independent power source, thereby automatically updating the panel. A power management method for a power management system includes a graphics processor, a memory unit, a monitoring control unit, a timing controller, and a display device, the method comprising: utilizing the monitoring control unit Monitoring a plurality of bus activities of a bus bar in which the graphics processor is located, and filtering, by the bus activities, a plurality of graphics processing activities corresponding to the graphics processor; using the monitoring control unit to estimate the motion according to the graphics processing activities One of the graphics processor is idle for a period of time, and controls the graphics processor to be in a low power state during the idle time period; dividing the memory unit into a first memory space and a second memory space; The monitoring control unit groups and rearranges the graphics processing activities after one of the interrupt signals sent from the timing controller, and controls the graphics processor to time one wake-up time in one of the first cycles after the interrupt signal Inserting a plurality of images into the first memory space in the memory unit, and Wake up time centralized control of the graphics processor such graphics processing activity; and When the timing controller performs panel automatic update and the graphics processor is in the low power consumption state, reading the images written by the graphics processor in the first memory space, and sequentially writing the image Waiting for one of the images to a video frame buffer in the timing controller, so that the timing controller is sufficient to play the images written by the graphics processor on the display device during the idle time period for performing The panel is automatically updated, wherein the first period includes the idle time period and the wake time, and the wake time is less than the idle time period. The power management method of claim 6, further comprising: sending a wake-up signal to the graphics processor according to the graphics processing activities, so that the graphics processor enters a working state to write the bursts. Transmitting an image to the first memory space in the memory unit; wherein when the graphics processor enters the working state, controlling the graphics processor to operate in the working state at a first operating frequency, wherein the first operating frequency It is higher than the predetermined operating frequency of one of the working states. The power management method of claim 7, further comprising: determining whether the images stored in the video frame buffer are sufficient for the timing controller to automatically update the panel during the idle time period; When the image stored in the video frame buffer is insufficient for the timing controller to automatically update the panel during the idle time period, the wake-up signal is forcibly transmitted to the graphics processor, so that the graphics processor enters a Working status. The power management method of claim 7, further comprising: determining whether the graphics processing activities are initiated by an application or an operating system; and when the graphics processing activities are performed by the application or the job The system is activated to forcibly transmit the wake-up signal to the graphics processor, thereby allowing the graphics processor to enter a working state. The power management method of claim 6, wherein the graphics processor further includes a memory controller for dividing the memory unit into the first memory space and the second memory space, wherein the a memory space and the memory controller are supplied by a first independent power source, and the graphics processor and the second memory space are supplied by a second independent power source; and the method further comprises: when When the graphics processor and the second memory space are in the low power consumption state and the timing controller performs automatic panel update, the first memory space and the memory controller are in a working state by using the first independent power source. Status, by which the panel is automatically updated.