TWI509788B - Resistive memory array and method for controlling operations of the same - Google Patents
Resistive memory array and method for controlling operations of the same Download PDFInfo
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Description
本發明是關於電阻性記憶體以及用於控制電阻性記憶體之操作之方法,且更具體言之,是關於電阻性記憶體具有用於儲存資料的兩個記憶體層的電阻性記憶體以及用於控制所述電阻性記憶體之操作之方法。本發明亦是關於基於上述電阻性記憶體之電阻性記憶體陣列以及用於控制電阻性記憶體陣列之操作之方法。The present invention relates to a resistive memory and a method for controlling the operation of a resistive memory, and more particularly to a resistive memory having two memory layers for storing data in a resistive memory and using A method of controlling the operation of the resistive memory. The present invention also relates to a resistive memory array based on the above-described resistive memory and a method for controlling the operation of the resistive memory array.
隨著通信技術之發展以及網際網路之風行,公眾對尤其關於大容量以及快速傳輸速度之音訊-視訊資料傳輸之資訊的通信及處理的需求正增長。另一方面,在全球競爭之情形下,工作環境不限於辦公室,而是可隨時在世界上任何地方,且需要大量資訊以支援此動作與決策。因此,對包含行動平台之攜帶型數位設備(諸如,數位筆記型電腦(notebook computer;NB)、個人數位助理(personal digital assistant;PDA)、電子書(electronic book;e-book)、行動電話以及數位靜態相機(digital still camera;DSC))之要求正顯著增長。相應地,經由儲存設備存取上述數位產品之要求亦極大增長。With the development of communication technologies and the popularity of the Internet, the demand for communication and processing of information on audio-visual data transmission, especially for large-capacity and fast transmission speeds, is growing. On the other hand, in the case of global competition, the work environment is not limited to the office, but can be anywhere in the world at any time, and requires a lot of information to support this action and decision. Therefore, for portable digital devices including mobile platforms (such as a notebook computer (NB), a personal digital assistant (PDA), an electronic book (e-book), a mobile phone, and The demand for digital still cameras (DSCs) is growing significantly. Accordingly, the requirements for accessing the above digital products via storage devices have also increased significantly.
自1990以來,開發出半導體儲存式記憶體,所述記憶體現成為儲存介質之新技術。為了滿足對記憶體與大量資料之儲存或傳輸的增長的要求,開發新型記憶體裝置極為重要且極具價值。新型記憶體裝置之一是電阻性記憶 體,電阻性記憶體藉由調整其記憶體層之電阻來儲存資料。因為習知電阻性記憶體具有用於儲存資料之單個記憶體層,所以其可儲存之資料量極其有限。Since 1990, semiconductor storage memory has been developed, which represents a new technology for storage media. In order to meet the growing demand for the storage or transmission of memory and large amounts of data, the development of new memory devices is extremely important and valuable. One of the new memory devices is resistive memory Body, resistive memory stores data by adjusting the resistance of its memory layer. Because conventional resistive memories have a single memory layer for storing data, the amount of data that can be stored is extremely limited.
因此,本發明之實施例之目標為提供一種用於控制電阻性記憶體之操作之方法。電阻性記憶體具有第一記憶體層、第二記憶體層以及介質層。介質層形成於第一記憶體層與第二記憶體層之間。所述方法包括至少以下步驟:(a)量測第一記憶體層與第二記憶體層之間的電阻,以及根據所量測之電阻來判定第一狀態、第二狀態以及第三狀態中之哪一者為電阻性記憶體之狀態。Accordingly, it is an object of embodiments of the present invention to provide a method for controlling the operation of a resistive memory. The resistive memory has a first memory layer, a second memory layer, and a dielectric layer. The dielectric layer is formed between the first memory layer and the second memory layer. The method includes at least the following steps: (a) measuring a resistance between the first memory layer and the second memory layer, and determining which of the first state, the second state, and the third state based on the measured resistance One is the state of the resistive memory.
本發明之實施例之另一目標為提供一種電阻性記憶體。電阻性記憶體具有第一固態電解質、第二固態電解質以及可氧化電極。可氧化電極形成於第一固態電解質與第二固態電解質之間。第一固態電解質以及第二固態電解質由過渡金屬氧化物或含有至少一種硫族元素之材料製成。Another object of embodiments of the present invention is to provide a resistive memory. The resistive memory has a first solid electrolyte, a second solid electrolyte, and an oxidizable electrode. An oxidizable electrode is formed between the first solid electrolyte and the second solid electrolyte. The first solid electrolyte and the second solid electrolyte are made of a transition metal oxide or a material containing at least one chalcogen element.
本發明之實施例之另一目標為提供一種電阻性記憶體。電阻性記憶體具有第一阻障層、第二阻障層以及金屬氧化物層。金屬氧化物層形成於第一阻障層與第二阻障層之間。第一阻障層與金屬氧化物層之間設置有第一作用區域,且第二阻障層與金屬氧化物層之間設置有第二作用區域。Another object of embodiments of the present invention is to provide a resistive memory. The resistive memory has a first barrier layer, a second barrier layer, and a metal oxide layer. A metal oxide layer is formed between the first barrier layer and the second barrier layer. A first active region is disposed between the first barrier layer and the metal oxide layer, and a second active region is disposed between the second barrier layer and the metal oxide layer.
本發明之實施例之另一目標為提供一種記憶體裝置。記憶體裝置包括第一記憶體層、第二記憶體層以及介 質層。第一記憶體層具有M種電阻性狀態,且第二記憶體層具有N種電阻性狀態。M大於或等於3。介質層形成於第一記憶體層與第二記憶體層之間。記憶體狀態之至少(M+N-1)種電阻性狀態可根據第一記憶體層與第二記憶體層之間的電阻來區別。Another object of embodiments of the present invention is to provide a memory device. The memory device includes a first memory layer, a second memory layer, and a mediator Quality layer. The first memory layer has M resistive states, and the second memory layer has N resistive states. M is greater than or equal to 3. The dielectric layer is formed between the first memory layer and the second memory layer. At least (M+N-1) resistive states of the memory state can be distinguished based on the resistance between the first memory layer and the second memory layer.
在本發明之實施例中,步驟(a)包括藉由將第一電壓施加至電阻性記憶體來量測電阻作為第一電阻;在第一電阻等於預定值時,判定電阻性記憶體之狀態為第一狀態;在第一電阻不同於預定值時,藉由將第二電壓施加至電阻性記憶體來量測電阻作為第二電阻;以及在第二電阻等於第一電阻時,判定電阻性記憶體之狀態為第二狀態,或在第二電阻不等於第一電阻時,判定電阻性記憶體之狀態為第三狀態。In an embodiment of the invention, the step (a) includes measuring the resistance as the first resistance by applying the first voltage to the resistive memory; determining the state of the resistive memory when the first resistance is equal to the predetermined value a first state; when the first resistance is different from the predetermined value, the resistance is measured as a second resistance by applying a second voltage to the resistive memory; and the resistivity is determined when the second resistance is equal to the first resistance The state of the memory is the second state, or when the second resistance is not equal to the first resistance, it is determined that the state of the resistive memory is the third state.
在本發明之實施例中,所述方法更包括在將電阻性記憶體之狀態判定為第三狀態時,將電阻性記憶體再程式化為處於第三狀態。In an embodiment of the invention, the method further includes reprogramming the resistive memory to be in the third state when the state of the resistive memory is determined to be the third state.
在本發明之實施例中,電阻性記憶體具有兩個記憶體層,其中之每一者能夠儲存資料。因此,可由電阻性記憶體儲存之總資料量增大。In an embodiment of the invention, the resistive memory has two memory layers, each of which is capable of storing data. Therefore, the total amount of data that can be stored by the resistive memory is increased.
本發明之實施例之另一目標為提供一種電阻性記憶體陣列,所述電阻性記憶體陣列包含配置成列及行之多個電阻性記憶體單元、多條字元線以及多條位元線。每一電阻性記憶體單元包含第一記憶體胞元以及第二記憶體胞元,所述第二記憶體胞元安置於第一記憶體胞元之下且與 其串聯電連接。每一字元線耦接至一列電阻性記憶體單元之第一記憶體胞元。每一位元線耦接至一行電阻性記憶體單元之第二記憶體胞元。Another object of embodiments of the present invention is to provide a resistive memory array including a plurality of resistive memory cells arranged in columns and rows, a plurality of word lines, and a plurality of bits line. Each of the resistive memory cells includes a first memory cell and a second memory cell, the second memory cell being disposed under the first memory cell and It is electrically connected in series. Each word line is coupled to a first memory cell of a column of resistive memory cells. Each bit line is coupled to a second memory cell of a row of resistive memory cells.
在本發明之實施例中,上述電阻性記憶體陣列中之每一電阻性記憶體單元可為上述之具有第一固態電解質、第二固態電解質以及可氧化電極的電阻性記憶體或上述之具有第一阻障層、第二阻障層以及金屬氧化物層的電阻性記憶體。In an embodiment of the present invention, each of the resistive memory cells in the resistive memory array may be the above-mentioned resistive memory having a first solid electrolyte, a second solid electrolyte, and an oxidizable electrode, or the above A resistive memory of the first barrier layer, the second barrier layer, and the metal oxide layer.
在每一電阻性記憶體單元具有第一固態電解質、第二固態電解質以及可氧化電極的狀況下,用於控制電阻性記憶體陣列之操作之方法包含:(a)經由字元線以及位元線來選擇待操作之電阻性記憶體單元;以及(b)量測所選擇之電阻性記憶體單元之電阻以及根據所量測之電阻來判定第一狀態、第二狀態以及第三狀態中之哪一者為所選擇之記憶體單元之狀態。In the case where each resistive memory cell has a first solid electrolyte, a second solid electrolyte, and an oxidizable electrode, the method for controlling the operation of the resistive memory array includes: (a) via word lines and bit elements a line to select a resistive memory cell to be operated; and (b) measuring a resistance of the selected resistive memory cell and determining the first state, the second state, and the third state based on the measured resistance Which is the state of the selected memory unit.
在每一電阻性記憶體單元具有第一阻障層、第二阻障層以及金屬氧化物層的狀況下,用於控制電阻性記憶體陣列之操作之方法包含:(a)對電阻性記憶體陣列進行程式化,以使得在每一電阻性記憶體單元中,第一記憶體胞元以及第二記憶體胞元不同時處於其低電阻狀態;(b)經由字元線以及位元線來選擇待操作之電阻性記憶體單元;以及(c)量測所選擇之電阻性記憶體單元之電阻以及根據所量測之電阻來判定第一狀態以及第二狀態中之哪一者為所選擇之電阻性記憶體單元之狀態。In the case where each of the resistive memory cells has a first barrier layer, a second barrier layer, and a metal oxide layer, the method for controlling the operation of the resistive memory array includes: (a) resistive memory The body array is programmed such that in each resistive memory cell, the first memory cell and the second memory cell are not in their low resistance state at the same time; (b) via the word line and the bit line Selecting a resistive memory cell to be operated; and (c) measuring a resistance of the selected resistive memory cell and determining which of the first state and the second state is based on the measured resistance Select the state of the resistive memory cell.
為讓本發明之上述及其他目標、特徵與優點明顯易懂,下文特舉若干實施例,並配合所附圖式,作詳細描述如下。The above and other objects, features, and advantages of the invention will be apparent from the description and appended claims.
應理解,上文一般描述以及下文詳細描述兩者為例示性的,且不意欲限制本發明之範疇。The above description, as well as the following detailed description, are intended to be illustrative, and are not intended to limit the scope of the invention.
請參看圖1,圖1為本發明之實施例之電阻性記憶體100的結構圖。電阻性記憶體100具有第一記憶體層110、介質層120以及第二記憶體層130。第一偏壓層140形成於第一記憶體層110上,且第二記憶體層130形成於第二偏壓層150上。在本發明之實施例中,電壓V施加至第一偏壓層140,且第二偏壓層150接地。然而,本發明不限於此。舉例而言,在本發明之實施例中,在第二偏壓層150未接地時,電壓源用於控制並調整第一偏壓層140與第二偏壓層150之間的電壓間隙。所施加之電壓V可為正值或負值。Please refer to FIG. 1. FIG. 1 is a structural diagram of a resistive memory 100 according to an embodiment of the present invention. The resistive memory 100 has a first memory layer 110, a dielectric layer 120, and a second memory layer 130. The first bias layer 140 is formed on the first memory layer 110, and the second memory layer 130 is formed on the second bias layer 150. In an embodiment of the invention, a voltage V is applied to the first bias layer 140 and the second bias layer 150 is grounded. However, the invention is not limited thereto. For example, in an embodiment of the invention, the voltage source is used to control and adjust the voltage gap between the first bias layer 140 and the second bias layer 150 when the second bias layer 150 is not grounded. The applied voltage V can be positive or negative.
當電壓V變化時,第一記憶體層110以及第二記憶體層130之電阻可相應地改變。因此,可藉由施加電壓V來調整(亦即,程式化或抹除)由第一記憶體層110以及第二記憶體層130儲存之資料。When the voltage V changes, the resistances of the first memory layer 110 and the second memory layer 130 may change accordingly. Therefore, the data stored by the first memory layer 110 and the second memory layer 130 can be adjusted (ie, programmed or erased) by applying a voltage V.
請參看圖2,圖2為本發明之實施例之電阻性記憶體200的結構圖。電阻性記憶體200亦具有第一記憶體層210、介質層220以及第二記憶體層230。介質層220形成於第一記憶體層210與第二記憶體層230之間。在此實施 例中,第一記憶體層210以及第二記憶體層230中之每一者為固態電解質,且介質層220為可氧化電極。固態電解質210以及230可為過渡金屬氧化物或含有至少一種硫族元素之材料。可氧化電極220由選自以下各者組成之群組的材料製成:銀(Ag)、銅(Cu)以及鋅(Zn)。Please refer to FIG. 2. FIG. 2 is a structural diagram of a resistive memory 200 according to an embodiment of the present invention. The resistive memory 200 also has a first memory layer 210, a dielectric layer 220, and a second memory layer 230. The dielectric layer 220 is formed between the first memory layer 210 and the second memory layer 230. Implemented here In the example, each of the first memory layer 210 and the second memory layer 230 is a solid electrolyte, and the dielectric layer 220 is an oxidizable electrode. The solid electrolytes 210 and 230 may be transition metal oxides or materials containing at least one chalcogen element. The oxidizable electrode 220 is made of a material selected from the group consisting of silver (Ag), copper (Cu), and zinc (Zn).
請參看圖3,圖3為本發明之實施例之電阻性記憶體300的結構圖。類似於電阻性記憶體200,電阻性記憶體300亦具有第一固態電解質210、可氧化電極220以及第二固態電解質230。此外,電阻性記憶體300更包括構成層240、氮化鈦層250以及內金屬介電質(inter-metal dielectric,IMD)層260以及基板270。構成層240具有兩層氧化矽(SiO2 )間隔物242以及一個鎢(W)層244。鎢層244形成於兩層氧化矽間隔物242之間,且第二固態電解質230形成於可氧化電極220與構成層240之間。此外,氮化鈦層250形成於構成層240與內金屬介電質層260之間,且內金屬介電質層260形成於氮化鈦層250與基板270之間。在此實施例中,第一偏壓層140為電極,且構成層240、氮化鈦層250、內金屬介電質層260以及基板270可被視為如圖2所示之第一偏壓層150。Please refer to FIG. 3. FIG. 3 is a structural diagram of a resistive memory 300 according to an embodiment of the present invention. Similar to the resistive memory 200, the resistive memory 300 also has a first solid electrolyte 210, an oxidizable electrode 220, and a second solid electrolyte 230. In addition, the resistive memory 300 further includes a constituent layer 240, a titanium nitride layer 250, an inter-metal dielectric (IMD) layer 260, and a substrate 270. The constituent layer 240 has two layers of yttrium oxide (SiO 2 ) spacers 242 and one tungsten (W) layer 244. A tungsten layer 244 is formed between the two layers of yttrium oxide spacers 242, and a second solid electrolyte 230 is formed between the oxidizable electrode 220 and the constituent layer 240. Further, a titanium nitride layer 250 is formed between the constituent layer 240 and the inner metal dielectric layer 260, and an inner metal dielectric layer 260 is formed between the titanium nitride layer 250 and the substrate 270. In this embodiment, the first bias layer 140 is an electrode, and the constituent layer 240, the titanium nitride layer 250, the inner metal dielectric layer 260, and the substrate 270 can be regarded as the first bias as shown in FIG. Layer 150.
當電壓V施加至電阻性記憶體300之第一偏壓層140時,可氧化電極220中之正金屬離子被驅動至第一固態電解質210或第二固態電解質230。詳言之,當電壓V為正電壓時,可氧化電極220中之正金屬離子被驅動至第二固態電解質230。當電壓V為負電壓時,可氧化電極220中 之正金屬離子被驅動至第一固態電解質210。因為可氧化電極220中之正金屬離子受到驅動,所以第一固態電解質210以及第二固態電解質230之電阻相應地改變。因此,可根據第一固態電解質210以及第二固態電解質230之電阻來判定由第一固態電解質210以及第二固態電解質230儲存之資料。When the voltage V is applied to the first bias layer 140 of the resistive memory 300, the positive metal ions in the oxidizable electrode 220 are driven to the first solid electrolyte 210 or the second solid electrolyte 230. In detail, when the voltage V is a positive voltage, the positive metal ions in the oxidizable electrode 220 are driven to the second solid electrolyte 230. When the voltage V is a negative voltage, the electrode 220 can be oxidized The positive metal ions are driven to the first solid electrolyte 210. Since the positive metal ions in the oxidizable electrode 220 are driven, the electrical resistances of the first solid electrolyte 210 and the second solid electrolyte 230 are correspondingly changed. Therefore, the materials stored by the first solid electrolyte 210 and the second solid electrolyte 230 can be determined based on the electrical resistances of the first solid electrolyte 210 and the second solid electrolyte 230.
請參看圖3以及圖4A至圖4C。圖4A為說明第一固態電解質210的電壓V與電阻的關係的圖式。圖4B為說明第二固態電解質230的電壓V與電阻的關係的圖式。圖4C為說明兩種固態電解質210以及230的電壓V與電阻的關係的圖式。水平軸表示施加至第一偏壓層140之電壓V之值。圖4A之垂直軸表示第一固態電解質210之電阻。圖4B之垂直軸表示第二固態電解質230之電阻。圖4C之垂直軸表示第一固態電解質210以及第二固態電解質230之電阻。如圖4A所示,當電壓V下拉至第一值V1 時,第一固態電解質210之電阻自R1RESET 改變至R1SET 。當電壓上拉至第三值V3 時,第一固態電解質210之電阻自R1SET 改變至R1RESET 。如圖4B所示,當電壓V下拉至第二值V2 時,第二固態電解質230之電阻自R2SET 改變至R2RESET 。當電壓上拉至第四值V4 時,第二固態電解質230之電阻自R2RESET 改變至R2SET 。換言之,第一固態電解質210以及第二固態電解質230中之每一者基於其電阻而具有兩種記憶體狀態,以使得電阻性記憶體300具有四種記憶體狀態。可根據第一固態電解質210以及第二固態電解 質230之電阻來判定電阻性記憶體300的當前記憶體狀態。Please refer to FIG. 3 and FIG. 4A to FIG. 4C. 4A is a diagram illustrating the relationship between the voltage V of the first solid electrolyte 210 and the electric resistance. 4B is a diagram illustrating the relationship between the voltage V of the second solid electrolyte 230 and the electric resistance. 4C is a diagram illustrating the relationship between the voltage V and the resistance of the two solid electrolytes 210 and 230. The horizontal axis represents the value of the voltage V applied to the first bias layer 140. The vertical axis of Fig. 4A indicates the electric resistance of the first solid electrolyte 210. The vertical axis of Fig. 4B represents the electrical resistance of the second solid electrolyte 230. The vertical axis of FIG. 4C indicates the resistance of the first solid electrolyte 210 and the second solid electrolyte 230. 4A, when the voltage V down to a first value V 1, the resistance of the first solid electrolyte 210 to change from R1 RESET R1 SET. When the voltage is pulled up to the third value V 3 , the resistance of the first solid electrolyte 210 changes from R1 SET to R1 RESET . As shown in FIG. 4B, when the voltage V is pulled down to the second value V 2 , the resistance of the second solid electrolyte 230 is changed from R2 SET to R2 RESET . When the voltage is pulled up to the fourth value V 4 , the resistance of the second solid electrolyte 230 is changed from R2 RESET to R2 SET . In other words, each of the first solid electrolyte 210 and the second solid electrolyte 230 has two memory states based on its resistance, so that the resistive memory 300 has four memory states. The current memory state of the resistive memory 300 can be determined based on the resistances of the first solid electrolyte 210 and the second solid electrolyte 230.
圖4C繪示在調整電壓V之值時第一固態電解質210以及第二固態電解質230之電阻之總和。如圖4C所示,電阻性記憶體300之四種記憶體狀態分別標記為字元A、B、C以及D。第一記憶體狀態A對應於第一值V1 以及電阻(R1SET +R2RESET )之總和,第二記憶體狀態B對應於第二值V2 以及電阻(R1RESET +R2RESET )之總和,第三記憶體狀態C對應於第三值V3 以及電阻(R1RESET +R2RESET )之總和,且第四記憶體狀態D對應於第四值V4 以及電阻(R1RESET +R2SET )之總和。因為對應於第二記憶體狀態B以及第三記憶體狀態C之電阻的總和相等(亦即,等於R1RESET +R2RESET ),所以難以區分第二記憶體狀態B與第三記憶體狀態C。然而,根據本發明,狀態B以及C亦可與狀態A以及狀態D區分。4C illustrates the sum of the electrical resistances of the first solid electrolyte 210 and the second solid electrolyte 230 when the value of the voltage V is adjusted. As shown in FIG. 4C, the four memory states of the resistive memory 300 are labeled as characters A, B, C, and D, respectively. The first memory state A corresponds to the sum of the first value V 1 and the resistance (R1 SET + R2 RESET ), and the second memory state B corresponds to the sum of the second value V 2 and the resistance (R1 RESET + R2 RESET ), The third memory state C corresponds to the sum of the third value V 3 and the resistance (R1 RESET + R2 RESET ), and the fourth memory state D corresponds to the sum of the fourth value V 4 and the resistance (R1 RESET + R2 SET ) . Since the sum of the resistances corresponding to the second memory state B and the third memory state C is equal (that is, equal to R1 RESET + R2 RESET ), it is difficult to distinguish the second memory state B from the third memory state C. However, according to the present invention, states B and C can also be distinguished from state A and state D.
請參看圖5,圖5為用於控制具有圖4A至圖4C所說明之關係的電阻性記憶體300之操作的方法的流程圖。在步驟S502中,對電阻性記憶體300進行程式化。接著,在步驟S504中,在將第一電壓施加至第一偏壓層140時,量測第一記憶體層210與第二記憶體層230之間的電阻,以便判定電阻性記憶體300之當前記憶體狀態。在此實施例中,第一電壓大於第二值V2 ,但小於第三值V3 ,以使得電阻性記憶體300之記憶體狀態將不會在第一電壓之施加之後改變。步驟S504中所量測之電阻被視為第一電阻Ra,且預定值等於(R1RESET +R2RESET )。若第一電阻Ra等於 預定值,則判定電阻性記憶體之狀態為第一狀態(亦即,記憶體狀態B或C)(步驟S506)。若第一電阻Ra不等於預定值,則將第二電壓Vp施加至第一偏壓層140(步驟S508)。在此實施例中,第二電壓Vp大於第三值V3 但小於第四值V4 。換言之,第二電壓Vp大於第一電壓。在步驟S510中,再次量測第一記憶體層210與第二記憶體層230之間的電阻。步驟S510中所量測之電阻被視為第二電阻Rb。若第二電阻Rb等於第一電阻Ra,則意謂電阻性記憶體300之狀態在第二電壓Vp之施加後未改變,以使得可判定電阻性記憶體300之狀態為第二狀態(亦即,記憶體狀態D)(步驟S512)。若第二電阻Rb不等於第一電阻Ra,則意謂電阻性記憶體300之狀態在第二電壓Vp之施加後改變,以使得可判定電阻性記憶體300之狀態為第三狀態(亦即,記憶體狀態A)(步驟S516)。因為若第二電阻Rb不等於第一電阻Ra,則電阻性記憶體300之狀態可在步驟S508中改變,所以在步驟S514中,將電阻性記憶體300再程式化至第三狀態(亦即,記憶體狀態A)。Please refer to FIG. 5. FIG. 5 is a flow chart of a method for controlling the operation of the resistive memory 300 having the relationship illustrated in FIGS. 4A-4C. In step S502, the resistive memory 300 is programmed. Next, in step S504, when the first voltage is applied to the first bias layer 140, the resistance between the first memory layer 210 and the second memory layer 230 is measured to determine the current memory of the resistive memory 300. Body state. In this embodiment, the first voltage is greater than the second value V 2 but less than the third value V 3 such that the memory state of the resistive memory 300 will not change after the application of the first voltage. The resistance measured in step S504 is regarded as the first resistance Ra, and the predetermined value is equal to (R1 RESET + R2 RESET ). If the first resistance Ra is equal to the predetermined value, it is determined that the state of the resistive memory is the first state (that is, the memory state B or C) (step S506). If the first resistance Ra is not equal to the predetermined value, the second voltage Vp is applied to the first bias layer 140 (step S508). In this embodiment, the second voltage Vp is greater than the third value but less than a fourth value V 3 V 4. In other words, the second voltage Vp is greater than the first voltage. In step S510, the resistance between the first memory layer 210 and the second memory layer 230 is measured again. The resistance measured in step S510 is regarded as the second resistance Rb. If the second resistor Rb is equal to the first resistor Ra, it means that the state of the resistive memory 300 is not changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the second state (ie, , memory state D) (step S512). If the second resistor Rb is not equal to the first resistor Ra, it means that the state of the resistive memory 300 is changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the third state (ie, , memory state A) (step S516). Because if the second resistor Rb is not equal to the first resistor Ra, the state of the resistive memory 300 can be changed in step S508, so in step S514, the resistive memory 300 is reprogrammed to the third state (ie, , memory state A).
請參看圖3以及圖6A至圖6C。圖6A為說明本發明之另一實施例中之第一固態電解質210的電壓V與電阻的關係的圖式。圖6B為說明本發明之另一實施例中之第二固態電解質230的電壓V與電阻的關係的圖式。圖6B為說明本發明之另一實施例中之兩種固態電解質210以及230的電壓V與電阻的關係的圖式。水平軸表示施加至第一偏壓層140之電壓V之值。圖6A之垂直軸表示第一固 態電解質210之電阻。圖6B之垂直軸表示第二固態電解質230之電阻。圖6C之垂直軸表示第一固態電解質210以及第二固態電解質230之電阻。在此實施例中,R1SET 之值大於R2SET 之值,且R1RESET 之值等於R2RESET 之值。因此,對應於記憶體狀態B之電阻(R1RESET +R2RESET )之總和等於對應於記憶體狀態C之電阻(R1RESET +R2RESET )之總和,且對應於記憶體狀態A之電阻(R1SET +R2RESET )之總和不同於對應於記憶體狀態D之電阻(R1RESET +R2SET )之總和。因此,在此實施例中,可直接根據第一電阻Ra來判定電阻性記憶體300之狀態。Please refer to FIG. 3 and FIG. 6A to FIG. 6C. Fig. 6A is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte 210 in another embodiment of the present invention. Fig. 6B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte 230 in another embodiment of the present invention. Figure 6B is a diagram illustrating the relationship between voltage V and resistance of two solid electrolytes 210 and 230 in another embodiment of the present invention. The horizontal axis represents the value of the voltage V applied to the first bias layer 140. The vertical axis of Fig. 6A indicates the electric resistance of the first solid electrolyte 210. The vertical axis of Fig. 6B indicates the electric resistance of the second solid electrolyte 230. The vertical axis of FIG. 6C indicates the resistance of the first solid electrolyte 210 and the second solid electrolyte 230. In this embodiment, the value of R1 SET is greater than the value of R2 SET , and the value of R1 RESET is equal to the value of R2 RESET . Therefore, the sum of the resistances (R1 RESET + R2 RESET ) corresponding to the memory state B is equal to the sum of the resistances corresponding to the memory state C (R1 RESET + R2 RESET ), and corresponds to the resistance of the memory state A (R1 SET) The sum of +R2 RESET ) is different from the sum of the resistances (R1 RESET + R2 SET ) corresponding to the memory state D. Therefore, in this embodiment, the state of the resistive memory 300 can be determined directly from the first resistance Ra.
請參看圖7,圖7為用於控制具有圖6A至圖6C所說明之關係的電阻性記憶體300之操作的方法的流程圖。在步驟S702中,對電阻性記憶體300進行程式化。接著,在步驟S704中,在將第一電壓施加至第一偏壓層140時,量測第一記憶體層210與第二記憶體層230之間的電阻作為第一電阻Ra。若第一電阻Ra等於(R1RESET +R2RESET ),則判定電阻性記憶體300之狀態為第一狀態(亦即,記憶體狀態B或C)(步驟S706)。若第一電阻Ra等於(R1RESET +R2SET ),則判定電阻性記憶體300之狀態為第二狀態(亦即,記憶體狀態D)(步驟S708)。若第一電阻Ra等於(R1SET +R2RESET ),則判定電阻性記憶體300之狀態為第三狀態(亦即,記憶體狀態A)(步驟S710)。Please refer to FIG. 7. FIG. 7 is a flow chart of a method for controlling the operation of the resistive memory 300 having the relationship illustrated in FIGS. 6A-6C. In step S702, the resistive memory 300 is programmed. Next, in step S704, when the first voltage is applied to the first bias layer 140, the resistance between the first memory layer 210 and the second memory layer 230 is measured as the first resistance Ra. If the first resistance Ra is equal to (R1 RESET + R2 RESET ), it is determined that the state of the resistive memory 300 is the first state (that is, the memory state B or C) (step S706). If the first resistance Ra is equal to (R1 RESET + R2 SET ), it is determined that the state of the resistive memory 300 is the second state (that is, the memory state D) (step S708). If the first resistance Ra is equal to (R1 SET + R2 RESET ), it is determined that the state of the resistive memory 300 is the third state (that is, the memory state A) (step S710).
請參看圖3以及圖8A至圖8C。圖8A為說明本發明之另一實施例中之第一固態電解質210的電壓V與電阻的 關係的圖式。圖8B為說明與圖8A相同之實施例中之第二固態電解質230的電壓V與電阻的關係的圖式。圖8C為說明與圖8A相同之實施例中之兩種固態電解質210以及230的電壓V與電阻的關係的圖式。水平軸表示施加至第一偏壓層140之電壓V之值。圖8A之垂直軸表示第一固態電解質210之電阻。圖8B之垂直軸表示第二固態電解質230之電阻。圖8C之垂直軸表示第一固態電解質210以及第二固態電解質230之電阻。如圖8A所示,當電壓V下拉至第一值V1 時,第一固態電解質210之電阻自R1RESET 改變至R1SET 。當電壓上拉至第四值V4 時,第一固態電解質210之電阻自R1SET 改變至R1RESET 。如圖8B所示,當電壓V下拉至第二值V2 時,第二固態電解質230之電阻自R2SET 改變至R2RESET 。當電壓上拉至第三值V3 時,第二固態電解質230之電阻自R2RESET 改變至R2SET 。Please refer to FIG. 3 and FIG. 8A to FIG. 8C. Fig. 8A is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte 210 in another embodiment of the present invention. Fig. 8B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte 230 in the same embodiment as Fig. 8A. Fig. 8C is a view showing the relationship between the voltage V and the electric resistance of the two solid electrolytes 210 and 230 in the same embodiment as Fig. 8A. The horizontal axis represents the value of the voltage V applied to the first bias layer 140. The vertical axis of Fig. 8A indicates the electric resistance of the first solid electrolyte 210. The vertical axis of Fig. 8B indicates the electric resistance of the second solid electrolyte 230. The vertical axis of FIG. 8C represents the resistance of the first solid electrolyte 210 and the second solid electrolyte 230. As shown in FIG. 8A, when the voltage V down to a first value V. 1, the first solid electrolyte 210, since the resistance R1 RESET changed to R1 SET. When the voltage is pulled up to the fourth value V 4 , the resistance of the first solid electrolyte 210 changes from R1 SET to R1 RESET . As shown in FIG. 8B, when the voltage V is pulled down to the second value V 2 , the resistance of the second solid electrolyte 230 is changed from R2 SET to R2 RESET . When the voltage is pulled up to the third value V 3 , the resistance of the second solid electrolyte 230 is changed from R2 RESET to R2 SET .
圖8C繪示在調整電壓V之值時第一固態電解質210以及第二固態電解質230之電阻之總和。如圖8C所示,電阻性記憶體300之四種記憶體狀態分別標記為字元A、B、C以及D。第一記憶體狀態A對應於第一值V1 以及電阻(R1SET +R2RESET )之總和,第二記憶體狀態B對應於第二值V2 以及電阻(R1RESET +R2RESET )之總和,第三記憶體狀態C對應於第三值V3 以及電阻(R1SET +R2SET )之總和,且第四記憶體狀態D對應於第四值V4 以及電阻(R1RESET +R2SET )之總和。FIG. 8C illustrates the sum of the resistances of the first solid electrolyte 210 and the second solid electrolyte 230 when the value of the voltage V is adjusted. As shown in FIG. 8C, the four memory states of the resistive memory 300 are labeled as characters A, B, C, and D, respectively. The first memory state A corresponds to the sum of the first value V 1 and the resistance (R1 SET + R2 RESET ), and the second memory state B corresponds to the sum of the second value V 2 and the resistance (R1 RESET + R2 RESET ), The third memory state C corresponds to the sum of the third value V 3 and the resistance (R1 SET + R2 SET ), and the fourth memory state D corresponds to the sum of the fourth value V 4 and the resistance (R1 RESET + R2 SET ) .
請參看圖9,圖9為用於控制具有圖8A至圖8C所說 明之關係的電阻性記憶體300之操作的方法的流程圖。在步驟S902中,對電阻性記憶體300進行程式化。接著,在步驟S904中,在將第一電壓施加至第一偏壓層140時,量測第一記憶體層210與第二記憶體層230之間的電阻作為第一電阻Ra。在此實施例中,預定值等於(R1RESET +R2RESET )或(R1SET +R2SET )。若第一電阻Ra等於(R1RESET +R2RESET ),則判定電阻性記憶體之狀態為第一狀態(亦即,記憶體狀態B)(步驟S906)。若第一電阻Ra等於(R1SET +R2SET ),則判定電阻性記憶體之狀態為第二狀態(亦即,記憶體狀態C)(步驟S908)。若第一電阻Ra不等於(R1RESET +R2RESET ),亦不等於(R1SET +R2SET ),則將第二電壓Vp施加至第一偏壓層140(步驟S910)。在步驟S912中,量測第一記憶體層210與第二記憶體層230之間的電阻作為第二電阻Rb。若第二電阻Rb等於第一電阻Ra,則意謂電阻性記憶體300之狀態在第二電壓Vp之施加後未改變,以使得可判定電阻性記憶體300之狀態為第三狀態(亦即,記憶體狀態D)(步驟S914)。若第二電阻Rb不等於第一電阻Ra,則意謂電阻性記憶體300之狀態已在第二電壓Vp之施加後改變,以使得可判定電阻性記憶體300之狀態為第四狀態(亦即,記憶體狀態A)(步驟S918)。因為若第二電阻Rb不等於第一電阻Ra,則電阻性記憶體300之狀態可在步驟S910中改變,所以在步驟S916中,將電阻性記憶體300再程式化至第四狀態(亦即,記憶體狀態A)。Please refer to FIG. 9, which is a flow chart of a method for controlling the operation of the resistive memory 300 having the relationship illustrated in FIGS. 8A-8C. In step S902, the resistive memory 300 is programmed. Next, in step S904, when the first voltage is applied to the first bias layer 140, the resistance between the first memory layer 210 and the second memory layer 230 is measured as the first resistance Ra. In this embodiment, the predetermined value is equal to (R1 RESET + R2 RESET ) or (R1 SET + R2 SET ). If the first resistance Ra is equal to (R1 RESET + R2 RESET ), it is determined that the state of the resistive memory is the first state (that is, the memory state B) (step S906). If the first resistance Ra is equal to (R1 SET + R2 SET ), it is determined that the state of the resistive memory is the second state (that is, the memory state C) (step S908). If the first resistance Ra is not equal to (R1 RESET + R2 RESET ) and is not equal to (R1 SET + R2 SET ), the second voltage Vp is applied to the first bias layer 140 (step S910). In step S912, the resistance between the first memory layer 210 and the second memory layer 230 is measured as the second resistor Rb. If the second resistor Rb is equal to the first resistor Ra, it means that the state of the resistive memory 300 is not changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the third state (ie, , memory state D) (step S914). If the second resistor Rb is not equal to the first resistor Ra, it means that the state of the resistive memory 300 has changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the fourth state (also That is, the memory state A) (step S918). Because if the second resistor Rb is not equal to the first resistor Ra, the state of the resistive memory 300 can be changed in step S910, so in step S916, the resistive memory 300 is reprogrammed to the fourth state (ie, , memory state A).
請參看圖3以及圖10A至圖10C。圖10A為說明本發明之另一實施例中之第一固態電解質210的電壓V與電阻的關係的圖式。圖10B為說明與圖10A相同之實施例中之第二固態電解質230的電壓V與電阻的關係的圖式。圖10C為說明與圖10A相同之實施例中之兩種固態電解質210以及230的電壓V與電阻的關係的圖式。水平軸表示施加至第一偏壓層140之電壓V之值。圖10A之垂直軸表示第一固態電解質210之電阻。圖10B之垂直軸表示第二固態電解質230之電阻。圖10C之垂直軸表示第一固態電解質210以及第二固態電解質230之電阻。如圖10A所示,當電壓V下拉至第二值V2 時,第一固態電解質210之電阻自R1RESET 改變至R1SET 。當電壓上拉至第三值V3 時,第一固態電解質210之電阻自R1SET 改變至R1RESET 。如圖10B所示,當電壓V下拉至第一值V1 時,第二固態電解質230之電阻自R2SET 改變至R2RESET 。當電壓上拉至第四值V4 時,第二固態電解質230之電阻自R2RESET 改變至R2SET 。Please refer to FIG. 3 and FIG. 10A to FIG. 10C. Fig. 10A is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte 210 in another embodiment of the present invention. Fig. 10B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte 230 in the same embodiment as Fig. 10A. Fig. 10C is a view showing the relationship between the voltage V and the electric resistance of the two solid electrolytes 210 and 230 in the same embodiment as Fig. 10A. The horizontal axis represents the value of the voltage V applied to the first bias layer 140. The vertical axis of Fig. 10A indicates the electric resistance of the first solid electrolyte 210. The vertical axis of Fig. 10B indicates the electric resistance of the second solid electrolyte 230. The vertical axis of FIG. 10C represents the resistance of the first solid electrolyte 210 and the second solid electrolyte 230. As shown in FIG. 10A, when the voltage V is pulled down to the second value V 2 , the resistance of the first solid electrolyte 210 is changed from R1 RESET to R1 SET . When the voltage is pulled up to the third value V 3 , the resistance of the first solid electrolyte 210 changes from R1 SET to R1 RESET . As shown in FIG. 10B, when the voltage V down to a first value 1 V, the resistance of the second solid electrolyte 230 from the R2 SET is changed to R2 RESET. When the voltage is pulled up to the fourth value V 4 , the resistance of the second solid electrolyte 230 is changed from R2 RESET to R2 SET .
圖10C繪示在調整電壓V之值時第一固態電解質210以及第二固態電解質230之電阻之總和。如圖10C所示,電阻性記憶體300之四種記憶體狀態分別標記為字元A、B、C以及D。第一記憶體狀態A對應於第一值V1 以及電阻(R1SET +R2RESET )之總和,第二記憶體狀態B對應於第二值V2 以及電阻(R1SET +R2SET )之總和,第三記憶體狀態C對應於第三值V3 以及電阻(R1RESET +R2RESET )之總和,且第四記憶體狀態D對應於第四值V4 以及電阻(R1RESET +R2SET ) 之總和。FIG. 10C illustrates the sum of the resistances of the first solid electrolyte 210 and the second solid electrolyte 230 when the value of the voltage V is adjusted. As shown in FIG. 10C, the four memory states of the resistive memory 300 are labeled as characters A, B, C, and D, respectively. The first memory state A corresponds to the sum of the first value V 1 and the resistance (R1 SET + R2 RESET ), and the second memory state B corresponds to the sum of the second value V 2 and the resistance (R1 SET + R2 SET ), The third memory state C corresponds to the sum of the third value V 3 and the resistance (R1 RESET + R2 RESET ), and the fourth memory state D corresponds to the sum of the fourth value V 4 and the resistance (R1 RESET + R2 SET ) .
請參看圖11,圖11為用於控制具有圖10A至圖10C所說明之關係的電阻性記憶體300之操作的方法的流程圖。在步驟S1102中,對電阻性記憶體300進行程式化。接著,在步驟S1104中,在將第一電壓施加至第一偏壓層140時,量測第一記憶體層210與第二記憶體層230之間的電阻作為第一電阻Ra。在此實施例中,預定值等於(R1RESET +R2RESET )或(R1SET +R2SET )。若第一電阻Ra等於(R1RESET +R2RESET ),則判定電阻性記憶體之狀態為第一狀態(亦即,記憶體狀態C)(步驟S1106)。若第一電阻Ra等於(R1SET +R2SET ),則判定電阻性記憶體之狀態為第二狀態(亦即,記憶體狀態B)(步驟S1108)。若第一電阻Ra不等於(R1RESET +R2RESET ),亦不等於(R1SET +R2SET ),則將第二電壓Vp施加至第一偏壓層140(步驟S1110)。在步驟S1112中,量測第一記憶體層210與第二記憶體層230之間的電阻作為第二電阻Rb。若第二電阻Rb等於第一電阻Ra,則意謂電阻性記憶體300之狀態在第二電壓Vp之施加後未改變,以使得可判定電阻性記憶體300之狀態為第三狀態(亦即,記憶體狀態D)(步驟S1114)。若第二電阻Rb不等於第一電阻Ra,則意謂電阻性記憶體300之狀態已在第二電壓Vp之施加後改變,以使得可判定電阻性記憶體300之狀態為第四狀態(亦即,記憶體狀態A)(步驟S1118)。因為若第二電阻Rb不等於第一電阻Ra,則電阻性記憶體300之狀態可在步驟S910中改變,所以 在步驟S1116中,將電阻性記憶體300再程式化至第四狀態(亦即,記憶體狀態A)。Please refer to FIG. 11, which is a flow chart of a method for controlling the operation of the resistive memory 300 having the relationship illustrated in FIGS. 10A-10C. In step S1102, the resistive memory 300 is programmed. Next, in step S1104, when the first voltage is applied to the first bias layer 140, the resistance between the first memory layer 210 and the second memory layer 230 is measured as the first resistance Ra. In this embodiment, the predetermined value is equal to (R1 RESET + R2 RESET ) or (R1 SET + R2 SET ). If the first resistance Ra is equal to (R1 RESET + R2 RESET ), it is determined that the state of the resistive memory is the first state (that is, the memory state C) (step S1106). If the first resistance Ra is equal to (R1 SET + R2 SET ), it is determined that the state of the resistive memory is the second state (that is, the memory state B) (step S1108). If the first resistance Ra is not equal to (R1 RESET + R2 RESET ) and is not equal to (R1 SET + R2 SET ), the second voltage Vp is applied to the first bias layer 140 (step S1110). In step S1112, the resistance between the first memory layer 210 and the second memory layer 230 is measured as the second resistor Rb. If the second resistor Rb is equal to the first resistor Ra, it means that the state of the resistive memory 300 is not changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the third state (ie, , memory state D) (step S1114). If the second resistor Rb is not equal to the first resistor Ra, it means that the state of the resistive memory 300 has changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the fourth state (also That is, the memory state A) (step S1118). Because if the second resistor Rb is not equal to the first resistor Ra, the state of the resistive memory 300 can be changed in step S910, so in step S1116, the resistive memory 300 is reprogrammed to the fourth state (ie, , memory state A).
請參看圖12,圖12為本發明之實施例之電阻性記憶體1200的結構圖。電阻性記憶體1200具有介質層1210、第一阻障層1220以及第二阻障層1230。位於介質層1210與第一阻障層1220之間的界面1212被視為電阻性記憶體1200之第一記憶體層,且位於介質層1210與第二阻障層1230之間的界面1214被視為電阻性記憶體1200之第二記憶體層。可根據第一記憶體層1212以及第二記憶體層1214之電阻來判定由電阻性記憶體1200儲存之資料。在此實施例中,第一阻障層1220以及第二阻障層1230由選自以下各者組成之群組的材料製成:氮化鈦(TiN)、氮化鉭(TaN)、鉑(Pt)以及金(Au);且介質層1210為金屬氧化物層,所述金屬氧化物層是由選自以下各者組成之群組的材料製成:氧化鎢、氧化鈦、氧化鎳、氧化鋁、氧化銅、氧化鋯、氧化鈮以及氧化鉭。Referring to FIG. 12, FIG. 12 is a structural diagram of a resistive memory 1200 according to an embodiment of the present invention. The resistive memory 1200 has a dielectric layer 1210, a first barrier layer 1220, and a second barrier layer 1230. The interface 1212 between the dielectric layer 1210 and the first barrier layer 1220 is considered to be the first memory layer of the resistive memory 1200, and the interface 1214 between the dielectric layer 1210 and the second barrier layer 1230 is considered The second memory layer of the resistive memory 1200. The data stored by the resistive memory 1200 can be determined based on the resistance of the first memory layer 1212 and the second memory layer 1214. In this embodiment, the first barrier layer 1220 and the second barrier layer 1230 are made of a material selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), and platinum ( Pt) and gold (Au); and the dielectric layer 1210 is a metal oxide layer made of a material selected from the group consisting of tungsten oxide, titanium oxide, nickel oxide, and oxidation. Aluminum, copper oxide, zirconium oxide, cerium oxide, and cerium oxide.
請參看圖13,圖13為本發明之實施例之電阻性記憶體1300的結構圖。電阻性記憶體1300亦具有金屬氧化物層1210、第一阻障層1220以及第二阻障層1230。此外,電阻性記憶體1300更包括兩層氧化矽間隔物1240、第一電極1250、第二電極1260、內金屬介電質層1270以及基板1280。兩層氧化矽間隔物1240與金屬氧化物層1210接觸,且形成於第一阻障層1220與第二阻障層1230之間。第一電極1250形成於第一阻障層1220上,且第二電極 1260形成於第二阻障層1230與內金屬介電質層1270之間。內金屬介電質層1270形成於第二電極1260與基板1280之間。在此實施例中,第一電極1250以及第一阻障層1220被視為電阻性記憶體1300之第一偏壓層140,且第二阻障層1230、第二電極1260、內金屬介電質層1270以及基板1280被視為電阻性記憶體1300之第二偏壓層150。Referring to FIG. 13, FIG. 13 is a structural diagram of a resistive memory 1300 according to an embodiment of the present invention. The resistive memory 1300 also has a metal oxide layer 1210, a first barrier layer 1220, and a second barrier layer 1230. In addition, the resistive memory 1300 further includes two layers of yttrium oxide spacers 1240, a first electrode 1250, a second electrode 1260, an inner metal dielectric layer 1270, and a substrate 1280. The two-layer yttrium oxide spacer 1240 is in contact with the metal oxide layer 1210 and is formed between the first barrier layer 1220 and the second barrier layer 1230. The first electrode 1250 is formed on the first barrier layer 1220, and the second electrode 1260 is formed between the second barrier layer 1230 and the inner metal dielectric layer 1270. The inner metal dielectric layer 1270 is formed between the second electrode 1260 and the substrate 1280. In this embodiment, the first electrode 1250 and the first barrier layer 1220 are regarded as the first bias layer 140 of the resistive memory 1300, and the second barrier layer 1230, the second electrode 1260, and the inner metal dielectric The layer 1270 and the substrate 1280 are considered to be the second bias layer 150 of the resistive memory 1300.
當將電壓V施加至電阻性記憶體1300之第一偏壓層140時,第一界面1212以及第二界面1214之電阻可相應地改變。請參看圖13以及圖14A至圖14E。圖14A為說明第一界面1212之電壓V與電阻的關係的圖式。圖14B為說明第二界面1214之電壓V與電阻的關係的圖式。圖14C為說明在電壓V自第四值V4 下拉至第一值V1 時第一界面1212與第二界面1214之間的電壓V與電阻的關係的圖式。圖14D為說明在電壓V自第一值V1 上拉至第四值V4 時第一界面1212與第二界面1214之間的電壓V與電阻的關係的圖式。圖14E為說明電阻性記憶體1300之記憶體狀態的切換的圖式。水平軸表示施加至第一偏壓層140之電壓V之值。圖14A之垂直軸表示第一界面1212之電阻。圖14B之垂直軸表示第二界面1214之電阻。圖14C至圖14E之垂直軸表示第一界面1212與第二界面1214之間的電阻。如圖14A所示,當電壓V下拉至第二值V2 時,第一界面1212之電阻自R1RESET 改變至R1SET 。當電壓上拉至第四值V4 時,第一界面1212之電阻自R1SET 改變至 R1RESET 。如圖14B所示,當電壓V下拉至第一值V1 時,第二界面1214之電阻自R2SET 改變至R2RESET 。當電壓上拉至第三值V3 時,第二界面1214之電阻自R2RESET 改變至R2SET 。換言之,第一界面1212以及第二界面1214中之每一者基於其電阻而具有兩種記憶體狀態,以使得電阻性記憶體1300具有四種記憶體狀態。可根據第一界面1212以及第二界面1214之電阻來判定電阻性記憶體1300的當前記憶體狀態。When a voltage V is applied to the first bias layer 140 of the resistive memory 1300, the resistance of the first interface 1212 and the second interface 1214 may change accordingly. Please refer to FIG. 13 and FIGS. 14A to 14E. FIG. 14A is a diagram illustrating the relationship between the voltage V of the first interface 1212 and the resistance. FIG. 14B is a diagram illustrating the relationship between the voltage V of the second interface 1214 and the resistance. 14C is a diagram illustrating the relationship between the voltage V and the resistance between the first interface 1212 and the second interface 1214 when the voltage V is pulled down from the fourth value V 4 to the first value V 1 . FIG 14D is an explanatory pulled to a fourth voltage value V from the first value V 1 V 4 the first interface 1212 and the resistance relationship between the voltage V between the 1214 interface and the second type of FIG. FIG. 14E is a diagram for explaining switching of the memory state of the resistive memory 1300. The horizontal axis represents the value of the voltage V applied to the first bias layer 140. The vertical axis of Figure 14A represents the resistance of the first interface 1212. The vertical axis of Figure 14B represents the resistance of the second interface 1214. The vertical axis of Figures 14C-14E represents the electrical resistance between the first interface 1212 and the second interface 1214. 14A, when the voltage V down to a second value V 2, the first interface of the resistor 1212 to change from R1 RESET R1 SET. When the voltage is pulled up to the fourth value V 4 , the resistance of the first interface 1212 changes from R1 SET to R1 RESET . As shown in FIG. 14B, when the voltage V down to a first value 1 V, from the second interface of the resistor R2 SET 1214 is changed to R2 RESET. When pulled to the third voltage value V 3, the second interface of the resistor 1214 is changed to R2 SET from R2 RESET. In other words, each of the first interface 1212 and the second interface 1214 has two memory states based on its resistance such that the resistive memory 1300 has four memory states. The current memory state of the resistive memory 1300 can be determined based on the resistance of the first interface 1212 and the second interface 1214.
圖14C以及圖14E繪示在電壓V之值下拉時第一界面1212以及第二界面1214之電阻之總和。在電壓V自第四電壓V4 下拉至第一電壓V1 時的程序期間,第一界面1212與第二界面1214之間的電阻自(R1RESET +R2SET )改變至(R1SET +R2SET )且接著改變至(R1SET +R2RESET )。圖14D以及圖14E繪示在電壓V之值上拉時第一界面1212以及第二界面1214之電阻之總和。在電壓V自第一電壓V1 上拉至第四電壓V4 時的程序期間,第一界面1212與第二界面1214之間的電阻自(R1SET +R2RESET )改變至(R1SET +R2SET )且接著改變至(R1RESET +R2SET )。14C and 14E illustrate the sum of the resistances of the first interface 1212 and the second interface 1214 when the value of the voltage V is pulled down. During the process when the voltage V is pulled down from the fourth voltage V 4 to the first voltage V 1 , the resistance between the first interface 1212 and the second interface 1214 is changed from (R1 RESET + R2 SET ) to (R1 SET + R2 SET ) And then change to (R1 SET + R2 RESET ). 14D and 14E illustrate the sum of the resistances of the first interface 1212 and the second interface 1214 when the value of the voltage V is pulled up. During the process when the voltage V is pulled from the first voltage V 1 to the fourth voltage V 4 , the resistance between the first interface 1212 and the second interface 1214 is changed from (R1 SET + R2 RESET ) to (R1 SET + R2). SET ) and then change to (R1 RESET + R2 SET ).
如圖14E所示,電阻性記憶體1300之四種記憶體狀態分別標記為字元A、B、C以及D。第一記憶體狀態A對應於第一值V1 以及電阻(R1SET +R2RESET )之總和,第二記憶體狀態B對應於第二值V2 以及電阻(R1SET +R2SET )之總和,第三記憶體狀態C對應於第三值V3 以及電阻(R1SET +R2SET )之總和,且第四記憶體狀態D對應於第四值 V4 以及電阻(R1RESET +R2SET )之總和。因為對應於第二記憶體狀態B以及第三記憶體狀態C之電阻的總和相等(亦即,等於R1SET +R2SET ),所以難以區分第二記憶體狀態B與第三記憶體狀態C。然而,根據本發明,狀態B以及C亦可與狀態A以及狀態D區分。As shown in FIG. 14E, the four memory states of the resistive memory 1300 are labeled as characters A, B, C, and D, respectively. The first memory state A corresponds to the sum of the first value V 1 and the resistance (R1 SET + R2 RESET ), and the second memory state B corresponds to the sum of the second value V 2 and the resistance (R1 SET + R2 SET ), The third memory state C corresponds to the sum of the third value V 3 and the resistance (R1 SET + R2 SET ), and the fourth memory state D corresponds to the sum of the fourth value V 4 and the resistance (R1 RESET + R2 SET ) . Since the sum of the resistances corresponding to the second memory state B and the third memory state C is equal (that is, equal to R1 SET + R2 SET ), it is difficult to distinguish the second memory state B from the third memory state C. However, according to the present invention, states B and C can also be distinguished from state A and state D.
請參看圖15,圖15為用於控制具有圖14A至圖14E所說明之關係的電阻性記憶體1300之操作的方法的流程圖。在步驟S1502中,對電阻性記憶體1300進行程式化。接著,在步驟S1504中,在將第一電壓施加至第一偏壓層140時,量測第一界面1212與第二記憶體層1214之間的電阻。在此實施例中,第一電壓大於第二值V2 ,但小於第三值V3 ,以使得電阻性記憶體1300之記憶體狀態將不會在第一電壓施加至第一偏壓層140之後改變。步驟S1504中所量測之電阻被視為第一電阻Ra,且預定值等於(R1SET +R2SET )。若第一電阻Ra等於預定值,則判定電阻性記憶體之狀態為第一狀態(亦即,記憶體狀態B或C)(步驟S1506)。若第一電阻Ra不等於預定值,則將第二電壓Vp施加至第一偏壓層140(步驟S1508)。在此實施例中,第二電壓Vp大於第三值V3 但小於第四值V4 。在步驟S1510中,再次量測第一界面1212與第二界面1214之間的電阻。步驟S1510中所量測之電阻被視為第二電阻Rb。若第二電阻Rb等於第一電阻Ra,則意謂電阻性記憶體1300之狀態在第二電壓Vp之施加後未改變,以使得可判定電阻性記憶體1300之狀態為第二狀態(亦即,記憶體 狀態D)(步驟S1512)。若第二電阻Rb不等於第一電阻Ra,則意謂電阻性記憶體1300之狀態在第二電壓Vp之施加後改變,以使得可判定電阻性記憶體1300之狀態為第三狀態(亦即,記憶體狀態A)(步驟S1516)。因為若第二電阻Rb不等於第一電阻Ra,則電阻性記憶體1300之狀態可在步驟S1508中改變,所以在步驟S1514中,將電阻性記憶體1300再程式化至第三狀態(亦即,記憶體狀態A)。Please refer to FIG. 15, which is a flow chart of a method for controlling the operation of the resistive memory 1300 having the relationship illustrated in FIGS. 14A-14E. In step S1502, the resistive memory 1300 is programmed. Next, in step S1504, when a first voltage is applied to the first bias layer 140, the resistance between the first interface 1212 and the second memory layer 1214 is measured. In this embodiment, the first voltage is greater than the second value V 2 but less than the third value V 3 such that the memory state of the resistive memory 1300 will not be applied to the first bias layer 140 at the first voltage. Then change. The resistance measured in step S1504 is regarded as the first resistance Ra, and the predetermined value is equal to (R1 SET + R2 SET ). If the first resistance Ra is equal to the predetermined value, it is determined that the state of the resistive memory is the first state (that is, the memory state B or C) (step S1506). If the first resistance Ra is not equal to the predetermined value, the second voltage Vp is applied to the first bias layer 140 (step S1508). In this embodiment, the second voltage Vp is greater than the third value but less than a fourth value V 3 V 4. In step S1510, the resistance between the first interface 1212 and the second interface 1214 is measured again. The resistance measured in step S1510 is regarded as the second resistance Rb. If the second resistor Rb is equal to the first resistor Ra, it means that the state of the resistive memory 1300 is not changed after the application of the second voltage Vp, so that the state of the resistive memory 1300 can be determined to be the second state (ie, , memory state D) (step S1512). If the second resistor Rb is not equal to the first resistor Ra, it means that the state of the resistive memory 1300 is changed after the application of the second voltage Vp, so that the state of the resistive memory 1300 can be determined to be the third state (ie, , memory state A) (step S1516). Because if the second resistor Rb is not equal to the first resistor Ra, the state of the resistive memory 1300 can be changed in step S1508, so in step S1514, the resistive memory 1300 is reprogrammed to the third state (ie, , memory state A).
請參看圖13以及圖16。圖16為說明根據本發明之實施例之電阻性記憶體1300的記憶體狀態的切換的圖式。水平軸表示施加至第一偏壓層140之電壓V之值,且垂直軸表示第一界面1212與第二界面1214之間的電阻。在此實施例中,R1RESET 之值小於R2RESET 之值,且R1SET 之值等於R2SET 之值。因此,對應於記憶體狀態B之電阻(R1SET +R2SET )之總和等於對應於記憶體狀態C之電阻(R1SET +R2SET )之總和,且對應於記憶體狀態A之電阻(R1SET +R2RESET )之總和不同于對應於記憶體狀態D之電阻(R1RESET +R2SET )之總和。因此,在此實施例中,可直接根據第一電阻Ra來判定電阻性記憶體1300之狀態。Please refer to FIG. 13 and FIG. 16. FIG. 16 is a diagram illustrating switching of a memory state of the resistive memory 1300 according to an embodiment of the present invention. The horizontal axis represents the value of the voltage V applied to the first bias layer 140, and the vertical axis represents the electrical resistance between the first interface 1212 and the second interface 1214. In this embodiment, the value of R1 RESET is less than the value of R2 RESET , and the value of R1 SET is equal to the value of R2 SET . Thus, corresponding to the resistance memory state B is (R1 SET + R2 SET) the sum is equal to correspond to the sum of the memory state C of a resistor (R1 SET + R2 SET) of, and corresponds to a memory state resistance A of (R1 SET The sum of +R2 RESET ) is different from the sum of the resistances (R1 RESET + R2 SET ) corresponding to the memory state D. Therefore, in this embodiment, the state of the resistive memory 1300 can be directly determined based on the first resistance Ra.
請參看圖17,圖17為用於控制具有圖16所說明之關係的電阻性記憶體1300之操作的方法的流程圖。在步驟S1702中,對電阻性記憶體1300進行程式化。接著,在步驟S1704中,在將第一電壓施加至第一偏壓層140時,量測第一界面1212與第二界面1214之間的電阻作為第一電阻Ra。若第一電阻Ra等於(R1SET +R2SET ),則判定電阻性 記憶體1300之狀態為第一狀態(亦即,記憶體狀態B或C)(步驟S1706)。若第一電阻Ra等於(R1RESET +R2SET ),則判定電阻性記憶體1300之狀態為第二狀態(亦即,記憶體狀態D)(步驟S1708)。若第一電阻Ra等於(R1SET +R2RESET ),則判定電阻性記憶體1300之狀態為第三狀態(亦即,記憶體狀態A)(步驟S1710)。Please refer to FIG. 17, which is a flow chart of a method for controlling the operation of the resistive memory 1300 having the relationship illustrated in FIG. In step S1702, the resistive memory 1300 is programmed. Next, in step S1704, when the first voltage is applied to the first bias layer 140, the resistance between the first interface 1212 and the second interface 1214 is measured as the first resistance Ra. If the first resistance Ra is equal to (R1 SET + R2 SET ), it is determined that the state of the resistive memory 1300 is the first state (that is, the memory state B or C) (step S1706). If the first resistance Ra is equal to (R1 RESET + R2 SET ), it is determined that the state of the resistive memory 1300 is the second state (that is, the memory state D) (step S1708). If the first resistance Ra is equal to (R1 SET + R2 RESET ), it is determined that the state of the resistive memory 1300 is the third state (that is, the memory state A) (step S1710).
請參看圖13以及圖18。圖18為說明根據本發明之實施例之電阻性記憶體1300的記憶體狀態的切換的圖式。水平軸表示施加至第一偏壓層140之電壓V之值,且垂直軸表示第一界面1212與第二界面1214之間的電阻。與圖16之實施例相比,當前實施例之第一界面1212多一種電阻性狀態。換言之,當前實施例之第一界面1212具有三種電阻性狀態,而圖16之實施例之第一界面1212具有兩種電阻性狀態。對應於當前實施例之第一界面1212之三種電阻性狀態的電阻分別為R1SET 、R1RESET1 以及R1RESET2 。因此,當前實施例之電阻性記憶體1300具有五種記憶體狀態,所述五種記憶體狀態分別標記為字元A、B、C、D以及E。當前實施例之狀態A、B以及C與圖16之實施例之狀態A、B以及C相同,當前實施例之狀態D對應於第四值V4 以及電阻(R1RESET1 +R2SET )之總和,且當前實施例之狀態E對應於第五值V5 以及電阻(R1RESET2 +R2SET )之總和。在當前實施例中,R2RESET 、R1RESET1 以及R1RESET2 之值相同,且R1RESET 之值等於R2RESET 之值。因此,對應於記憶體狀態B之電阻(R1SET +R2SET )之總和等於對應於記憶體狀態C 之電阻(R1SET +R2SET )之總和,且分別對應於記憶體狀態A、D以及E之電阻(R1SET +R2RESET )、(R1RESET1 +R2SET )以及(R1RESET2 +R2SET )之總和不同。因此,在當前實施例中,電阻性記憶體1300之四種記憶體狀態可直接根據第一電阻Ra來區分。Please refer to FIG. 13 and FIG. 18. FIG. 18 is a diagram illustrating switching of a memory state of the resistive memory 1300 according to an embodiment of the present invention. The horizontal axis represents the value of the voltage V applied to the first bias layer 140, and the vertical axis represents the electrical resistance between the first interface 1212 and the second interface 1214. The first interface 1212 of the current embodiment has a more resistive state than the embodiment of FIG. In other words, the first interface 1212 of the current embodiment has three resistive states, while the first interface 1212 of the embodiment of FIG. 16 has two resistive states. The resistances corresponding to the three resistive states of the first interface 1212 of the current embodiment are R1 SET , R1 RESET1 , and R1 RESET2 , respectively . Therefore, the resistive memory 1300 of the current embodiment has five memory states, which are labeled as characters A, B, C, D, and E, respectively. The states A, B, and C of the current embodiment are the same as the states A, B, and C of the embodiment of FIG. 16, and the state D of the current embodiment corresponds to the sum of the fourth value V 4 and the resistance (R1 RESET1 + R2 SET ), And the state E of the current embodiment corresponds to the sum of the fifth value V 5 and the resistance (R1 RESET2 + R2 SET ). In the current embodiment, the values of R2 RESET , R1 RESET1 , and R1 RESET2 are the same, and the value of R1 RESET is equal to the value of R2 RESET . Thus, corresponding to the resistance memory state B is (R1 SET + R2 SET) the sum is equal to correspond to the sum of the memory state C of a resistor (R1 SET + R2 SET) of, and respectively corresponding to the memory state A, D and E The sum of the resistors (R1 SET + R2 RESET ), (R1 RESET1 + R2 SET ), and (R1 RESET2 + R2 SET ) is different. Therefore, in the current embodiment, the four memory states of the resistive memory 1300 can be directly distinguished according to the first resistance Ra.
請參看圖19,圖19為用於控制具有圖18所說明之關係的電阻性記憶體1300之操作的方法的流程圖。在步驟S1902中,對電阻性記憶體1300進行程式化。接著,在步驟S1904中,在將第一電壓施加至第一偏壓層140時,量測第一界面1212與第二界面1214之間的電阻作為第一電阻Ra。若第一電阻Ra等於(R1SET +R2SET ),則判定電阻性記憶體1300之狀態為第一狀態(亦即,記憶體狀態B或C)(步驟S1906)。若第一電阻Ra等於(R1RESET2 +R2SET ),則判定電阻性記憶體1300之狀態為第二狀態(亦即,記憶體狀態E)(步驟S1908)。若第一電阻Ra等於(R1RESET1 +R2SET ),則判定電阻性記憶體1300之狀態為第三狀態(亦即,記憶體狀態D)(步驟S1910)。若第一電阻Ra等於(R1SET +R2RESET ),則判定電阻性記憶體1300之狀態為第四狀態(亦即,記憶體狀態A)(步驟S1912)。Referring to FIG. 19, FIG. 19 is a flow chart of a method for controlling the operation of the resistive memory 1300 having the relationship illustrated in FIG. In step S1902, the resistive memory 1300 is programmed. Next, in step S1904, when the first voltage is applied to the first bias layer 140, the resistance between the first interface 1212 and the second interface 1214 is measured as the first resistance Ra. If the first resistance Ra is equal to (R1 SET + R2 SET ), it is determined that the state of the resistive memory 1300 is the first state (that is, the memory state B or C) (step S1906). If the first resistance Ra is equal to (R1 RESET2 + R2 SET ), it is determined that the state of the resistive memory 1300 is the second state (that is, the memory state E) (step S1908). If the first resistance Ra is equal to (R1 RESET1 + R2 SET ), it is determined that the state of the resistive memory 1300 is the third state (that is, the memory state D) (step S1910). If the first resistance Ra is equal to (R1 SET + R2 RESET ), it is determined that the state of the resistive memory 1300 is the fourth state (that is, the memory state A) (step S1912).
請參看圖13以及圖20。圖20為說明根據本發明之實施例之電阻性記憶體1300的記憶體狀態的切換的圖式。水平軸表示施加至第一偏壓層140之電壓V之值,且垂直軸表示第一界面1212與第二界面1214之間的電阻。與圖18之實施例相比,當前實施例之第二界面1214多一種電阻性 狀態。換言之,當前實施例之第二界面1214具有三種電阻性狀態,而圖18之實施例之第二界面1214具有兩種電阻性狀態。對應於當前實施例之第一界面1212之三種電阻性狀態的電阻分別為R1SET 、R1RESET1 以及R1RESET2 。對應於當前實施例之第二界面1214之三種電阻性狀態的電阻分別為R2SET 、R2RESET1 以及R2RESET2 。當前實施例之電阻性記憶體1300具有六種記憶體狀態,所述六種記憶體狀態分別標記為字元A、B、C、D、E以及F。Please refer to FIG. 13 and FIG. FIG. 20 is a diagram illustrating switching of a memory state of the resistive memory 1300 according to an embodiment of the present invention. The horizontal axis represents the value of the voltage V applied to the first bias layer 140, and the vertical axis represents the electrical resistance between the first interface 1212 and the second interface 1214. The second interface 1214 of the current embodiment has a more resistive state than the embodiment of FIG. In other words, the second interface 1214 of the current embodiment has three resistive states, while the second interface 1214 of the embodiment of FIG. 18 has two resistive states. The resistances corresponding to the three resistive states of the first interface 1212 of the current embodiment are R1 SET , R1 RESET1 , and R1 RESET2 , respectively . The resistances corresponding to the three resistive states of the second interface 1214 of the current embodiment are R2 SET , R2 RESET1 , and R2 RESET2 , respectively . The resistive memory 1300 of the current embodiment has six memory states, which are labeled as characters A, B, C, D, E, and F, respectively.
請參看圖21,圖21為用於控制具有圖20所說明之關係的電阻性記憶體1300之操作的方法的流程圖。在步驟S2102中,對電阻性記憶體1300進行程式化。接著,在步驟S2104中,在將第一電壓施加至第一偏壓層140時,量測第一界面1212與第二界面1214之間的電阻作為第一電阻Ra。若第一電阻Ra等於(R1SET +R2SET ),則判定電阻性記憶體1300之狀態為第一狀態(亦即,記憶體狀態C或D)(步驟S2106)。若第一電阻Ra等於(R1SET +R2RESET1 ),則判定電阻性記憶體1300之狀態為第二狀態(亦即,記憶體狀態B)(步驟S2108)。若第一電阻Ra等於(R1RESET1 +R2SET ),則判定電阻性記憶體1300之狀態為第三狀態(亦即,記憶體狀態E)(步驟S2110)。Please refer to FIG. 21. FIG. 21 is a flow chart of a method for controlling the operation of the resistive memory 1300 having the relationship illustrated in FIG. In step S2102, the resistive memory 1300 is programmed. Next, in step S2104, when the first voltage is applied to the first bias layer 140, the resistance between the first interface 1212 and the second interface 1214 is measured as the first resistance Ra. If the first resistance Ra is equal to (R1 SET + R2 SET ), it is determined that the state of the resistive memory 1300 is the first state (that is, the memory state C or D) (step S2106). If the first resistance Ra is equal to (R1 SET + R2 RESET1 ), it is determined that the state of the resistive memory 1300 is the second state (that is, the memory state B) (step S2108). If the first resistance Ra is equal to (R1 RESET1 + R2 SET ), it is determined that the state of the resistive memory 1300 is the third state (that is, the memory state E) (step S2110).
在當前實施例中,預定值等於(R1SET +R2SET )、(R1SET +R2RESET1 )或(R1RESET1 +R2SET )。若第一電阻Ra不等於預定值,則將第二電壓Vp施加至第一偏壓層140(步驟S2112)。在步驟S2114中,再次量測第一界面1212與第 二界面1214之間的電阻。步驟S2114中所量測之電阻被視為第二電阻Rb。若第二電阻Rb等於第一電阻Ra,則意謂電阻性記憶體1300之狀態在第二電壓Vp之施加後未改變,以使得可判定電阻性記憶體1300之狀態為第四狀態(亦即,記憶體狀態F)(步驟S2116)。若第二電阻Rb不等於第一電阻Ra,則意謂電阻性記憶體1300之狀態在第二電壓Vp之施加後改變,以使得可判定電阻性記憶體1300之狀態為第五狀態(亦即,記憶體狀態A)(步驟S2120)。因為若第二電阻Rb不等於第一電阻Ra,則電阻性記憶體1300之狀態可在步驟S2114中改變,所以在步驟S2118中,將電阻性記憶體1300再程式化至第五狀態(亦即,記憶體狀態A)。In the current embodiment, the predetermined value is equal to (R1 SET + R2 SET ), (R1 SET + R2 RESET1 ), or (R1 RESET1 + R2 SET ). If the first resistance Ra is not equal to the predetermined value, the second voltage Vp is applied to the first bias layer 140 (step S2112). In step S2114, the resistance between the first interface 1212 and the second interface 1214 is measured again. The resistance measured in step S2114 is regarded as the second resistance Rb. If the second resistor Rb is equal to the first resistor Ra, it means that the state of the resistive memory 1300 is not changed after the application of the second voltage Vp, so that the state of the resistive memory 1300 can be determined to be the fourth state (ie, , memory state F) (step S2116). If the second resistor Rb is not equal to the first resistor Ra, it means that the state of the resistive memory 1300 is changed after the application of the second voltage Vp, so that the state of the resistive memory 1300 can be determined to be the fifth state (ie, , memory state A) (step S2120). Because if the second resistor Rb is not equal to the first resistor Ra, the state of the resistive memory 1300 can be changed in step S2114, so in step S2118, the resistive memory 1300 is reprogrammed to the fifth state (ie, , memory state A).
根據圖4A至圖11以及圖14A至圖21之實施例,可總結出電阻性記憶體之可區分記憶體狀態之總數至少為(N1+N2-1),其中N1為第一記憶體層之電阻性狀態之數目,且N2為第二記憶體層之電阻性狀態之數目。According to the embodiments of FIG. 4A to FIG. 11 and FIG. 14A to FIG. 21, it can be concluded that the total number of distinguishable memory states of the resistive memory is at least (N1+N2-1), wherein N1 is the resistance of the first memory layer. The number of sexual states, and N2 is the number of resistive states of the second memory layer.
在本發明之實施例中,電阻性記憶體具有兩個記憶體層,其中之每一者能夠儲存資料。因此,可由電阻性記憶體儲存之總資料量增大。此外,因為總資料量增大,所以電阻性記憶體之每一儲存單位(例如,十億位元組)之成本可降低。In an embodiment of the invention, the resistive memory has two memory layers, each of which is capable of storing data. Therefore, the total amount of data that can be stored by the resistive memory is increased. In addition, since the total amount of data increases, the cost per storage unit (for example, a billion bytes) of the resistive memory can be reduced.
此外,CBRAM(導電橋接RAM)類型之上述電阻性記憶體200或300或TMO(過渡金屬氧化物)類型之上述電阻性記憶體1200或1300可用作建構電阻性記憶體陣列 之記憶體單元,其中每一記憶體單元可被視為兩個電阻性記憶體胞元之堆疊。Further, the above-described resistive memory 200 or 300 of the CBRAM (conductive bridge RAM) type or the above-mentioned resistive memory 1200 or 1300 of the TMO (transition metal oxide) type can be used as the construction of the resistive memory array. A memory unit in which each memory unit can be viewed as a stack of two resistive memory cells.
圖22為根據本發明之實施例之電阻性記憶體陣列的結構圖。Figure 22 is a structural diagram of a resistive memory array in accordance with an embodiment of the present invention.
參看圖22,電阻性記憶體陣列包含配置成列及行之多個電阻性記憶體單元2202、多條字元線(WL)以及多條位元線(BL)。每一電阻性記憶體單元2202包含第一記憶體胞元2204以及第二記憶體胞元2206,第二記憶體胞元2206安置於第一記憶體胞元2204之下且與其串聯電連接。每一字元線(WL)耦接至一列電阻性記憶體單元2202之第一記憶體胞元2204。每一位元線(BL)耦接至一行電阻性記憶體單元2202之第二記憶體胞元2206。此種陣列設計可被稱為2D交叉點陣列。Referring to FIG. 22, the resistive memory array includes a plurality of resistive memory cells 2202 arranged in columns and rows, a plurality of word lines (WL), and a plurality of bit lines (BL). Each resistive memory unit 2202 includes a first memory cell 2204 and a second memory cell 2206, the second memory cell 2206 being disposed under the first memory cell 2204 and electrically coupled in series therewith. Each word line (WL) is coupled to a first memory cell 2204 of a column of resistive memory cells 2202. Each bit line (BL) is coupled to a second memory cell 2206 of a row of resistive memory cells 2202. Such an array design can be referred to as a 2D cross point array.
參看圖22以及圖2至圖3,電阻性記憶體單元2202可為上述電阻性記憶體200或300,其中第一固態電解質210為第一記憶體胞元2204之一部分,且第二固態電解質230為第二記憶體胞元2206之一部分。Referring to FIG. 22 and FIG. 2 to FIG. 3, the resistive memory unit 2202 may be the above-described resistive memory 200 or 300, wherein the first solid electrolyte 210 is part of the first memory cell 2204, and the second solid electrolyte 230 Is part of the second memory cell 2206.
參看圖22以及圖12至圖13,電阻性記憶體單元2202可或者為上述電阻性記憶體1200或1300,其中第一界面1212為第一記憶體胞元2204之一部分,且第二界面1214為第二記憶體胞元2206之一部分。Referring to FIG. 22 and FIG. 12 to FIG. 13, the resistive memory unit 2202 can be either the resistive memory 1200 or 1300, wherein the first interface 1212 is part of the first memory cell 2204, and the second interface 1214 is A portion of the second memory cell 2206.
當電阻性記憶體單元2202為上述電阻性記憶體200或300時,可藉由以下步驟來對電阻性記憶體陣列進行程式化。藉由選擇對應字元線以及位元線來選擇待程式化之 電阻性記憶體單元。接著,根據圖4C或圖6C所說明之程式化路徑之一而將所選擇之電阻性記憶體單元程式化為處於狀態A、狀態B或C以及狀態D之一。在此狀況下,可使用所有狀態A、B(或C)以及D,因為在每一種狀態下,第一記憶體胞元2204以及第二記憶體胞元2206不同時處於其低電阻(RSET )狀態,以使得可在如圖22所說明之2D交叉點陣列中防止潛洩電流(sneaking current)。When the resistive memory cell 2202 is the resistive memory 200 or 300 described above, the resistive memory array can be programmed by the following steps. The resistive memory cell to be programmed is selected by selecting a corresponding word line and a bit line. Next, the selected resistive memory cell is programmed to be in one of state A, state B or C, and state D according to one of the stylized paths illustrated in FIG. 4C or FIG. 6C. In this case, all states A, B (or C) and D can be used, because in each state, the first memory cell 2204 and the second memory cell 2206 are not at their low resistance at the same time (R SET The state is such that sneaking current can be prevented in the 2D cross point array as illustrated in FIG.
此後,在讀取操作中,可經由對應字元線以及位元線來選擇待讀取之電阻性記憶體單元2202且接著使用圖5或圖7所說明之演算法來判定其狀態。Thereafter, in the read operation, the resistive memory cell 2202 to be read can be selected via the corresponding word line and the bit line and then the algorithm described in FIG. 5 or FIG. 7 is used to determine its state.
當電阻性記憶體單元2202為上述TMO類型電阻性記憶體1200或1300時,可藉由以下步驟來對電阻性記憶體陣列進行程式化。經由對應字元線以及位元線來選擇待程式化之電阻性記憶體單元。接著,藉由圖14E或圖16所說明之程式化路徑來將所選擇之電阻性記憶體單元程式化為處於狀態A以及狀態D的其中一種。在此狀況下,無法使用狀態B或C,此是因為第一記憶體胞元2204以及第二記憶體胞元2206在狀態B或C下同時處於其低電阻(RSET )狀態,以致發生了大的潛洩電流。因此,讀取演算法不同於圖15或圖17所說明之演算法。When the resistive memory cell 2202 is the TMO type resistive memory 1200 or 1300 described above, the resistive memory array can be programmed by the following steps. The resistive memory cells to be programmed are selected via corresponding word lines and bit lines. Next, the selected resistive memory cell is programmed to be in one of state A and state D by the stylized path illustrated in FIG. 14E or FIG. In this case, state B or C cannot be used because the first memory cell 2204 and the second memory cell 2206 are simultaneously in their low resistance (R SET ) state under state B or C, so that Large snorkeling current. Therefore, the read algorithm is different from the algorithm illustrated in FIG. 15 or FIG.
將電阻性記憶體單元2202為上述電阻性記憶體1300且具有圖14A至圖14E所說明之關係的電阻性記憶體陣列的讀取演算法作為實例,此實例相比圖15所說明之實例缺少某些步驟,此是因為在程式化時,未使用狀態B以及狀 態C。A reading algorithm of the resistive memory cell 220 having the resistive memory cell 220 as the resistive memory 1300 and having the relationship illustrated in FIGS. 14A to 14E is taken as an example, and this example is absent compared to the example illustrated in FIG. Some steps, this is because the state B is not used when stylized State C.
參看圖23、圖13以及圖14E,在步驟S2302中,將電阻性記憶體單元1300程式化為狀態A以及狀態D之一。在步驟S2308中,將如圖14E所示之讀取電壓Vp施加至第一偏壓層140。在下一步驟S2310中,量測第一界面1212與第二界面1214之間的電阻且將所述電阻視為讀取電阻Rb。若Rb等於Ra(=R1RESET +R2SET 或R1SET +R2RESET ,亦見於圖15中),則意謂電阻性記憶體單元1300之狀態在讀取電壓Vp之施加後未改變,以使得可將電阻性記憶體單元1300之狀態判定為狀態D(步驟S2312)。若Rb不等於Ra,則意謂電阻性記憶體單元1300之狀態在讀取電壓Vp之施加後改變,以使得可將電阻性記憶體單元1300之狀態判定為狀態A(步驟S2316)。因為若Rb不等於Ra,則電阻性記憶體單元1300之狀態可在步驟S2308中改變,所以在步驟S2314中,將電阻性記憶體單元1300再程式化至狀態A。Referring to FIGS. 23, 13, and 14E, in step S2302, the resistive memory unit 1300 is programmed into one of the state A and the state D. In step S2308, the read voltage Vp as shown in FIG. 14E is applied to the first bias layer 140. In the next step S2310, the resistance between the first interface 1212 and the second interface 1214 is measured and the resistance is regarded as the read resistance Rb. If Rb is equal to Ra (=R1 RESET + R2 SET or R1 SET + R2 RESET , also seen in FIG. 15), it means that the state of the resistive memory cell 1300 is not changed after the application of the read voltage Vp, so that The state of the resistive memory cell 1300 is determined to be the state D (step S2312). If Rb is not equal to Ra, it means that the state of the resistive memory cell 1300 is changed after the application of the read voltage Vp, so that the state of the resistive memory cell 1300 can be determined as the state A (step S2316). Since the state of the resistive memory cell 1300 can be changed in step S2308 if Rb is not equal to Ra, the resistive memory cell 1300 is reprogrammed to state A in step S2314.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧電阻性記憶體100‧‧‧Resistive memory
110‧‧‧第一記憶體層110‧‧‧First memory layer
120‧‧‧介質層120‧‧‧ dielectric layer
130‧‧‧第二記憶體層130‧‧‧Second memory layer
140‧‧‧第一偏壓層140‧‧‧First bias layer
150‧‧‧第二偏壓層150‧‧‧Second bias layer
200‧‧‧電阻性記憶體200‧‧‧Resistive memory
210‧‧‧第一記憶體層/第一固態電解質210‧‧‧First memory layer/first solid electrolyte
220‧‧‧介質層/可氧化電極220‧‧‧Medium layer / oxidizable electrode
230‧‧‧第二記憶體層/第二固態電解質230‧‧‧Second memory layer/second solid electrolyte
240‧‧‧構成層240‧‧‧Composed layer
242‧‧‧氧化矽間隔物242‧‧‧Oxide spacer
244‧‧‧鎢層244‧‧‧Tungsten layer
250‧‧‧氮化鈦層250‧‧‧Titanium nitride layer
260‧‧‧內金屬介電質層260‧‧‧Metal dielectric layer
270‧‧‧基板270‧‧‧Substrate
300‧‧‧電阻性記憶體300‧‧‧Resistive memory
1200‧‧‧電阻性記憶體1200‧‧‧Resistive memory
1210‧‧‧介質層/金屬氧化物層1210‧‧‧Medium/metal oxide layer
1212‧‧‧第一界面/第一記憶體層1212‧‧‧First interface/first memory layer
1214‧‧‧第二界面/第二記憶體層1214‧‧‧Second interface/second memory layer
1220‧‧‧第一阻障層1220‧‧‧First barrier layer
1230‧‧‧第二阻障層1230‧‧‧second barrier layer
1240‧‧‧氧化矽間隔1240‧‧‧Oxide interval
1250‧‧‧第一電極1250‧‧‧First electrode
1260‧‧‧第二電極1260‧‧‧second electrode
1270‧‧‧內金屬介電質層1270‧‧‧Metal dielectric layer
1280‧‧‧基板1280‧‧‧Substrate
1300‧‧‧電阻性記憶體/電阻性記憶體單元1300‧‧‧Resistive memory/resistive memory unit
2202‧‧‧電阻性記憶體單元2202‧‧‧Resistive memory unit
2204‧‧‧第一記憶體胞元2204‧‧‧First memory cell
2206‧‧‧第二記憶體胞元2206‧‧‧Second memory cell
圖1至圖3為本發明之不同實施例之電阻性記憶體的 結構圖。1 to 3 show the ohmic memory of different embodiments of the present invention. Structure diagram.
圖4A為說明圖3所示之電阻性記憶體之第一固態電解質的電壓V與電阻的關係的圖式。4A is a view for explaining a relationship between a voltage V and a resistance of a first solid electrolyte of the resistive memory shown in FIG. 3.
圖4B為說明圖3所示之電阻性記憶體之第二固態電解質的電壓V與電阻的關係的圖式。4B is a view for explaining a relationship between a voltage V and a resistance of a second solid electrolyte of the resistive memory shown in FIG. 3.
圖4C為說明圖3所示之電阻性記憶體之第一固態電解質以及第二固態電解質的電壓V與電阻的關係的圖式。4C is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte and the second solid electrolyte of the resistive memory shown in FIG. 3.
圖5為用於控制具有圖4A至圖4C所說明之關係的電阻性記憶體之操作的方法的流程圖。Figure 5 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in Figures 4A-4C.
圖6A為說明本發明之另一實施例中之第一固態電解質的電壓V與電阻的關係的圖式。Fig. 6A is a view for explaining a relationship between a voltage V and a resistance of a first solid electrolyte in another embodiment of the present invention.
圖6B為說明與圖6A相同之實施例中之第二固態電解質的電壓V與電阻的關係的圖式。Fig. 6B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte in the same embodiment as Fig. 6A.
圖6C為說明與圖6A相同之實施例中之第一固態電解質以及第二固態電解質的電壓V與電阻的關係的圖式。Fig. 6C is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte and the second solid electrolyte in the same embodiment as Fig. 6A.
圖7為用於控制具有圖6A至圖6C所說明之關係的電阻性記憶體之操作的方法的流程圖。Figure 7 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in Figures 6A-6C.
圖8A為說明本發明之另一實施例中之第一固態電解質的電壓V與電阻的關係的圖式。Fig. 8A is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte in another embodiment of the present invention.
圖8B為說明與圖8A相同之實施例中之第二固態電解質的電壓V與電阻的關係的圖式。Fig. 8B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte in the same embodiment as Fig. 8A.
圖8C為說明與圖8A相同之實施例中之第一固態電解質以及第二固態電解質的電壓V與電阻的關係的圖式。Fig. 8C is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte and the second solid electrolyte in the same embodiment as Fig. 8A.
圖9為用於控制具有圖8A至圖8C所說明之關係的電 阻性記憶體之操作的方法的流程圖。Figure 9 is a diagram for controlling the electric power having the relationship illustrated in Figures 8A to 8C. A flow chart of a method of operation of a resistive memory.
圖10A為說明本發明之另一實施例中之第一固態電解質的電壓V與電阻的關係的圖式。Fig. 10A is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte in another embodiment of the present invention.
圖10B為說明與圖10A相同之實施例中之第二固態電解質的電壓V與電阻的關係的圖式。Fig. 10B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte in the same embodiment as Fig. 10A.
圖10C為說明與圖10A相同之實施例中之第一固態電解質以及第二固態電解質的電壓V與電阻的關係的圖式。Fig. 10C is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte and the second solid electrolyte in the same embodiment as Fig. 10A.
圖11為用於控制具有圖10A至圖10C所說明之關係的電阻性記憶體之操作的方法的流程圖。Figure 11 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in Figures 10A through 10C.
圖12至圖13為根據本發明之實施例之電阻性記憶體的結構圖。12 to 13 are structural views of a resistive memory according to an embodiment of the present invention.
圖14A為說明根據本發明之實施例之第一界面的電壓V與電阻的關係的圖式。Figure 14A is a diagram illustrating the relationship between voltage V and resistance of a first interface in accordance with an embodiment of the present invention.
圖14B為說明與圖14A相同之實施例中之第二界面的電壓V與電阻的關係的圖式。Fig. 14B is a view for explaining the relationship between the voltage V and the resistance of the second interface in the same embodiment as Fig. 14A.
圖14C為說明在與圖14A相同之實施例中在電壓V自第四值V4 下拉至第一值V1 時第一界面與第二界面之間的電壓V與電阻的關係的圖式。FIG 14C is a drawing illustrating the relationship between the value of the fourth embodiment from V 4 is pulled down to a first voltage value V is V. 1 between the first interface and the second interface voltage V and the resistor 14A in the same embodiment of FIG.
圖14D為說明在與圖14A相同之實施例中在電壓V自第一值V1 上拉至第四值V4 時第一界面與第二界面之間的電壓V與電阻的關係的圖式。FIG 14D is a drawing illustrating the relationship of the same embodiment of FIG. 14A to the voltage V and the resistance value between the fourth V 4 first interface and the second interface from the first voltage value V is V. 1 .
圖14E為說明與圖14A相同之實施例中之電阻性記憶體的記憶體狀態的切換的圖式。Fig. 14E is a view for explaining switching of the state of the memory of the resistive memory in the same embodiment as Fig. 14A.
圖15為用於控制具有圖14A至圖14E所說明之關係 的電阻性記憶體之操作的方法的流程圖。Figure 15 is a diagram for controlling the relationship illustrated in Figures 14A through 14E. A flow chart of a method of operation of a resistive memory.
圖16為說明根據本發明之實施例之電阻性記憶體的記憶體狀態的切換的圖式。Fig. 16 is a view for explaining switching of a memory state of a resistive memory according to an embodiment of the present invention.
圖17為用於控制具有圖16所說明之關係的電阻性記憶體之操作的方法的流程圖。17 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in FIG.
圖18為說明根據本發明之實施例之電阻性記憶體的記憶體狀態的切換的圖式。Fig. 18 is a diagram for explaining switching of a memory state of a resistive memory according to an embodiment of the present invention.
圖19為用於控制具有圖18所說明之關係的電阻性記憶體之操作的方法的流程圖。19 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in FIG.
圖20為說明根據本發明之實施例之電阻性記憶體的記憶體狀態的切換的圖式。Figure 20 is a diagram for explaining switching of a memory state of a resistive memory according to an embodiment of the present invention.
圖21為用於控制具有圖20所說明之關係的電阻性記憶體之操作的方法的流程圖。21 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in FIG.
圖22為根據本發明之實施例之電阻性記憶體陣列的結構圖。Figure 22 is a structural diagram of a resistive memory array in accordance with an embodiment of the present invention.
圖23為用於控制電阻性記憶體陣列之操作之方法的流程圖,所述電阻性記憶體陣列包含圖12或圖13所說明之多個電阻性記憶體單元且具有圖22所說明之陣列結構。23 is a flow diagram of a method for controlling operation of a resistive memory array comprising a plurality of resistive memory cells illustrated in FIG. 12 or FIG. 13 and having the array illustrated in FIG. structure.
100‧‧‧電阻性記憶體100‧‧‧Resistive memory
110‧‧‧第一記憶體層110‧‧‧First memory layer
120‧‧‧介質層120‧‧‧ dielectric layer
130‧‧‧第二記憶體層130‧‧‧Second memory layer
140‧‧‧第一偏壓層140‧‧‧First bias layer
150‧‧‧第二偏壓層150‧‧‧Second bias layer
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TW200947678A (en) * | 2008-05-13 | 2009-11-16 | Macronix Int Co Ltd | Phase change device having two or more substantial amorphous regions in high resistance state |
TW201019469A (en) * | 2008-11-03 | 2010-05-16 | Ind Tech Res Inst | Resistive memory array |
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TW200915539A (en) * | 2007-06-14 | 2009-04-01 | Micron Technology Inc | Circuit, biasing scheme and fabrication method for diode accessed cross-point resistive memory array |
TW200947678A (en) * | 2008-05-13 | 2009-11-16 | Macronix Int Co Ltd | Phase change device having two or more substantial amorphous regions in high resistance state |
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