TWI509788B - Resistive memory array and method for controlling operations of the same - Google Patents

Description

Resistive memory array and method for controlling operation of a resistive memory array

The present invention relates to a resistive memory and a method for controlling the operation of a resistive memory, and more particularly to a resistive memory having two memory layers for storing data in a resistive memory and using A method of controlling the operation of the resistive memory. The present invention also relates to a resistive memory array based on the above-described resistive memory and a method for controlling the operation of the resistive memory array.

With the development of communication technologies and the popularity of the Internet, the demand for communication and processing of information on audio-visual data transmission, especially for large-capacity and fast transmission speeds, is growing. On the other hand, in the case of global competition, the work environment is not limited to the office, but can be anywhere in the world at any time, and requires a lot of information to support this action and decision. Therefore, for portable digital devices including mobile platforms (such as a notebook computer (NB), a personal digital assistant (PDA), an electronic book (e-book), a mobile phone, and The demand for digital still cameras (DSCs) is growing significantly. Accordingly, the requirements for accessing the above digital products via storage devices have also increased significantly.

Since 1990, semiconductor storage memory has been developed, which represents a new technology for storage media. In order to meet the growing demand for the storage or transmission of memory and large amounts of data, the development of new memory devices is extremely important and valuable. One of the new memory devices is resistive memory Body, resistive memory stores data by adjusting the resistance of its memory layer. Because conventional resistive memories have a single memory layer for storing data, the amount of data that can be stored is extremely limited.

Accordingly, it is an object of embodiments of the present invention to provide a method for controlling the operation of a resistive memory. The resistive memory has a first memory layer, a second memory layer, and a dielectric layer. The dielectric layer is formed between the first memory layer and the second memory layer. The method includes at least the following steps: (a) measuring a resistance between the first memory layer and the second memory layer, and determining which of the first state, the second state, and the third state based on the measured resistance One is the state of the resistive memory.

Another object of embodiments of the present invention is to provide a resistive memory. The resistive memory has a first solid electrolyte, a second solid electrolyte, and an oxidizable electrode. An oxidizable electrode is formed between the first solid electrolyte and the second solid electrolyte. The first solid electrolyte and the second solid electrolyte are made of a transition metal oxide or a material containing at least one chalcogen element.

Another object of embodiments of the present invention is to provide a resistive memory. The resistive memory has a first barrier layer, a second barrier layer, and a metal oxide layer. A metal oxide layer is formed between the first barrier layer and the second barrier layer. A first active region is disposed between the first barrier layer and the metal oxide layer, and a second active region is disposed between the second barrier layer and the metal oxide layer.

Another object of embodiments of the present invention is to provide a memory device. The memory device includes a first memory layer, a second memory layer, and a mediator Quality layer. The first memory layer has M resistive states, and the second memory layer has N resistive states. M is greater than or equal to 3. The dielectric layer is formed between the first memory layer and the second memory layer. At least (M+N-1) resistive states of the memory state can be distinguished based on the resistance between the first memory layer and the second memory layer.

In an embodiment of the invention, the step (a) includes measuring the resistance as the first resistance by applying the first voltage to the resistive memory; determining the state of the resistive memory when the first resistance is equal to the predetermined value a first state; when the first resistance is different from the predetermined value, the resistance is measured as a second resistance by applying a second voltage to the resistive memory; and the resistivity is determined when the second resistance is equal to the first resistance The state of the memory is the second state, or when the second resistance is not equal to the first resistance, it is determined that the state of the resistive memory is the third state.

In an embodiment of the invention, the method further includes reprogramming the resistive memory to be in the third state when the state of the resistive memory is determined to be the third state.

In an embodiment of the invention, the resistive memory has two memory layers, each of which is capable of storing data. Therefore, the total amount of data that can be stored by the resistive memory is increased.

Another object of embodiments of the present invention is to provide a resistive memory array including a plurality of resistive memory cells arranged in columns and rows, a plurality of word lines, and a plurality of bits line. Each of the resistive memory cells includes a first memory cell and a second memory cell, the second memory cell being disposed under the first memory cell and It is electrically connected in series. Each word line is coupled to a first memory cell of a column of resistive memory cells. Each bit line is coupled to a second memory cell of a row of resistive memory cells.

In an embodiment of the present invention, each of the resistive memory cells in the resistive memory array may be the above-mentioned resistive memory having a first solid electrolyte, a second solid electrolyte, and an oxidizable electrode, or the above A resistive memory of the first barrier layer, the second barrier layer, and the metal oxide layer.

In the case where each resistive memory cell has a first solid electrolyte, a second solid electrolyte, and an oxidizable electrode, the method for controlling the operation of the resistive memory array includes: (a) via word lines and bit elements a line to select a resistive memory cell to be operated; and (b) measuring a resistance of the selected resistive memory cell and determining the first state, the second state, and the third state based on the measured resistance Which is the state of the selected memory unit.

In the case where each of the resistive memory cells has a first barrier layer, a second barrier layer, and a metal oxide layer, the method for controlling the operation of the resistive memory array includes: (a) resistive memory The body array is programmed such that in each resistive memory cell, the first memory cell and the second memory cell are not in their low resistance state at the same time; (b) via the word line and the bit line Selecting a resistive memory cell to be operated; and (c) measuring a resistance of the selected resistive memory cell and determining which of the first state and the second state is based on the measured resistance Select the state of the resistive memory cell.

The above and other objects, features, and advantages of the invention will be apparent from the description and appended claims.

The above description, as well as the following detailed description, are intended to be illustrative, and are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a structural diagram of a resistive memory 100 according to an embodiment of the present invention. The resistive memory 100 has a first memory layer 110, a dielectric layer 120, and a second memory layer 130. The first bias layer 140 is formed on the first memory layer 110, and the second memory layer 130 is formed on the second bias layer 150. In an embodiment of the invention, a voltage V is applied to the first bias layer 140 and the second bias layer 150 is grounded. However, the invention is not limited thereto. For example, in an embodiment of the invention, the voltage source is used to control and adjust the voltage gap between the first bias layer 140 and the second bias layer 150 when the second bias layer 150 is not grounded. The applied voltage V can be positive or negative.

When the voltage V changes, the resistances of the first memory layer 110 and the second memory layer 130 may change accordingly. Therefore, the data stored by the first memory layer 110 and the second memory layer 130 can be adjusted (ie, programmed or erased) by applying a voltage V.

Please refer to FIG. 2. FIG. 2 is a structural diagram of a resistive memory 200 according to an embodiment of the present invention. The resistive memory 200 also has a first memory layer 210, a dielectric layer 220, and a second memory layer 230. The dielectric layer 220 is formed between the first memory layer 210 and the second memory layer 230. Implemented here In the example, each of the first memory layer 210 and the second memory layer 230 is a solid electrolyte, and the dielectric layer 220 is an oxidizable electrode. The solid electrolytes 210 and 230 may be transition metal oxides or materials containing at least one chalcogen element. The oxidizable electrode 220 is made of a material selected from the group consisting of silver (Ag), copper (Cu), and zinc (Zn).

Please refer to FIG. 3. FIG. 3 is a structural diagram of a resistive memory 300 according to an embodiment of the present invention. Similar to the resistive memory 200, the resistive memory 300 also has a first solid electrolyte 210, an oxidizable electrode 220, and a second solid electrolyte 230. In addition, the resistive memory 300 further includes a constituent layer 240, a titanium nitride layer 250, an inter-metal dielectric (IMD) layer 260, and a substrate 270. The constituent layer 240 has two layers of yttrium oxide (SiO ₂ ) spacers 242 and one tungsten (W) layer 244. A tungsten layer 244 is formed between the two layers of yttrium oxide spacers 242, and a second solid electrolyte 230 is formed between the oxidizable electrode 220 and the constituent layer 240. Further, a titanium nitride layer 250 is formed between the constituent layer 240 and the inner metal dielectric layer 260, and an inner metal dielectric layer 260 is formed between the titanium nitride layer 250 and the substrate 270. In this embodiment, the first bias layer 140 is an electrode, and the constituent layer 240, the titanium nitride layer 250, the inner metal dielectric layer 260, and the substrate 270 can be regarded as the first bias as shown in FIG. Layer 150.

When the voltage V is applied to the first bias layer 140 of the resistive memory 300, the positive metal ions in the oxidizable electrode 220 are driven to the first solid electrolyte 210 or the second solid electrolyte 230. In detail, when the voltage V is a positive voltage, the positive metal ions in the oxidizable electrode 220 are driven to the second solid electrolyte 230. When the voltage V is a negative voltage, the electrode 220 can be oxidized The positive metal ions are driven to the first solid electrolyte 210. Since the positive metal ions in the oxidizable electrode 220 are driven, the electrical resistances of the first solid electrolyte 210 and the second solid electrolyte 230 are correspondingly changed. Therefore, the materials stored by the first solid electrolyte 210 and the second solid electrolyte 230 can be determined based on the electrical resistances of the first solid electrolyte 210 and the second solid electrolyte 230.

Please refer to FIG. 3 and FIG. 4A to FIG. 4C. 4A is a diagram illustrating the relationship between the voltage V of the first solid electrolyte 210 and the electric resistance. 4B is a diagram illustrating the relationship between the voltage V of the second solid electrolyte 230 and the electric resistance. 4C is a diagram illustrating the relationship between the voltage V and the resistance of the two solid electrolytes 210 and 230. The horizontal axis represents the value of the voltage V applied to the first bias layer 140. The vertical axis of Fig. 4A indicates the electric resistance of the first solid electrolyte 210. The vertical axis of Fig. 4B represents the electrical resistance of the second solid electrolyte 230. The vertical axis of FIG. 4C indicates the resistance of the first solid electrolyte 210 and the second solid electrolyte 230. 4A, when the voltage V down to a first value V _1, the resistance of the first solid electrolyte 210 to change from R1 _RESET R1 _SET. When the voltage is pulled up to the third value V ₃ , the resistance of the first solid electrolyte 210 changes from R1 _SET to R1 _RESET . As shown in FIG. 4B, when the voltage V is pulled down to the second value V ₂ , the resistance of the second solid electrolyte 230 is changed from R2 _SET to R2 _RESET . When the voltage is pulled up to the fourth value V ₄ , the resistance of the second solid electrolyte 230 is changed from R2 _RESET to R2 _SET . In other words, each of the first solid electrolyte 210 and the second solid electrolyte 230 has two memory states based on its resistance, so that the resistive memory 300 has four memory states. The current memory state of the resistive memory 300 can be determined based on the resistances of the first solid electrolyte 210 and the second solid electrolyte 230.

4C illustrates the sum of the electrical resistances of the first solid electrolyte 210 and the second solid electrolyte 230 when the value of the voltage V is adjusted. As shown in FIG. 4C, the four memory states of the resistive memory 300 are labeled as characters A, B, C, and D, respectively. The first memory state A corresponds to the sum of the first value V ₁ and the resistance (R1 _SET + R2 _RESET ), and the second memory state B corresponds to the sum of the second value V ₂ and the resistance (R1 _RESET + R2 _RESET ), The third memory state C corresponds to the sum of the third value V ₃ and the resistance (R1 _RESET + R2 _RESET ), and the fourth memory state D corresponds to the sum of the fourth value V ₄ and the resistance (R1 _RESET + R2 _SET ) . Since the sum of the resistances corresponding to the second memory state B and the third memory state C is equal (that is, equal to R1 _RESET + R2 _RESET ), it is difficult to distinguish the second memory state B from the third memory state C. However, according to the present invention, states B and C can also be distinguished from state A and state D.

Please refer to FIG. 5. FIG. 5 is a flow chart of a method for controlling the operation of the resistive memory 300 having the relationship illustrated in FIGS. 4A-4C. In step S502, the resistive memory 300 is programmed. Next, in step S504, when the first voltage is applied to the first bias layer 140, the resistance between the first memory layer 210 and the second memory layer 230 is measured to determine the current memory of the resistive memory 300. Body state. In this embodiment, the first voltage is greater than the second value V ₂ but less than the third value V ₃ such that the memory state of the resistive memory 300 will not change after the application of the first voltage. The resistance measured in step S504 is regarded as the first resistance Ra, and the predetermined value is equal to (R1 _RESET + R2 _RESET ). If the first resistance Ra is equal to the predetermined value, it is determined that the state of the resistive memory is the first state (that is, the memory state B or C) (step S506). If the first resistance Ra is not equal to the predetermined value, the second voltage Vp is applied to the first bias layer 140 (step S508). In this embodiment, the second voltage Vp is greater than the third value but less than a fourth value V ₃ V _4. In other words, the second voltage Vp is greater than the first voltage. In step S510, the resistance between the first memory layer 210 and the second memory layer 230 is measured again. The resistance measured in step S510 is regarded as the second resistance Rb. If the second resistor Rb is equal to the first resistor Ra, it means that the state of the resistive memory 300 is not changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the second state (ie, , memory state D) (step S512). If the second resistor Rb is not equal to the first resistor Ra, it means that the state of the resistive memory 300 is changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the third state (ie, , memory state A) (step S516). Because if the second resistor Rb is not equal to the first resistor Ra, the state of the resistive memory 300 can be changed in step S508, so in step S514, the resistive memory 300 is reprogrammed to the third state (ie, , memory state A).

Please refer to FIG. 3 and FIG. 6A to FIG. 6C. Fig. 6A is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte 210 in another embodiment of the present invention. Fig. 6B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte 230 in another embodiment of the present invention. Figure 6B is a diagram illustrating the relationship between voltage V and resistance of two solid electrolytes 210 and 230 in another embodiment of the present invention. The horizontal axis represents the value of the voltage V applied to the first bias layer 140. The vertical axis of Fig. 6A indicates the electric resistance of the first solid electrolyte 210. The vertical axis of Fig. 6B indicates the electric resistance of the second solid electrolyte 230. The vertical axis of FIG. 6C indicates the resistance of the first solid electrolyte 210 and the second solid electrolyte 230. In this embodiment, the value of R1 _SET is greater than the value of R2 _SET , and the value of R1 _RESET is equal to the value of R2 _RESET . Therefore, the sum of the resistances (R1 _RESET + R2 _RESET ) corresponding to the memory state B is equal to the sum of the resistances corresponding to the memory state C (R1 _RESET + R2 _RESET ), and corresponds to the resistance of the memory state A (R1 _SET) The sum of +R2 _RESET ) is different from the sum of the resistances (R1 _RESET + R2 _SET ) corresponding to the memory state D. Therefore, in this embodiment, the state of the resistive memory 300 can be determined directly from the first resistance Ra.

Please refer to FIG. 7. FIG. 7 is a flow chart of a method for controlling the operation of the resistive memory 300 having the relationship illustrated in FIGS. 6A-6C. In step S702, the resistive memory 300 is programmed. Next, in step S704, when the first voltage is applied to the first bias layer 140, the resistance between the first memory layer 210 and the second memory layer 230 is measured as the first resistance Ra. If the first resistance Ra is equal to (R1 _RESET + R2 _RESET ), it is determined that the state of the resistive memory 300 is the first state (that is, the memory state B or C) (step S706). If the first resistance Ra is equal to (R1 _RESET + R2 _SET ), it is determined that the state of the resistive memory 300 is the second state (that is, the memory state D) (step S708). If the first resistance Ra is equal to (R1 _SET + R2 _RESET ), it is determined that the state of the resistive memory 300 is the third state (that is, the memory state A) (step S710).

Please refer to FIG. 3 and FIG. 8A to FIG. 8C. Fig. 8A is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte 210 in another embodiment of the present invention. Fig. 8B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte 230 in the same embodiment as Fig. 8A. Fig. 8C is a view showing the relationship between the voltage V and the electric resistance of the two solid electrolytes 210 and 230 in the same embodiment as Fig. 8A. The horizontal axis represents the value of the voltage V applied to the first bias layer 140. The vertical axis of Fig. 8A indicates the electric resistance of the first solid electrolyte 210. The vertical axis of Fig. 8B indicates the electric resistance of the second solid electrolyte 230. The vertical axis of FIG. 8C represents the resistance of the first solid electrolyte 210 and the second solid electrolyte 230. As shown in FIG. 8A, when the voltage V down to a first value _{V. 1,} the first solid electrolyte 210, since the resistance R1 _RESET changed to R1 _SET. When the voltage is pulled up to the fourth value V ₄ , the resistance of the first solid electrolyte 210 changes from R1 _SET to R1 _RESET . As shown in FIG. 8B, when the voltage V is pulled down to the second value V ₂ , the resistance of the second solid electrolyte 230 is changed from R2 _SET to R2 _RESET . When the voltage is pulled up to the third value V ₃ , the resistance of the second solid electrolyte 230 is changed from R2 _RESET to R2 _SET .

FIG. 8C illustrates the sum of the resistances of the first solid electrolyte 210 and the second solid electrolyte 230 when the value of the voltage V is adjusted. As shown in FIG. 8C, the four memory states of the resistive memory 300 are labeled as characters A, B, C, and D, respectively. The first memory state A corresponds to the sum of the first value V ₁ and the resistance (R1 _SET + R2 _RESET ), and the second memory state B corresponds to the sum of the second value V ₂ and the resistance (R1 _RESET + R2 _RESET ), The third memory state C corresponds to the sum of the third value V ₃ and the resistance (R1 _SET + R2 _SET ), and the fourth memory state D corresponds to the sum of the fourth value V ₄ and the resistance (R1 _RESET + R2 _SET ) .

Please refer to FIG. 9, which is a flow chart of a method for controlling the operation of the resistive memory 300 having the relationship illustrated in FIGS. 8A-8C. In step S902, the resistive memory 300 is programmed. Next, in step S904, when the first voltage is applied to the first bias layer 140, the resistance between the first memory layer 210 and the second memory layer 230 is measured as the first resistance Ra. In this embodiment, the predetermined value is equal to (R1 _RESET + R2 _RESET ) or (R1 _SET + R2 _SET ). If the first resistance Ra is equal to (R1 _RESET + R2 _RESET ), it is determined that the state of the resistive memory is the first state (that is, the memory state B) (step S906). If the first resistance Ra is equal to (R1 _SET + R2 _SET ), it is determined that the state of the resistive memory is the second state (that is, the memory state C) (step S908). If the first resistance Ra is not equal to (R1 _RESET + R2 _RESET ) and is not equal to (R1 _SET + R2 _SET ), the second voltage Vp is applied to the first bias layer 140 (step S910). In step S912, the resistance between the first memory layer 210 and the second memory layer 230 is measured as the second resistor Rb. If the second resistor Rb is equal to the first resistor Ra, it means that the state of the resistive memory 300 is not changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the third state (ie, , memory state D) (step S914). If the second resistor Rb is not equal to the first resistor Ra, it means that the state of the resistive memory 300 has changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the fourth state (also That is, the memory state A) (step S918). Because if the second resistor Rb is not equal to the first resistor Ra, the state of the resistive memory 300 can be changed in step S910, so in step S916, the resistive memory 300 is reprogrammed to the fourth state (ie, , memory state A).

Please refer to FIG. 3 and FIG. 10A to FIG. 10C. Fig. 10A is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte 210 in another embodiment of the present invention. Fig. 10B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte 230 in the same embodiment as Fig. 10A. Fig. 10C is a view showing the relationship between the voltage V and the electric resistance of the two solid electrolytes 210 and 230 in the same embodiment as Fig. 10A. The horizontal axis represents the value of the voltage V applied to the first bias layer 140. The vertical axis of Fig. 10A indicates the electric resistance of the first solid electrolyte 210. The vertical axis of Fig. 10B indicates the electric resistance of the second solid electrolyte 230. The vertical axis of FIG. 10C represents the resistance of the first solid electrolyte 210 and the second solid electrolyte 230. As shown in FIG. 10A, when the voltage V is pulled down to the second value V ₂ , the resistance of the first solid electrolyte 210 is changed from R1 _RESET to R1 _SET . When the voltage is pulled up to the third value V ₃ , the resistance of the first solid electrolyte 210 changes from R1 _SET to R1 _RESET . As shown in FIG. 10B, when the voltage V down to a first value ₁ V, the resistance of the second solid electrolyte 230 from the R2 _SET is changed to R2 _RESET. When the voltage is pulled up to the fourth value V ₄ , the resistance of the second solid electrolyte 230 is changed from R2 _RESET to R2 _SET .

FIG. 10C illustrates the sum of the resistances of the first solid electrolyte 210 and the second solid electrolyte 230 when the value of the voltage V is adjusted. As shown in FIG. 10C, the four memory states of the resistive memory 300 are labeled as characters A, B, C, and D, respectively. The first memory state A corresponds to the sum of the first value V ₁ and the resistance (R1 _SET + R2 _RESET ), and the second memory state B corresponds to the sum of the second value V ₂ and the resistance (R1 _SET + R2 _SET ), The third memory state C corresponds to the sum of the third value V ₃ and the resistance (R1 _RESET + R2 _RESET ), and the fourth memory state D corresponds to the sum of the fourth value V ₄ and the resistance (R1 _RESET + R2 _SET ) .

Please refer to FIG. 11, which is a flow chart of a method for controlling the operation of the resistive memory 300 having the relationship illustrated in FIGS. 10A-10C. In step S1102, the resistive memory 300 is programmed. Next, in step S1104, when the first voltage is applied to the first bias layer 140, the resistance between the first memory layer 210 and the second memory layer 230 is measured as the first resistance Ra. In this embodiment, the predetermined value is equal to (R1 _RESET + R2 _RESET ) or (R1 _SET + R2 _SET ). If the first resistance Ra is equal to (R1 _RESET + R2 _RESET ), it is determined that the state of the resistive memory is the first state (that is, the memory state C) (step S1106). If the first resistance Ra is equal to (R1 _SET + R2 _SET ), it is determined that the state of the resistive memory is the second state (that is, the memory state B) (step S1108). If the first resistance Ra is not equal to (R1 _RESET + R2 _RESET ) and is not equal to (R1 _SET + R2 _SET ), the second voltage Vp is applied to the first bias layer 140 (step S1110). In step S1112, the resistance between the first memory layer 210 and the second memory layer 230 is measured as the second resistor Rb. If the second resistor Rb is equal to the first resistor Ra, it means that the state of the resistive memory 300 is not changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the third state (ie, , memory state D) (step S1114). If the second resistor Rb is not equal to the first resistor Ra, it means that the state of the resistive memory 300 has changed after the application of the second voltage Vp, so that the state of the resistive memory 300 can be determined to be the fourth state (also That is, the memory state A) (step S1118). Because if the second resistor Rb is not equal to the first resistor Ra, the state of the resistive memory 300 can be changed in step S910, so in step S1116, the resistive memory 300 is reprogrammed to the fourth state (ie, , memory state A).

Referring to FIG. 12, FIG. 12 is a structural diagram of a resistive memory 1200 according to an embodiment of the present invention. The resistive memory 1200 has a dielectric layer 1210, a first barrier layer 1220, and a second barrier layer 1230. The interface 1212 between the dielectric layer 1210 and the first barrier layer 1220 is considered to be the first memory layer of the resistive memory 1200, and the interface 1214 between the dielectric layer 1210 and the second barrier layer 1230 is considered The second memory layer of the resistive memory 1200. The data stored by the resistive memory 1200 can be determined based on the resistance of the first memory layer 1212 and the second memory layer 1214. In this embodiment, the first barrier layer 1220 and the second barrier layer 1230 are made of a material selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), and platinum ( Pt) and gold (Au); and the dielectric layer 1210 is a metal oxide layer made of a material selected from the group consisting of tungsten oxide, titanium oxide, nickel oxide, and oxidation. Aluminum, copper oxide, zirconium oxide, cerium oxide, and cerium oxide.

Referring to FIG. 13, FIG. 13 is a structural diagram of a resistive memory 1300 according to an embodiment of the present invention. The resistive memory 1300 also has a metal oxide layer 1210, a first barrier layer 1220, and a second barrier layer 1230. In addition, the resistive memory 1300 further includes two layers of yttrium oxide spacers 1240, a first electrode 1250, a second electrode 1260, an inner metal dielectric layer 1270, and a substrate 1280. The two-layer yttrium oxide spacer 1240 is in contact with the metal oxide layer 1210 and is formed between the first barrier layer 1220 and the second barrier layer 1230. The first electrode 1250 is formed on the first barrier layer 1220, and the second electrode 1260 is formed between the second barrier layer 1230 and the inner metal dielectric layer 1270. The inner metal dielectric layer 1270 is formed between the second electrode 1260 and the substrate 1280. In this embodiment, the first electrode 1250 and the first barrier layer 1220 are regarded as the first bias layer 140 of the resistive memory 1300, and the second barrier layer 1230, the second electrode 1260, and the inner metal dielectric The layer 1270 and the substrate 1280 are considered to be the second bias layer 150 of the resistive memory 1300.

When a voltage V is applied to the first bias layer 140 of the resistive memory 1300, the resistance of the first interface 1212 and the second interface 1214 may change accordingly. Please refer to FIG. 13 and FIGS. 14A to 14E. FIG. 14A is a diagram illustrating the relationship between the voltage V of the first interface 1212 and the resistance. FIG. 14B is a diagram illustrating the relationship between the voltage V of the second interface 1214 and the resistance. 14C is a diagram illustrating the relationship between the voltage V and the resistance between the first interface 1212 and the second interface 1214 when the voltage V is pulled down from the fourth value V ₄ to the first value V ₁ . FIG 14D is an explanatory pulled to a fourth voltage value V from the first value V ₁ V ₄ the first interface 1212 and the resistance relationship between the voltage V between the 1214 interface and the second type of FIG. FIG. 14E is a diagram for explaining switching of the memory state of the resistive memory 1300. The horizontal axis represents the value of the voltage V applied to the first bias layer 140. The vertical axis of Figure 14A represents the resistance of the first interface 1212. The vertical axis of Figure 14B represents the resistance of the second interface 1214. The vertical axis of Figures 14C-14E represents the electrical resistance between the first interface 1212 and the second interface 1214. 14A, when the voltage V down to a second value V _2, the first interface of the resistor 1212 to change from R1 _RESET R1 _SET. When the voltage is pulled up to the fourth value V ₄ , the resistance of the first interface 1212 changes from R1 _SET to R1 _RESET . As shown in FIG. 14B, when the voltage V down to a first value ₁ V, from the second interface of the resistor R2 _SET 1214 is changed to R2 _RESET. When pulled to the third voltage value V _3, the second interface of the resistor 1214 is changed to R2 _SET from R2 _RESET. In other words, each of the first interface 1212 and the second interface 1214 has two memory states based on its resistance such that the resistive memory 1300 has four memory states. The current memory state of the resistive memory 1300 can be determined based on the resistance of the first interface 1212 and the second interface 1214.

14C and 14E illustrate the sum of the resistances of the first interface 1212 and the second interface 1214 when the value of the voltage V is pulled down. During the process when the voltage V is pulled down from the fourth voltage V ₄ to the first voltage V ₁ , the resistance between the first interface 1212 and the second interface 1214 is changed from (R1 _RESET + R2 _SET ) to (R1 _SET + R2 _{SET )} And then change to (R1 _SET + R2 _RESET ). 14D and 14E illustrate the sum of the resistances of the first interface 1212 and the second interface 1214 when the value of the voltage V is pulled up. During the process when the voltage V is pulled from the first voltage V ₁ to the fourth voltage V ₄ , the resistance between the first interface 1212 and the second interface 1214 is changed from (R1 _SET + R2 _RESET ) to (R1 _SET + R2). _SET ) and then change to (R1 _RESET + R2 _SET ).

As shown in FIG. 14E, the four memory states of the resistive memory 1300 are labeled as characters A, B, C, and D, respectively. The first memory state A corresponds to the sum of the first value V ₁ and the resistance (R1 _SET + R2 _RESET ), and the second memory state B corresponds to the sum of the second value V ₂ and the resistance (R1 _SET + R2 _SET ), The third memory state C corresponds to the sum of the third value V ₃ and the resistance (R1 _SET + R2 _SET ), and the fourth memory state D corresponds to the sum of the fourth value V ₄ and the resistance (R1 _RESET + R2 _SET ) . Since the sum of the resistances corresponding to the second memory state B and the third memory state C is equal (that is, equal to R1 _SET + R2 _SET ), it is difficult to distinguish the second memory state B from the third memory state C. However, according to the present invention, states B and C can also be distinguished from state A and state D.

Please refer to FIG. 15, which is a flow chart of a method for controlling the operation of the resistive memory 1300 having the relationship illustrated in FIGS. 14A-14E. In step S1502, the resistive memory 1300 is programmed. Next, in step S1504, when a first voltage is applied to the first bias layer 140, the resistance between the first interface 1212 and the second memory layer 1214 is measured. In this embodiment, the first voltage is greater than the second value V ₂ but less than the third value V ₃ such that the memory state of the resistive memory 1300 will not be applied to the first bias layer 140 at the first voltage. Then change. The resistance measured in step S1504 is regarded as the first resistance Ra, and the predetermined value is equal to (R1 _SET + R2 _SET ). If the first resistance Ra is equal to the predetermined value, it is determined that the state of the resistive memory is the first state (that is, the memory state B or C) (step S1506). If the first resistance Ra is not equal to the predetermined value, the second voltage Vp is applied to the first bias layer 140 (step S1508). In this embodiment, the second voltage Vp is greater than the third value but less than a fourth value V ₃ V _4. In step S1510, the resistance between the first interface 1212 and the second interface 1214 is measured again. The resistance measured in step S1510 is regarded as the second resistance Rb. If the second resistor Rb is equal to the first resistor Ra, it means that the state of the resistive memory 1300 is not changed after the application of the second voltage Vp, so that the state of the resistive memory 1300 can be determined to be the second state (ie, , memory state D) (step S1512). If the second resistor Rb is not equal to the first resistor Ra, it means that the state of the resistive memory 1300 is changed after the application of the second voltage Vp, so that the state of the resistive memory 1300 can be determined to be the third state (ie, , memory state A) (step S1516). Because if the second resistor Rb is not equal to the first resistor Ra, the state of the resistive memory 1300 can be changed in step S1508, so in step S1514, the resistive memory 1300 is reprogrammed to the third state (ie, , memory state A).

Please refer to FIG. 13 and FIG. 16. FIG. 16 is a diagram illustrating switching of a memory state of the resistive memory 1300 according to an embodiment of the present invention. The horizontal axis represents the value of the voltage V applied to the first bias layer 140, and the vertical axis represents the electrical resistance between the first interface 1212 and the second interface 1214. In this embodiment, the value of R1 _RESET is less than the value of R2 _RESET , and the value of R1 _SET is equal to the value of R2 _SET . Thus, corresponding to the resistance memory state B is (R1 _SET + R2 _SET) the sum is equal to correspond to the sum of the memory state C of a resistor (R1 _SET + R2 _SET) of, and corresponds to a memory state resistance A of (R1 _SET The sum of +R2 _RESET ) is different from the sum of the resistances (R1 _RESET + R2 _SET ) corresponding to the memory state D. Therefore, in this embodiment, the state of the resistive memory 1300 can be directly determined based on the first resistance Ra.

Please refer to FIG. 17, which is a flow chart of a method for controlling the operation of the resistive memory 1300 having the relationship illustrated in FIG. In step S1702, the resistive memory 1300 is programmed. Next, in step S1704, when the first voltage is applied to the first bias layer 140, the resistance between the first interface 1212 and the second interface 1214 is measured as the first resistance Ra. If the first resistance Ra is equal to (R1 _SET + R2 _SET ), it is determined that the state of the resistive memory 1300 is the first state (that is, the memory state B or C) (step S1706). If the first resistance Ra is equal to (R1 _RESET + R2 _SET ), it is determined that the state of the resistive memory 1300 is the second state (that is, the memory state D) (step S1708). If the first resistance Ra is equal to (R1 _SET + R2 _RESET ), it is determined that the state of the resistive memory 1300 is the third state (that is, the memory state A) (step S1710).

Please refer to FIG. 13 and FIG. 18. FIG. 18 is a diagram illustrating switching of a memory state of the resistive memory 1300 according to an embodiment of the present invention. The horizontal axis represents the value of the voltage V applied to the first bias layer 140, and the vertical axis represents the electrical resistance between the first interface 1212 and the second interface 1214. The first interface 1212 of the current embodiment has a more resistive state than the embodiment of FIG. In other words, the first interface 1212 of the current embodiment has three resistive states, while the first interface 1212 of the embodiment of FIG. 16 has two resistive states. The resistances corresponding to the three resistive states of the first interface 1212 of the current embodiment are R1 _SET , R1 _{RESET1 ,} and R1 _{RESET2 , respectively} . Therefore, the resistive memory 1300 of the current embodiment has five memory states, which are labeled as characters A, B, C, D, and E, respectively. The states A, B, and C of the current embodiment are the same as the states A, B, and C of the embodiment of FIG. 16, and the state D of the current embodiment corresponds to the sum of the fourth value V ₄ and the resistance (R1 _RESET1 + R2 _SET ), And the state E of the current embodiment corresponds to the sum of the fifth value V ₅ and the resistance (R1 _RESET2 + R2 _SET ). In the current embodiment, the values of R2 _RESET , R1 _{RESET1 ,} and R1 _{RESET2 are} the same, and the value of R1 _RESET is equal to the value of R2 _RESET . Thus, corresponding to the resistance memory state B is (R1 _SET + R2 _SET) the sum is equal to correspond to the sum of the memory state C of a resistor (R1 _SET + R2 _SET) of, and respectively corresponding to the memory state A, D and E The sum of the resistors (R1 _SET + R2 _RESET ), (R1 _RESET1 + R2 _SET ), and (R1 _RESET2 + R2 _SET ) is different. Therefore, in the current embodiment, the four memory states of the resistive memory 1300 can be directly distinguished according to the first resistance Ra.

Referring to FIG. 19, FIG. 19 is a flow chart of a method for controlling the operation of the resistive memory 1300 having the relationship illustrated in FIG. In step S1902, the resistive memory 1300 is programmed. Next, in step S1904, when the first voltage is applied to the first bias layer 140, the resistance between the first interface 1212 and the second interface 1214 is measured as the first resistance Ra. If the first resistance Ra is equal to (R1 _SET + R2 _SET ), it is determined that the state of the resistive memory 1300 is the first state (that is, the memory state B or C) (step S1906). If the first resistance Ra is equal to (R1 _RESET2 + R2 _SET ), it is determined that the state of the resistive memory 1300 is the second state (that is, the memory state E) (step S1908). If the first resistance Ra is equal to (R1 _RESET1 + R2 _SET ), it is determined that the state of the resistive memory 1300 is the third state (that is, the memory state D) (step S1910). If the first resistance Ra is equal to (R1 _SET + R2 _RESET ), it is determined that the state of the resistive memory 1300 is the fourth state (that is, the memory state A) (step S1912).

Please refer to FIG. 13 and FIG. FIG. 20 is a diagram illustrating switching of a memory state of the resistive memory 1300 according to an embodiment of the present invention. The horizontal axis represents the value of the voltage V applied to the first bias layer 140, and the vertical axis represents the electrical resistance between the first interface 1212 and the second interface 1214. The second interface 1214 of the current embodiment has a more resistive state than the embodiment of FIG. In other words, the second interface 1214 of the current embodiment has three resistive states, while the second interface 1214 of the embodiment of FIG. 18 has two resistive states. The resistances corresponding to the three resistive states of the first interface 1212 of the current embodiment are R1 _SET , R1 _{RESET1 ,} and R1 _{RESET2 , respectively} . The resistances corresponding to the three resistive states of the second interface 1214 of the current embodiment are R2 _SET , R2 _{RESET1 ,} and R2 _{RESET2 , respectively} . The resistive memory 1300 of the current embodiment has six memory states, which are labeled as characters A, B, C, D, E, and F, respectively.

Please refer to FIG. 21. FIG. 21 is a flow chart of a method for controlling the operation of the resistive memory 1300 having the relationship illustrated in FIG. In step S2102, the resistive memory 1300 is programmed. Next, in step S2104, when the first voltage is applied to the first bias layer 140, the resistance between the first interface 1212 and the second interface 1214 is measured as the first resistance Ra. If the first resistance Ra is equal to (R1 _SET + R2 _SET ), it is determined that the state of the resistive memory 1300 is the first state (that is, the memory state C or D) (step S2106). If the first resistance Ra is equal to (R1 _SET + R2 _RESET1 ), it is determined that the state of the resistive memory 1300 is the second state (that is, the memory state B) (step S2108). If the first resistance Ra is equal to (R1 _RESET1 + R2 _SET ), it is determined that the state of the resistive memory 1300 is the third state (that is, the memory state E) (step S2110).

In the current embodiment, the predetermined value is equal to (R1 _SET + R2 _SET ), (R1 _SET + R2 _RESET1 ), or (R1 _RESET1 + R2 _SET ). If the first resistance Ra is not equal to the predetermined value, the second voltage Vp is applied to the first bias layer 140 (step S2112). In step S2114, the resistance between the first interface 1212 and the second interface 1214 is measured again. The resistance measured in step S2114 is regarded as the second resistance Rb. If the second resistor Rb is equal to the first resistor Ra, it means that the state of the resistive memory 1300 is not changed after the application of the second voltage Vp, so that the state of the resistive memory 1300 can be determined to be the fourth state (ie, , memory state F) (step S2116). If the second resistor Rb is not equal to the first resistor Ra, it means that the state of the resistive memory 1300 is changed after the application of the second voltage Vp, so that the state of the resistive memory 1300 can be determined to be the fifth state (ie, , memory state A) (step S2120). Because if the second resistor Rb is not equal to the first resistor Ra, the state of the resistive memory 1300 can be changed in step S2114, so in step S2118, the resistive memory 1300 is reprogrammed to the fifth state (ie, , memory state A).

According to the embodiments of FIG. 4A to FIG. 11 and FIG. 14A to FIG. 21, it can be concluded that the total number of distinguishable memory states of the resistive memory is at least (N1+N2-1), wherein N1 is the resistance of the first memory layer. The number of sexual states, and N2 is the number of resistive states of the second memory layer.

In an embodiment of the invention, the resistive memory has two memory layers, each of which is capable of storing data. Therefore, the total amount of data that can be stored by the resistive memory is increased. In addition, since the total amount of data increases, the cost per storage unit (for example, a billion bytes) of the resistive memory can be reduced.

Further, the above-described resistive memory 200 or 300 of the CBRAM (conductive bridge RAM) type or the above-mentioned resistive memory 1200 or 1300 of the TMO (transition metal oxide) type can be used as the construction of the resistive memory array. A memory unit in which each memory unit can be viewed as a stack of two resistive memory cells.

Figure 22 is a structural diagram of a resistive memory array in accordance with an embodiment of the present invention.

Referring to FIG. 22, the resistive memory array includes a plurality of resistive memory cells 2202 arranged in columns and rows, a plurality of word lines (WL), and a plurality of bit lines (BL). Each resistive memory unit 2202 includes a first memory cell 2204 and a second memory cell 2206, the second memory cell 2206 being disposed under the first memory cell 2204 and electrically coupled in series therewith. Each word line (WL) is coupled to a first memory cell 2204 of a column of resistive memory cells 2202. Each bit line (BL) is coupled to a second memory cell 2206 of a row of resistive memory cells 2202. Such an array design can be referred to as a 2D cross point array.

Referring to FIG. 22 and FIG. 2 to FIG. 3, the resistive memory unit 2202 may be the above-described resistive memory 200 or 300, wherein the first solid electrolyte 210 is part of the first memory cell 2204, and the second solid electrolyte 230 Is part of the second memory cell 2206.

Referring to FIG. 22 and FIG. 12 to FIG. 13, the resistive memory unit 2202 can be either the resistive memory 1200 or 1300, wherein the first interface 1212 is part of the first memory cell 2204, and the second interface 1214 is A portion of the second memory cell 2206.

When the resistive memory cell 2202 is the resistive memory 200 or 300 described above, the resistive memory array can be programmed by the following steps. The resistive memory cell to be programmed is selected by selecting a corresponding word line and a bit line. Next, the selected resistive memory cell is programmed to be in one of state A, state B or C, and state D according to one of the stylized paths illustrated in FIG. 4C or FIG. 6C. In this case, all states A, B (or C) and D can be used, because in each state, the first memory cell 2204 and the second memory cell 2206 are not at their low resistance at the same time (R _SET The state is such that sneaking current can be prevented in the 2D cross point array as illustrated in FIG.

Thereafter, in the read operation, the resistive memory cell 2202 to be read can be selected via the corresponding word line and the bit line and then the algorithm described in FIG. 5 or FIG. 7 is used to determine its state.

When the resistive memory cell 2202 is the TMO type resistive memory 1200 or 1300 described above, the resistive memory array can be programmed by the following steps. The resistive memory cells to be programmed are selected via corresponding word lines and bit lines. Next, the selected resistive memory cell is programmed to be in one of state A and state D by the stylized path illustrated in FIG. 14E or FIG. In this case, state B or C cannot be used because the first memory cell 2204 and the second memory cell 2206 are simultaneously in their low resistance (R _SET ) state under state B or C, so that Large snorkeling current. Therefore, the read algorithm is different from the algorithm illustrated in FIG. 15 or FIG.

A reading algorithm of the resistive memory cell 220 having the resistive memory cell 220 as the resistive memory 1300 and having the relationship illustrated in FIGS. 14A to 14E is taken as an example, and this example is absent compared to the example illustrated in FIG. Some steps, this is because the state B is not used when stylized State C.

Referring to FIGS. 23, 13, and 14E, in step S2302, the resistive memory unit 1300 is programmed into one of the state A and the state D. In step S2308, the read voltage Vp as shown in FIG. 14E is applied to the first bias layer 140. In the next step S2310, the resistance between the first interface 1212 and the second interface 1214 is measured and the resistance is regarded as the read resistance Rb. If Rb is equal to Ra (=R1 _RESET + R2 _SET or R1 _SET + R2 _RESET , also seen in FIG. 15), it means that the state of the resistive memory cell 1300 is not changed after the application of the read voltage Vp, so that The state of the resistive memory cell 1300 is determined to be the state D (step S2312). If Rb is not equal to Ra, it means that the state of the resistive memory cell 1300 is changed after the application of the read voltage Vp, so that the state of the resistive memory cell 1300 can be determined as the state A (step S2316). Since the state of the resistive memory cell 1300 can be changed in step S2308 if Rb is not equal to Ra, the resistive memory cell 1300 is reprogrammed to state A in step S2314.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Resistive memory

110‧‧‧First memory layer

120‧‧‧ dielectric layer

130‧‧‧Second memory layer

140‧‧‧First bias layer

150‧‧‧Second bias layer

200‧‧‧Resistive memory

210‧‧‧First memory layer/first solid electrolyte

220‧‧‧Medium layer / oxidizable electrode

230‧‧‧Second memory layer/second solid electrolyte

240‧‧‧Composed layer

242‧‧‧Oxide spacer

244‧‧‧Tungsten layer

250‧‧‧Titanium nitride layer

260‧‧‧Metal dielectric layer

270‧‧‧Substrate

300‧‧‧Resistive memory

1200‧‧‧Resistive memory

1210‧‧‧Medium/metal oxide layer

1212‧‧‧First interface/first memory layer

1214‧‧‧Second interface/second memory layer

1220‧‧‧First barrier layer

1230‧‧‧second barrier layer

1240‧‧‧Oxide interval

1250‧‧‧First electrode

1260‧‧‧second electrode

1270‧‧‧Metal dielectric layer

1280‧‧‧Substrate

1300‧‧‧Resistive memory/resistive memory unit

2202‧‧‧Resistive memory unit

2204‧‧‧First memory cell

2206‧‧‧Second memory cell

1 to 3 show the ohmic memory of different embodiments of the present invention. Structure diagram.

4A is a view for explaining a relationship between a voltage V and a resistance of a first solid electrolyte of the resistive memory shown in FIG. 3.

4B is a view for explaining a relationship between a voltage V and a resistance of a second solid electrolyte of the resistive memory shown in FIG. 3.

4C is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte and the second solid electrolyte of the resistive memory shown in FIG. 3.

Figure 5 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in Figures 4A-4C.

Fig. 6A is a view for explaining a relationship between a voltage V and a resistance of a first solid electrolyte in another embodiment of the present invention.

Fig. 6B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte in the same embodiment as Fig. 6A.

Fig. 6C is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte and the second solid electrolyte in the same embodiment as Fig. 6A.

Figure 7 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in Figures 6A-6C.

Fig. 8A is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte in another embodiment of the present invention.

Fig. 8B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte in the same embodiment as Fig. 8A.

Fig. 8C is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte and the second solid electrolyte in the same embodiment as Fig. 8A.

Figure 9 is a diagram for controlling the electric power having the relationship illustrated in Figures 8A to 8C. A flow chart of a method of operation of a resistive memory.

Fig. 10A is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte in another embodiment of the present invention.

Fig. 10B is a view for explaining the relationship between the voltage V and the electric resistance of the second solid electrolyte in the same embodiment as Fig. 10A.

Fig. 10C is a view for explaining the relationship between the voltage V and the electric resistance of the first solid electrolyte and the second solid electrolyte in the same embodiment as Fig. 10A.

Figure 11 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in Figures 10A through 10C.

12 to 13 are structural views of a resistive memory according to an embodiment of the present invention.

Figure 14A is a diagram illustrating the relationship between voltage V and resistance of a first interface in accordance with an embodiment of the present invention.

Fig. 14B is a view for explaining the relationship between the voltage V and the resistance of the second interface in the same embodiment as Fig. 14A.

FIG 14C is a drawing illustrating the relationship between the value of the fourth embodiment from V ₄ is pulled down to a first voltage value V is _{V. 1} between the first interface and the second interface voltage V and the resistor 14A in the same embodiment of FIG.

FIG 14D is a drawing illustrating the relationship of the same embodiment of FIG. 14A to the voltage V and the resistance value between the fourth V ₄ first interface and the second interface from the first voltage value V is _{V. 1} .

Fig. 14E is a view for explaining switching of the state of the memory of the resistive memory in the same embodiment as Fig. 14A.

Figure 15 is a diagram for controlling the relationship illustrated in Figures 14A through 14E. A flow chart of a method of operation of a resistive memory.

Fig. 16 is a view for explaining switching of a memory state of a resistive memory according to an embodiment of the present invention.

17 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in FIG.

Fig. 18 is a diagram for explaining switching of a memory state of a resistive memory according to an embodiment of the present invention.

19 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in FIG.

Figure 20 is a diagram for explaining switching of a memory state of a resistive memory according to an embodiment of the present invention.

21 is a flow chart of a method for controlling the operation of a resistive memory having the relationship illustrated in FIG.

Figure 22 is a structural diagram of a resistive memory array in accordance with an embodiment of the present invention.

23 is a flow diagram of a method for controlling operation of a resistive memory array comprising a plurality of resistive memory cells illustrated in FIG. 12 or FIG. 13 and having the array illustrated in FIG. structure.

100‧‧‧Resistive memory

110‧‧‧First memory layer

120‧‧‧ dielectric layer

130‧‧‧Second memory layer

140‧‧‧First bias layer

150‧‧‧Second bias layer

Claims (16)

A resistive memory array comprising: a plurality of resistive memory cells arranged in columns and rows, wherein each of the resistive memory cells comprises a first memory cell and a second memory cell And the second memory cell is disposed under the first memory cell and electrically connected in series therewith, wherein each of the resistive memory cells comprises: a first solid electrolyte, which is a portion of the first memory cell; a second solid electrolyte that is part of the second memory cell; and an oxidizable electrode formed on the first solid electrolyte and the second solid electrolyte Wherein the first solid electrolyte and the second solid electrolyte are made of a transition metal oxide or a material containing at least one chalcogen element; a plurality of word lines, wherein each of the word lines The first memory cell coupled to a column of the resistive memory cells; and a plurality of bit lines, wherein each of the bit lines is coupled to a row of the resistive memory Said unit Memory cell element. The resistive memory array of claim 1, wherein the oxidizable electrode is made of a material selected from the group consisting of silver, copper, and zinc. Resistive memory array as described in claim 1 The column further includes: a constituent layer having two layers of yttrium oxide spacers and a tungsten layer formed between the two layers of yttrium oxide spacers, wherein the second solid electrolyte is formed on the oxidizable electrode and Between the layers. The resistive memory array of claim 3, further comprising: a titanium nitride layer, an inner metal dielectric layer, and a substrate, wherein the titanium nitride layer is formed in the constituent layer and the inner layer Between the metal dielectric layers, the inner metal dielectric layer is formed between the titanium nitride layer and the substrate. A resistive memory array comprising: a plurality of resistive memory cells arranged in columns and rows, wherein each of the resistive memory cells comprises a first memory cell and a second memory cell And the second memory cell is disposed under the first memory cell and electrically connected in series therewith, wherein each of the resistive memory cells comprises: a first barrier layer; a second barrier layer; and a metal oxide layer formed between the first barrier layer and the second barrier layer; wherein the first barrier layer is disposed between the metal oxide layer Having a first active region and the first active region is a portion of the first memory cell, and a second active region is disposed between the second barrier layer and the metal oxide layer and The second active area is a portion of the second memory cell; a plurality of word lines, wherein each of the word lines is coupled to the first memory cell of the column of the resistive memory cells; and a plurality of bit lines, wherein the bit lines Each of the lines is coupled to the second memory cell of the row of the resistive memory cells. The resistive memory array of claim 5, wherein the first barrier layer and the second barrier layer are made of a material selected from the group consisting of: nitriding Titanium (TiN), tantalum nitride (TaN), platinum (Pt), and gold (Au); and the metal oxide layer is made of a material selected from the group consisting of tungsten oxide, titanium oxide , nickel oxide, aluminum oxide, copper oxide, zirconium oxide, cerium oxide and cerium oxide. The resistive memory array of claim 5, wherein each of the first active region and the second active region has two resistive states. The resistive memory array of claim 5, further comprising: two layers of yttrium oxide spacers, a first electrode, a second electrode, an inner metal dielectric layer, and a substrate, wherein the two layers of yttrium oxide a spacer is in contact with the metal oxide layer and formed between the first barrier layer and the second barrier layer, and the first electrode is formed on the first barrier layer, the first A second electrode is formed between the second barrier layer and the inner metal dielectric layer, and the inner metal dielectric layer is formed between the second electrode and the substrate. The resistive memory array of claim 8, wherein the first electrode and the second electrode are made of aluminum-copper alloy to make. A method for controlling the operation of a resistive memory array as described in claim 1, comprising: (a) selecting a resistive memory cell to be operated via a word line and a bit line; and b) measuring the resistance of the selected resistive memory cell, and determining which of the first state, the second state, and the third state is the selected one based on the measured resistance The state of the resistive memory unit. The method of claim 10, wherein the step (b) comprises: measuring the resistance as a first resistance by applying a first voltage to the selected resistive memory unit; Determining, when the first resistance is equal to a predetermined value, the state of the resistive memory cell is the first state; and when the first resistance is different from the predetermined value, by using a second voltage Applying to the selected resistive memory cell to measure the resistance as a second resistance; and when the second resistance is equal to the first resistance, determining the selected resistive memory cell The state is the second state, or when the second resistance is not equal to the first resistance, determining that the state of the selected resistive memory cell is the third state. The method of claim 11, further comprising: determining the state of the selected resistive memory unit When the third state is determined, the selected resistive memory cell is reprogrammed to be in the third state. The method of claim 12, wherein the first voltage is less than the second voltage. A method for controlling the operation of a resistive memory array as described in claim 5, comprising: (a) programming the resistive memory array such that the resistive memory In each of the units, the first memory cell and the second memory cell are not in a low resistance state at the same time; (b) the memory to be operated is selected via a word line and a bit line And (c) measuring a resistance of the selected resistive memory unit, and determining which of the first state and the second state is the selected one based on the measured resistance The state of the resistive memory unit. The method of claim 14, wherein the step (c) comprises: measuring the resistance as a read resistance by applying a read voltage to the selected resistive memory unit; And determining that the state of the selected resistive memory cell is the first state when the read resistance is equal to a predetermined value, or determining that the read resistance is not equal to the predetermined value The state of the selected resistive memory cell is the second state. The method of claim 15, further comprising: determining the state of the selected resistive memory unit When the second state is determined, the selected resistive memory cell is reprogrammed to be in the second state.