TWI506649B - Memory array plane select - Google Patents

Description

Memory array plane selection

The present invention is generally directed to semiconductor devices and methods, and more particularly to apparatus and methods for memory array plane selection.

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and resistors. Variable memory and flash memory. Types of resistive variable memory include, inter alia, phase change memory, programmable conductor memory, and resistive random access memory (RRAM).

The memory device is used as a non-volatile memory for a wide range of electronic applications requiring high memory density, high reliability, and data retention without power. Non-volatile memory can be used, for example, in personal computers, portable memory cards, solid state drives (SSDs), digital cameras, cellular phones, portable music players (such as MP3 players), movie players, and In other electronic devices.

Various memory devices can include a memory array. The memory array can include a plurality of memory cells. The plurality of memory cells can be arranged in one or more planes, each plane having a memory unit organized in a cross-point architecture. In such architectures, memory cells can be arranged in a matrix of columns and rows. The memory unit can be positioned at the intersection of the wires. The memory device can include a plurality of vertical stacking planes. That is, the planes can be in each other Formed at different heights.

Decoding logic (e.g., one or more decoders) associated with the (etc.) memory array can have elements (such as transistors) formed in the substrate material below the memory array. However, as the density of the memory cells increases due to a decrease in the size of the memory cells and/or the planes of the memory cells stacked on top of each other in a given region, the footprint of the decoding logic can exceed the memory. The footprint of the array.

100‧‧‧ memory array

102‧‧‧ memory unit

104‧‧‧Word line

106‧‧‧ bit line

108‧‧‧Electrode

110‧‧‧Resistive variable storage element materials

112‧‧‧ electrodes

114‧‧‧Unit selection device materials

116‧‧‧electrode

202‧‧‧ memory unit

204‧‧‧Local word line

206‧‧‧Local bit line

218‧‧‧ memory array

219‧‧‧ memory array

220‧‧‧ first plane

221‧‧‧ first plane

222‧‧‧ second plane

223‧‧‧ second plane

224‧‧‧ column decoding logic

226‧‧‧Decoding logic

228‧‧‧resistance

230‧‧‧resistance

236‧‧‧ Plane selection device

238‧‧‧Plane selection device

240‧‧‧ Plane activation

242‧‧‧ Plane activation

244‧‧‧ Plane activation

246‧‧‧ Plane activation

248‧‧‧ flat word line

250‧‧‧ flat word line

252‧‧‧Common word line

254‧‧‧ flat bit line

256‧‧‧ flat bit line

258‧‧‧Common bit line

302‧‧‧ memory unit

304‧‧‧Local word line

306‧‧‧Local bit line

318‧‧‧ memory array

320‧‧‧ first plane

322‧‧‧ second plane

328‧‧‧resistance

330‧‧‧resistance

336‧‧‧Plane selection device

338‧‧‧Plane selection device

340‧‧‧ Plane activation

342‧‧‧ Plane activation

344‧‧‧ Plane activation

346‧‧‧ Plane activation

348‧‧‧ flat word line

350‧‧‧ flat word line

352‧‧‧Common word line

354‧‧‧ flat bit line

356‧‧‧ flat bit line

358‧‧‧Common bit line

Vcc‧‧‧ supply voltage

1 is a perspective view of a portion of a memory array in accordance with many embodiments of the present invention.

2A is a schematic representation of one of a portion of a memory array of a three-terminal planar selection device having a "co-based" configuration in a planar isolation formed in accordance with many embodiments of the present invention.

2B is a schematic representation of one of a portion of a memory array formed by a three terminal plane selection device having a "collective" configuration in a planar isolation formed in accordance with many embodiments of the present invention.

3 is a perspective view of one of a portion of a memory array having a planar "isolated" configuration formed in accordance with many embodiments of the present invention.

The present invention provides memory arrays and methods of forming such memory arrays. An exemplary memory array can include at least one plane having a plurality of memory cells and a plurality of planar selection devices disposed in a matrix. The plurality of groups of memory cells are communicatively coupled to respective planar selection devices of one of a plurality of planar selection devices. A decoding logic having a component is formed in a substrate material and communicatively coupled to the plurality of planar selection devices. The plurality of memory cells and the plurality of planar selection devices are not formed in the substrate material.

Embodiments of the present invention can provide, for example, reducing the formation of a memory in a substrate material The benefit of the number of components associated with a volume array, such as a transistor including a decoding circuit. Reducing the number of components associated with a memory array formed in the substrate material reduces the physical footprint of the decoding logic and other circuitry associated with the memory array positioned below a memory array and thus increases memory Cell density.

In accordance with various embodiments of the present invention, selection means for selecting individual planes of the memory cells can be formed on the same plane as the memory device. Forming a planar selection device on the same plane as the memory device allows for multiplexing of circuitry formed in the substrate material and associated with the memory array. Because individual planes can be selected, the planes of the memory array do not require, for example, their own dedicated decoding circuitry. That is, the decoding circuit need not be uniquely associated with each plane of the memory array and the plurality of planes of the memory unit can be communicatively coupled in parallel to a same decoding circuit through the plane selection device. Forming a planar selection device on the same plane as the memory device reduces the footprint of circuitry associated with the memory array of components formed in the substrate material by planar selection devices that are not necessarily formed in the substrate material.

In the following detailed description of the invention, reference to the drawings The embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of the invention. change.

The figures herein follow the first digit or digits corresponding to the schema number and the remaining digits identify one of the components or components in the drawing numbering convention. Similar components or components between different figures can be identified by using similar digits. For example, 102 can refer to component "02" in FIG. 1 and a similar component can be referred to as 202 in FIG. Also, as used herein, "a plurality" of a particular element and/or feature may refer to one or more of such elements and/or features.

1 illustrates a portion of a memory array 100 in accordance with many embodiments of the present invention. One perspective. The memory array 100 can have a cross-point architecture having a plurality of wires 104 (e.g., access lines) that can be referred to herein as word lines and many of which can be referred to herein as bit lines. The memory unit 102 at the intersection of the wires 106 (eg, data/sensing lines). As depicted, the word lines 104 are substantially parallel to each other and substantially orthogonal to the bit lines 106 that are substantially parallel to each other. However, embodiments are not limited to a parallel/orthogonal configuration.

As used herein, the term "substantially" means that the modified characteristics need not be absolute, but are close enough to achieve the advantages of the characteristic. For example, "substantially parallel" is not limited to being absolutely parallel and may include an orientation that is at least closer to a parallel orientation than a vertical orientation. Similarly, "substantially orthogonal" is not limited to being absolutely orthogonal and may include an orientation that is at least closer to a vertical orientation than a parallel orientation.

In various embodiments, memory unit 102 can have a "stacked" structure. Each memory cell 102 can include a storage element, such as a cell access device, formed between word line 104 and bit line 106 in series with a respective cell selection device. The storage element can be a variable resistance storage element. The resistive variable storage element can include a resistive variable storage element material 110 formed between a pair of electrodes (eg, 108 and 112). The cell selection device can include a cell selection device material 114 formed between a pair of electrodes (eg, 112 and 116).

The memory unit 102 of the memory array 100 can include cell selection means in series with a phase change material such that the memory array 100 can be referred to as a phase change material and switch (PCMS) array. In many embodiments, the unit selection device can be, for example, one or two terminal two-way threshold switches (OTS). An OTS can comprise, for example, a chalcogenide material formed between a pair of electrically conductive materials (eg, conductive electrodes). In response to a voltage applied across one of the OTSs that is less than one threshold voltage, the OTS can remain in an "off" state (eg, a non-conducting state). Alternatively, the OTS rushes back to an "on" state in response to a voltage applied across the OTS that is greater than one of the threshold voltages. OTS device portable carrier in this "on" state There is a large amount of current at its terminal that remains almost constant at one of the so-called "holding voltage" levels.

Embodiments of the invention are not limited to PCMS crosspoint arrays or a particular cell selection switch. For example, the method and apparatus of the present invention can be applied to other cross-point arrays, such as, for example, resistive random access memory (RRAM) cells, conductive bridged random access memory (other than other types of memory cells). An array of CBRAM) cells and/or spin transfer torque random access memory (STT-RAM) cells.

In embodiments in which the variable resistance storage element comprises a PCM, the phase change material may be a chalcogenide alloy such as indium (In)-bismuth (Sb)-tellurium (Te) (IST) material, among other phase change materials. (for example, In ₂ Sb ₂ Te ₅ , In ₁ Sb ₂ Te ₄ , In ₁ Sb ₄ Te _{7 ,} etc.) or germanium (Ge)-germanium (Sb)-tellurium (Te) (GST) material (for example, Ge ₈ Sb) ₅ Te ₈ , Ge ₂ Sb ₂ Te ₅ , Ge ₁ Sb ₂ Te ₄ , Ge ₁ Sb ₄ Te ₇ , Ge ₄ Sb ₄ Te ₇ or the like). As used herein, a chemical symbol attached by a hyphen indicates an element contained in a particular mixture or compound and is meant to refer to all stoichiometric ratios of the indicated elements. Other phase change materials may include, for example, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In -Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te -Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te -Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, and Ge-Te-Sn -Pt. Other examples of resistance variable materials include transition metal oxide materials or alloys comprising two or more metals (eg, transition metals, alkaline earth metals, and/or rare earth metals). Embodiments are not limited to a particular resistive variable material or material associated with a storage element of memory unit 102. For example, other examples of resistively variable materials that can be used to form the storage element include, inter alia, binary metal oxide materials, giant magnetoresistive materials, and/or various polymer-based resistance variable materials.

In many embodiments, the unit and storage unit can be selected in the unit of the memory unit 102. An electrode is shared between the pieces. Again, in many embodiments, word line 104 and bit line 106 can be used as the top or bottom electrode corresponding to memory cell 102.

In many embodiments, the resistance variable storage element material 110 can include one or more of the same materials as the unit selection device material 114. However, the embodiments are not so limited. For example, the resistance variable storage element material 110 and the unit selection device material 114 can comprise different materials. In accordance with various embodiments of the present invention, the relative positioning of resistive storage element material 110 and unit selection device material 114 may be reversed relative to the relative orientation shown in FIG.

The materials described herein can be formed by a variety of thin film techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD) (such as low pressure CVD), plasma Auxiliary chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma assisted ALD, physical vapor deposition (PVD), thermal decomposition, and/or thermal growth. Alternatively, the material can grow in situ. Although the materials described and illustrated herein may be formed as layers, the materials are not limited thereto and may be formed in other three-dimensional configurations.

Although not shown in FIG. 1, in many embodiments memory array 100 can be part of a three-dimensional (3D) architecture having a plurality of planes (eg, tiles, cards) stacked vertically on each other. In such embodiments, for example, wires 104 and 106 can be communicatively coupled to a memory unit on one of the planes of the 3D array. Moreover, memory array 100 can be coupled, for example, via wires 104 and 106 to circuitry associated with the memory array (eg, in various other circuits associated with operating memory array 100). For example, elements of such circuitry (eg, transistors, etc.) associated with memory array 100 can be formed to form the basis of memory array 100.

In operation, the memory cell 102 of the memory array 100 can be programmed by applying a voltage (eg, a write voltage) across the memory cell 102 via the selected word line 104 and the bit line 106. The memory cell 102 can be programmed to a particular data state, for example, by adjusting the resistance level of the storage element to adjust (eg, change) the width and/or magnitude of the voltage pulse across the memory unit 102.

A sense (eg, read) operation can be used to determine the logic state of a memory unit 102. For example, a particular voltage can be applied to one of the bit lines 106 and word lines 104 corresponding to a selected memory cell 102 and can sense the current through the cell in response to a resulting voltage difference. The sensing operation can also include biasing unselected word lines 104 and bit lines 106 (eg, word lines and bit lines connected to unselected cells) at a particular voltage to sense the data state of a selected cell 102.

Word lines 104 and bit lines 106 from the planes of the memory cells can be connected to the substrate material under the memory array and used to interpret various signals (eg, voltages on word lines 104 and bit lines 106 and / or current) decoding circuit. The decoding circuits may include a column decoding circuit for decoding signals on word line 104 and a row decoding circuit for decoding signals on bit line 106.

As used in the present invention, the term "substrate" material may include silicon-on-insulator (SOI) or sapphire-on-the-spot (SOS) technology, doped and undoped semiconductors, and epitaxial germanium supported by a base semiconductor pedestal. Layer, conventional metal oxide semiconductor (CMOS) (eg, having a CMOS front end of a metal back end) and/or other semiconductor structures and techniques. Various elements (eg, transistors) and/or circuits (eg, such as decoding circuits associated with operating memory array 100) may be formed in/on the substrate material, such as via processing steps, at the base semiconductor structure or base. A region or junction is formed in the seat.

2A is a schematic representation of one of a portion of a memory array 218 of a three terminal plane selection device 236/238 having a "co-based" configuration in a planar isolation formed in accordance with many embodiments of the present invention. According to many embodiments, the three terminal plane selection devices 236 and 238 may be one-way threshold switch (OTS) similar to the two terminal OTS discussed above with respect to the unit selection device, but by adding a third terminal Control the "start" of the OTS. The OTS device is controlled by the third terminal. The three-terminal OTS is in a high-resistance non-conductive "off" state until a pulse is applied to the third terminal, the pulse turning on the three-terminal OTS (eg, the three-terminal OTS is in a conductive "on" state in). As long as a minimum holding current flows through the three-terminal OTS (eg, as long as a minimum holding voltage exists across the three-terminal OTS), the three-terminal OTS remains on after the control pulse is removed.

A three-terminal OTS is formed, for example, by contacting a third terminal with a portion of an active chalcogenide switching region (e.g., one or two terminal devices). Once the threshold voltage is exceeded, current flows through the third terminal to the lower electrode. There is less backtracking or no backtracking, since the third terminal is physically close to the lower electrode and is resistive. The three-terminal OTS plane selecting means 236 and 238 can be formed in the plane of the memory array 218 in a manner similar to the manner in which the two terminal unit selecting means are formed in the plane of a PCMS array.

Memory array 218 includes a plurality of memory cells 202. The memory array 218 is shown as having a plurality of planes including a first plane 220 and a second plane 222. The planes 220 and 222 can be formed in a vertically stacked configuration, for example, wherein the plane 220 is formed at a height different from the height at which the plane 222 is formed. In many other embodiments, planes 220 and 222 can be formed at the same height above a substrate material.

Although two planes are shown in Figure 2A, embodiments of the invention are not limited to this number of planes. Embodiments of the invention may be practiced where the memory cells are configured in more or fewer planes. For simplicity, a limited number of memory cells 202 are shown in the various planes of memory array 218. However, embodiments of the invention are not limited to a particular number of memory cells and may be implemented for a memory array having one or more memory cells.

The memory cells 202 of each plane are shown as being arranged in a column and row intersection structure (eg, a 4x4 matrix). One of the terminals of each of the memory cells 202 in a column is shown as being communicatively coupled to a local conductor (e.g., a local wordline 204). One end of the local word line 204 is shown in FIG. 2A as being coupled to a resistor 230 and the other end of the local word line 204 is shown as being coupled to a first terminal of a corresponding plane selection device 236 (eg, a three terminal One of the OTS emitter terminals).

However, embodiments of the present invention are not limited to the particular configuration depicted in FIG. 2A, particularly with respect to the positioning of resistor 230 and/or plane selection device 236. That is, the resistor 230 need not be positioned at one end of the local word line 204 opposite the corresponding plane selection device 236 and may be positioned closer to the corresponding plane selection device 236 and/or may be a distributed resistor (eg, embodied in The plurality of discrete resistive elements positioned in series with the local word lines 204 and/or the resistors caused by the material used to form the local word lines 204). In some configurations, the plane selection device 236 can also be positioned differently than that shown in Figure 2A. For example, plane selection device 236 and/or resistor 230 can be positioned away from the end of local word line 204 (such as near the center of local word line 204, among other locations). In another example, plane selection device 236 and resistor 230 can be interchanged with respect to the orientation shown in Figure 2A.

A second terminal (e.g., a collector terminal) of one of the corresponding plane selection devices 236 is coupled to a planar word line 248, which in turn is coupled to a common word line 252. The common word line 252 is shown as being communicatively coupled to the column decode logic 224. Although FIG. 2A illustrates one of the corresponding planar selection devices 236 positioned between each of the local wordlines 204 and a corresponding planar wordline 248/250, embodiments of the present invention are not so limited. A planar selection device can be positioned between not all of the word lines and corresponding planar word lines, and/or existing with respect to some of the planes and not present relative to other planes, and the like. For example, embodiments of the invention may include a plane selection device between one or more local word lines 204 (one or more planes) and a corresponding planar word line.

One of the terminals of each memory unit 202 in a row is shown as being communicatively coupled to a local bit line 206. One end of the local bit line 206 is shown coupled to a resistor 228 and the other end of the local bit line 206 is shown as being connected to a first terminal of a corresponding plane selection device 238 (eg, a three terminal OTS An emitter terminal).

However, embodiments of the present invention are not limited to the particular configuration depicted in FIG. 2A, particularly with respect to the positioning of resistor 228 and/or plane selection device 238. That is, the resistor 228 need not be positioned at one end of the local bit line 206 opposite the corresponding plane selection device 238 and The plurality of discrete resistive elements positioned in series with the local bit line 206 and/or used to form the local bit line may be located closer to the corresponding plane selection device 238 and/or being a distributed resistor (eg, embodied in series with the local bit line 206) The resistance caused by the material of 206). In some configurations the plane selection device 238 can also be positioned differently than that shown in Figure 2A. For example, plane selection device 238 and/or resistor 228 can be located away from the end of local bit line 206 (such as near the center of the local bit line 206, among other locations). In another example, plane selection device 238 and resistor 228 can be interchanged with respect to the orientation shown in Figure 2A.

A second terminal (e.g., a collector terminal) of one of the corresponding plane selection devices 238 is coupled to a planar bit line 256, which in turn is coupled to a common bit line 258. The common bit line 258 is shown as being communicatively coupled to the row decode logic 226. Although FIG. 2A illustrates one of the corresponding plane selection devices 238 positioned between each of the local bit lines 206 and a corresponding planar bit line 254/256, embodiments of the present invention are not so limited. A plane selection device can be positioned between not all of the bit lines and corresponding plane bit lines, and/or existing relative to some planes and not present relative to other planes, and the like. For example, embodiments of the invention may include a plane selection device between one or more local bit lines 206 (one or more planes) and a corresponding planar bit line. Furthermore, it may be relative to a local word line and a non-local bit line, or a local bit line and a non-local word line, or some or all of the planes in all planes (as shown in Figure 2A), or only A planar selection device (located in the plane itself) is used in some planes and not in other planes.

As shown in FIG. 2A, the terminals of resistors 228 and 230 that are not connected to memory unit 202 can be connected to a supply voltage (eg, Vcc). The resistors 228 and 230 can be sized to limit the current through the plane selection devices 236 and 238 and/or the voltage across the plane selection devices 236 and 238 to the operational levels associated with the plane selection devices 236 and 238. The size of the resistor 228 can be the same or different than the size of the resistor 230.

A third terminal (e.g., a base terminal) of each of the plane selection devices 236 can be coupled to a control signal (e.g., plane enable 240). Plane selection shown in Figure 2A The configuration of the device connected to a planar enabled base terminal is referred to as a "co-base" configuration because the base terminals are grouped together. Appropriate signals on the plane enablement 240 thereby applied to one of the base terminals of the plane selection device 236 may cause each of the plane selection devices 236 to conduct between the emitter terminal and the collector terminal, thereby passing the local word line 204 via The planar word line 248 is communicatively coupled to the common word line 252 such that the decode logic can operate (e.g., program/read) the word line of the first plane 220. The plane selection device 236 may continue to conduct as long as there is an appropriate signal on the plane enable 240 and/or the current through the plane selection device 236 and/or the voltage across the plane selection device 236 remains above the OTS hold threshold.

A third terminal (e.g., a base terminal) of each of the planar selection devices 238 can be coupled to one of the plane openings 242 of the first plane 220. An appropriate signal on the plane enable 242 thereby applied to one of the base terminals of the plane selection device 238 can cause each of the plane selection devices 238 to conduct between the emitter terminal and the collector terminal, thereby localizing the local bit line 206 is communicatively coupled to common word line 252 via planar bit line 254 such that the decode logic can operate (eg, program/read) the bit line of first plane 220.

If plane enable 240 and plane enable 242 are not connected together, they can be independently operated to independently enable continuity of word line 204 and/or bit line 206 of first plane 220. Alternatively, connectable plane enable 240 and plane enable 242 enable a signal to simultaneously enable continuity of both word line 204 and bit line 206. In this manner, a single plane enable can be used to enable operation/interrogation of the first plane 220 (e.g., select the first plane 220).

Regarding the second plane 222, between the memory unit 202, the local word line 204, the local bit line 206, the selection devices 236 and 238, the planar word line 250, the planar bit line 254, the common word line 252, the common bit line 258. The connections between resistors 228 and 230 and supply voltage Vcc may all be the same as described for similar features with respect to first plane 220 and as shown in FIG. 2A. Regarding the second plane 222, however, the base terminal of the plane selection device 236 can be coupled to the plane enable 244 and the base terminal of the plane selection device 238 can be coupled to the plane enable 246.

If the plane enable 244 and the plane enable 246 are not connected together, they can operate independently The continuity of the word line 204 and/or the bit line 206 of the second plane 222 is independently enabled. Alternatively, connectable plane enable 244 and plane enable 246 enable a signal to simultaneously enable continuity of both word line 204 and bit line 206 of second plane 222. In this manner, a single plane enable can be used to enable operation/interrogation of the second plane 222 (e.g., select the second plane 222).

2A shows that a plurality of planar word lines (eg, planar word lines 248 and 250) are connected in parallel to a common word line 252 leading to column decode logic 224. Similarly, a plurality of planar bit lines (e.g., planar bit lines 256 and 254) are connected in parallel to a common bit line 258 that is directed to row decode logic 226. Column decoding logic 224 and/or row decoding logic 226 may be used because each respective plane may be selected independently (eg, using plane enable 240 and 242 to select first plane 220 or using plane enable 244 and 246 to select second plane 222) In two planes. As such, the individual dedicated column 224 decoding logic and the row 226 decoding logic are not required for each plane. Because the column 224 decode logic and the row 226 decode logic have elements formed in a substrate material, sharing a single column 224 decode logic and row 226 decode logic reduces the footprint of circuitry integrated into the semiconductor substrate material.

When one of the memory cells 202 in a particular plane is to be accessed (e.g., associated with a stylized or read operation), only plane selection devices 236 and/or 238 on the plane are activated. The planar selection devices 236 and/or 238 can provide electrical isolation when either of the planar selection devices 236 and/or 238 are not being operated to conduct. In an unselected plane, the wires (eg, local word lines and local bit lines) and the memory elements within the plane are planar selection devices 236 and/or 238 by unselected closed states (eg, three-terminal OTS devices) ) and insulated from the signals on the perimeter. In this manner, plane selection devices 236 and/or 238 can be used to multiplex individual planar conductors to common word line 252 and common bit line 258.

Additionally, as depicted in Figure 2A, plane selection devices 236 and 238 are positioned on respective planes. That is, for example, plane selection devices 236 and 238 can be formed on the same plane as the PCMS intersection array. Therefore, a planar selection device (eg, a transistor) does not need to be formed in In the substrate material, thereby reducing the footprint of the circuitry integrated into the semiconductor substrate material.

In accordance with some embodiments, the planar selection and planar word/bit line multiplexing techniques of the present invention are implemented using planar selection devices (e.g., transistors) formed in a substrate material. For example, some or all of the planar selection means may be formed in the substrate material below the memory array and at the boundary of the memory array sufficient to accommodate regions of the planar selection device formed in the substrate material. Savings in area occupied by shared decoding logic in multiple planes via multiplexed planar word/bit lines.

Although FIG. 2A shows a plane selection device corresponding to local word line 204 and local bit line 206, embodiments of the invention are not so limited. Planar selection means can be utilized to connect and isolate other conductors (such as other signal lines) associated with a particular plane. Moreover, the matrix of memory cells 202 in a particular plane 220/222 can be further divided into, for example, pages, blocks, or other entities or logical groups, and the plane selection device is configured and configured to provide, for example, independence. The ability to select portions of that particular plane. Although FIG. 2A shows only one plane selection device per wire, embodiments are not so limited and one or more plane selection devices can be used to further isolate portions of the wires and/or particular memory cells and/or other control circuitry. Embodiments are not limited to the positioning, number, orientation, or configuration of the planar selection device and employ repeating circuits and components that achieve individual planar selection to facilitate signal multiplexing to reduce planar selection devices formed in the substrate material under a memory array. Other configurations and configurations.

2B is a schematic representation of one of a portion of a memory array 219 of one of three terminal plane selection devices 236/238 having a "collective" configuration in a planar isolation formed in accordance with many embodiments of the present invention. The memory array 219 is shown as having a plurality of planes including a first plane 221 and a second plane 223. As shown in Figure 2B, the connections are the same as those shown in Figure 2A, except that the plane selection devices 236/238 of the memory array 219 are interconnected in a "co-set" configuration. That is, one of the plane selection devices 236 (e.g., one of the three terminal OTS emitter terminals) is coupled to the local word line 204. A second terminal (eg, a collector terminal) corresponding to plane selection device 236 is coupled to plane enable 240 (rather than Connected to a planar word line 248) as shown in Figure 2A. A third terminal (e.g., a base terminal) of plane selection device 236 is coupled to planar word line 248. An appropriate signal on planar enable 240 whereby one of the collector terminals applied to plane select device 236 can cause each of plane select devices 236 to conduct between the emitter terminal and the base terminal, thereby passing local word line 204 via The planar word line 248 is communicatively coupled to a common word line 252.

Similarly, one of the plane selection devices 238 (e.g., an emitter terminal) is coupled to the local bit line 206. A second terminal (e.g., a collector terminal) of the corresponding plane selection device 238 is coupled to the plane enable 242 (rather than to a planar bit line 256 as shown in Figure 2A). A third terminal (e.g., a base terminal) of plane selection device 238 is coupled to planar bit line 256. An appropriate signal on the plane enable 242 thereby applied to one of the collector terminals of the plane selection device 238 can cause each of the plane selection devices 238 to conduct between the emitter terminal and the base terminal, thereby placing the local bit line 206 The common bit line 258 is communicatively coupled via a planar word line 256. The plane selection devices 236 and 238 of the second plane 223 are also coupled to the plane enablers 244 and 246, respectively, in a common set configuration.

3 is a perspective view of one of a portion of a memory array having a planar "isolated" configuration formed in accordance with many embodiments of the present invention. 3 is a perspective view of one exemplary embodiment of a memory array 218 that is schematically illustrated in FIG. 2A. FIG. 3 shows a memory array 318 comprising a plurality of memory cells 302. The memory array 318 is shown as having a plurality of planes including a first plane 320 (eg, an upper plane) and a second plane 322 (eg, a lower plane).

The memory cells 302 of each plane are shown as being arranged in a column and row intersection architecture (eg, a 4x4 matrix). One of the terminals of each of the memory cells 302 in a column is shown as being connected to a local word line 304. One end of the local word line 304 is shown coupled to a resistor 330 and the other end of the local word line 304 is shown as being connected to a first terminal of a corresponding plane selection device 336 (eg, one of three terminal OTS shots) Extreme terminal). However, as discussed with respect to FIG. 2A, embodiments of the present invention are not limited to the particular group illustrated in FIG. State, in particular, regarding the location of resistor 330, which may be positioned differently in series with local word line 304 and/or by resistors along local word line 304.

A second terminal (e.g., a collector terminal) of one of the plane selection devices 336 is coupled to a planar word line 348, which in turn is coupled to a common word line 352. The common word line 352 leading to column decoding logic (not shown in Figure 3) is shown.

One of the terminals of each memory unit 302 in a row is shown as being communicatively coupled to a local bit line 306. One end of the local bit line 306 is shown coupled to a resistor 328 and the other end of the local bit line 306 is shown as being coupled to a first terminal of a corresponding plane selection device 338 (eg, an emitter terminal) . However, and as discussed with respect to FIG. 2A, embodiments of the present invention are not limited to the particular configuration illustrated in FIG. 3, particularly with respect to the location of resistor 328, which may be in series with local bit line 306. It is positioned differently and/or consists of the resistance of the local bit line 306.

A second terminal (e.g., a collector terminal) of one of the plane selection devices 338 is coupled to a planar bit line 356, which in turn is coupled to a common bit line 358. The common bit line 358 leading to row decoding logic (not shown in Figure 3) is shown. One of the terminals of resistors 328 and 330 can be connected to a supply voltage (eg, Vcc).

A third terminal (e.g., a base terminal) of each of the plane selection devices 336 can be coupled to one of the plane openings 340 of the first plane 320. The configuration shown in FIG. 3 is a "co-based" configuration in which the base terminal of plane selection device 336 is coupled to the plane enable 340. A third terminal (e.g., a base terminal) of each of the planar selection devices 338 can be coupled to one of the plane openings 342 of the first plane 320. The plane enablers 340 and 342 can be connected together (to select the entire plane) or isolated from each other (to allow the selection of word lines and bit lines to be independent of each other).

Regarding the second plane 322, there are a memory unit 302, a local word line 304, a local bit line 306, selection devices 336 and 338, a planar word line 350, a planar bit line 354, a common word line 352, and a common bit line. 358. The connections between resistors 328 and 330 and supply voltage Vcc may all be the same as described with reference to similar features of first plane 320 and as shown in FIG. Of course Rather, with respect to the second plane 322, the base terminal of the plane selection device 336 can be coupled to the plane enable 344 and the base terminal of the plane selection device 338 can be coupled to the plane enable 346.

Although specific embodiments have been illustrated and described herein, it will be understood by those of ordinary skill in The invention is intended to cover adaptations and variations of the various embodiments of the invention. It is to be understood that the above description has been made in an illustrative and non-limiting manner. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of various embodiments of the invention encompasses other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of the invention is to be determined by the scope of the appended claims and the scope of the claims.

In the foregoing Detailed Description, various features are grouped together in a single embodiment to simplify the invention. This method of the invention is not to be interpreted as reflecting the intention that the disclosed embodiments of the invention must use more features than those explicitly recited in each claim. Rather, as the following claims are included, the invention is characterized by less than all features of a single disclosed embodiment. Accordingly, the scope of the following claims is incorporated into the embodiments, in which each claim

202‧‧‧ memory unit

204‧‧‧Local word line

206‧‧‧Local bit line

218‧‧‧ memory array

220‧‧‧ first plane

222‧‧‧ second plane

224‧‧‧ column decoding logic

226‧‧‧Decoding logic

228‧‧‧resistance

230‧‧‧resistance

236‧‧‧ Plane selection device

238‧‧‧Plane selection device

240‧‧‧ Plane activation

242‧‧‧ Plane activation

244‧‧‧ Plane activation

246‧‧‧ Plane activation

248‧‧‧ flat word line

250‧‧‧ flat word line

252‧‧‧Common word line

254‧‧‧ flat bit line

256‧‧‧ flat bit line

258‧‧‧Common bit line

Vcc‧‧‧ supply voltage

Claims (26)

A memory array comprising: a plurality of planes, each of the plurality of planes having a plurality of memory cells and a plurality of plane selection devices arranged in a matrix, the plurality of memory cells being grouped to communicate Means coupled to one of the plurality of plane selection devices, wherein a first plane is associated with a first number of access lines and a second plane is associated with a second number of access lines; and a decoding logic, The decoding logic has an element and is formed in a substrate material and communicatively coupled to the plurality of planar selection devices, wherein the first number of access lines and the second number of access lines are each coupled in parallel to be communicatively coupled to The plurality of common access lines of the decoding logic, and the plurality of memory cells and the plurality of plane selecting devices are not formed in the substrate material. The memory array of claim 1, wherein each of the plurality of memory cells is communicatively coupled to a respective pair of planar selection devices of the plurality of planar selection devices. The memory array of claim 1, wherein the component of the decoding logic comprises a transistor formed in a substrate material and the plurality of planar selection devices are thin film devices. The memory array of any one of claims 1 to 3, wherein each of the plurality of plane selection devices is a bidirectional threshold switch (OTS). The memory array of claim 4, wherein each of the plurality of plane selection devices is a three-terminal OTS. The memory array of claim 5, wherein the first terminal of the three terminal OTS is communicatively coupled in parallel to the plurality of memory cells of a group, and the second terminal of the three terminal OTS is communicatively coupled to The decoding logic and one of the three terminal OTSs The third terminal is communicatively coupled to a plane enable control line. The memory array of claim 6, wherein the three-terminal OTS is communicatively coupled to the planar enable control line in a common base configuration. The memory array of claim 6, wherein the three terminal OTS is communicatively coupled to the planar enable control line in a common set configuration. The memory array of any one of claims 1 to 3, wherein each memory unit comprises a storage device and a thin film unit selection device. The memory array of claim 9, wherein each of the memory cells is a phase change material and switch (PCMS) device. The memory array of claim 10, wherein the thin film unit selection device forms a two-terminal OTS in series with the phase change material. A memory array comprising: a plurality of planes configured in a stacked configuration, each plane being formed at a different height above a substrate material, each plane having a plurality of memory cells, the plurality of memory cells being disposed in In a matrix, the matrix consists of columns and rows, and for each of the plurality of planes: one column of the memory cells are connected to a first wire, and one row of the memory cells are connected to a second wire And at least one of: a column of decoding logic communicatively coupled to the first conductor of each plane through a column plane selection device positioned on each respective plane of the plurality of planes, the column plane selection device And a row of decoding logic communicatively coupled to the second conductor of each plane through a row plane selection device positioned on each respective plane of the plurality of planes, the row plane selection devices being arranged in parallel. The memory array of claim 12, wherein the column plane selection device of each plane and/or Or the row plane selection device is connected to a plane enable signal. The memory array of any one of claims 12 to 13, wherein the row plane selection means is coupled to a first plane enable signal and/or the row plane selection means of each plane is coupled to a second plane enable signal. A memory array comprising: decoding logic; and a plurality of planes, each plane having a plurality of memory cells, the plurality of memory cells being arranged in a matrix, the matrix being composed of columns and rows, and for the plurality of Each of the planes: one of the memory cells in the first terminal is connected to a first wire, and the second terminal of each of the memory cells in a row is connected to a second wire, the first wire is connected to a a terminal of one of the first resistors and a first terminal of a row of plane selecting devices, the second wire being connected to a terminal of one of the second resistors and one of the first terminals of the row of plane selecting devices, one of the column plane selecting devices The second terminal is connected to the decoding logic, and the second terminal of the row plane selecting device is connected to the decoding logic, and the third terminal of the column plane selecting device is connected to a respective column plane enable signal, and the row plane selecting device One of the third terminals is coupled to a respective row plane enable signal, wherein the second terminals of the column plane selection devices are connected in parallel to the decode logic and the row planes Such optional device connected in parallel to the second terminal of the decoding logic. The memory array of claim 15, wherein: the first end of the first wire is connected to the terminal of the first resistor; and a second end of the first wire is connected to the first terminal of the column plane selection device; a first end of the second wire is connected to the terminal of the second resistor; and one of the second wires The two ends are connected to the first terminal of the row plane selection device. The memory array of any one of claims 15 to 16, wherein the first wire is a word line and the second wire is a bit line. The memory array of any one of claims 15 to 16, wherein: the memory cells each comprise a two-terminal two-way threshold switch (OTS) phase change material and switch (PCMS) memory unit; The equal row plane selecting means and the row selecting means are three terminal OTSs. The memory array of claim 18, wherein the column plane selection means in each of the plurality of planes are coupled to the column plane enable signal in a common base configuration and in each of the plurality of planes The equal row plane selection device is connected to the row plane enable signal in a common base configuration. The memory array of claim 18, wherein the column plane selection means in each of the plurality of planes are connected to the column plane enable signal in a common set configuration and in each of the plurality of planes The equal row plane selection means is coupled to the row plane enable signal in a common set configuration. A method of forming a memory array, comprising: forming a decoding circuit in a substrate material; forming a plurality of planes over the substrate material, each of the plurality of planes having a phase change material disposed in a matrix and a switch (PCMS) memory unit and a plane selection device, wherein a first group of the PCMS memory cells are communicatively coupled to a first wire and the first wire is transmitted through the planar selection device via a common wire A communication mode is coupled to the decoding circuit, and wherein the PCMS memory cells of a second group are coupled to the decoding circuit in parallel with the PCMS memory cells of the first group via the common conductor. The method of claim 21, wherein forming the plane selection means comprises forming a three terminal bidirectional threshold switch (OTS) in a common base configuration, the common base being coupled to a respective plane enable signal. The method of claim 21, wherein forming the plane selection means comprises forming a three terminal bidirectional threshold switch (OTS) in a common set configuration, the common collector being coupled to a respective plane enable signal. A method of operating a memory array, comprising: selecting a plane from a plurality of planes via a control signal to a planar selection device positioned in a selected plane, the plane having a plurality of memory cells, the plurality of memories The body unit is disposed in a matrix consisting of columns and rows; and the wires from the selected plane are communicatively coupled to a decoding circuit having elements formed in a substrate material; and from the plurality The wires of the unselected planes of the plane are isolated from the decoding circuit. The method of claim 24, further comprising multiplexing the signals from the plurality of planes and transmitting the multiplexed signals to the decoding circuit by selecting at most one plane at any given time. The method of any one of claims 24 to 25, wherein the control signal is a planar enable signal and the planar selection device is a three terminal thin film device positioned in series with the wires of the selected plane, and wherein the one is selected The plane includes causing the three terminal thin film devices to conduct in response to the planar enable signal.