TWI506416B - Debug device and debug method - Google Patents

Description

Debugging device and debugging method

A debugging device, in particular, relates to a debugging device and a debugging method suitable for a server.

In the current server, when the server is started, the Basic Input Output System (BIOS) will be activated first, so that the basic input and output system can completely check the hardware devices in the server. And testing, this test and test action is also called Power On Self Test (POST). When the hardware device in the server passes the inspection and testing, the basic input and output system will deliver the hardware information in the server to the operating system, so that the operating system continues to complete the booting process. However, if a component in the server malfunctions, it will cause the boot program to stay at a certain level and cannot continue to boot normally.

Therefore, when the booting process does not enter the operating system before the booting is abnormal, just find the code of the specific input/output port (IO Port), such as Port 80, and find out the check phase corresponding to the code. It is possible to detect which component of the server is not functioning properly. At present, the most common way to debug is to use the Debug Module configured on the motherboard to retrieve the code of the Port 80 and display the code of the Port 80 for the user to determine whether the server is generated. Error status.

However, due to the limited space of the motherboard of the server, the debug module is often removed from the motherboard at the time of shipment, that is, the debugged motherboard is not equipped with a debug module, so After the message of the port 80 code is known, and the subsequent server board is mass-produced, debugging and error analysis are not easy. Therefore, how to provide an effective debugging device will be an important issue.

The disclosure aims to provide a debugging device and a debugging method, thereby reducing the debugging time, cost and difficulty of execution of the server, and improving the debugging efficiency.

A debug device of the present disclosure is applicable to a server, the server including a control chip. The debugging device includes a receiving unit, a signal processing unit and a plurality of ports. The receiving unit is coupled to the control chip for receiving the power-on detection signal. The signal processing unit is coupled to the receiving unit for receiving the power-on detection signal through the receiving unit, and converting the information code of the power-on detection signal into at least one debugging signal according to the at least one switching signal and the plurality of output interfaces, wherein the output interfaces are different from each other . The connection port is coupled to the signal processing unit and corresponding to one of the output interfaces for transmitting at least one error signal.

In one embodiment, the output interface includes a serial port interface, a parallel port interface, an internal integrated circuit, and a display signal interface.

In an embodiment, the foregoing debugging device further includes a storage unit. The storage unit is coupled to the signal processing unit for storing the information code of the power-on detection signal.

In an embodiment, the foregoing debugging device further includes a switching unit. The switching unit is coupled to the signal processing unit for generating a switching signal.

In an embodiment, the foregoing debugging device further includes a plurality of display units. The display units are respectively coupled to the connection port for receiving at least one debug signal and displaying the corresponding at least one debug signal.

In an embodiment, the aforementioned receiving unit includes a low-foot digit interface.

In an embodiment, the at least one switching signal is generated by connecting at least one of the ports to the display unit.

A method of debugging according to the present disclosure is applicable to a server including a control chip. This debugging method includes the following steps. Receiving a power-on detection signal generated by the control chip. And converting the information code of the power-on detection signal into at least one debugging signal according to the at least one switching signal and the plurality of output interfaces, wherein the output interfaces are different from each other. Transmit at least one debug signal.

The debugging device and the debugging method of the present disclosure are obtained by a signal processing unit Controlling the power-on detection signal generated by the chip, and converting the information code of the power-on detection signal into corresponding at least one debugging signal according to the switching signal and the output interface, and then transmitting the debugging signal by the connection port. In addition, the foregoing switching signal may be generated by connecting at least one of the ports to the display unit or by the switching unit. In this way, the debugging time, cost, and difficulty of execution of the server can be reduced, and the debugging efficiency can be improved.

The features and implementations of the present disclosure are described in detail below with reference to the drawings.

100, 200‧‧‧ server

102‧‧‧Central Processing Unit

104‧‧‧ memory

106‧‧‧Basic input and output system memory

108‧‧‧Control wafer

110‧‧‧Debugging device

120‧‧‧ receiving unit

130‧‧‧Signal Processing Unit

140_1~140_N‧‧‧Connector

150_1~150_N, 230_1~230_N‧‧‧ processing unit

210‧‧‧ storage unit

220‧‧‧Switch unit

BDS‧‧‧Start detection signal

Figure 1 is a schematic diagram of the server of the present disclosure.

Figure 2 is another schematic diagram of the server of the present disclosure.

Figure 3 is a flow chart of the method for debugging the disclosure.

In the various embodiments listed below, the same reference numerals will be used to refer to the same or similar elements.

Please refer to "Figure 1" for a schematic diagram of the server of the present disclosure. The server 100 includes a central processing unit (CPU) 102, a memory (Dual In-line Memory Module, DIMM) 104, a basic input output system (BIOS) memory 106, and a control chip 108. The debug device 110 of the present disclosure. The central processing unit 102 is coupled to the memory 104. The basic input/output system memory 106 is used to store a basic input/output system. The control chip 108 is coupled to the central processing unit 104 and the basic input output system unit 106.

Moreover, the control chip 108 is coupled to the central processing unit 102 via a direct media interface (DMI) bus bar, for example. The control chip 108 is coupled to the basic input/output system memory 106, for example, via a Serial Peripheral Interface (SPI) bus. The central processing unit 102, the memory 104, and the basic input/output system memory 106 are not the focus of the disclosure, and thus are not described herein.

The debug device 100 of the present disclosure includes a receiving unit 120, a signal processing unit 130 and a plurality of ports 140_1~140_N, where N is a positive integer greater than one.

The receiving unit 120 is coupled to the control chip 108 for receiving a Boot Device Select BDS. In this embodiment, the receiving unit 120 includes, for example, a low pin count (LPC) interface, and the debug device 110 is coupled to the control chip 108 through the low bit device interface to receive the boot of the control chip 108. Detection signal BDS.

The signal processing unit 130 is coupled to the receiving unit 120 for receiving the power-on detection signal BDS generated by the control chip 108 through the receiving unit 120, and converting the information code of the power-on detection signal BDS into at least one switching signal and a plurality of output interfaces. A debug signal, and the aforementioned output interface is different. The control chip 108 is, for example, a South Bridge Chip (SB Chip) or a Platform Controller Hub (PCH) chip of the motherboard of the server 100. The output interface includes a serial port interface, a Parallel Port interface, an Inter Integrated Circuit (I2C) and a display signal interface or other signal output interfaces.

In practical applications, the basic input/output system memory 106 pre-stores a plurality of Power On Self Test Codes (POST Codes), which are used to represent different stages of self-testing. When the server 100 is to enter a stage of power-on self-test, the value of the power-on self-test code represented by this stage is sent to a specific input/output port (IO Port), such as Port 80.

Moreover, the control chip 108 is coupled to the basic input/output system memory 106, and during the booting process of the server 100, the power-on detection signal corresponding to the boot self-test code is outputted from the motherboard. After receiving the boot detection signal BDS, the signal processing unit 130 extracts the information code of the boot detection signal BDS, and converts the information code into at least one debug signal according to the switching signal and the output interface. The information code corresponds to, for example, the aforementioned boot self test code.

The ports 140_1~140_N are coupled to the signal processing unit 130 and respectively correspond to one of the output interfaces for transmitting at least one error signal. For example, the connection 埠140_1 corresponds to The output interface is, for example, a serial port interface, the output interface corresponding to the port 140_2 is, for example, a parallel interface, the output interface corresponding to the port 140_3 is, for example, an internal integrated circuit, and the output interface corresponding to the port 140_4 is, for example, a display signal interface. The rest is analogous.

Further, the ports 140_1~140_N are adapted to be coupled to the display units 150_1~150_N, and the ports 140_1~140_N are in one-to-one correspondence with the display units 150_1~150_N. For example, the port 140_1 is adapted to be coupled to the display unit 150_1, the port 140_2 is adapted to be coupled to the display unit 150_2, and the port 140_3 is adapted to be coupled to the display unit 150_3. The rest is analogous. Further, the display unit 150_1 has, for example, a device having a serial interface, and the display unit 150_2 has, for example, a device that is parallel to the interface. The display unit 150_3 has, for example, a device such as an internal integrated circuit. The display unit 150_4 has, for example, a light-emitting diode that displays a signal interface. Body or seven-segment display. The rest is analogous.

In addition, the foregoing switching signal is generated, for example, by connecting at least one of the ports 140_1~140_N and the display units 150_1~150_N. For example, when the port 140_1 and the display unit 150_1 are connected, the display unit 150_1 transmits the switching signal to the signal processing unit 130 via the port 140_1, for example, the signal processing unit 130 according to the switching signal and the output interface corresponding to the switching signal (for example, The serial port interface converts the information code of the power-on detection signal BDS into a debug signal with a serial port interface. Then, the signal processing unit 130 transmits the error signal having the serial port interface to the display unit 150_1 through the port 140_1 to display the corresponding state of the debug signal on the display unit 150_1. In this way, the user can know the operation status of the server 100 through the display unit 150_1.

When the connection unit 140_2 and the display unit 150_2 are connected, the display unit 150_2 transmits the switching signal to the signal processing unit 130 through the connection 140_2, for example, the signal processing unit 130 switches the signal and the output interface corresponding to the switching signal (for example, the parallel interface). The information code of the power-on detection signal BDS is converted into a debugging signal with a parallel interface. Then, the signal processing unit 130 transmits the error signal having the parallel interface through the port 140_2 to the display unit 150_2 to display the corresponding state of the debug signal on the display unit 150_2. In this way, the user can know the operation status of the server 100 through the display unit 150_2.

First, when the power supply starts to supply power to the server 100, the server 100 performs a Power Sequence. Then, after the power-on sequence of the server 100 is completed, the basic input/output system enters a stage of power-on self-test to generate a corresponding power-on self-test code value to a specific output input, and the control chip 108 corresponds to the aforementioned self-test code value. , generate a power-on detection signal.

After receiving the power-on detection signal BDS through the receiving unit 120, the signal processing unit 130 will extract the information code of the power-on detection signal BDS. Then, the signal processing unit 130 waits for the switching signal generated by the connection between the ports 140_1~140_N and the display units 150_1~150_N and the output interface, converts the information code into at least one error signal, and then connects the debugging signal through the port. 140_1~140_N are transmitted to the display units 150_1~150_N for corresponding display.

For example, if the boot self-test code generated by the basic input/output system is, for example, "00001101", the control chip 108 will also provide a "00001101" power-on detection signal BDS. Then, the signal processing unit 130 receives the power-on detection signal BDS of "00001101" through the receiving unit 120, and extracts the information code of the power-on detection signal BDS, that is, the information code is, for example, "00001101".

Thereafter, the signal processing unit 130 converts the information code of "00001101" into at least one debug signal according to the switching signal and the output interface. When the switching signal is generated by the connection 埠140_1 being connected to the display unit 150_1, the signal processing unit 130 converts the information code of "00001101" into a debugging signal having the serial port interface corresponding to 埠140_1, and debugs the error. The signal is transmitted to the display unit 150_1 through the port 140_1 for corresponding display.

When the switching signal is generated by the connection of the ports 140_1, 140_2 and the display units 150_1, 150_2, the signal processing unit 130 converts the information code of "00001101" into a debugging signal having a serial port interface corresponding to the port 140_1 and has The error signal of the parallel interface corresponding to the 埠140_2 is connected, and the two debug signals are respectively transmitted to the display units 150_1 and 150_2 through the ports 140_1 and 140_2 for corresponding display. In this way, by obtaining and displaying the information code of the boot detection signal BDS of the server 100, the server 100 can be effectively reduced. The debugging time, cost and difficulty of execution, and improve the efficiency of debugging.

Please refer to "Figure 2", which is another schematic diagram of the server of the present disclosure. The debug device 110 of the present disclosure further includes a storage unit 210, a switching unit 220, and display units 230_1~230_N. The remaining components and their coupling relationship can be referred to in "Fig. 2", and therefore will not be described here.

The storage unit 210 is coupled to the signal processing unit 130 for storing the information code of the boot detection signal BDS. That is to say, the signal processing unit 130 receives the power-on detection signal BDS, extracts the information code of the power-on detection signal BDS, and stores the information code to the storage unit 210. The storage unit 210 is, for example, a register.

The switching unit 220 is coupled to the signal processing unit 130 for generating at least one switching signal. The switching unit 220 can be, for example, a dip switch. For example, when the switching unit 220 generates a switching signal of “0001”, for example, the signal processing unit 130 may have the switching signal of “0001” to find a corresponding output interface, such as a serial port interface, and the power-on detection signal BDS. The information code is converted into a debug signal having a serial port interface and transmitted through the port 140_1.

When the switching unit 220 generates the switching signal of "0010", for example, the signal processing unit 130 can have the switching signal of "0010" to find the corresponding output interface, for example, the parallel interface, and convert the information code of the power-on detection signal BDS into The debug signal with the parallel interface is transmitted through the connection 140_2.

When the switching unit 220 generates a switching signal of “0100”, for example, the signal processing unit 130 may have the “0100” switching signal to find a corresponding output interface, such as an internal integrated circuit interface, and the information code of the power-on detection signal BDS. The conversion signal is converted into an error signal having an internal integrated circuit interface, and transmitted through the connection port 140_3.

When the switching unit 220 generates, for example, a "1000" switching signal, the signal processing unit 130 can have the "1000" switching signal to find a corresponding output interface, such as a display signal interface, and convert the information code of the power-on detection signal BDS into The debugging signal with the display signal interface is transmitted through the connection 140_4. The foregoing is an example in which the switching unit 220 generates corresponding switching signals corresponding to the four ports 140_1~140_4, but the embodiment is not limited thereto. Field Those skilled in the art can use the foregoing description to derive an implementation manner in which the switching unit 220 generates corresponding switching signals corresponding to other numbers of ports, and therefore no further details are provided herein.

The display units 230_1~230_N are respectively coupled to the ports 140_1~140_N for receiving at least one debug signal and displaying corresponding at least one debug signal. Further, the display units 230_1~230_N are coupled to the ports 140_1~140_N in a one-to-one manner. Thereby, the user can control, by the switching unit 220, which display unit displays the information code of the power-on detection signal BDS of the server 100 to know the operation status of the server. In this way, the debugging time, cost, and difficulty of execution of the server 100 can be effectively reduced, and the debugging efficiency is improved.

By the description of the foregoing embodiments, a method of debugging can be summarized. Please refer to "Figure 3" for a flowchart of the troubleshooting method for this disclosure. The debug method of this embodiment is applicable to a server, and the server includes a control chip. In step S310, a power-on detection signal generated by the control chip is received. In step S320, the information code of the power-on detection signal is converted into at least one debugging signal according to the at least one switching signal and the plurality of output interfaces, wherein the output interfaces are different from each other. In step S330, at least one debug signal is transmitted. In this embodiment, the output interface includes a serial port interface, a parallel port interface, an internal integrated circuit and a display signal interface, or other signal output interfaces.

The debugging device and the debugging method of the embodiment of the present disclosure obtain the power-on detection signal generated by the control chip by the signal processing unit, and convert the information code of the power-on detection signal into corresponding corresponding signals according to the switching signal and the output interface. A debug signal is transmitted, and the aforementioned debug signal is transmitted by the port. In addition, the foregoing switching signal may be generated by connecting at least one of the ports to the display unit or by the switching unit. In this way, the debugging time, cost, and difficulty of execution of the server can be reduced, and the debugging efficiency can be improved.

The present disclosure is disclosed in the foregoing embodiments, and is not intended to limit the disclosure. Any subject matter of the present invention can be modified and retouched without departing from the spirit and scope of the disclosure. The scope of patent protection shall be subject to the definition of the scope of the patent application attached to this specification.

100‧‧‧Server

102‧‧‧Central Processing Unit

104‧‧‧ memory

106‧‧‧Basic input and output system memory

108‧‧‧Control wafer

110‧‧‧Debugging device

120‧‧‧ receiving unit

130‧‧‧Signal Processing Unit

140_1~140_N‧‧‧Connector

150_1~150_N‧‧‧ display unit

BDS‧‧‧Start detection signal

Claims (6)

A debugging device is applicable to a server, the server includes a control chip, and the debugging device includes: a receiving unit coupled to the control chip for receiving a boot detection signal; a signal processing unit coupled The receiving unit is configured to receive the power-on detection signal through the receiving unit, and convert the information code of the power-on detection signal into at least one of the output interfaces according to the at least one switching signal and the format of the plurality of output interfaces. One of the formats of the error signal, wherein the output interface formats are different from each other, and the output interfaces include a serial port interface, a parallel port interface, an internal integrated circuit and a display signal interface; and a switching unit coupled to the signal processing The unit is configured to generate the switching signal; and the plurality of ports are coupled to the signal processing unit and respectively correspond to one of the output interfaces for transmitting the error code converted by the information code. The debugging device of claim 1, further comprising: a storage unit coupled to the signal processing unit for storing the information code of the power-on detection signal. The debug device of claim 1, further comprising: a plurality of display units respectively coupled to the plurality of connection ports for receiving the at least one debug signal and displaying the corresponding at least one debug signal. The debug device of claim 1, wherein the receiving unit comprises a low-digit bit interface. The debugging device of claim 1, wherein the at least one switching signal is generated by connecting at least one of the ports to a display unit. A debugging method is applicable to a server, the server includes a control chip, and the debugging method includes: receiving a boot detection signal generated by the control chip; according to at least one switching signal and a format of multiple output interfaces Converting a message code of the power-on detection signal into one of formats conforming to at least one of the output interfaces The output interfaces are different from each other, and the output interfaces include a serial port interface, a parallel port interface, an internal integrated circuit and a display signal interface, and the debug signal converted by the information code.