TWI503942B - Circuit layout structure - Google Patents

Description

Circuit layout structure

The present invention relates to a circuit layout structure. In particular, the present invention relates to a particular circuit layout structure. In these circuit layout structures, the metal interconnects surrounded by the inter-metal dielectric layer are properly isolated from the metal pattern located in the scribe lines to reduce undesirable capacitive effects.

In the fabrication of semiconductor components, an etching process is often used to create a predetermined pattern in a predetermined layer of material. Figures 1 - 3 illustrate the process used in the prior art to create a predetermined pattern in a predetermined layer of material. First, please refer to FIG. 1 to provide a wafer 100. A plurality of layers of material have been pre-established above the wafer 100. For example, the interlayer dielectric layer 110 is on the germanium substrate 101, and a metal contact plug 111 is located in the interlayer dielectric layer 110 and surrounded by the interlayer dielectric layer 110. The inter-metal dielectric layer 120 is over the metal contact plugs 111 and covers the interlayer dielectric layer 110. The etch mask 130 is formed over the inter-metal dielectric layer 120 and has a predetermined pattern 131. The etch mask 130 can be a conductive mask of a composite layer, such as a metal mask containing titanium nitride and a composite material of Tetraethoxysilane (TEOS) and/or a low dielectric constant material, etc. Floor.

Next, referring to FIG. 2, the underlying metal interlayer dielectric layer 120 is etched in a plasma environment using a suitable etchant to transfer the predetermined pattern 131 downward into the metal interlayer dielectric layer 120 to define a metal wire. The trench 121 exposes the metal contact plug 111 in the interlayer dielectric layer 110 as shown in FIG. The trenches 121 formed by such etching processes can be used to form electrical connections of the metal contact plugs 111.

However, the inventors have observed that not all of the trenches 121 can smoothly expose the metal contact plugs 111 in the interlayer dielectric layer 110, as shown in FIG. In some areas, some of the etch residue 113 with a charge, such as a polymer compound, does not leave the trench 121 in a suitable etchant and plasma environment, so too much etch residue 113 is deposited in the trench 121. Excessive etch residue 113 blocks the bottom of the trench 121 such that the metal contact plugs 111 in the interlayer dielectric layer 110 are not exposed, resulting in an opening failure.

The inventors presume that one of the causes of excessive deposition of the etching residue 113 is that the electrostatic device (not shown) is often used to fix the wafer 100 during the etching step. Due to the static electricity generated by the electrostatic device, it is highly probable that a conductive metal mask 130, such as a titanium nitride mask, is induced through the substrate 101, and the metal pattern 114 located in the scribe line 103 is induced to form an unfavorable capacitance. Further, the excessively charged etch residue is attracted to the bottom of the trench 121 of the wafer region 102, so that the metal contact plug 111 underneath is not exposed, and the electrical connection cannot be effectively formed.

Therefore, there is still a need for a novel circuit layout structure, particularly when the metal interconnect is adjacent to a scribe line in which a metal pattern is arranged, and it is also necessary to avoid excessive etching residues which may block the trench and fail to expose the underlying metal contact plug. Potential problems to improve the yield of the etching step.

The present invention is to propose a novel circuit layout structure, which can avoid excessive etch residue clogging in the trench, making it difficult to expose the underlying metal contact plug, especially when the metal mask is arranged adjacent to the metal pattern. In the case of the channel, excessive etching residue can be prevented from being blocked in the trench in which the metal interconnect is to be formed, so that the metal interconnect is difficult to form an electrical connection with the underlying metal.

The invention firstly proposes a circuit layout structure comprising a metal interconnect, a metal interlayer dielectric layer, a dicing street and a metal pattern. The inter-metal dielectric layer surrounds the metal interconnect such that the area of the inter-metal dielectric layer is greater than 9 times the area of the metal interconnect in a given area. At the same time, the metal pattern is located in the scribe line and adjacent to the inter-metal interlayer dielectric layer and the metal interconnect, such that the scribe line is more than 250 microns from the metal interconnect.

The present invention secondly provides a circuit layout structure comprising a metal interconnect, a metal interlayer dielectric layer, a dicing street, and a metal pattern. The inter-metal dielectric layer surrounds the metal interconnect such that the area of the inter-metal dielectric layer is greater than 9 times the area of the metal interconnect in a given area. At the same time, the metal pattern is located in the scribe line, and the metal pattern is located in a given area of the dielectric layer and the metal interconnection between the adjacent metal layers, and the area of the metal pattern is less than 1/4 times the area of the given area.

The invention further proposes a circuit layout structure comprising a substrate, a shallow trench isolation, a metal pattern, a scribe line and an interlayer dielectric layer. The shallow trench isolation is located in the substrate, and the metal pattern in the scribe line is directly on the shallow trench isolation, so that the interlayer dielectric layer is on the substrate and surrounds the metal pattern.

The various circuit layout structures proposed by the present invention can properly isolate the metal interconnect region surrounded by the inter-metal dielectric layer and the metal pattern located in the scribe line, so that the metal mask and the adjacent metal pattern can be effectively reduced. The capacitive effect between.

The present invention provides a variety of novel circuit layout structures. In the circuit layout structure provided by the present invention, the metal mask and the metal pattern located in the scribe line can be appropriately isolated to reduce the charge sensing between the metal mask and the metal pattern. Therefore, it is possible to avoid that excessive etching residue is blocked in the trench during the etching step, hindering the etching process, making it difficult to expose the underlying metal contact plug. In particular, when the metal mask is adjacent to the dicing street in which the metal pattern is arranged, there is no excessive etch residue blocking in the trench of the metal interlayer dielectric layer for preparing the metal interconnect, thereby effectively avoiding the metal interconnect. It is difficult to form an electrical connection with the metal contact plug below.

Fig. 4A is a cross-sectional view showing a first embodiment of the circuit layout structure of the present invention. In the first embodiment of the present invention, the circuit layout structure 200 includes a substrate 201, an interlayer dielectric layer (ILD) 210, a metal contact plug 220, a dicing street 230, a metal pattern 240, and a metal layer. A dielectric layer (IMD) 250 and a metal interconnect 251. Substrate 201 can be a semiconductor substrate such as germanium. The metal interconnect 251 may be a damascene pattern, such as a single damascene pattern or a dual damascene pattern, and surrounded by a metal interlayer dielectric layer 250.

In the circuit layout structure 200, a metal pattern 240 is present in the scribe line 230. The interlayer dielectric layer 210 is on the substrate 201 and surrounds the metal pattern 240. Metal pattern 240 can comprise a metal, particularly tungsten. In addition, the interlayer dielectric layer 210 and the inter-metal dielectric layer 250 on the interlayer dielectric layer 210 may respectively contain one or more dielectric materials, such as hafnium oxide, hafnium oxynitride, hafnium nitride, tetraethoxydecane. With low dielectric constant materials...etc.

The metal pattern 240 is located adjacent to the scribe line 230, but adjacent to the interlayer dielectric layer 210 and the metal interconnect 251. The circuit layout structure of the present invention has fewer metal interconnects. For example, as shown in FIG. 4B, in a given region 260, the area of the inter-metal dielectric layer 250 is larger than the area of the metal interconnect 251. More than double, the metal interconnect 251 only occupies less than 10% of the given area 260. In this case, if a conventional etching method is used, the area of the conductive mask (not shown) used is extremely large, resulting in a conductive mask. A severe capacitive effect occurs between the metal pattern 240 and the etch residue during etching.

Therefore, in order to solve the capacitive effect problem, one of the features of the circuit layout structure of the present invention is that the metal interconnect 251 is arranged such that the metal interconnect 251 has a distance d from the dicing street 230 of at least 250 microns. In this way, a sufficiently large distance that the trench during etching, that is, the metal interconnect 251 of FIG. 4A, is minimized by the possible capacitive effect.

The analysis results show that, as shown in FIG. 4C, if the metal mask 252 at the time of etching is located in the wafer area 280 adjacent to the dicing street 230, the metal pattern 240 is present in the vicinity of the scribe line 230 adjacent to the metal mask 252, particularly large. A block or a large number of tungsten is designed because the distance d is at least 250 micrometers, which reduces the charge induction, so that no excessive etching residue is deposited in the bottom of the trench 253, and the interlayer dielectric layer can be exposed. The result of the metal contact plug 220 in 210.

The present invention secondly proposes another circuit layout structure. Fig. 5A is a cross-sectional view showing a second embodiment of the circuit layout structure of the present invention. In a second embodiment of the present invention, the circuit layout structure 300 includes a substrate 301, an interlayer dielectric layer (ILD) 310, a metal contact plug 320, a dicing street 330, a metal pattern 340, and a metal layer. A dielectric layer (IMD) 350 and a metal interconnect 351. Substrate 301 can be a semiconductor substrate such as tantalum. The metal interconnect 351 can be a damascene structure, such as a single damascene pattern or a dual damascene pattern, and the inter-metal dielectric layer 350 is surrounded.

In the circuit layout structure 300, there is a metal pattern 340 among the dicing streets 330. The interlayer dielectric layer 310 surrounds the metal contact plug 320 and the metal pattern 340, respectively. Metal pattern 340 can comprise a metal, particularly tungsten. In addition, the interlayer dielectric layer 310 and the inter-metal dielectric layer 350 may respectively comprise one or more dielectric materials, such as yttrium oxide, ytterbium oxynitride, tantalum nitride, tetraethoxy decane and a low dielectric constant material. .and many more.

Also, referring to Fig. 5B, a top view of a second embodiment of the circuit layout structure of the present invention is illustrated. A metal interlayer dielectric 350 surrounds the metal interconnect 351. The metal interconnect 351 is a patterned metal layer formed by etching a metal interlayer dielectric 350 step plus a deposition metal and a planarization step using a conductive mask (not shown). The metal interconnect layer 351 has a bent shape. The location of the metal pattern 340 is located in the scribe line 330, and a portion of the metal pattern 340 is likely to be adjacent to the inter-metal dielectric 350 and the metal interconnect 351. The circuit layout structure of the present invention has fewer metal interconnects. For example, as shown in FIG. 5B, in a given area 360, the area of the inter-metal dielectric layer 350 is larger than the area of the metal interconnect 351. More than double, the metal interconnect 351 only occupies less than 10% of the given area 360. In this case, if a conventional etching method is used, the area of the conductive mask used is extremely large, which will cause the conductive mask and the metal pattern 340. A severe capacitive effect occurs, which in turn causes etch residue to become clogged during etching.

Therefore, the circuit layout structure of the present invention adopts a method of reducing the area occupied by the metal pattern 340 to reduce the capacitance effect. As shown in FIG. 5B, the dielectric interlayer 350 and the metal interconnection are adjacent to each other in a given region 370. The metal pattern 340 of 351, the area of the metal pattern 340 is much smaller than the area of a given area 370. As such, there are no excessive metal patterns 340 in a given region 370 that can create undesirable capacitive effects with adjacent metal masks (not shown). Preferably, the area of the metal pattern 340 is less than or equal to a quarter of the area of the given area 370. The given area 370 refers to a predetermined area containing one of the metal patterns 340. The given area 370 is preferably rectangular.

The analysis results show that, as shown in FIG. 5C, if the metal mask 352 at the time of etching is located in the wafer area 380 adjacent to the dicing street 330, and the metal pattern 340 is located adjacent to the metal mask 352 in the dicing street 330, it may be because The aforementioned capacitive effect is most pronounced, so it is most likely to deposit too much etching residue at the bottom of the trench 353. However, the structural design of the present invention does not have such a problem that the metal contact 320 in the interlayer dielectric layer 310 can be exposed. The metal mask 352 in the dicing street 330 may also be designed with a dummy ring 354 to reduce the aforementioned capacitive effect, as desired.

The metal pattern 340 can be any metal pattern that would be located in the scribe line 330, typically formed of metal. For example, the metal pattern 340 may be a contact alignment mark, a contact AIM mark, an SCM mark, an active area box logo, or a CD dimension mark. Logo) or other metal graphics, such as the cross mark...etc. The various patterns above can be used in different ways to reduce the total area.

For example, when the number of contact alignment marks is large, for example, when 9 marks are used, the number of marks can be appropriately reduced, for example, from 9 to 7, without affecting the function. Reduce the total area of the mark. Or remove it completely. On the other hand, for the AA mark or the CD mark, the font can be reduced, or the dot pattern can be used instead of the solid pattern to reduce the total area. Also, like a cross mark, you can use a hollow graphic instead of a solid graphic to reduce the total area. In other words, as long as the function is not affected, a variety of different possible methods can be used to reduce the total area of the mark.

The present invention further proposes another circuit layout structure. Fig. 6 is a cross-sectional view showing a third embodiment of the circuit layout structure of the present invention. In a third embodiment of the present invention, the circuit layout structure 400 includes a substrate 401, a shallow trench isolation 402, an interlayer dielectric layer 410, a metal contact plug 420, a scribe line 430, and a metal pattern 440. An inter-metal dielectric layer 450 and a metal interconnect 451. Substrate 401 can be a semiconductor substrate such as tantalum.

In the circuit layout structure 400, shallow trench isolations 402 are located in the substrate 401. In addition, the circuit layout structure 400 also has a scribe line 430 such that the scribe line 430 has a metal pattern 440 therein. The metal pattern 440 is located directly on the shallow trench isolation 402. Metal pattern 440 can comprise a metal, particularly tungsten. The interlayer dielectric layer 410 is then over the substrate 401 and surrounds the metal pattern 440 and the metal contact plug 420, respectively. Conventional steps can be used to create shallow trench isolation 402, and only the reticle pattern used to create shallow trench isolation 402 can be modified, which makes the circuit layout structure 400 of the present invention compatible with conventional semiconductor processes.

The metal interconnect 451 is located on the interlayer dielectric layer 410 and adjacent to the metal pattern 440. The metal interconnect 451 is also surrounded by an inter-metal dielectric layer 450 that is also on the interlayer dielectric layer 410. The metal interconnects 451 and the inter-metal dielectric layer 450 may also together form a damascene structure, such as a single damascene pattern or a dual damascene pattern.

The interlayer dielectric layer 410 and the inter-metal dielectric layer 450 may respectively contain one or more dielectric materials such as hafnium oxide, hafnium oxynitride, tantalum nitride, tetraethoxydecane, and a low dielectric constant material, etc. Wait. Located between the substrate 401 and the metal interconnect 451 is a metal contact plug 420. The metal contact plug 420 will directly contact the metal interconnect 451.

The analysis results show that if the metal interconnect 451 in the inter-metal dielectric layer 450 is located adjacent to the wafer region 480 of the dicing street 430, and the metal pattern 440 is located adjacent to the metal interconnect 451 in the dicing street 430, it may be because The aforementioned capacitive effect is most pronounced, resulting in the inability of metal contact plugs 420 located in interlayer dielectric layer 410 to be exposed.

In addition, an electrostatic device (not shown) is often used to fix the wafer during the etching step. Due to the static electricity generated by the electrostatic device, it is highly probable that a conductive mask (not shown) is induced through the substrate 401, forming an unfavorable capacitance with the metal pattern 440 located in the scribe line 430, thereby attracting excessively charged The etching residue is deposited in a trench (not shown). Since the metal pattern 440 of the present invention is directly on the shallow trench isolation 402, the shallow trench isolation 402 isolates the substrate 401 from the metal pattern 440 such that the metal pattern 440 is not easily induced by the substrate 401.

As a result, due to the electrical isolation of the shallow trench isolation 402, the conductive mask (not shown) and the metal pattern 440 located in the scribe line 430 are less likely to form a capacitance. Even if a conductive mask (not shown) forms a capacitance with the metal pattern 440, the resulting capacitive effect is relatively small due to the thickness of the shallow trench isolation 402.

The present invention provides a plurality of circuit layout structures capable of reducing the capacitance effect between a metal interconnect and an adjacent metal pattern. The circuit layout structure of the invention has the advantages of increasing the etching yield, avoiding the accumulation of etching residues, and causing a smashing window.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Wafer

101. . . Substrate

102. . . Wafer area

103. . . cutting line

110. . . Interlayer dielectric layer

111. . . Metal graphics

121. . . Contact window

113. . . Etch residue

114. . . Metal graphics

120. . . Metal interlayer dielectric layer

130. . . Etched mask

131. . . Predetermined pattern

200/300/400. . . Circuit layout structure

201/301/401. . . Substrate

210/310/410. . . Interlayer dielectric layer

220/320/420. . . Metal contact

230/330/430. . . cutting line

240340/440. . . Metal graphics

250/350/450. . . Metal interlayer dielectric layer

251/351/451. . . Metal interconnect

252/352. . . Metal mask

253/353. . . ditch

260/360/370. . . Given area

280/380/480. . . Wafer area

354. . . Pseudo ring

402. . . Shallow trench isolation

Figures 1 - 3 illustrate the process used in the prior art to create a predetermined pattern in a predetermined layer of material.

Fig. 4A is a cross-sectional view showing a first embodiment of the circuit layout structure of the present invention.

Fig. 4B is a top view showing a first embodiment of the circuit layout structure of the present invention.

Fig. 4C is a cross-sectional view showing the post-etched structure of the first embodiment of the circuit layout structure of the present invention.

Fig. 5A is a cross-sectional view showing a second embodiment of the circuit layout structure of the present invention.

Fig. 5B is a top view showing a second embodiment of the circuit layout structure of the present invention.

Fig. 5C is a cross-sectional view showing the structure of the second embodiment of the circuit layout structure of the present invention.

Fig. 6 is a cross-sectional view showing a third embodiment of the circuit layout structure of the present invention.

400‧‧‧Circuit layout structure

401‧‧‧Substrate

402‧‧‧Shallow trench isolation

410‧‧‧Interlayer dielectric layer

420‧‧‧Metal contact

430‧‧ ‧ cutting road

440‧‧‧metal graphics

450‧‧‧Metal interlayer dielectric layer

451‧‧‧Metal interconnection

480‧‧‧ wafer area

Claims (13)

A circuit layout structure comprising: a metal interconnect; an inter-metal dielectric layer (IMD) surrounding the metal interconnect, wherein an area of the inter-metal dielectric layer is larger than the metal in a given region 9 times the area of the connection area; a scribe line extending from the metal interconnect by more than 250 microns; and a metal pattern located in the scribe line adjacent to the inter-metal interlayer dielectric layer and the metal interconnect. The circuit layout structure of claim 1, which has a mosaic structure. A circuit layout structure comprising: a metal interconnect; an inter-metal dielectric layer surrounding the metal interconnect, wherein a dielectric region of the metal layer is larger than the metal interconnect region in a given region 9 times; a scribe line adjacent to the metal interlayer dielectric and the metal interconnect; and a metal pattern located in the scribe line, wherein a dielectric region between the metal layer and the metal interconnect is located adjacent to the metal layer The metal pattern is located in the given area and the area of the metal pattern is less than 1/4 times the area of the given area. The circuit layout structure of claim 3 has a mosaic structure. The circuit layout structure of claim 3, wherein the metal interconnect has a curved shape. The circuit layout structure of claim 3, wherein the metal pattern comprises a hollow pattern. The circuit layout structure of claim 3, wherein the metal pattern comprises a dot pattern. The circuit layout structure of claim 3, wherein the given area is rectangular. A circuit layout structure comprising: a substrate; a shallow trench isolation, located in the substrate; a metal pattern located in a scribe line and directly on the shallow trench isolation; and an interlayer dielectric layer at the base The metal pattern is placed around the metal. The circuit layout structure of claim 9, further comprising: a metal interconnect on the interlayer dielectric layer adjacent to the metal pattern; and a metal interlayer dielectric layer on the interlayer dielectric layer and surrounding the metal Internal connection. The circuit layout structure of claim 10, wherein the metal interconnect and the inter-metal dielectric layer form a damascene structure. The circuit layout structure of claim 10, further comprising: a metal contact plug located between the substrate and the metal interconnect and directly contacting the metal interconnect. The circuit layout structure of claim 9, wherein the shallow trench isolating the substrate from the metal pattern.