TWI502633B - Method for forming metal gate - Google Patents

Description

Method of forming a metal gate

This invention relates to a method of forming a metal gate. More particularly, the present invention relates to the use of selective etching to remove undoped replacement materials without substantially affecting the doped replacement material to form substantially undercut-free pockets, and then The method of forming a metal gate substantially without the undercut recess can avoid the problem of undercut caused by lateral erosion of the recess during etching.

In the fabrication of semiconductor components, etching methods are often used to define the location of the desired components. For example, in the manufacture of static random access memory (SRAM), it is necessary to form a set of gate structures adjacent to each other. In general, if a metal gate structure is to be formed, two etching steps are typically used in succession to define the locations of the first metal and second metal gate structures, respectively.

During the first etching process, typically a wet etching step, a mask is used to protect areas that do not require etching to limit the range of action of the etchant. In fact, despite the protection of the mask, in addition to removing the target material downwards, the etchant inevitably erodes the target material laterally, particularly the target material that removes the edge of the mask. As a result of these lateral erosions, a hollow undercut structure is formed beneath the mask after the etching step is completed. The hollow undercut structure will distort the shape of the desired recess and also impair the performance of adjacent semiconductor components.

Therefore, there is a need for a solution that can substantially eliminate the surrounding material during the removal of the target material, and can form a perfect recess that is substantially free of undercut.

The present invention thus proposes a solution that does not substantially affect the surrounding material during the removal of the target material. Therefore, the method of the present invention can be used to form a perfect recess that is substantially free of undercut, particularly for forming a recess for a metal gate.

The present invention thus proposes a method of forming a metal gate. First, a substrate is provided. Second, a dummy material is deposited integrally on the substrate. Thereafter, a dopant is selectively implanted in the replacement material to form a dopant region. Next, a portion of the replacement material is removed, and a portion of the substrate is exposed and an alternate gate is formed. The replacement gate includes a dopant region between the first region and the second region. Further, an interlayer dielectric layer surrounding one of the replacement gates is formed on the exposed substrate. Continuing, a selective etching step is performed to remove the first region of the replacement gate to form a first recess. The etching step does not substantially remove the second region from the dopant region such that the first recess does not extend to the dopant region. A first set of materials is then used to fill the first pocket to form a first metal gate.

In an embodiment of the invention, the dopant may be a Group III (III) element or carbon. In another embodiment of the invention, a mask may be used to cover the second region of the replacement material for the selective etching step. In still another embodiment of the present invention, after the first metal gate is completed, the second region of the replacement gate and the dopant region are further removed to form a second recess, and the second material group is further filled. The second recess is formed to form a second metal gate adjacent to the first metal gate. In still another embodiment of the present invention, the second region and the dopant region of the replacement gate may be removed simultaneously or before and after. In still another embodiment of the present invention, the first metal gate may be one of a PMOS and an NMOS, and the second metal gate is the other one. The first metal gate and the second metal gate may be located in a static random access memory (SRAM).

The present invention uses selective etching to remove undoped replacement material without substantially affecting the doped replacement material to form a substantially undercut cavity. Then, a recess that is substantially free of undercut is suitable for constructing a good metal gate. The use of the method of the present invention avoids the lateral erosion associated with the pockets during etching, resulting in underlying undercutting of the edges of the mask.

Referring to Figures 1-10, exemplary steps of a method of forming a metal gate of the present invention are illustrated. Referring first to Figure 1, a substrate 101 is provided. The substrate 101 is typically a semiconductor material such as a germanium wafer or a Silicon-On Insulator (SOI). Next, a dielectric layer and a dummy material 110 are integrally formed on the substrate 101 in this order. The dielectric layer comprises a general dielectric constant dielectric layer 102 and/or a high-k dielectric layer 103, and the replacement material 110 is currently used to temporarily replace the position of a future metal gate (not shown), so it is a sacrifice. (sacrificial) material, for example, may be undoped germanium. The alternative material 110 having a suitable thickness can be blanketed using conventional deposition methods. In addition, a structure of a desired doping well, shallow trench isolation (STI) 104, and the like may be formed in the substrate 101, and will not be further described herein. A barrier/etch stop layer as desired may also be formed between the replacement material 110 and the high-k dielectric layer 103. The material of this layer may be TiN, SiN, etc. This layer can increase the matching between the alternative material 110 and the high-k dielectric layer 103 material and/or serve as an etch stop layer when the replacement material 110 is removed in a subsequent step.

Thereafter, referring to FIG. 2, a suitable dopant 121, such as a group III (III) element such as boron or aluminum, or carbon is selectively implanted in the substitute material 110 to form a dopant region 120. The position of the dopant region 120 is preferably planned in advance, and is located on a boundary region of a metal gate that is different in incoming and adjacent, such as a PMOS and an NMOS (not shown). For example, a mask 131 such as a photoresist may be used to protect other regions prior to implantation, and then the desired dopant 121 is implanted in the exposed region. Subsequently, the mask 131 is removed.

Next, referring to FIG. 3, a portion of the replacement material 110 is removed, and a portion of the substrate 101 is exposed, so that the replacement material 110 becomes an island-like replacement gate 110. The replacement gate 110 includes a first region 111, a second region 112, and a dopant region 120 between the first region 111 and the second region 112, that is, the dopant region 120 does not overlap with the first region 111 or the second region. . The first region 111 and the second region 112 are used to form predetermined PMOS and NMOS. The shallow trench isolation 104 is an isolation structure of the first region 111 and the second region 112 portion. The dopant region 120 will be located on an isolated isolation structure, such as shallow trench isolation 104. For example, the alternative gate 110 can be protected with another mask 132 while the excess portion of the replacement material 110 is removed via an etching step. When the etching is completed, the mask 132 can be temporarily retained. The mask 132 may comprise a metallic material or a dielectric material such as titanium nitride, tantalum nitride or tantalum carbide.

Referring again to FIG. 4, after the replacement of the gate 110, the desired source/drain doping step can be performed as needed, thus forming a substrate 101 exposed on both sides of the replacement gate 110. Source/bungee 140 required. Preferably, a plurality of source/drain electrodes 140 of different conductivity types are respectively formed in the substrate 101 exposed on both sides of the first region 111 and the second region 112 of the replacement gate 110. At this time, the mask 132 protects the replacement gate 110 in the source/drain doping step without participating in the doping step. In addition, depending on the product specifications and process requirements, the present embodiment may further form a structure of a desired sidewall substructure, a shallow doped region, a self-aligned metal germanide, and/or a recessed epitaxial layer. I will not repeat them here.

Referring to FIG. 5, then, an interlayer dielectric layer 150 is initially formed to cover the exposed substrate 101 while surrounding the replacement gate 110. However, the interlayer dielectric layer 150 does not cover the replacement gate 110. For example, the interlayer dielectric layer 150 can be formed to completely cover the exposed substrate 101, the mask 132, and the replacement gate 110. Then, a planarization process is performed to remove a portion of the interlayer dielectric layer 150, so that the mask 132 is exposed. Therefore, the interlayer dielectric layer 150 has approximately the same height as the mask 132. Alternatively, the mask 132 is removed when a portion of the interlayer dielectric layer 150 is removed, so the interlayer dielectric layer 150 has approximately the same height as the replacement gate 110, as shown in FIG.

Continuing, referring to FIG. 6, a selective etching step is performed to remove the first region 111 of the replacement gate 110 to form the first recess 113. For example, an etch mask 133 may be used to completely cover the second region 112, or even a portion of the dopant region 120, but completely expose the first region 111. The selective etching step has a relatively high etch rate for the undoped region, i.e., the first region 111, so that the second region 112 protected by the etch mask 133 is not substantially removed and the etch rate is relatively low. The dopant region 120. Therefore, the first recess 113 does not extend to the dopant region 120, so there is no disadvantage of lateral etching to create undercut under the etch mask 133. The term "substantially not removing" the dopant region 120 having a relatively low etching rate as used herein means that the etching ratio of the first region 111 to the dopant region 120 is greater than at least in this selective etching step. 50. These etching rate ratios vary depending on the etchant and the etching temperature.

In the present embodiment, the etching step of selectively removing the first region 111 in the replacement gate 110 may be performed using a wet etching method, for example, using an alkaline etchant. Suitable etchants can be diluted hydrofluoric acid (DHF) with ammonia or tetramethylammonium hydroxide (TMAH). For example, pre-etching is performed at room temperature using diluted hydrofluoric acid (DHF). Thereafter, the first region 111 is selectively removed completely using an alkaline etchant to form the first recess 113. After the etching is completed, the etch mask 133 can be removed. Alternatively, an etching step of selectively removing the first region 111 in the replacement gate 110 may be performed by using dry etching and wet etching, for example, using dry etching and then wet etching.

Then, referring to FIG. 7, the first material group 161 is used to fill the first cavity 113 to form the first metal gate 160. If the excess first material group 161 covers the interlayer dielectric layer 150, a planarization process may be performed to remove the excess first material group 161 to expose the interlayer dielectric layer 150. The first material group 161 may include a work function gate metal layer 163 and a low resistance metal 164. The work function gate metal layer 163 may be a single metal layer or a composite metal layer. The first metal gate 160 can be adjusted to have an appropriate work function via a suitable combination of the work function gate metal 163 in the first material group 161. Suitable high-k dielectric layers 103 and work function gate metal materials 163 are known to those skilled in the art.

In another embodiment, please refer to FIG. 7A, which illustrates a cross-sectional view. A U-shaped high-k dielectric layer 103 may be formed prior to removing the first region 111 in the replacement gate 110 and before filling the first recess 113 with the first material group 161. The function gate metal layer 163 and the low resistance metal 164 are then successfully formed. In this case, the high-k dielectric layer originally formed under the replacement material is not formed.

Next, referring to FIG. 8 which illustrates the side view of the other direction, the etching step is performed again, and the second region 112 and the dopant region 120 in the replacement gate 110 are removed to form the second recess 115. The second region 112 and the dopant region 120 in the replacement gate 110 may be removed using a dry etch and wet etch, or directly using a wet etch, such as an alkaline etchant, without masking. . Suitable etchants may be tetramethylammonium hydroxide (TMAH) or other tetraalkylammonium hydroxide solution at a higher temperature and a higher concentration (selective etching with respect to the first region 111). .

Then, referring to FIG. 9, the second material set 166 is used to fill the second recess 115 to form the second metal gate 165. If the excess second material set 166 covers the interlayer dielectric layer 150, a planarization process can also be performed to remove the excess second material set 166 to expose the interlayer dielectric layer 150. The second material set 166 can include a work function gate metal layer 167 and a low resistance metal 168. The work function gate metal layer 167 can be a single metal layer or a composite metal layer. The second material set 166 can be adjusted to have an appropriate work function via a suitable combination of work function gate metals 167 in the second material set 166.

If the first metal gate 160 is one of the PMOS and the NMOS, and the second metal gate 165 is the other one, correspondingly, the source of the first metal gate 160 and the second metal gate 165 The /poles 140 have corresponding P-type or N-type conductivity, respectively. Thus, the first metal gate 160 and the second metal gate 165 may be gates adjacent to the SRAM, and the first metal gate 160 is in direct contact with the second metal gate 165. The work function gate metals are electrically connected to each other. Suitable high-k dielectric layer 103 and work function gate metal material 163/167 are known to those skilled in the art. For example, high-k dielectric layer 103 is selected from the group consisting of bismuth citrate (HfSiO) and citric acid. Niobium oxynitride (HfSiON), hafnium oxide (HfO), lanthanum oxide (LaO), lanthanum aluminate (LaAlO), zirconia (ZrO), zirconium oxynitride (ZrSiO), hafnium zirconate (HfZrO) or In combination, the N-type work function gate metal material is preferably selected from the group consisting of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum nitride (TaSiN), and aluminum. The P-type work function gate metal material is preferably selected from the group consisting of titanium nitride (TiN), tungsten (W), tungsten nitride (WN), platinum (Pt), nickel (Ni), ruthenium (Ru), and tantalum carbonitride. (TaCN) or a group of tantalum oxynitride (TaCNO).

After the first metal gate 160 and the second metal gate 165 have been completed, the contact plugging for electrically connecting the source/drain 140 of the first metal gate 160 and the second metal gate 165 can be continued. Plug 170. For example, referring to FIG. 10, an interlayer dielectric layer 150 is formed to completely cover the first metal gate 160 and the second metal gate 165, and then a contact hole (not shown) exposing the source/drain 140 is formed. Contact plug 170 is then completed by filling the contact hole with a suitable conductive material. A metal halide (not shown) may be formed in advance between the contact plug 170 and the source/drain 140 as occasion demands.

Referring to Figures 11-17, another exemplary step of forming a metal gate of the present invention is illustrated, which is characterized by the use of a photoresist to define a pattern of a hard mask that is filled with a low-resistance metal while filling the original replacement material. a region to form a first metal gate and a second metal gate. First, please refer to Fig. 11 and Fig. 12 at the same time. The tangential line A-A' in Fig. 11 is expanded to show a cross-sectional view of Fig. 12. A substrate 101 is provided. The substrate 101 is typically a semiconductor material such as a germanium wafer or a Silicon-On Insulator (SOI). The substrate 101 is covered by an interlayer dielectric layer 150. The substrate 101 includes a source/drain 140 and a shallow trench isolation 104. An adjacent replacement material 110 has been formed on the substrate 101, and an active region 105 is additionally provided on the substrate 101. Where the alternative material 110 meets the active region 105 is where the MOS gate is located.

The replacement gate 1110 includes an alternative material 110, a sealing layer 116 including tantalum nitride, a sidewall spacer 117, an etch stop layer 118, and a general dielectric constant dielectric layer 102 or a high-k dielectric layer 103 as occasion demands. . The replacement gate 2110 also includes an alternative material, a sealing layer comprising tantalum nitride, a sidewall spacer, an etch stop layer, and a dielectric layer as desired, but is not shown for simplicity. The side wall sub-117 can be a single or composite structure.

The substrate 101 has been previously subjected to chemical mechanical polishing such that the replacement gate 1110/2110 is flush with the top surface of the interlayer dielectric layer 150, and the top surface of the portion of the gate 1110/2110 is exposed. The alternative material 110 is currently used to temporarily replace the location of future metal gates (not shown) and is therefore a sacrificial material, such as may be undoped germanium. A structure in which a desired doping well or the like is additionally formed in the substrate 101 will not be described herein.

A barrier/etch stop layer as desired may also be formed between the replacement material 110 and the high-k dielectric layer 103. The material of this layer may be TiN, SiN, etc. This layer can increase the matching between the alternative material 110 and the high-k dielectric layer 103 material and/or serve as an etch stop layer when the replacement material 110 is removed in a subsequent step. The alternate gate 1110 can be one of an NMOS or a PMOS, and the alternate gate 2110 is the other.

Fig. 12A is a cross-sectional view showing a tangent B-B' in Fig. 11. Referring to FIG. 12A, a suitable dopant 121, such as a group III (III) element such as boron or aluminum, or carbon is selectively implanted in the replacement material 110 to form a dopant region 120. The location of the dopant region 120 is preferably pre-programmed to be located on a boundary region of a metal gate that is different in incoming and adjacent, such as a PMOS and an NMOS (not shown), such as over the shallow trench isolation 104. For example, a mask such as a photoresist (not shown) may be used to protect other areas prior to implantation, and then the desired dopant 121 is implanted in the exposed area. Then, remove the mask.

Thereafter, referring to FIG. 13, a mask 131, such as a titanium nitride hard mask, is deposited on the interlayer dielectric layer 150 in a comprehensive manner, and then an oxide 134 such as cerium oxide is deposited in a comprehensive manner. A patterned photoresist 135 is also used to selectively cover one of the alternate gates 1110/2110 (NMOS or PMOS). FIG. 13 illustrates the patterned photoresist 135 covering the replacement gate 2110. Next, the patterned photoresist 135 can be used to pattern the mask 131, for example, using an etching step to transfer the pattern of the photoresist 135 onto the mask 131, and then the photoresist 135 can be removed.

Next, referring to FIG. 14, the replacement material 110 of one of the exposed replacement gates 1110 or 2110 is removed by an etching step via the protection of the mask 131. Due to the protection of the mask 131, only the replacement material 110 of one of the alternative gates 1110 and 2110 will be removed. Figure 14 illustrates that only the replacement material 110 in the replacement gate 1110 is removed to form the first pocket 113, while the replacement material 110 in the replacement gate 2110 is retained.

Fig. 14A is a cross-sectional view showing a tangent B-B' in Fig. 11. Due to the protection of the mask 131 and the dopant region 120, the etching step of this time does not substantially remove the replacement gate 2110 protected by the etch mask 131 and the dopant region 120 and the dopant region having a relatively low etching rate. 120. Therefore, the first recess 113 does not extend to the dopant region 120, so there is no disadvantage of lateral etching to create undercut under the etch mask 131.

The term "substantially not removing" the dopant region 120 having a relatively low etching rate as used herein means that the etching ratio of the first region 111 to the dopant region 120 is greater than at least in this selective etching step. 50. These etching rate ratios vary depending on the etchant and the etching temperature.

In the present embodiment, the etching step of selectively removing the replacement gate 1110 may be performed using a wet etching method, for example, using an alkaline etchant. Suitable etchants can be diluted hydrofluoric acid (DHF) with ammonia or tetramethylammonium hydroxide (TMAH). For example, pre-etching is performed at room temperature using diluted hydrofluoric acid (DHF). Thereafter, the replacement gate 1110 is selectively removed completely using an alkaline etchant to form the first recess 113. Alternatively, an etching step of selectively forming the first recess 113 in the gate 1110 may be performed by dry etching and wet etching, for example, using dry etching and then wet etching.

Then, referring to Fig. 15, under the protection of the etching mask 131, the first work function gate metal layer 163 can be filled in the first cavity 113. Fig. 15A is a cross-sectional view showing a tangent B-B' in Fig. 11. The first work function gate metal layer 163 also covers the mask 131 if a comprehensive deposition is used. Depending on the situation, at this time, according to the plan for establishing PMOS or NMOS, the corresponding first work function gate metal layer 163 may be filled. Therefore, the first work function gate metal layer 163 may be an N-type work function gate metal material or a P-type work function gate metal material, and the N-type work function gate metal material is preferably selected from titanium nitride (TiN). a group consisting of tantalum carbide (TaC), tantalum nitride (TaN), tantalum nitride (TaSiN), and aluminum. The P-type work function gate metal material is preferably selected from titanium nitride (TiN), tungsten. (W), a group consisting of tungsten nitride (WN), platinum (Pt), nickel (Ni), ruthenium (Ru), tantalum carbonitride (TaCN) or tantalum oxynitride (TaCNO).

Referring to FIG. 16, then, another patterned photoresist 135 is used to cover the portion not protected by the mask 131, so the patterned photoresist 135 covers the first recess 113 and a portion of the first work function. Gate metal layer 163. Fig. 16A is a cross-sectional view showing a tangent B-B' in Fig. 11. A patterned anti-reflective layer (BARC) may be included in the patterned photoresist 135 as needed.

Continuing, the patterned photoresist 135 is used as a mask to strip the exposed first work function gate metal layer 163 and the mask 131. Thus, another alternative gate (illustrated as an alternate gate 2110 in the figure) and the replacement material 110 therein are exposed. Subsequently. The patterned photoresist 135 can be removed.

Then, referring to FIG. 17, the exposed substitute material 110 and the dopant region 120 are completely removed to form the second recess 115. Next, a second work function gate metal 167 layer is used to fill the second cavity 115, and at the same time, it is also filled into the first cavity 113. Then, a low-resistance metal 164 is used to simultaneously fill the regions occupied by the original replacement gates 1110 and 2110, that is, the first recess 113 and the second recess 115, to form the first metal gate 160 and the second, respectively. Metal gate 165.

Next, after removing the excess first work function gate metal 163, the second work function gate metal layer 167 layer and the low resistance metal 164, for example, using a chemical mechanical polishing method, the required first metal gate is completed. The pole 160 and the second metal gate 165. If the first metal gate 160 is one of the PMOS and the NMOS, the second metal gate 165 is the other one, and correspondingly, the source of the first metal gate 160 and the second metal gate 165 The /poles 140 have corresponding P-type or N-type conductivity, respectively. Thus, the first metal gate 160 and the second metal gate 165 can be gates adjacent to the SRAM.

Suitable high-k dielectric layer 103 and work function gate metal material 163/167 are known to those skilled in the art. For example, high-k dielectric layer 103 is selected from the group consisting of bismuth citrate (HfSiO) and citric acid. Niobium oxynitride (HfSiON), hafnium oxide (HfO), lanthanum oxide (LaO), lanthanum aluminate (LaAlO), zirconia (ZrO), zirconium oxynitride (ZrSiO), hafnium zirconate (HfZrO) or In combination, the N-type work function gate metal material is preferably selected from the group consisting of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum nitride (TaSiN), and aluminum. The P-type work function gate metal material is preferably selected from the group consisting of titanium nitride (TiN), tungsten (W), tungsten nitride (WN), platinum (Pt), nickel (Ni), ruthenium (Ru), and tantalum carbonitride. (TaCN) or a group of tantalum oxynitride (TaCNO).

After the first metal gate 160 and the second metal gate 165 have been completed, the contact plugging for electrically connecting the source/drain 140 of the first metal gate 160 and the second metal gate 165 can be continued. Plug 170. For example, please refer to Figure 10.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

101. . . Substrate

102. . . General dielectric constant dielectric layer

103. . . High dielectric constant dielectric layer

104. . . Shallow trench isolation

105. . . Active area

110. . . Alternative material

110. . . Alternative gate

1110. . . Alternative gate

2110. . . Alternative gate

111. . . First area

112. . . Second area

113. . . First pocket

115. . . Second pocket

116. . . Sealing layer

117. . . Side wall

118. . . Etch stop layer

120. . . Doping region

121. . . Doping

131. . . Mask

132. . . Mask

133. . . Etched mask

134. . . Oxide

135. . . Photoresist

140. . . Source/bungee

150. . . Interlayer dielectric layer

160. . . First metal gate

161. . . First material group

163‧‧‧Work function gate metal layer

164‧‧‧Low-resistance metal

165‧‧‧Second metal gate

166‧‧‧Second material group

167‧‧‧Work function gate metal layer

168‧‧‧Low-resistance metal

170‧‧‧Contact plug

1-10 illustrate exemplary steps of a method of forming a metal gate of the present invention.

Figures 11-17 illustrate exemplary steps of a method of forming a metal gate of the present invention.

101. . . Substrate

102. . . General dielectric constant dielectric layer

103. . . High dielectric constant dielectric layer

110. . . Alternative gate

113. . . First pocket

120. . . Doping region

133. . . Etched mask

140. . . Source/bungee

150. . . Interlayer dielectric layer

Claims (22)

A method of forming a metal gate, comprising: providing a substrate; depositing a dummy material integrally on the substrate; selectively implanting a dopant in the replacement material to form a dopant region After forming the dopant region, removing a portion of the replacement material to expose a portion of the substrate and forming an alternate gate, the replacement gate including a first region, a second region, and the dopant region; Forming an interlayer dielectric layer around the replacement gate on the exposed substrate; performing a selective etching step to remove the replacement gate without substantially removing the dopant region and the second region The first region is formed to form a first recess such that the first recess does not extend substantially to the dopant region; and the first recess is filled into the first recess to form a The first metal gate. A method of forming a metal gate as claimed in claim 1, wherein the substitute material comprises germanium. A method of forming a metal gate as claimed in claim 1, wherein the dopant is selected from the group consisting of a tri-family element and carbon. A method of forming a metal gate as claimed in claim 1, wherein a first mask is used to define the dopant region. A method of forming a metal gate as claimed in claim 1, wherein in the removing portion of the replacement material, a second mask is used to cover the replacement material to assist in forming the replacement gate. A method of forming a metal gate according to claim 5, wherein after the removing step, further comprising: performing a source/drain doping step, and forming a group in the substrate exposed by the replacement gate a source/drain, wherein the second mask covers the replacement gate in the source/drain doping step. A method of forming a metal gate as claimed in claim 1, wherein the selective etching step is performed using a wet etch. A method of forming a metal gate as in claim 7, wherein the wet etching uses an alkaline etchant. A method of forming a metal gate as claimed in claim 1, wherein the first recess is substantially free of undercut. A method of forming a metal gate according to claim 1, wherein the first material group comprises a low resistance metal and a first work function material. The method of claim 1, wherein the method further comprises: removing the second region of the replacement gate and the dopant region to form a second recess; A second set of materials is used to fill the second recess to form a second metal gate. A method of forming a metal gate as claimed in claim 11 while removing the second region of the replacement gate from the dopant region. As claimed in claim 11, the method of forming a metal gate periodically removes the second region of the replacement gate from the dopant region. The method of claim 11, wherein the method further comprises: thickening the interlayer dielectric layer to cover the first metal gate and the second metal gate; and forming a contact plug to pass through the interlayer dielectric The layers are electrically connected to the substrate. A method of forming a metal gate according to claim 11, wherein the second material group comprises a second high dielectric constant material and a second work function material. A method of forming a metal gate according to claim 11, wherein the first metal gate is one of a PMOS and an NMOS, and the second metal gate is the other one. A method of forming a metal gate according to claim 16, wherein the first metal gate and the second metal gate are in a static random access memory (SRAM). A method of forming a metal gate according to claim 5, wherein the second mask comprises a metal material. A method of forming a metal gate as claimed in claim 1, wherein the second region is protected using an etch mask to perform the selective etching step. A method of forming a metal gate as claimed in claim 19, wherein the etch mask is formed using a photoresist to pattern a hard mask material comprising a nitride and an oxide. A method of forming a metal gate as claimed in claim 11, wherein a low resistance material is simultaneously filled into the first recess and the second recess to form the first metal gate and the second metal gate. A method of forming a metal gate as claimed in claim 1, wherein the dopant region does not overlap the first region or the second region.