TWI502179B - Apparatus and method for measuring the internal stress of electronic construction - Google Patents

Description

Device and method for measuring internal stress of electronic assembly

The present invention relates to an apparatus and method for measuring internal stresses of an electronic package, and more particularly to a piezoresistive stress meter and its associated circuit for use in an electronic package.

A piezoresistive stress meter refers to a piezoresistive element used as a stress meter, and a piezoresistive element fabricated on a tantalum wafer refers to a resistive element made of a tantalum material layer. Since the resistance value of the tantalum material layer changes under stress, the resistance value of the resistive element made of the tantalum material layer under unstressed conditions is different from the resistance value under stress. From the change of the resistance value of the piezoresistive element on the germanium wafer before and after the force, the stress of the germanium wafer at the position of the piezoresistive element can be derived.

By fabricating a piezoresistive element on a tantalum wafer, the magnitude and distribution of stress caused by the electronic package on the tantalum wafer can be measured. For example, in advanced electronic packages, there is a through-silicon via (TSV) technique that is perforated on a germanium wafer and filled with a conductive material into the via to form a via hole. The via holes electrically connect the upper and lower layers of the wafer to achieve the effect of vertical integration of the wafer. However, after the silicon wafer is drilled, it is worn. The edge of the hole will thus cause stress concentration, and when the conductive material is filled into the through hole, a thermal stress effect will also occur, and these stress effects will cause the wafer to be broken or broken. In order to understand the magnitude and distribution of these stresses, a piezoresistive stress meter can be fabricated around the via hole, for example at a distance of 10 μm, 20 μm, 30 μm, etc. from the via hole, to measure at these locations. What is the value of the stress.

For more clarity, referring to FIG. 1, there are through-silicon via vias 12 on the wafer 10, and three sets of piezoresistive stress gauges 14, 16 and 18 are prepared in the vicinity of the through-silicon vias 12 for measuring wafers. [110], [ 10] and stress values in the [010] direction. The two ends of the piezoresistive stress meter 14 are electrically connected to the metal wires 24 and 26 through the contact regions 20 and 22, respectively, and the two ends of the piezoresistive stress meter 16 are electrically connected to the metal wires 32 and 34 through the contact regions 28 and 30, respectively. The two ends of the piezoresistive stress meter 18 are electrically connected to the metal wires 32 and 40 through the contact regions 36 and 38 respectively. The metal wires 24 and 32 may be metal layers on different planes, and the two are electrically connected to each other by using the via holes. . The resistance values R1, R2, and R3 are measured from the three sets of piezoresistive stress meters 14, 16 and 18, respectively, and compared with their original design values to obtain respective resistance value changes, thereby further deriving the wafer [ 110], [ 10] and stress values in the [010] direction.

The prior art technique uses a two-point probe measurement method to measure the resistance value of a piezoresistive stress gauge on a tantalum wafer. For example, referring to FIG. 2, a voltage source V is used to apply a voltage to both ends of the piezoresistive stress meter R, and the ammeter A is used to measure the current of the loop, and then the magnitude of the applied voltage and the measured current are large. The relationship between the two is calculated as the resistance value of the piezoresistive stress meter R. However, the piezoresistive element R is formed on the germanium wafer 41. Therefore, the circuit components outside the germanium wafer 41 must be electrically connected to the germanium wafer 41 through the output input contacts 42 and 44, and the output input contacts 42 and 44 must be respectively The metal wires 46 and 48 are electrically connected to the contact regions 50 and 52 at both ends of the piezoresistive stress meter R. Since the current flowing through the piezoresistive stress meter R also flows through all the objects in the same current path, such as wires and probes, the components other than the piezoresistive stress meter R will cause a voltage drop, that is, these objects will Contributing its resistance value to the measured value results in an inevitable error in the resistance value of the finally calculated piezoresistive stress meter R. In particular, the resistance values of the metal wires 46 and 48 are relatively high, so the influence is also large.

The four-point probe measurement method is another technique for measuring the resistance value. Referring to FIG. 3, this technique uses a current source 54 to provide a current I to the resistive element R to be tested, and uses a DC voltmeter 56 to measure the voltage across the resistive element R, and then from the supplied current I and The relationship between the measured voltages V calculates the resistance value of the resistance element R. Although this technique is more accurate than the two-point probe measurement method, it is not applied to the resistance value of the piezoresistive stress meter on the measurement wafer, and as can be seen from FIG. 2, this technique does not avoid the above parasitic resistance. The error caused.

In order to reduce the influence of parasitic resistance on the measured value, the piezoresistive stress gauges on the conventional tantalum wafer are fabricated in a series winding manner, as shown in FIG. 1 or FIG. 2, to accumulate extremely high resistance values. Generally, the size of a piezoresistive stress gauge on a conventional tantalum wafer is about 200 x 200 μm ² , which occupies a considerable wafer area. When the integrated circuit manufacturing technology is more advanced, such a large-sized piezoresistive stress gauge is disadvantageous for the size reduction of the integrated circuit. With the advancement of integrated circuit process technology, the size of the internal components of the wafer is getting smaller and smaller, so the relative scale of the stress gauge used to measure the stress it is subjected to should be reduced, but the piezoelectric resistor on the conventional silicon wafer. The stress gauges are all arranged in a zigzag winding and cannot be further reduced in size, so they cannot be applied to integrated circuits produced by newer process technologies. In recent years, the integrated circuit process technology has evolved from micron to nanometer level, and electronic assembly has also developed toward three-dimensional three-dimensional design. One of the main developments is the aforementioned TSV technology. Since the piezoresistive stress gauge on the conventional tantalum wafer can no longer be downsized to adapt to the new integrated circuit process technology, it also hinders the use of advanced electronic components in the integrated circuit.

More seriously, when the size of the integrated circuit is reduced, the parasitic resistance has a greater influence on the accuracy of the force measurement. The resistance value of the traditional piezoresistive stress meter is tens of thousands of ohms. Relatively speaking, the ratio of the resistance of the metal wire and the probe to the measured total resistance value is very low, which is negligible. However, for a smaller size or higher density integrated circuit, the required resistance of the piezoresistive stress meter is only about several hundred to several thousand ohms, so the resistance of metal wires and probes can seriously affect the amount of stress. The accuracy of the measurements. If the two-point probe measurement method is still used to measure the resistance value of the piezoresistive stress meter, it will be occupied by the resistance value of other non-pressure resistance stress meters such as metal wires. The overall measured resistance ratio is too high, which affects the accuracy of the measurement. Assume that the resistance of the piezoresistive stress meter after miniaturization is 800 ohms, and the resistance value of the inner wire of the chip may be 200 ohms. If the two-point probe measurement method is used, it will measure more than 1000 ohms, but the pressure is measured. The resistance value of the resistance stress meter is actually only 800 ohms, and the measurement error is very large.

In order to improve the accuracy of the measurement, the present invention provides an apparatus and method for measuring the internal stress of an electronic assembly, and uses a four-point probe measurement method to measure the resistance value of a piezoresistive stress meter on a wafer. And the new matching circuit eliminates the influence of the resistance of the wire on the measurement.

In one embodiment, a first pair of wires on the wafer are electrically connected to the wires of the contact regions at both ends of the piezoresistive stress meter, and a current is injected into the piezoresistive stress meter, thereby generating a stress gauge in the piezoresistive stress meter. The voltage across the voltage is measured by a second pair of wires electrically connected to the two contact regions on the wafer, thereby avoiding measurement error of the resistance of the first pair of wires.

Since the influence of the resistance of the first pair of wires on the measurement is excluded, a piezoresistive strain gauge having a small resistance value can be used.

In one embodiment, the piezoresistive stress meter includes a strip-shaped resistive element between the two contact regions. In an embodiment, the resistive element comprises a layer of germanium material doped with an n-type or p-type.

In one embodiment, the piezoresistive stress meter comprises a meandering A resistive element of the wire is between the two contact regions. In an embodiment, the resistive element comprises a layer of germanium material doped with an n-type or p-type.

In one embodiment, the wires each comprise a metal, a metal halide or a polysilicon.

In an embodiment, a plurality of via holes are further electrically connected to one of the two contact regions.

In one embodiment, the piezoresistive stress gauge is adjacent to the via via on the wafer.

The use of a piezoresistive stress gauge as a tool for measuring the internal stress of an electronic package is known to have many advantages. For example, the chip occupies a small area of the chip, and a plurality of piezoresistive stress gauges can be fabricated on one wafer; The body circuit process is directly fabricated on the germanium wafer and does not require additional wafer processing steps; it can be fabricated simultaneously with other components and integrated circuits; it can be measured in-site; it can be measured in real-time; No expensive measuring equipment is required; the measuring process is simple; it is a nondestructive measurement. The present invention not only has these advantages, but also further removes many of the disadvantages of the prior art, and can be applied where conventional piezoresistive stress gauges cannot be used.

10‧‧‧ wafer

12‧‧‧through through silicon via

14‧‧‧pressure resistance strain gauge

16‧‧‧pressure resistance strain gauge

18‧‧‧pressure resistance strain gauge

20‧‧‧Contact area

22‧‧‧Contact area

24‧‧‧Metal wire

26‧‧‧Metal wire

28‧‧‧Contact area

30‧‧‧Contact area

32‧‧‧Metal wire

34‧‧‧Metal wire

36‧‧‧Contact area

38‧‧‧Contact zone

40‧‧‧Metal wire

41‧‧‧矽 wafer

42‧‧‧Output input contacts

44‧‧‧Output input contacts

46‧‧‧Metal wire

48‧‧‧Metal wire

50‧‧‧Contact area

52‧‧‧Contact area

54‧‧‧current source

56‧‧‧ DC Voltmeter

58‧‧‧pressure resistance strain gauge

60‧‧‧Contact area

62‧‧‧Contact area

64‧‧‧Wire

66‧‧‧Output input contacts

68‧‧‧Wire

70‧‧‧Output input contacts

72‧‧‧ wire

74‧‧‧Output input contacts

76‧‧‧Wire

78‧‧‧Output input contacts

79‧‧‧ wafer

80‧‧‧ circuit components

82‧‧‧ Circuit components

84‧‧‧ circuit components

86‧‧‧ circuit components

88‧‧‧ Guide hole

90‧‧‧ Guide hole

92‧‧‧pressure resistance strain gauge

94‧‧‧pressure resistance strain gauge

Figure 1 is a schematic diagram of a conventional piezoresistive stress meter fabricated around a via hole on a wafer; Figure 2 is a two-point probe measurement method for measuring a germanium wafer. FIG. 3 is a schematic view of a conventional four-point probe measurement method; FIG. 4 is a schematic view of a preferred embodiment of the present invention; FIG. 5 is a schematic view showing a conductive connection contact region of a wire; Figure 6 is a schematic view showing the direction of the piezoresistive stress meter with respect to the wafer.

Figure 4 is a schematic view of a preferred embodiment of the present invention, wherein the left side of the circuit is arranged in a top view, and the right side is an equivalent circuit diagram. The device comprises a piezoresistive stress meter 58 and a matching circuit electrically connected thereto. Contact areas 60 and 62 at both ends. Specifically, the matching circuit includes a wire 64 electrically connecting the contact area 60 and an output input contact 66. The wire 68 is electrically connected to the contact area 62 and the output input contact 70. The wire 72 is electrically connected to the contact area 60 and the output input connection. At point 74, conductor 76 is electrically coupled to contact region 62 and output input contact 78. The piezoresistive stress meter 58, contact regions 60 and 62, wires 64, 68, 72 and 76, and output input contacts 66, 70, 74 and 78 are all fabricated on one of the wafers 79 in an electronic package.

When the resistance value of the piezoresistive stress meter 58 is measured by the four-point probe measurement method, a current source 54 is electrically connected between the output input contacts 66 and 70, thereby forming a first loop including the piezoresistive stress. The first path, the contact areas 60 and 62, the wires 64 and 68, and the electrical connection between the output input contacts 74 and 78 are electrically connected to the voltmeter 56, thus forming a second The circuit includes a second path including a piezoresistive stress meter 58, contact regions 60 and 62, and wires 72 and 76. The current I provided by the current source 54 flows through the first path through the piezoresistive stress meter 58. The piezoresistive stress meter 58 thus produces a voltage across which the DC voltmeter 56 measures the voltage across the second path. The resistance value R of the piezoresistive stress meter 58 can be calculated from the voltage V measured by the current I and the DC voltmeter 56, and further calculated to obtain the stress value at which the piezoresistive stress meter 58 is located.

Since the conductors 72 and 76 across the voltage of the piezoresistive stress gauge 58 are electrically connected to the contact regions 60 and 62, respectively, the wires 64 and 68 for supplying the current I are excluded from the measurement range, thereby avoiding The resistance of the wires 64 and 68 causes an error in the measurement of the resistance value of the piezoresistive stress meter 58. In other words, by the matching circuit, the four-point probe measurement method can accurately measure the resistance value of the piezoresistive stress meter 58. The device of the present invention differs from the prior art when using the four-point probe measurement method to measure the resistance value of the piezoresistive stress meter 58. As shown in the right circuit diagram of FIG. 4, the DC voltmeter 56 is directly measured. The voltage across the piezoresistive stress meter 58 and the voltage across the wires 64 and 68 do not affect the voltage V measured by the DC voltmeter 56.

Since the resistance of the wires 64 and 68 is excluded from the resistance measurement of the piezoresistive stress meter 58, a piezoresistive stress meter 58 having a small resistance value can be used, so that not only the wafer of the piezoresistive stress meter 58 but also the wafer The area can be greatly reduced, and it is possible to accumulate high resistance values without using a zigzag winding layout. Compared with the size of the conventional piezoresistive stress meter of 200×200 μm ² , the size of the piezoresistive stress gauge of the present invention can be reduced to 20×20 μm ² or less, and the area is reduced by 99%, that is, the piezoresistive stress gauge is highly miniaturized. . In the current trend of shrinking the size of integrated circuit products and increasing component density, the present invention can save more wafer fabrication area and can more accurately measure the stress stress of smaller components than conventional piezoresistive stress meters. .

Although the embodiment of FIG. 4 uses a straight strip-shaped piezoresistive stress meter 58, in other embodiments, the piezoresistive strain gauge can still use a zigzag winding layout, such as that shown in FIG. Large size piezoresistive stress meter. Even if a zigzag-wound piezoresistive stress meter is used, since the matching circuit of the present invention can eliminate the influence of the resistance of the other items other than the piezoresistive stress meter, the resistance of the piezoresistive stress meter is measured more accurately than the prior art. value.

In one embodiment, the piezoresistive stress meter comprises a strip-shaped resistive element, as shown in FIG. In an embodiment, the resistive element comprises a layer of germanium material doped with an n-type or p-type.

In one embodiment, the piezoresistive stress meter comprises a meandering resistance element, as shown in FIG. In an embodiment, the resistive element comprises a layer of germanium material doped with an n-type or p-type.

In one embodiment, wires 64, 68, 72, and 76 all comprise a metal, a metal halide, or a polysilicon.

Those of ordinary skill in the art are aware of the The wires 64, 68, 72 and 76 are only schematic views. In practice, each wire may be composed of a conductive material on a certain plane, or may be electrically connected by conductive materials located on different planes through the guide holes. For example, a metal wire using a multilayer metal wiring structure is used.

Preferably, wires 64 and 72 are continuous at contact area 60, i.e., physically connected, as shown in Figure 4, to reduce parasitic resistance. In other embodiments, wires 64 and 72 are also It can be separate from each other. Likewise, wires 68 and 76 are also at contact zone 62.

Typically, the wires 64, 68, 72, and 76 are electrically connected to the contact regions 62 and 62. As shown in FIG. 5, the top is a top view, and the lower portion is a cross-sectional view taken from the AA line in the plan view, and the wires 64 and 72 are taken. The contact holes 60 are electrically connected to the contact regions 60 through the plurality of via holes 88, and the wires 68 and 76 are electrically connected to the contact regions 62 through the plurality of via holes 90.

In the embodiment of FIG. 4, the widths of the contact regions 60 and 62 are much larger than the width of the piezoresistive stress meter 58 for the purpose of illustrating that the plurality of vias 88 and 90 are electrically connected as shown in FIG. Parasitic resistance. In various embodiments, if the piezoresistive stress meter 58 has a different geometry, its width may be the same or similar to the width of the contact regions 60 and 62. It is known to those of ordinary skill in the art that the size and spacing of the vias are limited by the integrated circuit process, so that in applying the present invention, the integrated circuit designer can design the widths of the contact regions 60 and 62 according to specifications. Allow more or lesser number of leads Holes 88 and 90.

The output input contact required for the four-point probe measurement method can be an output input contact that is only used for the four-point probe measurement method, or can be used without affecting the internal component circuit of the chip. Some of the output input contacts are used in combination. For example, referring to FIG. 4, the output input contacts 66, 70, 74, and 78 are the output input contacts of the circuit components 80, 82, 84, and 86 on the wafer 79, respectively. When the resistance value of the resistance stress meter 58 is reached, the circuit elements 80, 82, 84, and 86 are not activated, so that the wires 64, 68, 72, and 76 are only used as part of the matching circuit for measurement, and are not affected by other circuit components. interference.

In one embodiment, the piezoresistive stress gauge is adjacent to the through-silicon via, such as the through-silicon via 12 shown in FIG.

As with the matching circuit shown above, in addition to the resistance value of the piezoresistive stress meter 58 can be measured using a four-point probe measurement method, it can also be measured using a two-point probe measurement method. For example, in an embodiment, when performing the component circuit design, the length of the metal wire located in the circuit and its resistance value are calculated in advance with the sheet resistance of the metal wire in the process technical data, and then the two-point probe amount is used. The measurement method is performed, and then the actually measured resistance value is subtracted from the pre-calculated resistance value of the metal wire, the resistance value of the piezoelectric resistance stress meter 58 is obtained, and the measured resistance value is recorded, and then the data is recorded. It is provided as a reference for the resistance value measured by the four-point probe measurement method.

The resistance change rate of the piezoresistive stress meter is related to the stress and temperature changes it receives. For example, referring to FIG. 6, the piezoresistive stress meters 92 and 94 having an angle of 0 degrees and 90 degrees with respect to the direction of the wafer [110] have a rate of change in resistance. Can be expressed separately as the following two formulas:

Wherein, ΔR ₁ and ΔR ₂ are resistance change amounts of the piezoresistive stress meters 92 and 94 before and after stress is applied without temperature change, and R ₁₀ and R ₂₀ are pressure resistance stress meters 92 and 94 respectively at the reference temperature. The initial resistance value when no stress is applied, σ _x and σ _y are the positive stresses of the X-axis and the Y-axis, the stress coefficients of the π _s and π _44-type resistors, and the temperature coefficient of the α-series resistors. The measurement is performed on the wafer, so the value of α is the same, and ΔT is the temperature difference between the temperature at the time of measurement and the correction of R ₁₀ and R ₂₀ . After the correction, the piezoresistive stress meter can know the values of π _s , π ₄₄ , and α. The initial resistance values R ₁₀ and R _{20 of the} piezoresistive stress gauges of the same geometry are also known under the same process conditions. After the piezoresistive stress meter is stressed, the resistance value will change, as long as the resistance of the piezoresistor is under the stress, and then the measured value is subtracted from the initial resistance of the piezoresistive stress meter. The resistance value change amounts ΔR ₁ and ΔR ₂ are substituted into the above two equations to obtain the values of the forward stresses σ _x and σ _y of the X-axis and the Y-axis. Fig. 6 is only a schematic view showing the direction of the piezoresistive stress meter with respect to the wafer, and does not show the size of the piezoresistive stress gauge with respect to the wafer.

54‧‧‧current source

56‧‧‧ DC Voltmeter

58‧‧‧pressure resistance strain gauge

60‧‧‧Contact area

62‧‧‧Contact area

64‧‧‧Wire

66‧‧‧Output input contacts

68‧‧‧Wire

70‧‧‧Output input contacts

72‧‧‧ wire

74‧‧‧Output input contacts

76‧‧‧Wire

78‧‧‧Output input contacts

79‧‧‧ wafer

80‧‧‧ circuit components

82‧‧‧ Circuit components

84‧‧‧ circuit components

86‧‧‧ circuit components

Claims (8)

A device for measuring an internal stress of an electronic package, the electronic assembly having a wafer, the device comprising: a piezoelectric resistance stress meter, wherein the piezoelectric contact strain meter has a first contact region at each end thereof And a second contact region; the first to fourth output input contacts are all on the wafer; and the first to fourth wires are all on the wafer, the first wire is electrically connected to the first contact region and the a first output input contact, the second wire is electrically connected to the second contact area and the second output input contact, the third wire is electrically connected to the first contact area and the third output input contact, The fourth wire is electrically connected to the second contact region and the fourth output input contact; wherein the first to fourth wires are electrically connected to at least one circuit component on the wafer. The device of claim 1, wherein the piezoresistive stress meter comprises a strip-shaped resistive element between the first contact region and the second contact region. The device of claim 2, wherein the resistive element comprises a layer of germanium material doped with an n-type or p-type. The device of claim 1, wherein the piezoresistive stress meter comprises a meandering resistance element between the first contact region and the second contact region. The device of claim 4, wherein the resistive element comprises doping n-type or P-type tantalum material layer. The device of claim 1, wherein the first to fourth wires comprise a metal, a metal halide or a polysilicon. The device of claim 1, wherein the first to fourth wires are electrically connected to the first contact region or the second contact region by one or a plurality of via holes. The device of claim 1, wherein the piezoresistive stress gauge is adjacent to the through-hole via.