TWI500141B - Integration of sense fet into discrete power mosfet - Google Patents

Description

The discrete power MOS field effect transistor combined with the element of the sensing field effect transistor Parts and methods

The present invention relates generally to semiconductor components, and more particularly to a sensing MOS field effect transistor including a power MOS field effect transistor and one or more source terminals with common gate and 汲 extremes and discrete sources. Semiconductor component.

In the circuit, one of the methods to determine the current flowing through the load is to use a metal oxide semiconductor field effect transistor (MOS field effect transistor) for current sensing. Conventional current sensing power MOS field effect transistors typically contain thousands of transistor units connected in parallel, sharing a common drain, source and gate electrode. Each transistor unit or component within the component is identical, and the current at the extremes of the component is the same between them. A common situation in this design is where the source electrodes of some of the transistors are separated from the remaining source electrodes and connected to a separate source terminal. Thus, the resulting current sense MOS field effect transistor can be viewed as equivalent to two or more parallel transistors, with common gate and 汲 extremes, and discrete source terminals. The first part of these transistors, including the current sensing power MOS field Most of the transistor units in the effect transistor are commonly referred to as main field effect transistors. The second part, comprising a plurality of transistor units with discrete source terminals, is called a field effect transistor.

During use, the sensing field effect transistor only conducts a small portion of the current at the 汲 terminal. This small portion of the current is inversely proportional to the sensing ratio n, where n is the current ratio, depending on the power in the main field effect transistor. The ratio of the number of crystal units to the number of transistor units in the field-effect transistor. The sensing ratio n is defined so that the source terminals of the sensing field effect transistor and the main field effect transistor are kept at the same potential for conduction. When the sense ratio is known, the total current flowing through the component, and the load current on the load to which the component is connected, can be measured by sensing the source current on the field effect transistor (ie, at the drain and source electrodes) The current flowing through the current path of the sensing field effect transistor is calculated.

A method and apparatus for measuring and/or controlling the level of current in a field-effect transistor is proposed in U.S. Patent No. 5,079,456, wherein the field-effect transistor comprises a power transistor and a sensing transistor. . The two transistors are biased and operated in a linear mode to sense the source-drain voltage Vds of the transistor compared to the predetermined portion of Vds of the power transistor. The resulting control signal indicates the result of the comparison. In one embodiment, the control signal is used in the feedback device for driving the Vds of the sensing transistor to a predetermined portion Vds of the power transistor. Thus, the level of current carried on the sensing transistor is made equal to the predetermined portion of the current carried on the power transistor.

U.S. Patent No. 5,408,141 discloses a combined power component comprising a power transistor and five sensing transistors. Four of the sensing transistors, in size, are proportional to the power transistor and are fabricated near the peripheral region of the active region of the power transistor using the same fabrication process as the components of the power transistor. The fifth sense transistor is located inside the active region of the power transistor, and is connected to the source region required by the fifth sense transistor by a second level of metal interconnection to form a source contact.

U.S. Patent No. 5,962,912 teaches a power semiconductor component having a transistor cell structure that includes a metal resistance trace that is insulated from the semiconductor body of the power semiconductor component and the control electrode by a non-conductive layer. The resistance tracking is located in a horizontal region between the power semiconductor units. With resistance tracking, the active area of the part is not made smaller, and a metal layer of resistance tracking and parts is prepared. The metal layer of the part provides contact with the main electrode of the power semiconductor, so that additional tracking steps are not required to increase resistance tracking.

However, wire bonding between the sense field effect transistor and the main field effect transistor can affect performance during the period. Furthermore, without adding mask layers and the number of fabrication process procedures, it is necessary to develop a power component that incorporates one or more sense field effect transistors in a discrete power MOS field effect transistor. It is on this premise that various embodiments of the invention have been presented.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a power component incorporating one or more sense field effect transistors in a discrete power MOS field effect transistor without increasing the number of mask layers and fabrication process Its preparation method.

The technical means of the present invention provides a semiconductor device comprising: a main field effect transistor including a source, a body and a gate; and a sensing field effect transistor including a source, a body and a gate, wherein the field effect is sensed The transistor portion of the transistor is surrounded by the transistor of the main field effect transistor and located near the transistor of the main field effect transistor; a sensing field effect transistor source pad at the edge of the semiconductor component, wherein the field effect is sensed The transistor portion of the transistor is separated from the sense field effect transistor source pad and senses the field effect transistor The source pad is connected to the transistor portion of the sensing field effect transistor by a sensing field effect transistor probe metal; and an electrically insulating structure is used to make the source and body regions and the sensing field of the main field effect transistor The source of the effect transistor is electrically insulated from the body region; wherein the main field effect transistor, the sensing field effect transistor and the electrically insulating structure are formed in a single semiconductor wafer, and the sensing field effect is achieved by configuring an insulating structure The transistor portion of the crystal and the sensing field effect transistor source pad are located outside the active region of the main field effect transistor; wherein the semiconductor component is a discrete vertical field effect transistor.

Wherein, the sensing field effect transistor probe metal, the main field effect transistor source metal and the gate metal are all separate parts of the same single metal layer.

Among them, sensing the field effect transistor probe metal is not a resistor.

Wherein, the portion of the transistor that senses the field effect transistor is not as wide as the metal of the field effect transistor probe.

Wherein, the portion of the transistor that senses the field effect transistor is located near the center of the main field effect transistor.

Wherein, the transistor portion of the sensing field effect transistor, the sensing field effect transistor probe metal and the sensing field effect transistor source pad are separated from the main field effect transistor by an insulating structure, and by sensing The field effect transistor source pad is located on the periphery of the main field effect transistor.

The insulating structure comprises one or a plurality of deep potential wells formed on top of the epitaxial layer, wherein the deep potential well senses the source and body regions of the field effect transistor, and the source and body of the main field effect transistor Zone insulation, wherein the conductivity type of the deep potential well is the same as that of the main field effect transistor body region.

Wherein, the depth of the deep energy well is greater than the depth of the body region of the main field effect transistor.

Wherein, the depth of the deep potential well is between about 1 micrometer and 2 micrometers, and the depth of the body region of the main field effect transistor is between about 0.5 micrometers and 0.7 micrometers.

Wherein, the doping concentration of the deep energy well is smaller than the doping concentration of the body region of the main field effect transistor.

Among them, the doping concentration of the deep energy well is about 4×10 ¹⁶ /cm ³ .

Wherein, the deep energy well between the transistor portion of the field effect transistor and the main field effect transistor is sensed to be about twice the width of the transistor unit pitch.

Wherein, the deep energy well width between the transistor portion of the field-effect transistor and the main field effect transistor is about 2 to 10 micrometers.

Among them, the main field effect transistor and the sensing field effect transistor are composed of a metal oxide semiconductor field effect transistor MOSFET.

Wherein, the electrically insulating structure between the sensing field effect transistor and the main field effect transistor is formed by a body ring near the insulating trench, wherein a metal layer above the electrically insulating structure senses the field effect transistor The gate is electrically connected to the gate of the main field effect transistor.

Another technical means of the present invention is to provide a method for preparing a semiconductor device including a main field effect transistor and a sensing field effect transistor, comprising: a) preparing a source of a main field effect transistor in a substrate. , a body and a gate; b) in the substrate, preparing a source, a body and a gate of the sensing field effect transistor, wherein the sensing field effect transistor is located near the center of the main field effect transistor, wherein the field effect transistor is sensed The crystal part of the crystal is surrounded by the transistor of the main field effect transistor and is located near the transistor of the main field effect transistor to reduce the distortion and error of the sensing field effect transistor measurement, wherein the field effect transistor and the home field are sensed. The effect transistor is a vertical field effect transistor sharing a common substrate; c) in the substrate, preparing an electrically insulating structure, the source and body regions of the main field effect transistor, and the source of the sensing field effect transistor Electrical insulation of the body region; d) preparing a sensing field effect transistor source pad at the edge of the main field effect transistor, and connecting to the sensing field effect transistor by sensing the field effect transistor probe metal; wherein the field effect transistor is sensed The crystal and sense field effect transistor source pads are separated from the main field effect transistor by an electrically insulating structure.

Wherein a) to d) comprise: i) preparing a first conductivity type outer layer over a heavily doped first conductivity type substrate; ii) preparing a deep potential well mask over the epitaxial layer; Iii) implanting a dopant of a second conductivity type on top of the epitaxial layer in the insulating structure region of the semiconductor component to form a deep potential well region, the second conductivity type being opposite to the first conductivity type.

Wherein, iii) further comprises preparing a deep energy well region such that the depth of the deep energy well region is about 1 to 2 microns and the doping concentration is about 4×10 ¹⁶ /cm ³ .

The method further includes: preparing a main field effect transistor gate trench, sensing a field effect transistor gate trench, and an insulating trench, wherein the insulating trench is located between the main field effect transistor and the sensing field effect transistor, and A part of the electrically insulating structure, wherein the insulating trench is not connected to the gate voltage; an insulating layer is deposited over the electrically insulating structure; and an insulating layer is formed over the electrical insulating to prepare a metal layer, the metal layer sensing the field effect The gate of the crystal is connected to the gate of the main field effect transistor.

Wherein, the semiconductor component is a discrete vertical field effect transistor.

100, 300, 301, 310, 500‧‧‧ semiconductor components

101‧‧‧Substrate

102, 302, 502‧‧‧ main field effect crystal

103‧‧‧汲pad

104, 304, 312, 314‧‧‧ sensing field effect transistor

106, 421, 508, 618, 921‧‧‧ main field effect transistor source metal

107‧‧‧Home field effect transistor source pad

108, 422, 608, 922‧‧‧ Sense field effect transistor source metal

110, 111, 420, 509‧‧ ‧ gate metal

112‧‧‧First metal gap

114‧‧‧Second metal gap

115‧‧‧ Third metal gap

118, 503, 925‧‧‧ sense field effect transistor source pad

120, 306, 317, 506‧‧ ‧ gate pads

122, 309, 320‧‧‧ electrical insulators

201, 221, 606, 616, 909, 912‧‧‧ body area

202, 210, 614, 622‧‧ ‧ gate

203, 205, 620, 621, 623‧‧‧ conductive through holes

204, 212, 602, 612‧‧‧ source

206, 416, 516, 916‧‧‧ insulation

207‧‧‧ Body implant ring

208, 426, 533, 926‧‧‧ passivation layer

209, 403A, 403B, 405A, 405B, 406, 903, 905, 906‧‧‧ trench

211, 225, 626‧‧‧ through holes

222‧‧‧gate chute trench

224‧‧ ‧ gate slide

303, 308, 311, 313, 315‧‧‧ source pad

305, 307, 316, 318, 319, 505, 507‧ ‧ gap

321‧‧‧Semiconductor

402, 902‧‧‧N+ substrate

404, 904‧‧‧ epitaxial layer

408, 908‧‧‧ conductive materials

410‧‧‧gate oxide

412‧‧‧P-type dopant

413, 913‧‧‧Home field effect transistor source region

414, 914‧‧‧ Sense field effect transistor source region

417, 418, 430, 431, 917, 930, 931 ‧ ‧ contact openings

423, 424‧‧‧ openings

432, 434‧‧‧ contact implants

501‧‧‧Semiconductor wafer

510‧‧‧Sensor field effect transistor probe

511‧‧‧Electrical pins (probe metal)

512, 905A‧‧‧ deep energy well

513‧‧‧N-epitaxial layer

514‧‧‧Semiconductor substrate layer

515‧‧‧Insulation structure

610‧‧‧ Body contact

910‧‧‧gate dielectric

932‧‧‧ Body contact implants

A-A, B-B, C-C‧‧‧ lines

Other features and advantages of the present invention will become apparent from the following detailed description, in which <RTIgt; A top plan view of a semiconductor device to show a passivation layer; a second view showing a cross-sectional view of the semiconductor device shown in FIG. 1 along line BB; and FIGS. 3A to 3D are diagrams showing a semiconductor device according to an embodiment of the present invention; A top view of the selected field effect transistor structure; FIGS. 4A-4H illustrate a series of schematic cross-sectional views of a semiconductor device in accordance with an embodiment of the present invention; and FIG. 5A shows a cross-sectional view of an embodiment of the present invention. A top view of a semiconductor device with a sense field effect transistor probe located near the center of the device; a fifth top view showing a top view of the semiconductor device with a passivation layer shown in FIG. 5A; and a sixth view showing a fifth embodiment to FIG. 5B is a top plan view of the sensing field effect transistor probe; FIG. 6B is a cross-sectional view taken along line AA of FIG. 6A; and FIG. 6C is a view along line A of FIG. -B is a sectional view; FIG. 7 is a cross-sectional view of the semiconductor element shown in FIGS. 5A to 5B along line CC; and FIG. 8 is a schematic view showing a current line of the main wafer and the sensing field effect transistor probe; 9 and FIGS. 10B-B' to 16B-B' are schematic views showing a series of cross-sectional views of a semiconductor element of the type of semiconductor elements shown in FIGS. 5A to 5B and 6C; and FIGS. 9A and 10C. The -C' map to Fig. 16C-C' is a schematic cross-sectional view showing a series of semiconductor elements along the line CC shown in Figs. 5A to 5B and Fig. 7.

While the following detailed description contains numerous specific details Thus, the exemplary embodiments of the present invention are presented without any general loss to the claimed invention without any limitation.

Please refer to FIG. 1, FIG. 1A and FIG. 2 for understanding various aspects of embodiments of the present invention. 1 shows a top plan view of a semiconductor device 100 in accordance with an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 includes a common substrate 101, a main field effect transistor 102 deposited in the common substrate 101, and one or more sensing field effect transistors 104 also deposited in the common substrate. As shown in the example of FIG. 1, the sense field effect transistor 104 can be located in a region surrounded by the active region of the main field effect transistor 102. The main field effect transistor 102 can be a metal oxide semiconductor field effect transistor (MOS field effect transistor), typically a power MOS field effect transistor, which can be configured as a stripe unit or a closed unit. The sense field effect transistor 104 can also be a metal oxide semiconductor field effect transistor (MOS field effect transistor) configured to be a stripe unit or a closed cell. Both the main field effect transistor 102 and the sense field effect transistor 104 are formed on the common substrate 101. Each of the main field effect transistor 102 and the sense field effect transistor 104 has its own source, gate and drain structure. The source structure is formed in the body layer of the common substrate 101. A drain pad 103 (see FIG. 2) is formed on the back of the substrate 101.

The gate and source structures that make up the main field effect transistor 102 are typically located below the main field effect transistor source metal 106. The source structure of the sense field effect transistor 104 is electrically coupled to the sense field effect transistor source metal 108. The gate and source structures that make up the field effect transistor 104 are typically located below a portion of the sense field effect transistor source metal 108. However, to avoid damage from wire bonding, these structures are typically not located below the sense field effect transistor source pad 118 (sometimes referred to as a sensing pad). Since the number of sense field effect transistor units is typically many orders of magnitude smaller than the number of main field effect transistor units, such damage to the sense field effect transistor unit will greatly affect the desired sense ratio. accuracy. Although the main field effect transistor component is also damaged by wire bonding, However, the number of damaged main field effect transistor cells is much smaller than the total number of main field effect transistor cells, so that the accuracy of the required sensing ratio is not greatly affected. The sensing field effect transistor source metal 108 can cover the entire sensing field effect transistor source region and extend to an area outside the active sensing field effect transistor unit 104, and the sensing pad is directly formed in the field effect battery. Above the crystal source metal 108, or over the passivation layer over the field effect transistor source metal 108. For the sake of simplicity, Figure 1 does not show a passivation layer. Figure 1A shows the same top view as Figure 1, but showing the passivation layer 208 and the window opened in the passivation layer 208, which is used to bond to the main field effect transistor source in accordance with an embodiment of the present invention. The pole metal 106 senses the field effect transistor source metal 108 and the outer gate metal 111. The exposed metal of the window in passivation layer 208 actually constitutes gate pad 120, main field effect transistor source pad 107, and sense field effect transistor source pad 118. Clearly, the sense field effect transistor 104 is not directly below the sense field effect transistor source pad 118.

The gate structures of the main field effect transistor 102 and the sense field effect transistor 104 are electrically connected to each other by a common gate metal 110. The first metal gap 112 can electrically insulate the main field effect transistor source metal 106 from the common gate metal 110. The second metal gap 114 can be between the common gate metal 110 and the sense field effect transistor source metal 108. The third metal gap 115 may be located between the main field effect transistor source metal 106 and the outer gate metal 111. A conductor-filled trench (not shown in FIG. 1) is formed in the body of the substrate 101, and is insulated from the substrate by a layer of oxide lining the sidewalls of the trench, for example, by filling the trench with a conductor to achieve a main field effect. The transistor 102 and the gate terminal of the sense field effect transistor 104 are electrically connected to the common gate metal 110. These conductor-filled trenches also connect the common gate metal 110 to the external gate metal 111. The main field effect transistor source metal 106, the sensing field effect transistor source metal 108, the external gate metal 111, and the common gate metal 110 may be formed on a single patterned metal layer deposited over the substrate 101. The gate pad 120 may be deposited on the outer gate metal 111.

The main field effect transistor source metal 106, the sensing field effect transistor source metal 108, the external gate metal 111, and the common gate metal 110 may all be covered by the passivation layer 208 (see FIGS. 1A and 2). Figure). The external electrical connection to the main field effect transistor source metal 106 can be connected to the main field effect transistor source pad deposited on the passivation layer 208 by vias in the passivation layer 208. Alternatively, the main field effect transistor source pad can be formed in a portion of the main field effect transistor source metal 106, and the main field effect transistor source metal 106 is exposed through the window in the passivation layer 208. Similarly, the external electrical connection to the sense field effect transistor source metal 108 can be coupled to the passivation layer deposited over the sense field effect transistor source metal 108 by the passivation layer 208. Field effect transistor source metal pad 118 (sensing pad). Alternatively, the sense field effect transistor source pad 118 can be formed in a portion of the sense field effect transistor source metal 108, and the sense field effect transistor source metal 108 is exposed through a window in the passivation layer 208. Almost the entire surface of the main field effect transistor source metal 106 can generally be used for wire bonding. In addition, an external electrical connection to the gate metal 110 may be coupled to the gate pad 120 deposited on the passivation layer over the gate metal 110 by a passivation layer. However, in the embodiments shown in FIGS. 1 , 1A and 2 , the gate pad 120 is formed on the outer gate metal 111 . The common gate metal 110 and the external gate metal 111 are connected together under the gate chute trench 222 (Fig. 2). The drains of the main field effect transistor 102 and the sense field effect transistor 104 can be electrically connected to a common drain pad 103 (see FIG. 2) by the lower portion of the substrate 101, and the common drain pad 103 may be formed in common. The back of the substrate 101.

The semiconductor device 100 also includes an electrical insulator 122 formed in the body layer of the common substrate 101 between the main field effect transistor 102 and the sense field effect transistor 104, as shown in FIG. In the example shown in FIG. 1, the electrical insulator 122 is located between the first metal gap 112 and the second metal gap 114. As an example, electrical insulator 122 can be fabricated in a combination of doped body 207 and trench ring 209. The electrical insulator 122 provides electrical isolation between the main field effect transistor 102 and the source structure of the sense field effect transistor 104 within the body of the common substrate 101.

Referring to FIG. 2, the main field effect transistor 102 may include a plurality of field effect transistor structures, each field effect transistor structure including a trenched gate 202 and a suitable doped substrate 101. A source 204 formed by a portion of the body region 201. The gate 202 of each of the main field effect transistor elements is The trench is in the form of an insulator such as an oxide and is filled with a conductive polysilicon. The gate 202 may be perpendicular to the cross section BB, passing through one or more trench gates parallel to the cross section BB, electrically connected to the gate runner trench 222, and the gate runner trench 222 is provided with an insulating layer 206, electrically connected to the common gate metal 110 via one or more conductive vias 203. Gate runner channel 222 is also connected to external gate metal 111. The source 204 of a main field effect transistor unit can be connected in parallel to other such elements by a main field effect transistor source metal 106. The source region 204 can pass through the insulating layer 206 through the conductive vias 205. Electrically connected to the main field effect transistor source metal 106. The main field effect transistor source metal 106 can be electrically connected to the main field effect transistor source pad by a conductive via passing through a portion of the passivation layer 208, the portion of the passivation layer 208 being under the source pad, the main field effect transistor source Above the metal 106. Alternatively, the main field effect transistor source pad can be formed in the portion of the main field effect transistor source metal 106 that is not covered by the window in the passivation layer 208. Almost the entire surface of the main field effect transistor source metal 106 is generally allowed to serve as a junction region for bonding the leads.

Similarly, the sense field effect transistor 104 also includes a plurality of component structures, each of which includes a trenched gate 210, and the trenched gate 210 is formed by one or more vertical gate trenches. The slots are electrically coupled to the gate runners 224. The gate runner 224 is connected to the common gate metal 110 by a via 211. Starting from the common gate metal 110, the gate runner 224 is also electrically coupled to the gate pad 120 via the external gate metal 111 and the gate runner 222. The sense field effect transistor source 212 is electrically coupled to the source of the other sense field effect transistor unit via the via 225 via the sense field effect transistor source metal 108. The trenched gate 210, source 212, and body region 221 can all be configured as described above for the primary field effect transistor gate 202, source 204, and body 201. The sense field effect transistor source metal 108 can be electrically coupled to the sense field effect transistor source pad (sensing pad) 118 by conductive vias formed in the passivation layer 208. Alternatively, the sensing pad is formed in a portion of the sensing field effect transistor source metal 108 that is exposed by a window in the passivation layer 208. The common gate metal 110 slides the trenched gate 222 of the main field effect transistor 102 with the gated gate of the sense field effect transistor 104. Road 224 is electrically connected. The first metal gap 112 electrically insulates the main field effect transistor source metal 106 from the common gate metal 110, and the second metal gap 114 electrically insulates the sense field effect transistor source metal 108 from the common gate metal 110.

As described above, the source and body regions of the main field effect transistor and the sensing field effect transistor element are both formed in the same substrate 101. Electrical insulator 122 insulates the two source and body regions. As an example, electrical insulator 122 may contain a body implant ring 207 and an electrically insulating and electrically floating polysilicon fill trench 209 that provides electrical isolation between main field effect transistor 102 and sense field effect transistor 104. The preparation of the body implant ring 207 can be performed by appropriately doping a portion of the substrate 101. The trench 209 is similar in structure to the trench gates 202, 210 but is electrically isolated from the trench gate. In order to electrically insulate the main field effect transistor from the sense field effect transistor source metals 106 and 108 and the common gate metal 110, the passivation layer 208 may be filled in the metal gaps 112 and 114, and the passivation layer 208 is deposited in the main field effect The crystal source metal 106, the sense field effect transistor source metal 108, and the common gate metal 110 are over. Alternatively, some or all of the passivation layer 208 is omitted, and the bond wires are directly connected to the main field effect transistor source metal 106, the sense field effect transistor source metal 108, and the common gate metal 110, respectively.

Semiconductor devices can have a variety of different design layouts in accordance with embodiments of the present invention. 3A through 3D are top plan views showing several alternative sensing field effect transistor structures of a semiconductor device in accordance with an embodiment of the present invention. As an example, semiconductor component 300 may contain a sense field effect transistor located within the active region of the main field effect transistor, as shown in FIG. 3A. Semiconductor component 300 includes a sense field effect transistor 304 located near the center of main field effect transistor 302. The source metal of the main field effect transistor 302 and the sense field effect transistor 304 are located between the field effect transistor and the corresponding source pads 303 and 308 and the gate pad 306. The slits 305, 307 formed in the common metal layer divide the common metal layer into the main field effect transistor 302 and the gate metal region and the source metal region of the sense field effect transistor 304. The source pads 303, 308 of the main field effect transistor and the sense field effect transistor are located above the respective metal regions. The gate pad 306 is located above a portion of the gate metal region. An electrical insulator 309 indicated by a broken line may be formed on the substrate In the body portion, the main field effect transistor 302 and the source region of the sense field effect transistor 304 are electrically insulated in a suitable manner.

The sense field effect transistor 304 is located near the corner of the main field effect transistor 302, as shown by the semiconductor component 301 in FIG. 3B. More optionally, the sense field effect transistor 304 is positioned adjacent the edge of the main field effect transistor 302, as shown by the semiconductor 321 in FIG. 3C. By changing only one source mask layer, the current ratio between the main field effect transistor and the sense field effect transistor can be adjusted.

Multiple sense field effect transistors with different current ratios can be easily incorporated into the main power MOS field effect transistor. Figure 3D shows a semiconductor component 310 containing two sense field effect transistors 312 and 314 located near the corners of the main field effect transistor 302. The source metal of the main field effect transistor and the two sense field effect transistors are located between the field effect transistor and the corresponding source pads 311, 313, 315 and the gate pad 317. The slits 316, 318, 319 formed in the common metal layer divide the common metal layer into a main field effect transistor and a gate metal region and a source metal region of each of the sense field effect transistors. The source pads 311, 313, 315 of the main field effect transistor and the sense field effect transistor are located above the respective metal regions. The gate pad 317 is located above a portion of the gate metal region. An electrical insulator 320, indicated by dashed lines, may be formed in the body portion of the substrate to electrically insulate the source regions of the main field effect transistor and the sense field effect transistor in a suitable manner.

It is more likely that there are many different methods of preparing semiconductor components of the above type. By way of example, Figures 4A through 4H show a series of cross-sectional views of a series of N-channel MOS field effect transistor semiconductor devices in accordance with an embodiment of the present invention. A P-channel MOS field effect transistor component can be fabricated using a similar process. As shown in FIG. 4A, an N- epitaxial layer 404 can be formed over the N+ substrate 402. A trench mask (not shown) is then formed over the N- epitaxial layer 404. The N- epitaxial layer 404 is etched to a predetermined depth by a trench mask to form a main field effect transistor gate trench 403A, a main field effect transistor gate trace trench 403B, and a sense field effect transistor. The gate trench 405A and the sense field effect transistor gate runner trench 405B and the insulating trench 406 are as shown in FIG. 4B. Gate oxide 410 is then grown on the sidewalls of trenches 403A, 403B, 405A, 405B, and 406. Filled with a conductive material 408 such as polysilicon The grooves 403, 405 and 406 are etched back as shown in Fig. 4C. According to this method, source terminals, trench gates, and insulating trenches can be simultaneously formed in a common preparation process.

To prepare the source region and the electrical insulator, the epitaxial layer 404 can be implanted with dopants that are opposite in their doping polarity (ie, conductivity type). As an example, a body mask (not shown) can be implanted into the P-type dopant 412, and in the main field effect transistor gate trench 403A, the main gate runner trench 403B, sensing field effect The transistor gate trench 405A, the sense field effect transistor gate runner trench 405B, and the N- epitaxial layer 404 near the insulating trench 406 are annealed. As shown in FIG. 4D, the P-type dopant 412 near the insulating trench 406 constitutes a body ring that helps provide electrical isolation between the main field effect transistor and the sense field effect transistor. In this way, both the main field effect transistor and the sensing field effect transistor element region and the body ring can be simultaneously formed in a common preparation process. It is to be noted that in the present embodiment, in order to prepare an N-channel element, a P-type dopant is implanted in the N-type doped epitaxial layer 404. Alternatively, an N-type dopant is implanted in the P-type doped epitaxial layer to prepare a P-channel element.

Referring to FIG. 4E, an N+ type dopant is implanted and annealed to prepare a main field effect transistor source region 413 and a sense field effect transistor source region 414. Over the N- epitaxial layer 404, an insulating layer 416, such as barium glass containing boronic acid (BPSG), is deposited. As shown in FIG. 4F, the insulating layer 416 is etched back to form contact openings 417 and 418 above the main field effect transistor gate channel 403B and the sensing field effect gate gate channel 405B, respectively; And forming contact openings 430 and 431 of the main field effect transistor source and the sense field effect transistor source, respectively. Contact implants 432, 434 can be implanted through contact openings 430 and 431.

A conductive layer is deposited within contact openings 417, 418, 430, and 431 over insulating layer 416 to form a common gate metal 420 (electrically coupled to main field effect transistor gate runner trench 403B and sensing field The effect transistor gate chute trench 405B), the main field effect transistor source metal 421 and the sense field effect transistor source metal 422. As shown in FIG. 4G, the conductive layer is etched back to form an opening 423 to insulate between the common gate metal 420 and the main field effect transistor source metal 421, and an opening 424 is formed to The insulation is insulated from the gate metal 420 and the sense field effect transistor source metal 422. Finally, as shown in FIG. 4H, a passivation layer 426 is deposited over openings 423, 424 and over common gate metal 420, main field effect transistor source metal 421, and sense field effect transistor source metal 422.

Please refer to FIG. 4A to FIG. 4H, the method shown only shows that the N-channel main field effect transistor and the sensing field effect transistor are prepared on one common substrate, and the sensing field effect transistor is not in the sensing field. The power transistor is under the source pad. However, with this method, it is possible to easily prepare a plurality of sensing field effect transistors with a plurality of different current ratios on a common substrate with a main field effect transistor without using an additional fabrication process and an additional mask layer. . Embodiments of the present invention enable the primary field effect transistor, the sense field effect transistor, and the electrical isolation therebetween to be formed on the same semiconductor substrate during a common fabrication process. Although, in accordance with embodiments of the present invention, the process characteristics and sequence used to fabricate the components are common, the masks used to fabricate the electrically insulating and field effect transistor components are different during the fabrication process.

According to an alternative embodiment of the present invention, a sensing field effect transistor probe can be formed at the center of the main field effect transistor, and the current ratio of the main field effect transistor is more accurate due to the reduced conduction current around the probe. stable. This current ratio is an important parameter for current regulation. The connection of the sense field effect transistor probe is achieved by a sensing pad located at the edge of the discrete power MOS field effect transistor. This combination does not require an additional mask layer and does not require an additional preparation process. This combined sense field effect transistor probe will share the same gate terminal and the same 汲 terminal with the main field effect transistor, but the source terminal is separated from the main field effect transistor.

Please refer to Figures 5A to 5B and Figures 6A to 6C. As shown, in the structure of the semiconductor device 500, except that the sensing field effect transistor probe is located at the center of the main field effect transistor, away from the sensing field effect transistor source pad, the other is shown in FIG. 3A. The structure of the semiconductor component 300 is similar. Semiconductor component 500 includes a main field effect transistor located above semiconductor wafer 501 and a sense field effect transistor probe 510 located at the center of main field effect transistor 502. The sensing field effect transistor probe 510 includes one or more sensing field effect transistor structures formed between field effect transistor structures, these field effects The transistor structure constitutes a main field effect transistor. The sense field effect transistor source pad 503 is located adjacent the edge of the semiconductor component 500 away from the sense field effect transistor probe 510. The sensing field effect transistor probe 510 is connected to the sensing field effect transistor source pad 503 via a conductive pin 511. The conductive pin 511 is sometimes also referred to as a sensing field effect transistor probe metal or sense. Measure the field effect transistor antenna. The sense field effect transistor probe metal 511 can be fabricated using the same metal layer as the main field effect transistor source metal 508 and gate metal 509. Preferably, a high conductivity material such as copper or aluminum is used to prepare the field effect transistor probe metal 511, and the field effect transistor probe metal 511 is made wide enough that the conductive pins do not become a resistor. The sense field effect transistor 510 (located under the probe metal 511) must not be wider or longer than the probe metal 511. The sense field effect transistor source pad 503 is preferably located at the periphery of the component 500 and is spatially remote from the location where the field effect transistor is located. The portion of the transistor that senses the field effect transistor 510 is surrounded by the main field effect transistor, most of which is surrounded by the main field effect transistor to minimize distortion or variation in the measurement.

The sensing field effect transistor probe 510, the conductive pin 511 and the sensing field effect transistor source pad 503 are both electrically insulated from the main field effect transistor 502 by the gap 505 and the underlying electrically insulating structure, which is the same as the above The electrical insulator 122 with the doped body looped insulating trenches shown in Figure 2 is similar. A gap 505 and an insulating structure surround the sense field effect transistor probe 510. As an example, semiconductor component 500 can be a discrete vertical power MOS field effect transistor. The main field effect transistor 502 is different from the combined circuit (IC) chip in that the IC chip has a plurality of transistors that are not connected in parallel, and the transistor has different gate signals, and the main field effect transistor 502 is The plurality of transistors operating in parallel with the common gate signal function as a separate discrete power MOS field effect transistor.

An electrical insulator (such as the electrical insulator 122 shown in Figure 2 above), or a region with a gate trench, without an active pole implant, or a deep well implant 512, may be suitably A pattern is formed on top of the substrate to insulate the source and body regions of the main field effect transistor 502 from the source and body regions of the sense field effect transistor probe 510. The conductivity type of the deep energy well 512 may be the same as that of the main field effect transistor body region, but the doping concentration is low, for example, about 4 x 10 ¹⁶ /cm ³ . The deep energy well may be deeper than the main field effect transistor body region, for example, about 1 to 2 micrometers (μm) deep, or more specifically between 1.4 and 2 micrometers (or about 1.7 μm), but not deeper. Gate trench. For reference, a typical body region has a depth of about 0.5 to 0.7 [mu]m. The deep well insulation may be several times the width of the cell spacing, for example 2 to 10 μm wide. The width of the deep well insulation can be as small as the pitch of a transistor unit. This depends on the processing capabilities of the manufacturing equipment. The sense field effect transistor source metal 608 and the main field effect transistor source metal 618 must not be shorted or bridged so that there is sufficient gap between them, the size of the gap depending on the processing capabilities of the manufacturing equipment.

Sensing the insulating structure around the field effect transistor also terminates the active region voltage, thereby causing the sense field effect transistor probe 510, the conductive pin 511, and the sense field effect transistor source pad 503 to be located due to the gap 505. The active field of the main field effect transistor and the "outer" of the insulating structure, the insulating structure extends from the edge of the active area. However, the sense field effect transistor probe 510 and the conductive pins 511 cause the sense field effect transistor probe 510 to be located in the main field effect transistor 502 transistor with minimal distortion. Forming the field effect transistor source pad 503, the conductive pin 511, and the metal layer of the sense field effect transistor probe source metal 608 may be the same as the gate metal 509 and the main field effect transistor source metal 508. It is to be noted that the conductive pin 511 is not a resistive element. As an example, as shown in FIG. 6A, its width can be at least the same as the sense field effect transistor.

The slits 507 are formed in a common metal layer, and the main field effect transistor 502 is separated from the gate metal 509 and the main field effect transistor source metal 508. Gate pad 506 is located over a portion of gate metal 509. The 汲 extreme (not shown) is located at the bottom of the semiconductor substrate and is shared by the main field effect transistor 502 and the sense field effect transistor 510.

Please refer to FIG. 5B, which shows the same top view as the semiconductor device 500 shown in FIG. 5A, except that in the figure, the passivation layer 533 covers the main field effect transistor source pad 508, the gate pad 506, and The entire wafer outside of the field effect transistor source pad 503 is sensed. The position of the sense field effect transistor probe 510 and the conductive pin 511 that are not covered by the passivation layer 533 is indicated by a broken line.

Please refer to Figures 5A and 6B. As shown, the sense field effect transistor probe 510 is located at the center of the main field effect transistor 502 and is insulated from the main field effect transistor 502 and the insulating structure 515 by a gap 505. As an example, the insulating structure 515 may contain an insulating layer 516, such as BPSG. The insulating structure may further comprise a deep potential well 512 formed on top of the N- epitaxial layer 513 and below the insulating layer 516. The deep potential well 512 insulates the source and body regions of the sense field effect transistor probe 510 from the main field effect transistor 502. The deep energy well 512 has the same conductivity type as the body region, but it is deeper than the body region. The layout of the deep energy well 512 generally follows the layout of the slit 505 shown in FIG. 5A. An epitaxial layer is deposited over the semiconductor substrate layer 514.

Please refer to Figures 5A and 6C. As shown, the conductive pin 511, the sense field effect transistor source pad 503, and the sense field effect transistor probe 510 are insulated from the main field effect transistor source pad 508 and the insulating structure 515 by a slit 505. . The deep potential well 512 insulates the source and body regions of the sense field effect transistor probe 510 from the source and body regions of the main field effect transistor 502. The deep well 512 further enhances the breakdown in the termination region and the insulating structure 515 to ensure that breakdown does not occur first here (in relatively small terminations and isolation regions), thereby enhancing the durability of the component. The deep energy well can be used as part of the termination structure surrounding the main field effect transistor (not shown) for use in semiconductor devices.

The insulating structure 515 can be configured such that the sense field effect transistor 510 is external to the insulating structure 515 (and therefore also "external" of the active field of the main field effect transistor) but the transistor portion of the sense field effect transistor 510 is substantially dominated by the home field. The active transistor unit of the effect transistor 502 is surrounded. In addition, the sense field effect transistor 502, the probe metal 511, and the sense field effect transistor source pad 503 can all be external to the insulating structure 515. The deep well 512 can also be located below the sense field effect transistor source pad 503 (shown in FIG. 7) and below the field effect transistor probe metal 511.

Similar to FIG. 2, as shown in FIG. 6C, the main field effect transistor 502 may contain a plurality of field effect transistor structures, each field effect transistor structure including a trenched gate 614, and suitably doped. A source 612 formed by a portion of the body region 616 of the N- epitaxial layer 513. Brake for each main field effect transistor component The poles 614 are all in the form of trenches, the trenches are lined with insulators such as oxides, and are filled with conductive polysilicon, and the gates 614 can be connected to the gate runners (not shown), and the gate runners Connected to the gate metal (not shown). Gate 614 may be perpendicular to the gate gate in cross section A-A. Alternatively, gate 614 is parallel to those elements in cross section A-A, but is shown here as being vertical for ease of illustration. The source 612 of a home field effect transistor unit can be coupled in parallel with other such elements by a main field effect transistor source metal 618. The source region 612 can be in electrical contact with the main field effect transistor source metal 618 via the conductive vias 620, 621 via the insulating layer 515. Body contacts 610 can be implanted at the bottom of vias 620, 621, and 623.

Similarly, the sense field effect transistor probe 510 also contains a plurality of component structures, each of which includes a trenched gate 622 electrically coupled to the gate runner (not shown). The gate runner is connected to a common gate metal (not shown). The gate runner is electrically connected to the gate pad 506 by an external gate metal 509. The sense field effect transistor source 602 is electrically coupled to other sense field effect transistor units via the vias 626 by sensing the field effect transistor source metal 608. The trenched gate 622, source 602, and body region 606 can be disposed as described above for the main field effect transistor gate 614, source 612, and body 616.

A source and body region of the main field effect transistor element, and a sensing field effect transistor probe are formed in the same N- epitaxial layer 513 on the (N+) substrate 514. The deep potential well 512 insulates the source and body regions of the main field effect transistor and the sense field effect transistor.

Referring to Fig. 7, there is shown a cross-sectional view of the semiconductor device 500 shown in Figs. 5A to 5B taken along line C-C. As shown in FIG. 7, the sensing field effect transistor source pad 503 is insulated from the main field effect transistor 502, the insulating layer 516, and the deep potential well 512 by the slit 505, and the insulating layer 516 and the deep potential well 512 can be Located below the sense field effect transistor source pad 503.

Please refer to Figure 5, Figure 6B to Figure 6C and Figure 7. As shown, the gate pad 506, the sense field effect transistor source pad 503, and the sense field effect transistor probe 510 can be located outside of the active region, ie The termination field of the main field effect transistor 502. The gate pad 506, the sense field effect transistor source pad 503, and the sense field effect transistor probe 510 can be combined with the main field effect by an insulating structure 515 with a sense field effect transistor source pad 503. The transistors 502 are separated.

Referring to FIG. 3A, although the sense field effect transistor 304 is located at the center of the main field effect transistor 302, it is difficult to control current propagation under a relatively large source pad 303 (eg, 150 micrometers by 150 micrometers). Therefore, it is difficult to control the current ratio of the field effect transistor current to the main field effect transistor current. By placing a relatively small sensing field effect transistor probe (eg, approximately 20 microns x 20 microns in size) at the center of the main field effect transistor and with a narrow sensing field effect The crystal probe conductive pin (as shown in Figures 5A-5B above) connects the sensing field effect transistor probe to the sensing field effect transistor pad, which easily controls current propagation. A suitable current ratio (eg, the true sensing ratio should be within 5% of the designed sensing ratio). In addition, this design places the sense field effect transistor at a temperature closer to the main field effect transistor (temperature affects the field effect transistor resistance/current) to resist the field effect transistor due to the larger sense. The distortion caused by the temperature difference generated by the source pad. The width from the edge of the main field effect transistor to the sense field effect transistor probe is about half the width of the main field effect transistor. Characterized in that the home effect transistor in shape close to a square or a rectangle approximately 10mm ² in.

In addition, a large temperature difference will also affect the current ratio and Rds-on. By placing the sensing field effect transistor at the center of the main field effect transistor and being surrounded by the main field effect transistor crystal, the temperature difference between the main field effect transistor crystal and the sensing field effect transistor crystal is reduced, avoiding It senses excessive distortion caused by the field effect transistor source pad. Multiple sense field effect transistor probes with various current ratios can also be easily incorporated into the center of the main field effect transistor.

Referring to Fig. 8, there is shown a schematic cross-sectional view showing current lines in the main field effect transistor 5O2 and the sense field effect transistor probe 510 of the semiconductor device of the type shown in Fig. 5A. As shown in Figure 8, the relatively large sense field effect transistor wafer pad (not shown) has been moved away from sensing. Where the field effect transistor probe 510 is located, the spacing between the sense field effect transistor probe and the main field effect transistor is reduced, thereby achieving less current propagation. Therefore, it is possible to more accurately design the Rds-on of the sensing field effect transistor, so that the sensing field effect transistor probe with the smallest distortion obtains the required current ratio.

Referring to Figure 5A, the type of semiconductor component shown can be used for striping in a gate trench power MOS field effect transistor (including a shield gate trench (SGT) or a planar gate power MOS field effect transistor). Or in closed cell technology.

It is more likely that there are many different methods for preparing the semiconductor element of the type shown in Fig. 5A above. As an example, FIGS. 9 to 9A and 10B-B' to 16B-B' and 10C-C' to 16C-C' are a series of representations of preparations 5A and 6 A schematic cross-sectional view of an N-channel MOS field effect transistor semiconductor device of the type shown along lines BB and CC. (A similar technique can be used to fabricate P-channel components.) This process requires no additional fabrication and additional masking layers as compared to the processes illustrated in Figures 4A through 4H.

Please refer to Figure 9. As shown, an N- epitaxial layer 904 is formed over the N+ substrate 902. A deep potential well mask (not shown) is formed over the N- epitaxial layer 904. As shown in FIG. 9A, a dopant having a polarity (i.e., conductivity type) opposite to the doping of epitaxial layer 904 is implanted into epitaxial layer 904 to form deep potential well 905A.

A trench mask (not shown) is then formed over the N- epitaxial layer 904. As shown in FIGS. 10B-B' and 10C-C', the N- epitaxial layer 904 is etched to a predetermined depth by a trench mask to form a main field effect transistor gate trench 903, sense The field effect transistor gate trench 905 and the insulating trench 906 are measured. A gate dielectric (e.g., oxide) 910 is then grown on the sidewalls of trenches 903, 905, and 906. As shown in Figures 11B-B' and 11C-C', the trenches 903, 905 and 906 are filled with a conductive material (e.g., polysilicon) 908 and etched back. According to this method, the source terminal and the trench gate can be simultaneously formed in a common preparation process.

As an example, as shown in Figures 12B-B' and 12C-C', the P-type dopant is implanted by the bulk mask (not shown) and is in the main field effect gate. The trench 903, the N-epitaxial layer 904 in the vicinity of the sense field effect gate trench 905, is annealed to form body regions 912 and 909. The depth of the body implant is less than the depth of the deep well implant. It is to be noted that in this example, in order to fabricate an N-channel element, a P-type dopant is implanted in the N-type doped epitaxial layer 904 to form body regions 912 and 909. Alternatively, an N-type dopant is implanted in the P-type doped epitaxial layer to form a P-channel element.

Please refer to Figures 13B-B' and 13C-C'. As shown, an N+ type dopant (in the case of an n-channel MOS field effect transistor) is implanted and annealed to form a main field effect transistor source region 913 and a sense field effect transistor source region. 914. Over the N- epitaxial layer 904, an insulating layer 916 (eg, barium glass containing boronic acid (BPSG)) is deposited. As shown in Figures 14B-B' and 14C-C', the insulating layer 916 is masked and etched back to prepare a contact opening 917 over the deep well 905A, and respectively form a source and sense of the main field effect transistor. Contact openings 930 and 931 of the field effect transistor source are measured. At the bottom of the contact openings 917, 930, and 931, the implant body contacts the implant 932.

Please refer to Figures 15B-B' and 15C-C'. As shown, a conductive layer is deposited over the insulating layer 916, and within the contact openings 917, 918, 930, and 931, forming a pattern to produce a primary field effect transistor source metal 921 and a sense field effect transistor source metal 922, And sensing the field effect transistor source pad 925. As shown in FIGS. 15B-B' and 15C-C', the conductive layer is etched back to form an opening 930 to insulate between the main field effect transistor source metal 921 and the sense field effect transistor source metal 922. An opening 932 is formed to insulate between the main field effect transistor source metal 921 and the sense field effect transistor source pad 925. Finally, as shown in FIGS. 16B-B' and 16C-C', a passivation layer 926 is deposited in the openings 930, 932 and deposited on the main field effect transistor source metal 921 and the sense field effect transistor source. Above the metal 922.

Please refer to Fig. 9, Fig. 9A, Figs. 10B-B' to 16B-B' and Figs. 10C-C' to 16C-C'. As shown, it is only indicated that the N-channel main field effect transistor and the sensing field effect transistor are fabricated on a common substrate, and the sensing field effect transistor is not located in the sensing field effect transistor source pad. Below. However, with this method, multiple sensing field effect transistors with various current ratios can be easily fabricated on a common substrate without the need for additional fabrication processes and additional masking layers. In an embodiment of the present invention, a main field effect transistor, a sense field effect transistor, and electrical insulation therebetween may be formed by the same semiconductor substrate in a common fabrication process. Although, in accordance with embodiments of the present invention, the process characteristics and sequence used to fabricate the components are common, the masks used to prepare the electrical insulation and field effect transistor components during fabrication are different.

Although the invention has been described in detail with respect to certain preferred versions, other versions are possible. Therefore, the scope of the invention should be construed as being limited by the scope of the appended claims. Any option (whether preferred or not) can be combined with any other option (whether preferred or not). In the following claims, the indefinite article "a" or "an" The scope of the appended patent application shall not be construed as a limitation of meaning and function unless the meaning of the function is clearly indicated by "meaning".

Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the description Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

500‧‧‧Semiconductor components

501‧‧‧Semiconductor wafer

502‧‧‧Home field effect transistor

503‧‧‧ Sense field effect transistor source pad

505, 507‧ ‧ gap

506‧‧‧Gate pad

508‧‧‧Home field effect transistor source metal

509‧‧‧gate metal

510‧‧‧Sensor field effect transistor probe

511‧‧‧Electrical pins

C-C‧‧‧ line

Claims (20)

A semiconductor component comprising: a main field effect transistor comprising a source, a body and a gate; a sensing field effect transistor comprising a source, a body and a gate, wherein the transistor of the field effect transistor is sensed Part of being surrounded by a transistor of the main field effect transistor and located adjacent to the transistor of the main field effect transistor; a sensing field effect transistor source pad located at an edge of the semiconductor component, wherein the sensing field effect transistor a portion of the transistor that is separate from the sense field effect transistor source pad, and the sense field effect transistor source pad is coupled to the sense field effect transistor by a sense field effect transistor probe metal a portion of the crystal of the crystal; and an electrically insulating structure electrically insulating the source and body regions of the main field effect transistor from the source and body regions of the sensing field effect transistor; wherein the main field effect transistor, the sense The field effect transistor and the electrically insulating structure are formed in a single semiconductor wafer, and the transistor portion of the sensing field effect transistor and the sensing field effect transistor source pad are disposed by configuring an insulating structure Active field of the main field effect transistor Portion; wherein the semiconductor element is a separate system of vertical field effect transistors. The semiconductor device of claim 1, wherein the sensing field effect transistor probe metal, the main field effect transistor source metal, and the gate metal are separate portions of the same single metal layer. . The semiconductor component of claim 1, wherein the sense field effect transistor probe metal is not a resistor. The semiconductor component according to claim 1, wherein the sensing field effect power The portion of the crystal of the crystal is not as wide as the metal of the sense field effect transistor probe. The semiconductor component of claim 1, wherein the transistor portion of the sense field effect transistor is located near a center of the main field effect transistor. The semiconductor device of claim 1, wherein the transistor portion of the sensing field effect transistor, the sensing field effect transistor probe metal, and the sensing field effect transistor source pad are all The insulating structure is separated from the main field effect transistor and is located at the periphery of the main field effect transistor by the field effect transistor source pad. The semiconductor device of claim 1, wherein the insulating structure comprises one or more deep potential wells formed on top of the epitaxial layer, wherein the deep potential well enables the source of the sense field effect transistor The pole and body regions are insulated from the source and body regions of the main field effect transistor, wherein the conductivity type of the deep potential well is the same as the conductivity type of the body region of the main field effect transistor. The semiconductor component of claim 7, wherein the depth of the deep well is greater than the depth of the body region of the main field effect transistor. The semiconductor component of claim 8, wherein the deep potential well has a depth of between about 1 micrometer and 2 micrometers, and the main field effect transistor has a body region depth of between about 0.5 micrometers and 0.7 micrometers. The semiconductor device of claim 8, wherein the deep potential well has a doping concentration that is less than a doping concentration of the body region of the main field effect transistor. The semiconductor device according to claim 10, wherein the deep energy well has a doping concentration of about 4 × 10 ¹⁶ /cm ³ . The semiconductor device of claim 7, wherein the deep potential well between the transistor portion of the field-effect transistor and the main field effect transistor is approximately Double the width of the cell spacing. The semiconductor device of claim 7, wherein the deep well width between the transistor portion of the sense field effect transistor and the main field effect transistor is about 2 to 10 microns. The semiconductor device of claim 1, wherein the main field effect transistor and the sensing field effect transistor are formed of a metal oxide semiconductor field effect transistor MOSFET. The semiconductor device of claim 1, wherein the electrically insulating structure between the sensing field effect transistor and the main field effect transistor is formed by a body ring near an insulating trench, wherein one A metal layer over the electrically insulating structure electrically connects the gate of the sense field effect transistor to the gate of the main field effect transistor. A method for preparing a semiconductor device including a main field effect transistor and a sensing field effect transistor, comprising: a) preparing a source, a body and a gate of the main field effect transistor in a substrate; Preparing a source, a body and a gate of the sensing field effect transistor in the substrate, wherein the sensing field effect transistor is located near a center of the main field effect transistor, wherein the sensing field effect transistor a portion of the transistor surrounded by the transistor of the main field effect transistor and located adjacent to the transistor of the main field effect transistor to reduce distortion and error of the field-effect transistor measurement, wherein the field-effect transistor is sensed And the main field effect transistor is a vertical field effect transistor sharing a common substrate; c) in the substrate, preparing an electrically insulating structure, the source and body regions of the main field effect transistor, and the sensing field effect The source of the transistor is electrically insulated from the body region; and d) preparing a sensing field effect transistor source pad at the edge of the main field effect transistor and connecting to the metal via a sensing field effect transistor probe Sense field effect transistor The sensing field effect transistor and the sensing field effect transistor source pad are separated from the main field effect transistor by the electrically insulating structure. The method of claim 16, wherein a) to d) further comprise: i) preparing a first conductivity type outer layer over a heavily doped first conductivity type substrate; ii) Preparing a deep well mask above the epitaxial layer; and iii) implanting a dopant of the second conductivity type on top of the epitaxial layer in the insulating structure region of the semiconductor device to form a deep well region The second conductivity type is opposite to the first conductivity type. The method of claim 17, wherein iii) further comprises preparing the deep energy well region such that the deep energy well region has a depth of about 1 to 2 microns and a doping concentration of about 4×10 ^{16 .} /cm ³ . The method of claim 16, further comprising: preparing a main field effect transistor gate trench, a sensing field effect transistor gate trench, and an insulating trench, wherein the insulating trench is located in the main field effect Between the transistor and the sensing field effect transistor, and forming part of the electrically insulating structure, wherein the insulating trench is not connected to a gate voltage; an insulating layer is deposited over the electrically insulating structure; and the electrically insulating structure is Above the insulating layer, a metal layer is prepared which connects the gate of the sense field effect transistor to the gate of the main field effect transistor. The method of claim 16, wherein the semiconductor component is a discrete vertical field effect transistor.