TWI499969B - Reordering buffer - Google Patents

Description

Reorder buffer

The present invention relates to a reordering buffer, and more particularly to a reordering buffer suitable for continuous flow fast Fourier transform operations.

At present, Fast Fourier Transform (FFT) is widely used in wired and wireless communication systems and electronic motor engineering fields, and has great application value, but its computational complexity is extremely high. There are several ways in which the data stream can be read out in a natural order in the application literature for reordering buffers. For example, an improved Multipath Delay Commutator fast Fourier transform architecture divides an input data stream into an even-indexed and odd-indexed data stream. Then perform the Butterfly Operation for each level through appropriate scheduling; to achieve the natural order output, add a Reordering buffer to the even index data stream before the last level of the base unit. Write in reversed bits, read out in natural order, while odd indexed data streams are written in natural order and bits are read back. However, this architecture is only applicable to single data stream input and output, resulting in a low overall system throughput.

In addition, in practical applications (such as OFDM systems), it is often necessary to perform a continuous-flow fast Fourier transform operation, taking a parallel pipelined Fast Fourier Transform Processor (Parallel Pipelined FFT Processor) as an example, because of high computation output (throughput), so it is used by many high-speed communication systems, but the output of the general pipelined fast Fourier transform processor has bit-reverse characteristics. If you want to convert it into a natural order output, you need to add An additional reordering buffer. However, at present, there is no technology that can convert the inverted output of the bit line output of the parallel pipeline type fast Fourier transform processor into a natural order output, which is not a delay problem, or a technical dilemma of single path input and output. Furthermore, in order to maintain the fast Fourier transform calculation output without delay, it is necessary to have enough temporary memory space and high-performance data access mechanism. However, the required memory area must be quite large, which does not make the overall system architecture shrink. Therefore, how to design a novel reorder buffer can use the minimum memory area as the data access mechanism and the bit of the parallel pipeline fast Fourier transform processor when supporting continuous flow fast Fourier transform operation. The conversion of the inverted output to a natural sequence is an urgent problem to be solved.

In view of the above, the present invention has been directed to the lack of the prior art described above, and proposes a reordering buffer to effectively overcome the above problems.

It is a primary object of the present invention to provide a reordering buffer that converts the bit reverse output of a parallel pipelined fast Fourier transform processor into a natural sequential, continuous, delayless output in a manner that is most cost effective.

To achieve the above objective, the present invention provides a reordering buffer including a first memory module, a second memory module, a write switch, a read/write controller, and a read switch. . The first memory module has m first memory cells, each first memory cell stores N/2m pen bit data, N is a bit length of the Fourier transform, and m is a power of 2. The integer of the second power; the second memory module has m second memory units, each second single The memory unit stores N/2m pen bit data. The write switch is electrically connected to the first memory module and the second memory module, and the write switch receives the inverse bit data of the m Fourier transforms, and exchanges the reverse bit data into a preset. The bit data is written in the arrangement mode and alternately written into the first memory module and the second memory module. The read/write controller is electrically connected to the write switch, the first memory module and the second memory module, and the read/write controller controls the write bit data to be written into the first memory module or the second memory In the module, the bit data is read from the first memory module or the second memory module. The read switch is electrically connected to the first memory module, the second memory module and the read/write controller, and the read switch alternates the bits in the first memory module and the second memory module The data is exchanged for the natural order output bit data, and the output bit data is output in m output paths. The novel reordering buffer architecture designed by the invention not only supports m times parallel fast Fourier transform input and output, but also can be applied to continuous flow fast FFT operation, which can be used quickly. The communication products of Fourier transform operation have higher application value of computing output.

The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

10‧‧‧First memory module

12‧‧‧Second memory module

14‧‧‧Write switch

16‧‧‧Reading and writing controller

18‧‧‧Reading switch

20‧‧‧Parallel Pipeline Fast Fourier Transform Processor

22‧‧‧Multiplexer

Figure 1 is a block diagram of the circuit of the present invention.

2A-2E is a schematic diagram of an embodiment of the present invention in which 128-bit lengths are exchanged for natural sequential output.

Figure 3 is a schematic diagram of the switching mode of the write switch of the present invention.

4A to 4E are diagrams showing an embodiment in which the 256-bit length is exchanged for natural order output. schematic diagram.

Please refer to FIG. 1 , which is a circuit block diagram of the present invention. The reordering buffers are a first memory module 10, a second memory module 12, a write switch 14, a read/write controller 16, and a read switch 18. The write switch 14 is electrically connected to the first memory module 10 and the second memory module 12; the read/write controller 16 is electrically connected to the write switch 14, the first memory module 10, and the second memory. The module 12 is electrically connected to the first memory module 10, the second memory module 12, and the read/write controller 16. The first memory module 10 has m first memory cells, each first memory cell stores N/2m pen bit data, N is the bit length of the Fourier transform, and m is 2 An integer of the power of the power. The second memory module 12 has m second memory cells, and each second memory cell stores N/2m pen metadata. The write switch 14 is an inverse bit data of m pen Fourier transforms each time, and the reverse bit data is output by a parallel pipeline type fast Fourier transform processor 20, and a parallel pipeline type fast Fourier transform processor ( The parallel pipelined FFT processor 20 is electrically connected to the write switch 14. The write switch 14 exchanges the reverse bit data into a preset arrangement of the bit data, and alternately writes the first memory module 10 and the second memory module 12. The read/write controller 16 controls the write bit data to be written into the first memory module or the second memory module, or is read from the first memory module 10 or the second memory module 12. Bit data. The read switch 18 alternately exchanges the bit data in the first memory module 10 and the second memory module 12 into natural bit output data, and outputs the bit data in m output paths. Output. The reordering buffer further includes a multiplexer 22 electrically connected to the first memory module 10, the second memory module 12, and the read switch 18, the first memory module 10 and the second memory. The bit data in module 12 is multiplexed The device 22 selects the output, and the read switch 18 receives the bit data output by the multiplexer 22 for exchange as a natural order output bit data.

In order to further explain how to exchange the inverse bit data outputted by the parallel pipeline type fast Fourier transform processor into the natural order output bit data, the present invention divides the switching mode into two types according to the fast Fourier transform (FFT) length N. And applies to any power of 2 power points, as explained later. The write switch 14 or the read switch 18 respectively selects to write the write bit data into the first memory module 10 or the second memory module 12 according to the bit length N of the Fourier transform, or The bit data is read from the first memory module 10 or the second memory module 12, and the alternating formula (1) is as follows: α = log ₂ ( N /2 m ² )..... (1 )

Wherein, α is an integer, N is a bit length of the Fourier transform, and m is an even number, that is, the number of parallelisms output by the parallel pipeline type fast Fourier transform processor 20.

The following will explain in detail the two read and write scheduling modes in which α is even and odd. First, let α be an even number as an example. Please refer to FIG. 1 , 2A to 2E , and 3 , and 2A to 2E are examples in which N is 128-bit length exchanged to natural sequential output. Schematic diagram, FIG. 3 is a schematic diagram of an exchange mode of the write switch of the present invention. When the length N of the Fourier transform bit is 128, and after the parallel pipeline type fast Fourier transform processor 20 whose m is 8 times parallel, the inverted bit data of 128 points is output, and the α system is even, then the first exchange is implemented. Mode; in detail, the write switch 14 writes the write bit data into the first memory module 10 and the second memory module after processing the reverse bit data in an alternate manner. In the group 12, the read switch 18 reads the bit data from the first memory module 10 and the second memory module 12 in an alternate manner. First, as shown in FIG. 2A, the output of the present invention is 128 bits past the 8-time parallel pipeline type fast Fourier transform processor 20. The write switch 14 exchanges the reverse bit data according to a control signal selected by a preset arrangement. The control signal selected by the preset arrangement is generated by a clock cycle counter to generate each memory bit. The address, the preset arrangement is related to the bit length N of the Fourier transform. The Fourier transform bit length N is 128, which is divided into 16 groups of eight bit parameters, for example, 16 groups are numbered C0~C15. Further, as shown in FIG. 2B, the inverted bit data of 128 points of the present invention is outputted by the switch exchange; the write switch 14 is the eight bits of each of the two sets of reverse bit data. The meta-parameters are arranged in eight ways, for example, the eight arrays are numbered CROT(0)~CROT(7), and each arrangement follows the CROT(0)~CROT(7) eight write exchanges of Figure 3. The mode is exchanged, the reverse bit data is exchanged for writing the bit data, and the written bit data is alternately written into the first memory module 10 and the second memory module 12. 2C, 2D, and 2E, 2C and 2D are respectively a schematic diagram of reading and writing scheduling of the present invention, and a schematic diagram of storing the written bit data in the memory in the present invention; wherein 2D is an odd frame (frame) storage time division, 2E is the storage of the even frame, the frame is a period of (N / m), and is assumed to count from one. The first memory module 10 has m first memory cells. If m is 8, the first memory cells of the eight groups are Bank_A0~Bank_A7, and each first memory cell stores N. /2m pen bit data, so each first memory cell has 8 storage addresses. Similarly, the second memory module 12 has m second memory cells. If m is 8, the eight second memory cells are Bank_B0~Bank_B7, because each second memory is The unit stores N/2m pen bit data, so each second memory cell has 8 storage addresses.

After understanding the relative relationship between each of the above components, the following is a detailed description of the actual operation. The write switch 14 will associate eight bits of each of the two sets of reverse bit data. The order is in the order of CROT(0), CROT(4), CROT(2), CROT(6), CROT(1), CROT(5), CROT(3), CROT(7). In detail, the write switch 14 will reverse the bit data C0[0, 64, 32, 96, 16, 80, 48, 112] and C1 [8, 72, 40, 104, of the parallel pipelined fast Fourier transform processor 20, 24, 88, 56, 120] is exchanged in CROT (0) arrangement, the exchange mode is to input the eight bit parameters [0, 64, 32, 96, 16, 80, 48, 112] of the first group into eight in parallel. The first address A0 of the first memory cell Bank_A0~Bank_A7, the eight bit parameters of the second group [8, 72, 40, 104, 24, 88, 56, 120] are input in parallel to the eighth group of the second single第 The first address B0 of the memory cells Bank_B0~Bank_B7, and the first memory cell of each first memory cell and each second memory cell is displaced Initial memory unit.

In the continuation, the write switch 14 will reverse the bit data C2 [4, 68, 36, 100, 20, 84, 52, 116] and C3 [12, 76, 44, 108, 28, 92 of the parallel pipelined fast Fourier transform processor 20, 60,124] exchanged in CROT(4) arrangement; the exchange mode is to arrange eight bit parameters of the third group from the initial memory cell unit by four memory cells. It is [20, 84, 52, 116, 4, 68, 36, 100] and is input to the second address A1 of the eight groups of first memory cells Bank_A0~Bank_A7; the eight bit parameters of the fourth group are After the initial memory cell is shifted by four memory cells, the eight bit parameters are arranged as [28, 92, 60, 124, 12, 76, 44, 108] and input to the eight groups of second memory cells Bank_B0. The second address B1 in ~Bank_B7.

In the continuation, the write switch 14 will reverse the bit data C4 [2, 66, 34, 98, 18, 82, 50, 114] and C5 [10, 74, 42, 106, 26 of the parallel pipelined fast Fourier transform processor 20, 90,58,122] Exchanged in CROT(2) arrangement; the exchange mode is to shift the eight bit parameters of the fifth group from the initial memory cell to two memory cells, and the eight bit parameters are arranged as [ 50, 114, 2, 66, 34, 98, 18, 82], and input to the third address A2 of the eight groups of first memory cells Bank_A0~Bank_A7; the eight bit parameters of the sixth group are After the initial memory cell is shifted by two memory cells, the eight bit parameters are arranged as [58, 122, 10, 74, 42, 106, 26, 90] and input to the eight groups of second memory cells Bank_B0. The third address in the ~Bank_B7 is B2.

In the continuation, the write switch 14 will reverse the bit data C6 [6, 70, 38, 102, 22, 86, 54, 118] and C7 [14, 78, 46, 110, 30, 94 of the parallel pipelined fast Fourier transform processor 20, 62,126] exchanged in CROT(6) arrangement; the exchange mode is to arrange eight bit parameters of the seventh group from the initial memory unit by six memory cells. [38,102,22,86,54,118,6,70], and input to the fourth address A3 of the eight groups of first memory cells Bank_A0~Bank_A7; the eight bit parameters of the eighth group are After the initial memory cell is shifted by six memory cells, the eight bit parameters are arranged as [46, 110, 30, 94, 62, 126, 14, 78] and input to the eight groups of second memory cells Bank_B0. The fourth address B3 in ~Bank_B7.

In the continuation, the write switch 14 will reverse the bit data C8 [1, 65, 33, 97, 17, 81, 49, 113] and C9 [9, 73, 41, 105, 25 of the parallel pipeline type fast Fourier transform processor 20, 89,57,121] exchanges in CROT(1) arrangement; the exchange mode is to shift the eight bit parameters of the ninth group from the initial memory cell to one memory cell, and eight bit parameters. Arranged as [113,1,65,33,97,17,81,49] and input to the fifth address A4 of the eight groups of first memory cells Bank_A0~Bank_A7; One bit parameter from initial memory After the cell is shifted by one memory cell, the eight bit parameters are arranged as [121, 9, 73, 41, 105, 25, 89, 57] and input into the eight groups of second memory cells Bank_B0~Bank_B7. The fifth address is B4.

In the continuation, the write switch 14 will reverse the bit data C10 [5, 69, 37, 101, 21, 85, 53, 117] and C11 [13, 77, 45, 109, 29, 93 of the parallel pipelined fast Fourier transform processor 20, 61,125] exchanges in CROT(5) arrangement; the exchange mode is to shift the eight bit parameters of the eleventh group from the initial memory cell to five memory cells, and eight bit parameters. Arranged as [101, 21, 85, 53, 117, 5, 69, 37] and input to the sixth address A5 of the eight groups of first memory cells Bank_A0~Bank_A7; eight of the twelveth group After the bit parameter is shifted from the initial memory cell by five memory cells, the eight bit parameters are arranged as [109, 29, 93, 61, 125, 13, 77, 45] and input to the eighth group.第六 The sixth address B5 in the memory cells Bank_B0~Bank_B7.

In the continuation, the write switch 14 converts the inverse bit data C12 [3, 67, 35, 99, 19, 83, 51, 115] and C13 [11, 75, 43, 107, 27 of the parallel pipelined fast Fourier transform processor 20, 91, 59, 123] exchanged in CROT (3) arrangement; the exchange mode is to shift the eight bit parameters of the thirteenth group from the initial memory cell to three memory cells, eight bits The meta-parameters are arranged as [83, 51, 115, 3, 67, 35, 99, 19] and input to the seventh address A6 of the eight sets of first memory cells Bank_A0~Bank_A7; After the eight bit parameters are shifted from the initial memory cell to three memory cells, the eight bit parameters are arranged as [91, 59, 123, 11, 75, 43, 107, 27] and input to the eighth group.第七 The seventh address B6 in the memory cells Bank_B0~Bank_B7.

Continuing, the write switch 14 will parallel the pipeline type fast Fourier transform processor 20 The reverse bit data C14[7,71,39,103,23,87,55,119] and C16[15,79,47,111,31,95,63,127] are exchanged in the CROT(7) arrangement; the exchange mode is After shifting the eight bit parameters of the fifteenth group from the initial memory cell to seven memory cells, the eight bit parameters are arranged as [71, 39, 103, 23, 87, 55, 119, 7], and Input to the eighth address A7 of the first group of memory cells Bank_A0~Bank_A7; and shift the eight bit parameters of the sixteenth group from the initial memory cell to seven memory cells The eight bit parameters are arranged as [79, 47, 111, 31, 95, 63, 127, 15] and input to the eighth address B7 of the eight sets of second memory cells Bank_B0~Bank_B7.

The write switch 14 exchanges all the 128-bit reverse bit data into the write bit data, and alternately writes the first memory module 10 and the second memory module 12, and then the multiplexer The device selects and outputs the bit data in the first memory module 10 and the second memory module 12, for example, selects to output the bit data 0~7 in Bank_A0~Bank_A7 (as shown by the dashed box in the 2D picture) Then, the read switch 18 exchanges the 0~7 bit data into the output bit data in the natural order from 0 to 7; then alternately selects the bit data 8~15 in Bank_B0~Bank_B7 to output (such as As shown by the dashed box of the 2D map, the read switch 18 then exchanges 8 to 15 bits of data into output bit data in natural order from 8 to 15. Further, as shown in FIG. 2E, the 128-bit data is exchanged for the natural-sequential output output bit data for the read switch 18, and is presented in the other two groups of memory modules GroupA and GroupB, for example, Bank_A0~Bank_A7 in GroupA. The first address will be sequentially arranged as 0~7 bits, and the first address of Bank_B0~Bank_B7 in GroupB will be sequentially arranged as 8~15 bits; Bank_A0~Bank_A7 will be the second bit. The address will be in the order of 16~23 bits, and the second address of Bank_B0~Bank_B7 in GroupB will be arranged in the order of 24~31 bits, and the 128-bit data will be all natural in this order. Read out sequentially. At this time, when The 0~7 bits in GroupA are output to the function end of the next stage, and the vacated address can be written by the write switch 14 to write the next 128-bit reverse bit data. Since the next bit data can be written as long as the address is vacated, the second memory module 12 is read when the first memory module 10 is written, and the parallel pipeline can be alternately read/written. The bit-inverted output of the fast Fourier transform processor transforms into a natural sequential, continuous, delay-free output, which in turn increases output efficiency.

Next, taking α as an odd number as an example, please refer to FIG. 1 , FIG. 3 , and FIG. 4A to FIG. 4E simultaneously. FIGS. 4A to 4E are schematic diagrams showing an embodiment in which the 256-bit length is exchanged as a natural sequential output. When the length N of the Fourier transform bit is 256, the output is 256 points of reverse bit data after the parallel pipeline type fast Fourier transform processor 20 whose m is 8 times parallel. Since the α system is an odd number, the second type is implemented. Switch mode; in detail, the write switch 14 first writes the write bit data to the first memory module 10 once, and then writes the write bit data in an alternate manner of each write twice. In the second memory module 12 and the first memory module 10, the read switch 18 is read out from the first memory module 10 and the second memory module 12 in an alternate manner. Bit data. As shown in FIG. 4A, it is a schematic diagram of the output of the present invention having a bit length of 256 points and an 8-time parallel pipeline type fast Fourier transform processor 20. The write switch 14 exchanges the reverse bit data according to the control signal selected by the preset arrangement. The length of the Fourier transform bit is 256, which is divided into 32 groups of eight bit parameters, for example, 32 groups are numbered as C0. ~C31. As shown in FIG. 4B, the 256-point reverse bit data of the present invention is outputted by the switch exchange; the write switch 14 is the eight bits of each of the four sets of reverse bit data. The meta-parameters are arranged in eight ways, for example, the eight arrays are numbered CROT(0)~CROT(7), and each arrangement follows the CROT(0)~CROT(7) eight write exchanges of Figure 3. The mode is exchanged, and the reverse bit data is exchanged by the write switch 14 into the write bit data of the preset arrangement mode, and the write bit data is alternately written into the first memory module 10 and the second memory. In the body module 12. 4C, 4D, and 4E, FIG. 4C and FIG. 4D are respectively a schematic diagram of reading and writing scheduling of the present invention, and a schematic diagram of storing the writing bit data in the memory in the memory; the first memory model Group 10 has m first memory cells. If m is 8, then the first memory cells of the 8 groups are Bank_A0~Bank_A7, and each N^m pen cell is stored for each first memory cell. Data, so each first memory unit has 16 storage addresses. Similarly, the second memory module 12 has m second memory cells. If m is 8, the eight second memory cells are Bank_B0~Bank_B7, because each second memory is The unit stores N/2m pen bit data, so each second memory cell has 16 storage addresses.

After understanding the relative relationship between each of the above components, the actual operation will be described in detail as an example. The write switch 14 will arrange the reverse bit data in eight ways, in the order of CROT (0), CROT ( 4), CROT (2), CROT (6), CROT (1), CROT (5), CROT (3), CROT (7), as will be described later.

First, the write switch 14 will reverse the bit data C0[0,128,64,192,32,160,96,224], C1[16,144,80,208,48,176,112,240], C2[8,136,72,200,40,168,104,232 of the parallel pipelined fast Fourier transform processor 20. ] and C3 [24, 152, 88, 216, 56, 184, 120, 248] are exchanged in CROT (0) arrangement, the exchange mode is the first group of eight bit parameters [0, 128, 64, 192, 32, 160, 96, 224] and the fourth group of eight The bit parameters [24, 152, 88, 216, 56, 184, 120, 248] are input in parallel to the first address A0 and the fourth address A1 of the first group of memory cells Bank_A0~Bank_A7, respectively, and the eight bits of the second group. The meta-parameters [8, 136, 72, 200, 40, 168, 104, 232] and the third set of eight bit parameters [24, 152, 88, 216, 56, 184, 120, 248] are input in parallel to the eight sets of second memory cells, respectively. The first address B0 and the second address B1 in Bank_B0~Bank_B7, and the first memory cell in each first memory cell and each second memory cell As the initial memory unit of the displacement.

In the continuation, the write switch 14 will reverse the bit data C4 [4, 132, 68, 196, 36, 164, 100, 228], C5 [20, 148, 84, 212, 52, 180, 116, 244], C6 [12, 140, 76, 204, 44, 172, 108, 236] of the parallel pipelined fast Fourier transform processor 20 and C7[28,156,92,220,60,188,124,252] is exchanged in CROT(4) arrangement; the exchange mode is to shift the eight bit parameters of the fifth and eighth groups from the initial memory cell by four memory. After the body unit, the eight bit parameters of the fifth group are arranged as [36, 164, 100, 228, 4, 132, 68, 196] and input to the third address A2 of the eight groups of first memory cells Bank_A0~Bank_A7; The eight bit parameters are arranged as [60, 188, 124, 252, 28, 156, 92, 220] and input to the fourth address A3 of the eight sets of first memory cells Bank_A0~Bank_A7. After shifting the eight bit parameters of the sixth group and the seventh group from the initial memory cell to four memory cells, the eight bit parameters of the sixth group are arranged as [52, 180, 116, 244, 20, 148, 84, 212], And input to the third address B2 of the eight groups of the second memory cells Bank_B0~Bank_B7; the eight bit parameters of the seventh group are arranged as [44, 172, 108, 236, 12, 140, 76, 204] and input to the eighth group of the second group.第 The fourth address B3 in the memory cells Bank_B0~Bank_B7.

Next, the write switch 14 will reverse the bit data C8 [2, 130, 66, 194, 34, 162, 98, 226], C9 [18, 146, 82, 210, 50, 178, 114, 242], C10 [10, 138, 74, 202, 42, 170, 106, 234 of the parallel pipelined fast Fourier transform processor 20. ] and C11 [26, 154, 90, 218, 58, 186, 122, 250] exchanged in CROT (2) arrangement; The change mode is to shift the eight bit parameters of the ninth group and the twelfth group from the initial memory cell to two memory cells, and the eight bit parameters of the ninth group are arranged as [98, 226, 2, 130 , 66, 194, 34, 162], and input to the fifth address A4 of the eight groups of first memory cells Bank_A0~Bank_A7; the eight bit parameters of the twelfth group are arranged as [122, 250, 26, 154, 90, 218, 58, 186 ], and input to the sixth address A5 of the eight groups of first memory cells Bank_A0~Bank_A7. After shifting the eight bit parameters of the tenth and eleventh groups from the initial memory cell to two memory cells, the eight bit parameters of the tenth group are arranged as [114, 242, 18, 146, 82, 210, 50, 178], and input to the fifth address B4 of the eight sets of second memory cells Bank_B0~Bank_B7; the eight bit parameters of the eleventh group are arranged as [106, 234, 10, 138, 74, 202, 42, 170], and Input to the sixth address B5 of the eight sets of second memory cells Bank_B0~Bank_B7.

In the continuation, the write switch 14 will reverse the bit data C12 [6, 134, 70, 198, 38, 166, 102, 230], C13 [22, 150, 86, 214, 54, 182, 118, 246], C14 [14, 142, 78, 206, 46, 174, 110, 238] of the parallel pipelined fast Fourier transform processor 20 and C15[30,158,94,222,62,190,126,254] is exchanged in the arrangement of CROT(6); the exchange mode is to shift the eight bit parameters of the thirteenth group and the sixteenth group from the initial memory cell unit by six singles. After the memory unit, the eight bit parameters of the thirteenth group are arranged as [70, 198, 38, 166, 102, 230, 6, 134], and are input to the seventh address A6 of the eight groups of first memory cells Bank_A0~Bank_A7; The eight bit parameters of the sixteenth group are arranged as [94, 222, 62, 190, 126, 254, 30, 158] and input to the eighth address A7 of the eight sets of first memory cells Bank_A0~Bank_A7. After shifting the eight bit parameters of the fourteenth and fifteenth groups from the initial memory cell to six memory cells, the eightteenth group of eight The bit parameters are arranged as [86, 214, 54, 182, 118, 246, 22, 150] and input to the seventh address B6 of the eight sets of second memory cells Bank_B0~Bank_B7; the eight bit parameters of the fifteenth group are arranged as [ 78, 206, 46, 174, 110, 238, 14, 142], and input to the eighth address B7 of the eight sets of second memory cells Bank_B0~Bank_B7.

Next, the write switch 14 will reverse the bit data C16 [1, 129, 65, 193, 33, 161, 97, 225], C17 [17, 145, 81, 209, 49, 177, 113, 241], C18 [9, 137, 73, 201, 41, 169, 105, 233 of the parallel pipeline type fast Fourier transform processor 20. And C19 [25, 153, 89, 217, 57, 185, 121, 249] are exchanged in the arrangement of CROT (1); the exchange mode is to shift the eight bit parameters of the seventeenth and twentieth groups from the initial memory cell. After the memory unit, the eight-bit parameters of the seventeenth group are arranged as [225, 1, 129, 65, 193, 33, 161, 97] and input to the ninth of the eight groups of first memory cells Bank_A0~Bank_A7. Address A8; the octet parameters of the twentieth group are arranged as [249, 25, 153, 89, 217, 57, 185, 121] and input to the tenth address A9 of the eight groups of first memory cells Bank_A0~Bank_A7. . After shifting the eight bit parameters of the eighteenth and nineteenth groups from the initial memory cell to one memory cell, the eight bit parameters of the eighteenth group are arranged as [241, 17, 145, 81, 209 , 49, 177, 113], and input to the ninth address B8 of the eight sets of second memory cells Bank_B0~Bank_B7; the eight bit parameters of the nineteenth group are arranged as [233, 9, 137, 73, 201, 41, 169, 105], And input to the tenth address B9 of the eight groups of the second memory cells Bank_B0~Bank_B7.

In the continuation, the write switch 14 converts the inverse bit data C20 [5, 133, 69, 197, 37, 165, 101, 229], C21 [21, 149, 85, 213, 53, 181, 117, 245], C22 [13, 141, 77, 205, 45, 173, 109, 237] of the parallel pipeline type fast Fourier transform processor 20 and C23[29,157,93,221,61,189,125,253] is exchanged in the arrangement of CROT(5); the exchange mode is to shift the eight bit parameters of the twenty-first group and the twenty-fourth group from the initial memory unit by five. After the memory unit, the eight bit parameters of the twenty-first group are arranged as [197, 37, 165, 101, 229, 5, 133, 69] and input to the tenth of the eight groups of the first memory cells Bank_A0~Bank_A7. One address A10; the eight bit parameters of the twenty-fourth group are arranged as [221, 61, 189, 125, 253, 29, 157, 93] and input to the twelfth of the eight groups of first memory cells Bank_A0~Bank_A7 Address A11. After the eight bit parameters of the twenty-second group and the twenty-third group are shifted from the initial memory cell unit by five memory cells, the eight-bit parameter of the twenty-second group is arranged as [213] , 53, 181, 117, 245, 21, 149, 85], and input to the eleventh address B10 of the eight sets of second memory cells Bank_B0~Bank_B7; the eight bit parameters of the twenty-third group are arranged as [205, 45, 173, 109, 237 , 13, 141, 77], and input to the twelfth address B11 of the eight sets of second memory cells Bank_B0~Bank_B7.

In the continuation, the write switch 14 will reverse the bit data C24 [3, 131, 67, 195, 35, 163, 99, 227], C25 [19, 147, 83, 211, 51, 179, 115, 243], C26 [11, 139, 75, 203, 43, 171, 107, 235 of the parallel pipeline type fast Fourier transform processor 20. ] and C27 [27, 155, 91, 219, 59, 187, 123, 251] are exchanged in CROT (3) arrangement; the exchange mode is to convert the eight bit parameters of the twenty-fifth group and the twenty-eighth group from the initial memory unit. After shifting three memory cells, the eight bit parameters of the twenty-fifth group are arranged as [163, 99, 227, 3, 131, 67, 195, 35] and input to the eight groups of first memory cells Bank_A0~Bank_A7. The thirteenth address in the A12; the eight bit parameters of the twenty-eighth group are arranged as [187, 123, 251, 27, 155, 91, 219, 59] and input to the eight groups of the first memory cells Bank_A0~Bank_A7 The fourteenth address is A13. The twenty-sixth group and the twenty-seventh group After the eight bit parameters are shifted from the initial memory cell by three memory cells, the eight bit parameters of the twenty-sixth group are arranged as [179, 115, 243, 19, 147, 83, 211, 51] and input to eight groups. The thirteenth address B12 of the second memory cell Bank_B0~Bank_B7; the eight bit parameters of the twenty-seventh group are arranged as [171,107,235,11,139,75,203,43] and input to the eighth group of the second group. The fourteenth address B13 in the memory cells Bank_B0~Bank_B7.

In the continuation, the write switch 14 will reverse the bit data C28 [7, 135, 71, 199, 39, 167, 103, 231], C29 [23, 151, 87, 215, 55, 183, 119, 247], C30 [15, 143, 79, 207, 47, 175, 111, 239] of the parallel pipeline type fast Fourier transform processor 20 and C31[31,159,95,223,63,191,127,255] is exchanged in the arrangement of CROT(7); the exchange mode is to shift the eight bit parameters of the twenty-ninth group and the thirty-third group from the initial memory cell. After the memory unit, the eight bit parameters of the twenty-ninth group are arranged as [135, 71, 199, 39, 167, 103, 231, 7] and input to the tenth of the eight groups of first memory cells Bank_A0~Bank_A7. Five address A14; the eight-bit eight-bit parameter is arranged as [159, 95, 223, 63, 191, 127, 255, 31] and is input to the sixteenth of the eight groups of first memory cells Bank_A0~Bank_A7. Address A15. After the eight bit parameters of the thirtieth and thirty-first groups are shifted from the initial memory cell by seven memory cells, the eight bit parameters of the thirtieth group are arranged as [151, 87, 215 , 55, 183, 119, 247, 23], and input to the fifteenth address B14 of the eight sets of second memory cells Bank_B0~Bank_B7; the eight bit parameters of the thirty-first group are arranged as [143, 79, 207, 47, 175, 111, 239 , 15], and input to the sixteenth address B15 of the eight sets of second memory cells Bank_B0~Bank_B7.

The write switch 14 exchanges all 256-point reverse bit data into write bit data, and converts every 4 clock cycles by a clock cycle counter. The secondary switching mode is alternately written into the first memory module 10 and the second memory module 12; therefore, the 256-point inverted bit data output by the parallel pipelined fast Fourier transform processor 20 is inverted with 128 points. The reading and writing schedule of the bit data is different, which is mainly determined according to the length and parallelism of the fast Fourier transform. Then, the multiplexer selects and outputs the bit data in the first memory module 10 and the second memory module 12, for example, when the reverse bit data C30 is selected, the first memory module 10 is selected. Bank_A0~Bank_A7 starts to output the first data (as shown by the dashed box in Figure 4D), and then the read switch 18 exchanges 0~7 bits of data into output bit data with natural order from 0 to 7. Then choose to output the bit data 8~15 and 16~23 in Bank_B0~Bank_B7 (as shown by the dashed box in Figure 4D), and then read the switch 18 to 8~15 and 16~23 bit data. The exchange is the output bit data of the natural order from 8 to 15 and 16 to 23; and then continuously output two bit data 24~31 and 32~39 from Bank_A0~Bank_A7, and the read switch 18 will be 24~ The 31 and 32-39-bit data exchanges are output bit data of natural order from 24 to 31 and 32 to 39, and continue to proceed according to this rule until all 256-bit bit data is output. Among them, the exchange mode of writing is similar to the exchange mode of reading. As shown in FIG. 2E, the 256-bit data is exchanged for the natural-sequential output output bit data for the read switch 18, and is presented in the other two groups of memory modules GroupA and GroupB, for example, Bank_A0~Bank_A7 in GroupA. The first address will be sequentially arranged as 0~7 bits, and the first address of Bank_B0~Bank_B7 in GroupB will be sequentially arranged as 8~15 bits, and the second address will be The order is arranged as a bit of 16~23; the second address of Bank_A0~Bank_A7 will be in the order of 24-31 bits and the third address will be in the order of 32~39 bits, and 256 in this order. The point bit data is all read in natural order. At this time, when 0~7 bits in GroupA are output to the function end of the next stage, the vacated address can be written by the write switch 14 to write the next 256-point reverse bit data. As long as the address is vacated The next bit data can be written. Therefore, when the first memory module 10 is written, the second memory module 12 is read, and the parallel pipeline type fast Fourier transform processor can be alternately read/written. The bit reverse output is converted to a natural sequential, continuous, delay-free output, which in turn increases output efficiency.

Wherein, the present invention is directed to a new design of a reordering buffer architecture of a parallel pipelined Fourier transform processor, which is converted into a natural sequential output, so that α is an even or odd number by an alternating formula (1). The special read and write schedules can be used to support the fast Fourier transform operation, and the natural sequence output function is completed by using two groups of first memory modules and second liquid modules.

In summary, the memory write/read address of the reorder buffer of the present invention is relatively regular, and a clock counter is used to generate the address of each memory, and the address is written. The generation manner is different according to the bit length of the fast Fourier transform at that time, which is calculated as an odd or even number by the alternating formula (1), and the period of the bit length of each fast Fourier transform is N/m. Assuming that the bit length of the fast Fourier transform is counted from 1, the data exchanged by the write switch will start to fill in the first memory module or the second memory mode during the odd symbol period. The group is written sequentially from address 0. After each write, the memory address of the first memory module or the second memory module is incremented by one. As for the writing of the first memory module or the second memory module at each clock, it is determined according to the length and parallelism of the fast Fourier transform. In the case of even symbols, the data exchanged by the write switch at this time is written at the position where the length of the bit of the previous fast Fourier transform is opposite to the data of the presentation bit. Furthermore, the present invention designs a fast Fourier transform operation capable of performing continuity, and only requires a size N memory when supporting continuous flow fast Fourier transform operations, for the overall system architecture design. Very small area effect Benefits, and multiple times the data input and output in parallel, has a very high operational output, and has great application value in the field of wired and wireless communication systems and electronic motor engineering.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Equivalent changes or modifications of the features and spirits of the inventions are intended to be included within the scope of the invention.

10‧‧‧First memory module

12‧‧‧Second memory module

14‧‧‧Write switch

16‧‧‧Reading and writing controller

18‧‧‧Reading switch

20‧‧‧Parallel Pipeline Fast Fourier Transform Processor

22‧‧‧Multiplexer

Claims (8)

A reordering buffer includes: a first memory module having m first memory cells, each of the first memory cells storing N/2m pen data, N is Fourier The length of the converted bit, m is a power of 2; a second memory module having m second memory cells, each of which stores N/2m pens Metadata; a write switch electrically connected to the first memory module and the second memory module, wherein the write switch receives the inverse bit data of the power-of-fourth Fourier transform of 2, and The reverse bit data is exchanged into a preset arrangement of the bit data, and is alternately written into the first memory module and the second memory module; a read/write controller, electrical Connecting the write switch, the first memory module and the second memory module, the read/write controller controlling the write bit data to be written into the first memory module or the second memory In the body module, or reading the bit data from the first memory module or the second memory module; and reading The switch is electrically connected to the first memory module, the second memory module, and the read/write controller, and the read switch alternates the first memory module and the second memory module The bit data in the group is exchanged for the natural order output bit data, and the output bit data is output by m output paths. The reordering buffer of claim 1, wherein the write switch or the read switch selects to write the write bit data in an alternating formula according to the bit length N of the Fourier transform, respectively. The first memory module or the second memory module, or reading the bit data from the first memory module or the second memory module, the alternating formula is as follows: α = log ₂ ( N /2 m ² ) where α is an integer, N is the length of the Fourier transform bit, and m is the power of 2. The reordering buffer of claim 2, wherein the alpha is an even number, the write switch writes the write bit data to the first memory module in an alternating manner of writing once. In the group and the second memory module, the read switch reads the bit data from the first memory module and the second memory module in an alternate manner. The reordering buffer of claim 3, wherein the write switch exchanges the reverse bit data according to the control signal selected by the preset arrangement, and the length of the Fourier transform bit is 128. It is divided into 16 groups of eight bit parameters, and the eight bit parameters of each two groups in the reverse bit data are exchanged into the bit data in eight arrangements, and the bit is written. The data is alternately written into the first memory module and the second memory module; wherein the order of the eight arrangements is: the eight bit parameters of the first group and the second group are input into the eight groups in parallel The first memory cell and the second memory cell, and each of the first memory cells and the first one of each of the second memory cells The unit system is used as the initial memory unit of the displacement; the eight bit parameters of the third group and the fourth group are respectively displaced from the initial memory unit by four memory units and input to the first group of the eight groups.單埠 memory unit and the second memory unit; fifth group Parameter eight bytes from the sixth group were the initial displacement of the single-port memory unit of two single-port memory cell and input to the first set of eight single-port memory unit and the second single-port note In the memory unit, the eight bit parameters of the seventh group and the eighth group are respectively shifted from the initial memory unit to six memory cells and input to the eight first memory units and In the second memory unit, the eight bit parameters of the ninth group and the tenth group are respectively shifted from the initial memory cell to one memory cell and input to the eight first memory. In the unit and the second memory unit; the eight bit parameters of the eleventh group and the twelfth group are respectively displaced from the initial memory unit by five memory cells and input to the eight groups The first memory cell and the second memory cell; the eight bit parameters of the thirteenth and fourteenth groups are respectively displaced from the initial memory cell by three memory cells And inputting to the eight sets of the first memory unit and the second memory unit; and the eight bit parameters of the fifteenth and sixteenth groups are respectively displaced from the initial memory unit Seven memory cells are input to the eight first memory Element and the second single-port memory unit. The reordering buffer of claim 2, wherein the alpha is an odd number, the write switch first writes the write bit data to the first memory module for the first time, and then writes each Writing the bit data into the second memory module and the first memory module in an alternate manner of two times, the read switch is from the first in an alternate manner of reading each time The bit data is read out in the memory module and the second memory module. The reordering buffer of claim 5, wherein the write switch is arranged according to the preset The selected control signal exchanges the reverse bit data. When the bit length of the Fourier transform is 256, it is divided into 32 groups of eight bit parameters, and eight bits of each of the four sets of the inverted bit data are The bit parameter is exchanged for the write bit data of the preset arrangement in eight arrangements, and the write bit data is alternately written into the first memory module and the second memory module. The order of the eight arrangements is that the eight bit parameters of the first group and the fourth group are input in parallel to eight groups of the first memory unit, and the second group and the third group are eight. The bit parameters are input in parallel to the eight groups of the second memory unit, and the first group of the first group of the first group of memory cells and the group of the second group of memory cells The memory cell is used as the initial memory cell of the displacement; the eight bit parameters of the fifth and eighth groups are respectively displaced from the initial memory cell by four memory cells and input to the eight Among the first memory cells in the group, eight bits in the sixth and seventh groups Four memory cells are respectively displaced from the initial memory cell and input into the eight second memory cells; the eight bit parameters of the ninth group and the twelfth group are respectively from the initial The memory unit shifts two memory cells and inputs to the eight first memory cells, and the eight bit parameters of the tenth and eleventh groups respectively from the initial memory cell Displaces two memory cells and inputs them into the eight second memory cells; the eight bit parameters of the thirteenth and sixteenth groups are respectively shifted from the initial memory cell by six單埠 memory unit is input to the eight sets of first memory cells, and eight bit parameters of the fourteenth and fifteenth groups are respectively displaced from the initial memory cell by six memory Units are input to the eight sets of second memory cells; The eight bit parameters of the seventeenth group and the twentieth group are respectively shifted from the initial memory cell to one memory cell and input to the eight first memory cells, the eighteenth group and The eight-bit parameters of the nineteenth group are respectively shifted from the initial memory unit to one memory unit and input to the eight-group second memory unit; the twenty-first group and the twentieth The eight bit parameters of the four groups are respectively displaced from the initial memory cell by five memory cells and input to the eight first memory cells, the twenty-second group and the twenty-third group The eight bit parameters are respectively shifted from the initial memory cell by five memory cells and input into the eight second memory cells; the twenty-fifth and twenty-eighth groups The eight bit parameters are respectively displaced from the initial memory cell by three memory cells and input to the eight groups of the first memory cells, the twenty-fourth group and the twenty-seventh group of eight The bit parameters are shifted from the initial memory cell by three memory The unit address is input to the eight sets of second memory cells; and the eight bit parameters of the twenty-ninth and thirty-second groups are respectively displaced from the initial memory cell by seven單埠The memory unit is input to the eight sets of first memory cells, and the eight bit parameters of the thirtieth and thirty-first groups are respectively displaced from the initial memory cell by seven memory cells. And input to the eight groups of second memory cells. The reordering buffer of claim 1, wherein the reverse bit data is output by a parallel pipelined fast Fourier transform processor electrically connected to the write switch . The reordering buffer of claim 1, further comprising a multiplexer electrically connected to the first memory module, the second memory module, and the read switch, the first memory Module and the The bit data in the second memory module is selected and output by the multiplexer, and the read switch receives the bit data output by the multiplexer to exchange the output bit data in a natural order. .