TWI497885B - Multiphase converting controller - Google Patents

Description

Multiphase conversion controller

The invention relates to a multi-phase conversion controller, in particular to a multi-phase conversion controller capable of adjusting the length of an on-time according to a mode signal.

Please refer to the first figure, which is a circuit diagram of a conventional multi-phase conversion controller. Here, a two-phase (conversion circuit) will be described as an example. The conversion circuit 2, 4 is coupled to an input voltage Vin, which includes an upper arm transistor MU1 and MU2, lower arm transistors ML1 and ML2, inductors L1 and L2, and an output terminal coupled to an output capacitor C to provide a common Output voltage Vout. The multiphase conversion controller 10 sequentially controls the conversion circuits 2, 4. When the system enters the light load, a mode signal Sm is provided. When the multi-phase conversion controller 10 receives the mode signal Sm, the phase-reduction operation is performed. The conventional method is to keep the first phase working, and shield the second phase, that is, the conversion circuit 2 The operation continues without the conversion circuit 4 being stopped, so that the switching loss can be reduced and the light load efficiency can be improved.

Since the traditional practice always keeps a stationary phase (such as the first phase) working, that is, if the phase-reduction action is performed, the other phases are reduced, and the stationary phase is always kept, which results in power transistor and inductive workload of each phase. Unbalanced, commonly used stationary phases will be damaged earlier than other phases, affecting the life of the overall circuit.

Please refer to the second figure for a control circuit diagram of the power supply circuit disclosed in Taiwan Patent Publication No. 201034356. An error amplifier EA compares a feedback signal FB with an output voltage reference signal Vref to generate an error amplification signal, and inputs the error amplification signal into different phases. The bit width modulation comparators PWM1, PWM2. The operational amplifiers OP1 and OP2 compare the voltage signals ISEN1 and ISEN1_N, ISEN2 and ISEN2_N across the phase current detecting resistors (not shown), and measure the currents of the respective phases and generate corresponding current difference amplification signals, and Input the corresponding pulse width modulation comparators PWM1 and PWM2. In addition, an oscillating circuit 12 generates a sawtooth wave signal, which is input into a driving gate control circuit 14 together with the outputs of the pulse width modulation comparators PWM1 and PWM2. The drive gate control circuit 14 generates drive signals UG1, LG1, UG2, LG2, and drives the corresponding power transistors through the drive gate control circuit 14.

An external phase control signal PSC determines if the circuit is to enter a phase decrement operation. After receiving the external phase control signal PSC, a phase selection circuit 16 passively decides whether to enter the phase-reduction operation. When it determines that it needs to enter the phase-reduction operation, it controls the drive gate control circuit 14 to turn off one or more phases. When entering the subtraction operation, the phase of the pause operation is not fixed.

The vertical phase control uses the phase selection control to not close the same phase when performing the phase decrement operation, and turns off at least one of the plurality of conversion circuits when the phase loss is first determined; and turns off the multiple conversions when another phase loss is determined. At least one other of the circuits is expected to "average" the operating time of each phase. In fact, each time the circuit is restarted, the control circuit of the power supply circuit will still restart the first phase of the preset phase, so that the power transistor and the inductor workload of each phase will still have a significant imbalance.

In other words, the prior art does not change the phase that is turned off when the phase is dephasing. The disadvantage is that the power transistor and the inductor workload of each phase are not balanced, and the commonly used phase will be damaged earlier than other phases, which affects the lifetime of the overall circuit.

In view of the prior art multiphase conversion controller, when the phase is dephasing, the power transistor and the inductance of each phase are unbalanced, so that the commonly used phase will be damaged earlier than other phases, affecting the life of the overall circuit. The invention does not reduce the phase operation at light load, thus not only ensuring the average of the workload of each phase, but also extending the phases The on-time reduces the frequency of the system and achieves an efficiency equivalent to the effect of subtraction.

To achieve the above objective, the present invention provides a multi-phase conversion controller for controlling a plurality of conversion circuits coupled to an input voltage such that a plurality of conversion circuits collectively provide an output voltage. The multiphase conversion controller includes a feedback control circuit, an on time control circuit, and a polyphase logic control circuit. The feedback control circuit determines a conduction time point according to the output voltage and generates a pilot communication number accordingly. The on-time control circuit determines a conduction period. The multi-phase logic control circuit sequentially controls the plurality of conversion circuits to be turned on according to the conduction number and the conduction period. The on-time control circuit adjusts the length of the on-period according to a mode signal.

The present invention also provides a multi-phase conversion controller for controlling a plurality of conversion circuits coupled to an input voltage such that a plurality of conversion circuits collectively provide an output voltage. The multiphase conversion controller includes a clock generation circuit, a feedback control circuit, and a polyphase logic control circuit. The clock generation circuit generates a clock signal and a ramp signal according to an operating frequency. The feedback control circuit generates a pilot communication number based on the output voltage and the ramp signal. The multi-phase logic control circuit sequentially controls the plurality of conversion circuits to be turned on according to the conduction signal number and the time pulse signal. The feedback control circuit adjusts the clock signal and the frequency of the ramp signal according to a mode signal.

The above summary and the following detailed description are exemplary in order to further illustrate the scope of the claims. Other objects and advantages of the present invention will be described in the following description and drawings.

Prior art:

2, 4‧‧‧ conversion circuit

10‧‧‧Multiphase Conversion Controller

12‧‧‧ oscillating circuit

14‧‧‧Drive gate control circuit

16‧‧‧ Phase selection circuit

C‧‧‧ output capacitor

EA‧‧‧Error Amplifier

FB‧‧‧ feedback signal

ISEN1 and ISEN1_N, ISEN2 and ISEN2_N‧‧‧ voltage signals

L1, L2‧‧‧ inductance

LG1, LG2, UG1, UG2‧‧‧ drive signals

MU1, MU2‧‧‧ upper arm transistor

ML1, ML2‧‧‧ lower arm transistor

OP1, OP2‧‧‧Operational Amplifier

PSC‧‧‧ external phase control signal

PWM1, PWM2‧‧‧ pulse width modulation comparator

Sm‧‧‧ mode signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vref‧‧‧ output voltage reference signal

this invention:

100‧‧‧Multiphase Conversion Controller

102‧‧‧ comparator

103‧‧‧Error amplifier

104‧‧‧ On-time control circuit

105‧‧‧ Clock generation circuit

106‧‧‧Multiphase logic control circuit

108, 110, 112‧‧‧ drive circuits

202‧‧‧reference voltage generator

204‧‧‧current source

206‧‧‧ comparator

208‧‧‧D type flip-flop

CJ‧‧‧ clock input

Clk‧‧‧ clock signal

COMP‧‧‧ error amplification signal

CTON‧‧‧ On-time capacitance

D‧‧‧ input

FB‧‧‧ feedback signal

ITON‧‧‧ current

K1‧‧‧Reset switch

LG1, LG2, LG3, UG1, UG2, UG3‧‧‧ drive signals

PWM‧‧‧ communication number

Q‧‧‧output

Q’‧‧‧inverted output

R‧‧‧Reset

RAMP‧‧‧ ramp signal

Sm‧‧‧ mode signal

Sp1, Sp2, Sp3‧‧‧ phase control signals

Sto‧‧‧ on time signal

Vref‧‧‧ output voltage reference signal

VTH‧‧‧ On-time reference voltage

VTON‧‧‧ capacitor voltage

VQN‧‧‧ switch signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

The first picture shows the circuit diagram of a traditional multiphase conversion controller.

The second figure is a schematic diagram of the control circuit of the power supply circuit disclosed in Taiwan Patent Publication No. 201034356.

The third figure is a multi-phase switching control according to a first preferred embodiment of the present invention. Schematic diagram of the circuit of the controller.

The fourth figure is a circuit diagram of an on-time control circuit in accordance with a first preferred embodiment of the present invention.

Figure 5 is a circuit diagram of an on-time control circuit in accordance with a second preferred embodiment of the present invention.

Figure 6 is a circuit diagram of a multiphase conversion controller in accordance with a second preferred embodiment of the present invention.

Referring to the third figure, there is shown a circuit diagram of a multiphase conversion controller according to a first preferred embodiment of the present invention. The multi-phase conversion controller 100 is configured to control a plurality of conversion circuits (not shown, see the first figure) coupled to an input voltage, so that the plurality of conversion circuits jointly provide an output voltage. In the embodiment, two conversion circuits are taken as an example for explanation. The multiphase conversion controller 100 includes a feedback control circuit, an on time control circuit 104, and a polyphase logic control circuit 106. The feedback control circuit includes a comparator 102. One non-inverting terminal of the comparator 102 receives an output voltage reference signal Vref, and a reverse terminal receives a feedback signal FB representing one of the output voltages. The comparator 102 generates a pilot signal PWM when a level of the feedback signal FB is lower than a level of the output voltage reference signal Vref. The on-time control circuit 104 starts counting when receiving the communication number PWM, and generates an on-time signal Sto when the timing reaches a predetermined conduction period. Therefore, the time interval at which the conduction signal PWM and the on-time signal Sto are generated represents a length of a conduction period of the conversion circuit. The multi-phase logic control circuit 106 sequentially controls the plurality of conversion circuits to be turned on one by one according to the conduction period represented by the conduction communication number PWM and the on-time signal Sto. For example, the multi-phase logic control circuit 106 counts the number of times of the communication number PWM, and turns on the upper arm transistor of the corresponding conversion circuit in the plurality of conversion circuits corresponding to the number of times of counting (refer to the first figure).

The polyphase logic control circuit 106 receives the pilot communication number PWM When the phase control signals Sp1 and Sp2 are generated, the corresponding driving signals of the driving signals UG1 and UG2 are generated by the driving circuits 108 and 110 to turn on the upper arm transistor of the corresponding conversion circuit, and when the conduction time signal Sto is received later, the corresponding end is ended. The on-period of the conversion circuit stops turning on the upper arm transistor of the corresponding conversion circuit and generates a corresponding driving signal of the driving signals LG1, LG2 to turn on the lower arm transistor of the corresponding conversion circuit. The driving signals LG1 and LG2 of the lower arm transistor are generated to allow a current of one inductor to flow, so that it can be based on continuous current mode (CCM), discontinuous current mode (DCM), inductor current detection, and analog diode. The mode (DEM) determines the pulse width of the generated and generated drive signals. When the level of the feedback signal FB is again lower than the level of the output voltage reference signal Vref, the polyphase logic control circuit 106 turns on the next conversion circuit. Therefore, the on periods of the plurality of conversion circuits of the present embodiment are shifted from each other.

The on-time control circuit 104 additionally receives a mode signal Sm. The mode signal Sm can be obtained from a load circuit, such as a digital control signal sent by a microcontroller or microprocessor in the load circuit, or an analog signal related to the load current. When the mode signal Sm represents a light load state, the on-time control circuit 104 delays the generation of the on-time signal Sto, that is, the time interval at which the conduction signal PWM and the on-time signal Sto are generated is extended. In this way, the upper arm transistor on-time of the plurality of conversion circuits is extended, so that the energy of each conversion circuit is increased to the load and the timing of the feedback signal FB is lower than the level of the output voltage reference signal Vref. point. As such, the present invention achieves the effect of reducing the operating frequency, thereby reducing switching losses and improving efficiency at light loads. Moreover, the multi-phase logic control circuit 106 still controls the plurality of conversion circuits to be turned on without performing the phase-reduction operation, thereby avoiding the problem of uneven workload due to the respective phases in the prior art.

Please refer to the fourth figure, which is a circuit diagram of an on-time control circuit according to a first preferred embodiment of the present invention. The on-time control circuit mainly includes a reference voltage generator 202, a current source 204, and a comparator 206. And an on-time capacitor CTON. The current source 204 generates a current ITON to charge the on-time capacitor CTON to generate a capacitor voltage VTON. The reference voltage generator 202 generates an on-time reference voltage VTH. The comparator 206 compares the capacitor voltage VTON and the on-time reference voltage VTH to generate a turn-on period signal. The on-time control circuit can include a D-type flip-flop 208 and a reset switch K1 to enable the capacitor voltage VTON of the on-time capacitor CTON to start at zero voltage during the next phase operation. When receiving the communication number PWM, the D-type flip-flop 208 outputs a low-level switching signal at a reverse output terminal Q' according to a logic signal "1" received by an input terminal D. VQN, reset switch K1 with a cutoff. The current source 204 begins to charge the on-time capacitor CTON, causing the on-time reference voltage VTH to begin to rise. At this time, the capacitor voltage VTON is lower than the on-time reference voltage VTH. After a predetermined conduction period, the capacitor voltage VTON is higher than the on-time reference voltage VTH, and the comparator 206 outputs the on-time signal Sto. When a reset terminal R of the D-type flip-flop 208 receives the on-time signal Sto, the output is reset, so that an output terminal Q outputs a low-level signal, and the inverting output terminal Q' outputs a high-level switching signal VQN. To turn on the reset switch K1. At this time, the capacitor voltage VTON is reset to zero to wait for the next cycle (ie, the pilot communication number PWM returns to the high level).

The current source 204 determines the magnitude of the current ITON for charging the on-time capacitor CTON according to an input voltage Vin coupled to the plurality of conversion circuits and/or a common output voltage Vout, that is, determining the on-period of the plurality of conversion circuits. The predetermined length. The current source 204 also receives the mode signal Sm additionally. When the mode signal Sm represents the light load state, the current ITON is reduced, so that the conduction period of the conversion circuit is extended. For example, when the current ITON is reduced to 1/N, the on-period becomes N times the original, and the equivalent is equivalent to the effect of subtracting the (N-1) phase.

Referring to FIG. 5, it is a circuit diagram of an on-time control circuit according to a second preferred embodiment of the present invention. Compared with the embodiment shown in the third figure, the reference voltage generator 202 is adjusted according to the mode signal Sm. change. When the mode signal Sm represents the light load state, the reference voltage generator 202 increases the voltage of the on-time reference voltage VTH, so that the on-period of the conversion circuit is extended. For the operation of other circuits, please refer to the circuit description corresponding to the fourth figure.

6 is a circuit diagram of a multi-phase conversion controller according to a second preferred embodiment of the present invention. The multi-phase conversion controller 100 is configured to control a plurality of conversion circuits coupled to an input voltage, so that the plurality of conversion circuits jointly provide an output voltage. In the embodiment, the three conversion circuits are taken as an example to illustrate that the multi-phase conversion controller 100 generates phase control signals Sp1, Sp2, and Sp3, and generates driving signals UG1, LG1, UG2, LG2, and UG3 through the driving circuits 108, 110, and 112. LG3 controls the upper arm transistor and the lower arm transistor of the corresponding conversion circuit. This embodiment is a fixed frequency circuit architecture. The multiphase conversion controller 100 includes a feedback control circuit, a clock generation circuit 105, and a polyphase logic control circuit 106. The feedback control circuit includes a comparator 102 and an error amplifier 103. A non-inverting terminal of the error amplifier 103 receives an output voltage reference signal Vref, and a reverse terminal receives a feedback signal FB representing one of the output voltages, and accordingly generates an error amplification signal COMP. The clock generation circuit 105 generates a clock signal Clk and a ramp signal RAMP according to a preset operating frequency, so that the clock signal Clk and the ramp signal RAMP have the same frequency. A non-inverting terminal of the comparator 102 receives an error amplification signal COMP, and a reverse terminal receives the ramp signal RAMP, and generates a pilot signal PWM accordingly. The multi-phase logic control circuit 106 sequentially controls the plurality of conversion circuits to be turned on one by one according to a pilot communication number PWM and a timely pulse signal Clk.

The clock generation circuit 105 receives a mode signal Sm, and reduces the frequency of the clock signal Clk and the ramp signal RAMP when the mode signal Sm represents a light load state. When the frequency is reduced to 1/N, the embodiment achieves the effect of reducing the (N-1) phase.

As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial applicability. The present invention has been disclosed above in the preferred embodiments, but it should be understood by those skilled in the art that this embodiment is only used for The invention is depicted and should not be construed as limiting the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

100‧‧‧Multiphase Conversion Controller

102‧‧‧ comparator

104‧‧‧ On-time control circuit

106‧‧‧Multiphase logic control circuit

108, 110‧‧‧ drive circuit

FB‧‧‧ feedback signal

LG1, LG2, UG1, UG2‧‧‧ drive signals

PWM‧‧‧ communication number

Sm‧‧‧ mode signal

Sp1, Sp2‧‧‧ phase control signals

Sto‧‧‧ on time signal

Vref‧‧‧ output voltage reference signal

Claims (10)

A multi-phase conversion controller for controlling a plurality of conversion circuits coupled to an input voltage, wherein the plurality of conversion circuits jointly provide an output voltage, the multi-phase conversion controller comprising: a feedback control circuit, according to the output The voltage determines a conduction time point and generates a communication number accordingly; an on-time control circuit starts to perform timing in response to the generation of the communication number, and generates an on-time signal when the timing reaches a conduction period; and a polyphase logic The control circuit sequentially controls the plurality of conversion circuits to be turned on according to the conduction period and the on-period represented by the on-time signal; wherein the on-time control circuit adjusts the on-period of the plurality of conversion circuits according to a mode signal The length. The multi-phase switching controller of claim 1, wherein the on-time control circuit extends the length of the on-period when the mode signal represents a light load state. The multi-phase conversion controller of claim 1, wherein the multi-phase logic control circuit further turns on a corresponding one of the plurality of conversion circuits according to the number of the communication numbers, and the plurality of conversion circuits The on periods are staggered from each other. The multiphase conversion controller according to any one of the first to third aspects of the invention, wherein the on-time control circuit further determines the conduction period of the plurality of conversion circuits according to the input voltage and the output voltage. length. The multiphase conversion controller according to any one of claims 1 to 3, wherein the on-time control circuit comprises a comparator, a current source, an on-time capacitor, and a reference voltage generator. Current source is turned on The time capacitor is charged to generate a capacitor voltage, the reference voltage generator generates an on-time reference voltage, and the comparator compares the capacitor voltage and the on-time reference voltage to generate the on-period signal. The multiphase conversion controller of claim 5, wherein the current source adjusts a current amount of the capacitor voltage according to the mode signal. The multiphase conversion controller of claim 5, wherein the reference voltage generator adjusts the on-time reference voltage according to the mode signal. A multi-phase conversion controller for controlling a plurality of conversion circuits coupled to an input voltage, wherein the plurality of conversion circuits jointly provide an output voltage, the multi-phase conversion controller comprising: a clock generation circuit, according to an operating frequency Generating a clock signal and a ramp signal; a feedback control circuit generating a pilot signal according to the output voltage and the ramp signal; and a polyphase logic control circuit for sequentially controlling the communication signal and the clock signal according to the signal The plurality of conversion circuits are turned on; wherein the feedback control circuit adjusts the clock signal and the frequency of the ramp signal according to a mode signal. The multi-phase switching controller of claim 8, wherein the mode signal reduces the operating frequency when the mode signal represents a light load condition. The multi-phase conversion controller according to claim 8 or 9, wherein the feedback control circuit comprises an error amplifier and a comparator, and the error amplifier outputs a signal according to the output voltage and an output voltage reference signal. An error amplification signal, and the comparator amplifies the signal according to the error and the ramp signal The student's communication number.