TWI496263B - Package structure having embedded chip and method for making the same - Google Patents

Description

Encapsulated structure of embedded wafer and preparation method thereof

The present invention relates to a package structure for embedded cells and a method for fabricating the same, and more particularly to a package structure and a method for preventing cracks from being embedded in a package substrate.

With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types. Generally, a semiconductor device is mainly used to mount a wafer on a package substrate or a lead frame, and then the wafer is electrically connected to the package substrate or the lead frame, and then encapsulated by a colloid. In order to reduce the package height, there is a structure in which a wafer is embedded in a package substrate. Such a package can reduce the volume of the overall semiconductor device and enhance the electrical function, and becomes a packaging trend.

Please refer to FIGS. 1A and 1B for a schematic view of a package structure of a conventional embedded wafer. As shown in FIG. 1A, it is on a substrate 10 having a first surface 10a and a second surface 10b opposite thereto and having an opening 100 therethrough, and an internal circuit layer on the first and second surfaces 10a, 10b. 11, and a portion of the inner wiring layer 11 is located around the opening 100 as shown in FIG. 1B. A wafer 13 having an opposite active surface 13a and an inactive surface 13b is received in the opening 100. The active surface 13a has a plurality of electrode pads 130 thereon. A dielectric layer 12 is disposed on the first and second surfaces 10a, 10b of the substrate 10, and the active surface 13a and the non-active surface 13b of the wafer 13, and the dielectric layer 12 is filled in the sidewall surface of the opening 100. In the gap s between the wafers 13, the wafer 13 is fixed in the opening 100. A circuit layer 15 is disposed on the dielectric layer 12, and the circuit layer 15 has a conductive via 150 in the dielectric layer 12 and electrically connected to the electrode pad 130.

The opening 100 of the conventional package structure is formed by a laser opening method. When the inner circuit layer 11 is formed, a metal frame 101, 102 surrounding the opening 100 is usually formed to define the opening. The aperture of 100, and then the laser opening, to avoid the lack of hole shape caused by laser melting.

However, since the substrate 10 and the metal frame 101, 102 absorb laser energy to such an extent that the sidewall surface of the opening 100 is often over-ablated compared to the metal frame 101, 102, the metal is caused. The frame body 101', 102' protrudes from the side wall surface of the opening 100, as shown in FIG. 1C; therefore, when the wafer 13 is placed, the wafer 13 is easily brought into contact with the protruding metal frame body 101', 102'. The rupture causes the electrical function of the wafer 13 to be lost or malfunctioned, thus affecting the electrical function of the final package.

Moreover, since the upper and lower apertures of the opening 100 of the conventional package structure are equal, the space formed by the gap s between the sidewall surface of the opening 100 and the wafer 13 is limited after the wafer 13 is placed, resulting in filling by thermal pressing. The number of dielectric layers 12 entering the gap s is limited.

In addition, the inner layer region of the surface of the substrate 10 (the region where the inner wiring layer 11 is to be disposed) has a wider wiring area, so that the thickness of the dielectric layer 12 on the region can be allowed to be thicker. Big blind hole. However, when the embedded wafer 13 is inside the substrate 10, since the contact area of the electrode pad 130 of the wafer 13 is narrow and densely arranged, if the electrode pad 130 is pressed against the thick dielectric layer 12, the laser will be melted. The depth of the blind via is deep, and the shape of the via is too large, so that it is difficult to form an effective electrical connection when the conductive via 150 is subsequently plated, resulting in loss of electrical function or abnormal operation of the wafer 13, thus affecting the final package. Electrical function.

Therefore, how to avoid the loss of the blind hole shape on the wafer caused by the crack of the metal frame and the excessive thickness of the dielectric layer on the wafer, which has become a current desire The problem to be solved.

In view of the above-mentioned various deficiencies of the prior art, the main object of the present invention is to provide a package structure for embedded wafers that avoids wafer cracking and a method of fabricating the same.

To achieve the above and other objects, the present invention discloses a package structure for embedding a wafer, comprising: a substrate having opposite first and second surfaces, and having internal wiring layers on the first and second surfaces, and An opening having a first and second surface, the opening having a first aperture at the first surface and a second aperture at the second surface, the first aperture being smaller than the second aperture, and the substrate The surface has a metal frame around the opening; a wafer is disposed in the opening, and the wafer has opposite active and non-active surfaces, and the active surface has a plurality of electrode pads, and the active surface of the wafer The first dielectric layer covers the first and second surfaces of the substrate, the active surface and the non-active surface of the wafer, and the first dielectric layer is filled in the first dielectric layer And a first circuit layer disposed on the first dielectric layer, A conductive blind hole.

The package structure of the embedded wafer includes a build-up structure disposed on the first dielectric layer and the first circuit layer, the build-up structure having a second dielectric layer disposed on the second dielectric layer a second circuit layer, and a second conductive via hole disposed in the second dielectric layer and electrically connected to the first and second circuit layers, and the second circuit layer of the outermost layer has a plurality of electrical contact pads. Further, an insulating protective layer is disposed on the layered structure, and the insulating protective layer has a plurality of insulating protective layer openings, so that the electrical contact pads are correspondingly exposed to the openings of the insulating protective layers.

The invention provides a method for fabricating a package structure for embedding a wafer, comprising: providing a substrate having opposite first and second surfaces; forming an internal circuit layer on the first and second surfaces of the substrate, and Forming a metal frame on the substrate; forming an opening through the first and second surfaces in the substrate, wherein the metal frame is located around the opening, and the opening has a first aperture and a first surface on the first surface a second aperture of the second surface, the first aperture is smaller than the second aperture; forming a first initial dielectric layer on the first or second surface of the substrate to seal one end of the opening; Providing a wafer having a corresponding active surface and a non-active surface, wherein the active surface has a plurality of electrode pads, and the active surface of the wafer is on the same side as the second aperture; the first initial dielectric is opposite to the substrate Forming a second initial dielectric layer on the surface of the layer, and pressing the first and second initial dielectric layers to fill the gap between the opening and the wafer, so that the first and second initial dielectric layers are laminated Be the first to become one An electric layer, wherein the wafer is fixed in the opening; and a first wiring layer is formed on the first dielectric layer, and the first wiring layer has a first dielectric layer and is electrically connected to the electrode pad The first conductive blind hole.

In the above method, the internal wiring layer is formed by forming a metal layer on the first and second surfaces of the substrate, and then forming the internal wiring layer by the metal layer by a patterning process.

The method further includes forming a build-up structure on the first dielectric layer and the first circuit layer, the build-up structure having a second dielectric layer, a second circuit layer disposed on the second dielectric layer, and a second conductive via hole disposed in the second dielectric layer and electrically connected to the first and second circuit layers, and the second circuit layer of the outermost layer has a plurality of electrical contact pads on the buildup structure An insulating protective layer is formed, and the insulating protective layer has a plurality of insulating protective layer openings, so that each of the electrical contact pads is exposed to each of the insulating protective layer openings.

In the package structure of the embedded wafer described above and the method of manufacturing the same, the wafer is an integrated circuit chip (IC) or a multilayer ceramic capacitor (MLCC). The thickness of the first dielectric layer on the active surface of the wafer is less than the thickness of the first dielectric layer on the second surface of the substrate.

As can be seen from the above, the package structure of the embedded wafer of the present invention and the manufacturing method thereof, by using the metal frame, can prevent the internal circuit layer from being deformed when the opening is formed, so when the wafer is placed in the opening, The wafer does not touch the inner wiring layer and is scratched or broken. Furthermore, the first aperture of the opening is smaller than the second aperture, so that the wafer can be inserted into the opening by a second aperture having a larger aperture to prevent the wafer from being scratched by touching the metal frame or The situation of rupture.

In addition, since the second aperture of the opening of the substrate is large, the second initial dielectric layer on the same side thereof can be filled with a larger amount in the gap, and the thickness of the first dielectric layer on the active surface of the wafer is increased. Thinner, and can form a better blind hole shape, so that the conductive blind hole formed in the blind hole can be electrically connected, and the wafer can maintain a normal electrical function, thereby avoiding affecting the final package completion. Electrical function.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

Please refer to FIGS. 2A to 2I , which are schematic cross-sectional views showing respective processes of the package structure of the embedded wafer of the present invention.

As shown in FIG. 2A, first, a substrate 20 having a first surface 20a and a second surface 20b opposite to each other is provided, and metal layers 21a, 21b are formed on the first surface 20a and the second surface 20b.

As shown in FIG. 2B, the metal layers 21a, 21b are formed by a patterning process to form the internal wiring layer 21, and a metal frame 210 is formed on the substrate 20.

2C and 2C', wherein the 2C' is a top view of FIG. 2C; then, the first surface 20a and the second surface are formed through the laser opening technique in the substrate 20. The opening 200 of the surface 20b is such that the metal frame 210 is located around the opening 200, and the opening 200 has a first aperture 200a at the first surface 20a and a second aperture 200b at the second surface 20b. The aperture 200a is smaller than the second aperture 200b.

By the metal frame 210, the stress can be differentiated, and when the laser is opened, the substrate 20 can be prevented from being deformed, and the internal circuit layer 21 can be prevented from being deformed.

As shown in FIG. 2D, a first initial dielectric layer 22a is formed on the first surface 20a side of the substrate 20 to seal one end of the opening 200.

As shown in FIG. 2E, a wafer 23 which is an integrated circuit chip (IC) or a multilayer ceramic capacitor (MLCC) is provided in the opening 200, and the wafer 23 has a corresponding active surface 23a and an inactive surface 23b. The active surface 23a has a plurality of electrode pads 230, and the wafer 23 is disposed on the first initial dielectric layer 22a of the opening 200 by the non-active surface 23b.

The first aperture 200a of the opening 200 is smaller than the second aperture 200b, so that the wafer 23 is received in the opening 200 by the second aperture 200b having a larger aperture, so that the wafer 23 can be prevented from touching the opening. A metal frame 210 on the surface around the ends of the 200.

As shown in FIGS. 2F and 2G, a second initial dielectric layer 22b is formed on the second surface 20b of the substrate 20, as shown in FIG. 2F; then, the first initial dielectric layer 22a and the second are laminated. The first dielectric layer 22b and the second initial dielectric layer 22b are integrated into the first dielectric layer 22, and the first dielectric layer 22 fills the opening 200 and the wafer. In the gap s between 23, the wafer 23 is fixed in the opening 200.

Since the second aperture 200b of the opening 200 is larger, the second initial dielectric layer 22b on the same side thereof can be filled with a larger amount in the gap s, so that the first dielectric on the active surface 23a of the wafer 23 The thickness t of the layer 22 is less than the thickness w of the first dielectric layer 22 on the second surface 20b of the substrate 20, as shown in FIG. 2G. Therefore, in the subsequent process, a better blind hole shape can be formed, so that the conductive blind hole formed in the blind hole can be effectively electrically connected.

As shown in FIG. 2H, a first circuit layer 25 is formed on the first dielectric layer 22, and the first circuit layer 25 has a first electrical connection between the electrode pads 230 in the first dielectric layer 22. The conductive blind hole 250; wherein the active surface 23a of the wafer 23 is on the same side as the second aperture 200b having a larger aperture, as shown in FIG. 2H.

As shown in FIG. 2I, a build-up structure 26 is formed on the first dielectric layer 22 and the first circuit layer 25. The build-up structure 26 has a second dielectric layer 260 disposed on the second dielectric layer. a second circuit layer 261 on the second dielectric layer 260, and a second conductive blind via 262 electrically connected to the first circuit layer 25 and the second circuit layer 261, and the second outer line located at the outermost layer A plurality of electrical contact pads 263 on layer 261. An insulating protective layer 28 is formed on the build-up structure 26, and the insulating protective layer 28 has a plurality of insulating protective layer openings 280 for exposing each of the electrical contact pads 263 to each of the insulating protective layer openings 280.

The present invention provides a package structure for embedding a wafer, comprising: a substrate 20, a wafer 23, a first dielectric layer 22, and a first wiring layer 25.

The substrate 20 has an opposite first surface 20a and a second surface 20b, and the first and second surfaces 20a, 20b have an internal wiring layer 21 and have through the first and second surfaces 20a, 20b. The opening 200 has a first aperture 200a at the first surface 20a and a second aperture 200b at the second surface 20b. The first aperture 200a is smaller than the second aperture 200b, and the substrate 20 is A metal frame 210 is formed around the opening 200.

The wafer 23 is disposed in the opening 200, and the wafer 23 has an opposite active surface 23a and an inactive surface 23b. The active surface 23a has a plurality of electrode pads 230. The wafer 23 is an integrated circuit. Wafer (IC) or multilayer ceramic capacitor (MLCC).

The first dielectric layer 22 covers the first and second surfaces 20a, 20b of the substrate 20, and the active surface 23a and the non-active surface 23b of the wafer 23. The first dielectric layer 22 is filled in. The gap s between the opening 200 and the wafer 23, and the thickness t of the first dielectric layer 22 on the active surface 23a of the wafer 23 is smaller than the first dielectric layer 22 on the second surface 20b of the substrate 20. Thickness w.

The first circuit layer 25 is disposed on the first dielectric layer 22, and the first circuit layer 25 has a first conductive blind in the first dielectric layer 22 and electrically connected to the electrode pad 230. Hole 250.

In the package structure, the active surface 23a of the wafer 23 is on the same side as the second aperture 200b, as shown in FIG. 2H.

The package structure includes a build-up structure 26 disposed on the first dielectric layer 22 and the first circuit layer 25. The build-up structure 26 has a second dielectric layer 260 disposed on the second dielectric layer. a second circuit layer 261 on the layer 260, and a second conductive via 262 disposed in the second dielectric layer 260 and electrically connected to the first circuit layer 25 and the second circuit layer 261, and the outermost layer The second circuit layer 261 has a plurality of electrical contact pads 263, and an insulating protective layer 28 is disposed on the build-up structure 26, and the insulating protective layer 28 has a plurality of insulating protective layer openings 280 for the electrical contact pads. 263 is correspondingly exposed to each of the insulating protective layer openings 280.

As described above, the package structure of the embedded wafer of the present invention and the method for manufacturing the same are formed on the substrate to form a metal frame. When the laser is opened, the opening can be consolidated by the metal frame to avoid the laser melting station. The lack of poor shape of the hole.

Furthermore, a through opening is formed in the substrate, and the first aperture of the opening is smaller than the second aperture, so that the wafer is inserted into the opening by the second aperture having a larger aperture, thereby effectively preventing the wafer from being touched. The metal frame around the two ends of the opening is scratched or broken, so that the wafer can maintain a normal electrical function, thereby avoiding affecting the electrical function of the final package.

In addition, when the first dielectric layer is pressed, the dielectric layer material will fill the gap between the opening and the wafer, because the second aperture of the opening of the substrate is larger, and the second initial dielectric on the same side thereof The layer can be filled with a larger amount in the gap, so that the thickness of the first dielectric layer on the active surface of the wafer is thinner, and a better blind hole shape can be formed, so that the conductive blind hole formed in the blind hole is formed later. It can be effectively connected electrically, and the wafer can maintain normal electrical functions, thereby avoiding affecting the electrical function of the final package.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10, 20‧‧‧ substrate
100,200‧‧‧ openings
10a, 20a‧‧‧ first surface
10b, 20b‧‧‧ second surface
101, 102, 101', 102', 210‧‧‧ metal frame
11, 21‧‧‧ internal circuit layer
12‧‧‧Dielectric layer
13, 23‧‧‧ wafer
13a, 23a‧‧‧ action surface
13b, 23b‧‧‧ non-active surface
130, 230‧‧‧electrode pads
15‧‧‧Line layer
150‧‧‧conductive blind holes
200a‧‧‧first aperture
200b‧‧‧second aperture
21a, 21b‧‧‧ metal layer
22‧‧‧First dielectric layer
22a‧‧‧First initial dielectric layer
22b‧‧‧Second initial dielectric layer
25‧‧‧First line layer
250‧‧‧First conductive blind hole
26‧‧‧Additional structure
260‧‧‧Second dielectric layer
261‧‧‧second circuit layer
262‧‧‧Second conductive blind hole
263‧‧‧Electrical contact pads
28‧‧‧Insulation protection layer
280‧‧‧Insulating protective layer opening
S‧‧‧ gap
t, w‧‧‧ thickness

1A to 1C are schematic views of a package structure of a conventional embedded wafer, wherein the first panel BB is a top view of the substrate and the opening;

2A to 2I are cross-sectional views showing respective processes of the package structure of the embedded wafer of the present invention; wherein the 2C' is a top view of the 2C.

20‧‧‧Substrate

20a‧‧‧ first surface

20b‧‧‧second surface

200‧‧‧ openings

200a‧‧‧first aperture

200b‧‧‧second aperture

21‧‧‧Internal circuit layer

210‧‧‧Metal frame

22‧‧‧First dielectric layer

23‧‧‧ wafer

23a‧‧‧Action surface

23b‧‧‧Non-active surface

230‧‧‧electrode pads

25‧‧‧First line layer

250‧‧‧First conductive blind hole

S‧‧‧ gap

t, w‧‧‧ thickness

Claims (11)

A package structure for embedding a wafer, comprising: a substrate having opposite first and second surfaces, wherein the first and second surfaces have internal wiring layers and have through the first and second surfaces An opening having a first aperture at the first surface and a second aperture at the second surface, the first aperture being smaller than the second aperture, and wherein the surface of the substrate has a metal around the opening a frame; the wafer is disposed in the opening, and the wafer has opposite active and non-active surfaces, and the active surface has a plurality of electrode pads, and the active surface of the wafer is on the same side of the second aperture a first dielectric layer covering the first and second surfaces of the substrate, the active surface and the non-active surface of the wafer, and the first dielectric layer is filled in the gap between the opening and the wafer And the first circuit layer is disposed on the first dielectric layer, and the first circuit layer has a first conductive blind hole in the first dielectric layer and electrically connected to the electrode pad. The package structure of the embedded wafer of claim 1, wherein the wafer is an integrated circuit chip (IC) or a multilayer ceramic capacitor (MLCC). The package structure of the embedded wafer of claim 1, further comprising a build-up structure disposed on the first dielectric layer and the first circuit layer, the build-up structure having a second dielectric layer disposed on a second circuit layer on the second dielectric layer, and a second conductive layer disposed in the second dielectric layer and electrically connected to the first and second circuit layers, and the second circuit layer of the outermost layer There are a plurality of electrical contact pads. Such as the package structure of the embedded wafer of the third application patent scope, including The edge protective layer is disposed on the build-up structure, and the insulating protective layer has a plurality of insulating protective layer openings, so that the electrical contact pads are correspondingly exposed to the openings of the insulating protective layers. The package structure of the embedded wafer of claim 1, wherein the thickness of the first dielectric layer on the active surface of the wafer is less than the thickness of the first dielectric layer on the second surface of the substrate. A method for fabricating a package structure for embedding a wafer, comprising: providing a substrate having opposite first and second surfaces; forming an internal wiring layer on the first and second surfaces of the substrate, and on the substrate Forming a metal frame; forming an opening in the substrate through the first and second surfaces, wherein the metal frame is located around the opening, and the opening has a first aperture and a second surface on the first surface a second aperture, the first aperture is smaller than the second aperture; forming a first initial dielectric layer on the first or second surface of the substrate to seal one end of the opening; a wafer having a corresponding active surface and a non-active surface, wherein the active surface has a plurality of electrode pads, and the active surface of the wafer is on the same side as the second aperture; and the first initial dielectric layer is opposite to the substrate Forming a second initial dielectric layer on the surface, and pressing the first and second initial dielectric layers to fill the gap between the opening and the wafer, so that the first and second initial dielectric layers are combined into Integrated into the first dielectric layer, 俾The wafer is fixed to the opening; and forming a first wiring layer on the first dielectric layer, and the first circuit having a first conductive layer located between the first dielectric layer and electrically connected to the electrode pads of Electric blind hole. The method for manufacturing a package structure of an embedded wafer according to claim 6 , wherein the method of forming the internal circuit layer is to form a metal layer on the first and second surfaces of the substrate, and then by a patterning process The metal layer forms the inner wiring layer. The method for fabricating a package structure of an embedded wafer according to claim 6, wherein the wafer is an integrated circuit chip (IC) or a multilayer ceramic capacitor (MLCC). The method for fabricating a package structure of an embedded wafer according to claim 6 further includes forming a build-up structure on the first dielectric layer and the first circuit layer, the build-up structure having a second dielectric layer disposed on the a second circuit layer on the second dielectric layer, and a second conductive via hole disposed in the second dielectric layer and electrically connected to the first and second circuit layers, and the second circuit layer of the outermost layer has A plurality of electrical contact pads. The method for manufacturing a package structure of an embedded wafer according to claim 9 is characterized in that the insulating layer is formed on the layered structure, and the insulating layer has a plurality of insulating protective layer openings to make the electrical contact The pad is correspondingly exposed to each of the insulating protective layer openings. The method for manufacturing a package structure of an embedded wafer according to claim 6 , wherein a thickness of the first dielectric layer on the active surface of the wafer is less than a thickness of the first dielectric layer on the second surface of the substrate; .