TWI490456B - Differential Capacitance Sensing Circuit and Method - Google Patents

Differential Capacitance Sensing Circuit and Method Download PDF

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Publication number
TWI490456B
TWI490456B TW100115139A TW100115139A TWI490456B TW I490456 B TWI490456 B TW I490456B TW 100115139 A TW100115139 A TW 100115139A TW 100115139 A TW100115139 A TW 100115139A TW I490456 B TWI490456 B TW I490456B
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capacitor
sensing
output voltage
storage
circuit
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TW100115139A
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Chinese (zh)
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TW201243290A (en
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Chao Chi Yang
Shih How Peng
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Elan Microelectronics Corp
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Priority to TW100115139A priority Critical patent/TWI490456B/en
Priority to CN201110160912.1A priority patent/CN102759367B/en
Priority to CN201410448257.3A priority patent/CN104236595B/en
Priority to US13/457,096 priority patent/US9007074B2/en
Publication of TW201243290A publication Critical patent/TW201243290A/en
Priority to US14/657,621 priority patent/US9529020B2/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
    • G01D5/14—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
    • G01D5/24—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R17/00—Measuring arrangements involving comparison with a reference value, e.g. bridge
    • G01R17/02—Arrangements in which the value to be measured is automatically compared with a reference value

Description

差動電容的感測電路及方法Sensing circuit and method for differential capacitor

本發明係有關一種差動電容的感測電路，特別是關於一種差動電容的感測電路及方法，可降低RF干擾及電源雜訊。The invention relates to a sensing circuit for a differential capacitor, in particular to a sensing circuit and method for a differential capacitor, which can reduce RF interference and power noise.

差動電容(differential Capacitance)又稱為電極電容，係針對兩電極各自形成的電容之差值大小作感測，廣泛地應用於感測壓力、加速度、直線位移、旋轉角度等物理作用所造成的電容變化的感測器(sensor)，其電路結構依感測量的要求不同而不同，但基本皆是以感測器中兩電極各自形成的電容之差異來產生感測值。Differential Capacitance (also known as electrode capacitance) is used to sense the difference between the capacitances formed by the two electrodes. It is widely used in sensing physical effects such as pressure, acceleration, linear displacement and rotation angle. The sensor of the capacitance change has a different circuit structure depending on the requirements of the sensing, but basically the sensing value is generated by the difference in capacitance formed by the two electrodes in the sensor.

圖1係習知量測差動電容10的感測電路，於美國專利公告第6,949,937號所提出，包含有切換式電容前端電路12及放大級(Amplifier Stage)14。差動電容10為兩電極之間的電容，可視為由一對可變電容CT1、CT2組成。切換式電容前端電路12具有切換電路16及電荷儲存電路18，於感測端Input1、Input2分別連接電容CT1、CT2，利用切換電路16中開關S1~S8的切換，讓電容CT1、CT2連接電源VDD和VSS以供應適當的電荷，再重複將電容CT1、CT2的電荷轉移至電荷儲存電路18中的電容C1、C2中，最後將電容C1、C2中的電荷儲存於一浮接的電容CD兩端，以電容CD兩端之電位差VCD 對應電容CT1、CT2的差值，最後將電容CD之兩端連接放大器14的輸入，將此電位差VCD 由放大級14放大輸出， 達到感測差動電容10的效果。其中放大器14為多級放大器，其包括差動放大級AMP1根據輸出電壓VOUT1 及VOUT2 的差異VCD 產生放大信號Va，以及阻抗轉換級AMP2根據放大信號Va產生感測值VSENS 。圖2a~2e所示係圖1中切換式電容前端電路12的操作示意圖。而此習知技術更以過取樣(Over-sampling)之方式，在不重置開關SR1及SR2的情況下重複圖2a~2d之動作，對電容CT1及CT2重複充放電，並重複轉移電荷至內部的單一儲存電容C1或C2中，用以於前端的切換式電容前端電路12中進行平均以抑制RF干擾或電源雜訊後，之後，如圖2e將電容C1、C2中的電荷儲存於電容CD兩端，最後，由圖1中後端的放大級(Amplifier Stage)14連接電容CD之兩端，放大輸出。由於此習知技術是重複操作前端的切換式電容前端電路12以進行平均，並不是重複操作整個電路後再平均，具有節省功率消耗的效果。FIG. 1 is a schematic diagram of a sensing circuit for measuring a differential capacitor 10, which is disclosed in U.S. Patent No. 6,949,937, which includes a switched capacitor front end circuit 12 and an Amplifier Stage 14. The differential capacitor 10 is a capacitor between the two electrodes and can be regarded as consisting of a pair of variable capacitors CT1 and CT2. The switched capacitor front end circuit 12 has a switching circuit 16 and a charge storage circuit 18, and the capacitors CT1 and CT2 are respectively connected to the sensing terminals Input1 and Input2, and the capacitors CT1 and CT2 are connected to the power source VDD by switching the switches S1 to S8 in the switching circuit 16. And VSS to supply an appropriate charge, and then repeatedly transfer the charges of the capacitors CT1, CT2 to the capacitors C1, C2 in the charge storage circuit 18, and finally store the charges in the capacitors C1, C2 at both ends of a floating capacitor CD The potential difference V CD at both ends of the capacitor CD corresponds to the difference between the capacitances CT1 and CT2. Finally, the two ends of the capacitor CD are connected to the input of the amplifier 14, and the potential difference V CD is amplified and output by the amplifier stage 14 to reach the sense differential capacitor. 10 effects. The amplifier 14 is a multi-stage amplifier including a differential amplifier stage AMP1 that generates an amplified signal Va according to a difference V CD between the output voltages V OUT1 and V OUT2 , and an impedance conversion stage AMP2 that generates a sensed value V SENS according to the amplified signal Va. 2a-2e are schematic diagrams showing the operation of the switched capacitor front end circuit 12 of FIG. The conventional technique repeats the operations of FIGS. 2a to 2d without resetting the switches SR1 and SR2 in an over-sampling manner, repeats charging and discharging of the capacitors CT1 and CT2, and repeatedly transfers the charge to The internal single storage capacitor C1 or C2 is used to average the switched capacitor front-end circuit 12 at the front end to suppress RF interference or power supply noise. Then, the charge in the capacitors C1 and C2 is stored in the capacitor as shown in FIG. 2e. At both ends of the CD, finally, the two ends of the capacitor CD are connected by the Amplifier Stage 14 at the rear end in FIG. 1 to amplify the output. Since this conventional technique repeats the operation of the front-end switched capacitor front-end circuit 12 for averaging, it is not averaging after repeatedly operating the entire circuit, and has the effect of saving power consumption.

但是上述之操作方式，卻無法有效地平均，以降低雜訊。以經由電荷守恆計算可得n次電荷轉移後，以C1電容為例，其輸出電壓VOUT1 如下：VOUT1 =Vn +Vn-1 ．X+Vn-2 ．X2 +Λ+V1 ．Xn-1 ， 公式1 其中其X的數值通常位於0.1~0.5之間，VDDi 可視為包含RF干擾及電源雜訊影響而等效電源VDD於各時間點產生不同數值。由公式1~3可知，經n次取樣電荷轉移後，除第n次取樣轉移外，其他次取樣皆受一係數X所影響，且因X<1，使得越前取樣之結果對輸出影響程度越少，亦即VOUT1 將近似於Vn ，因此在此架構下進行過取樣，並無法有效平均降低雜訊。However, the above operation methods cannot be effectively averaged to reduce noise. After n charge transfer can be obtained by the conservation of charge, taking C1 capacitor as an example, the output voltage V OUT1 is as follows: V OUT1 =V n +V n-1 . X+V n-2 . X 2 +Λ+V 1 . X n-1 , formula 1 The value of X is usually between 0.1 and 0.5, and VDD i can be regarded as containing RF interference and power noise. The equivalent power VDD produces different values at each time point. It can be seen from Equations 1~3 that after n times of sample charge transfer, except for the nth sample transfer, the other subsamplings are affected by a coefficient X, and because X<1, the effect of the result of the Echizen sample on the output is more Less, that is, V OUT1 will approximate V n , so oversampling under this architecture does not effectively reduce noise on average.

此外，放大級14是利用運算放大器直接將對應輸出電壓VOUT1 、VOUT2 的差值VCD 放大，會同時將運算放大器的非理想效應一併於輸出端輸出，如偏移(Offset)、閃爍雜訊(Flicker Noise)、有限增益的錯誤(Finite Gain error)…等，使得感測結果受到影響。In addition, the amplifier stage 14 directly amplifies the difference V CD of the corresponding output voltages V OUT1 and V OUT2 by using an operational amplifier, and simultaneously outputs the non-ideal effect of the operational amplifier at the output end, such as offset (offset), blinking. Flicker Noise, Finite Gain error, etc., so that the sensing results are affected.

本發明的目的，在於提出一種差動電容的感測電路及方法，可降低RF干擾及電源雜訊。It is an object of the present invention to provide a sensing circuit and method for a differential capacitor that can reduce RF interference and power supply noise.

根據本發明，一種差動電容的感測電路包含連接該差動電容之兩端的第一感測端及第二感測端，連接該第一感測端及該第二感測端的切換電路，經由切換使該差動電容之兩端連接於高電壓源、低電壓源或是進行電荷轉移，耦接該切換電路的電荷儲存電路，配合該切換電路的切換，儲存該差動電容所轉移的電荷，其中該電荷儲存電路包含多個第一儲存電容的第一儲存電路，分次儲存該差動電容之一端的電荷於該不同第一儲存電容中，產生第一輸出電壓，與多個第二儲存電容的第二儲存 電路，分次儲存該差動電容之另一端的電荷於該不同第二儲存電容中，產生第二輸出電壓，以及根據該第一輸出電壓及該第二輸出電壓的差異產生感測值的放大級。According to the present invention, a sensing circuit of a differential capacitor includes a first sensing terminal and a second sensing terminal connected to both ends of the differential capacitor, and a switching circuit connecting the first sensing terminal and the second sensing terminal. The two ends of the differential capacitor are connected to a high voltage source, a low voltage source or a charge transfer via a switch, coupled to the charge storage circuit of the switching circuit, and the switching of the switching circuit is performed to store the transferred of the differential capacitor. a charge, wherein the charge storage circuit includes a plurality of first storage circuits of the first storage capacitor, and the charge stored at one end of the differential capacitor is stored in the different first storage capacitors to generate a first output voltage, and a plurality of Second storage of the storage capacitor a circuit that sequentially stores the charge of the other end of the differential capacitor in the different second storage capacitor to generate a second output voltage, and generates an amplification of the sensing value according to the difference between the first output voltage and the second output voltage level.

根據本發明，一種差動電容的感測方法包含切換開關使該差動電容之兩端連接於高電壓源、低電壓源或是進行電荷轉移，分次儲存該差動電容之一端的電荷於不同第一儲存電容中，並聯產生第一輸出電壓，分次儲存該差動電容之另一端的電荷於不同第二儲存電容中，並聯產生第二輸出電壓，以及根據該第一輸出電壓及該第二輸出電壓的差異產生感測值。According to the present invention, a method for sensing a differential capacitor includes switching a switch to connect both ends of the differential capacitor to a high voltage source, a low voltage source, or performing charge transfer, and sequentially storing the charge at one end of the differential capacitor. a first output voltage is generated in parallel according to different first storage capacitors, and the charge at the other end of the differential capacitor is stored in different second storage capacitors in parallel, and a second output voltage is generated in parallel, and according to the first output voltage and the The difference in the second output voltage produces a sensed value.

根據本發明，一種差動電容的感測電路包含連接該差動電容之兩端的第一感測端及第二感測端，連接該第一感測端及該第二感測端的切換電路，經由切換使該差動電容之兩端連接於高電壓源、低電壓源或是進行電荷轉移，耦接該切換電路的電荷儲存電路，配合該切換電路的切換，儲存該差動電容所轉移的電荷，其中該電荷儲存電路包含第一儲存電路儲存該差動電容之一端的電荷於第一儲存電容中，第二儲存電路儲存該差動電容之另一端的電荷於第二儲存電容中，以及多個第三儲存電容的第三儲存電路，其中每一該第三儲存電容之兩端分別連接於該第一儲存電路及第二儲存電路，分次將該第一儲存電路及第二儲存電路中的電荷儲存於該不同第三儲存電容中，並聯時於兩端產生第一輸出電壓及第二輸出電壓，以及根據該第一輸出電壓及該第二輸出電壓的差異產生感測值的放大級，。According to the present invention, a sensing circuit of a differential capacitor includes a first sensing terminal and a second sensing terminal connected to both ends of the differential capacitor, and a switching circuit connecting the first sensing terminal and the second sensing terminal. The two ends of the differential capacitor are connected to a high voltage source, a low voltage source or a charge transfer via a switch, coupled to the charge storage circuit of the switching circuit, and the switching of the switching circuit is performed to store the transferred of the differential capacitor. a charge, wherein the charge storage circuit includes a first storage circuit for storing charge at one end of the differential capacitor in the first storage capacitor, and a second storage circuit storing charge at the other end of the differential capacitor in the second storage capacitor, and a third storage circuit of the plurality of third storage capacitors, wherein the two ends of each of the third storage capacitors are respectively connected to the first storage circuit and the second storage circuit, and the first storage circuit and the second storage circuit are respectively divided The charge in the second storage capacitor is stored in the second storage capacitor, and generates a first output voltage and a second output voltage at both ends in parallel, and according to the first output voltage and the second output voltage Producing an amplified level difference sensed value.

根據本發明，一種差動電容的感測方法包含切換開關使該差動電容之兩端連接於高電壓源、低電壓源或是進行電荷轉 移，儲存該差動電容之一端的電荷於第一儲存電容中，儲存該差動電容之另一端的電荷於第二儲存電容中，分次將該第一儲存電路及第二儲存電路中的電荷儲存於該不同第三儲存電容中，並聯時於兩端產生第一輸出電壓及第二輸出電壓，以及根據該第一輸出電壓及該第二輸出電壓的差異產生感測值。According to the present invention, a sensing method for a differential capacitor includes switching a switch to connect both ends of the differential capacitor to a high voltage source, a low voltage source, or perform charge transfer. Shifting, storing the charge at one end of the differential capacitor in the first storage capacitor, storing the charge at the other end of the differential capacitor in the second storage capacitor, and dividing the first storage circuit and the second storage circuit in stages The charge is stored in the different third storage capacitors. When connected in parallel, the first output voltage and the second output voltage are generated at both ends, and the sensing value is generated according to the difference between the first output voltage and the second output voltage.

本發明利用多個內部儲存電容以供過取樣，來取代在單一儲存電容上重複電荷轉移，進而有效地對輸入及雜訊平均取樣，以降低RF干擾及電源雜訊。The present invention utilizes multiple internal storage capacitors for oversampling instead of repeating charge transfer on a single storage capacitor, thereby effectively sampling the input and noise evenly to reduce RF interference and power supply noise.

圖3係本發明差動電容感測電路之第一實施例。圖中之感測電路具有切換電路16、電荷儲存電路20以及放大級22，其中電荷儲存電路20具有多個儲存電容，操作時以開關控制將每次取樣所轉移的電荷儲存於不同儲存電容中，最後再將儲存電容並聯輸出，達到對輸入及雜訊取樣平均的效果。切換電路16於感測端Input1、Input2分別連接電容CT1、CT2，利用切換電路16中開關S1~S8的切換，讓電容CT1、CT2連接低電壓源或高電壓源，於本說明時之所有實施例皆以電源VSS為低電壓源，電源VDD為高電壓源，以供應適當的電荷，再重複將電容CT1、CT2的電荷轉移至電荷儲存電路20中(過程如Fig.2a~2d所示)。電荷儲存電路20具有儲存電路24、26，而儲存電路24與儲存電路26具有完全相同的結構，儲存電路24包含多個電容CS11、CS12、CS13，操作時以開關SC11、SC12、SC13控制，將電容CT1不同次取樣所轉移的電荷儲存 於不同的電容CS11、CS12、CS13中，最後同時導通開關SC14、SC15、SC16將所有電容並聯產生輸出電壓VOUT1 ，而儲存電路26包含多個電容CS21、CS22、CS23，操作時以開關SC21、SC22、SC23控制，將電容CT2不同次取樣所轉移的電荷儲存於不同的電容CS21、CS22、CS23中，最後同時導通開關SC24、SC25、SC26將所有電容並聯產生輸出電壓VOUT2 。而本實施例中的放大級22以一類關聯雙取樣技術(Pseudo Correlated Double Sampling)的操作方式，分次輸入前端電路取樣的電壓，並利用一電容儲存該非理想特性的誤差值來抵減運算放大器的非理想特性。放大級22包含有運算放大器28、開關SW1~SW6、取樣電容CA、CB，運算放大器28的正輸入端連接共同參考電壓源，開關SW1連接儲存電路24輸入輸出電壓VOUT1 ，開關SW2連接儲存電路26用以輸入輸出電壓VOUT2 ，開關SW3連接於該運算放大器之負輸入端及輸出端之間，取樣電容CA一端連接於該運算放大器28之負輸入端，另一端連接開關SW1、SW2，而取樣電容CB一端連接於該運算放大器28之負輸入端，另一端連接開關SW4、SW5，使取樣電容連接於共同參考電壓源或運算放大器28之輸出端，而開關SW6則用於重置取樣電容CA之電位。一實施例中，使用電源VSS作為共同參考電壓源。另一實施例中，使用(VDD-VSS)/2作為共同參考電壓源。圖4A~4C係圖3中放大級22之操作示意圖。一開始，如圖4A所示，先導通開關SW6，重置取樣電容CA之電位，並同時於運算放大器28的負輸入端，儲存運算放大器28的非理想誤差值Verr於取樣電 容CB中，接著如圖4B所示，導通開關SW1、SW4，利用取樣電容CA對該輸出電壓VOUT1 取樣，最後導通開關SW2、SW5使取樣電容CB連接於該運算放大器28的負輸入端與輸出端之間，而取樣電容CA對該輸出電壓VOUT2 取樣，經由放大級放大後，此時取樣電容CB跨壓VCB 為[(VOUT1 -VOUT2 )*(CA/CB)+Verr]+(-Verr)，其中的非理想誤差值Verr與運算放大器28的非理想效應互相抵消，產生感測值VSENS =(VOUT1 -VOUT2 )*(CA/CB)，只與輸出電壓VOUT1 、VOUT2 之間的差值相關。3 is a first embodiment of a differential capacitance sensing circuit of the present invention. The sensing circuit in the figure has a switching circuit 16, a charge storage circuit 20 and an amplification stage 22, wherein the charge storage circuit 20 has a plurality of storage capacitors, and the switches control the charge transferred in each sampling to be stored in different storage capacitors. Finally, the storage capacitors are connected in parallel to achieve an average of the input and noise sampling. The switching circuit 16 is connected to the capacitances CT1 and CT2 at the sensing terminals Input1 and Input2, respectively, and the capacitors CT1 and CT2 are connected to the low voltage source or the high voltage source by switching the switches S1 to S8 in the switching circuit 16, and all implementations in the present description are performed. For example, the power supply VSS is a low voltage source, and the power supply VDD is a high voltage source to supply an appropriate charge, and then the charges of the capacitors CT1 and CT2 are repeatedly transferred to the charge storage circuit 20 (the process is shown in Fig. 2a~2d). . The charge storage circuit 20 has storage circuits 24, 26, and the storage circuit 24 has exactly the same structure as the storage circuit 26. The storage circuit 24 includes a plurality of capacitors CS11, CS12, CS13, which are controlled by switches SC11, SC12, SC13 during operation, The charge transferred by the capacitor CT1 in different samplings is stored in different capacitors CS11, CS12, CS13, and finally the conduction switches SC14, SC15, SC16 connect all the capacitors in parallel to generate the output voltage V OUT1 , and the storage circuit 26 includes a plurality of capacitors CS21, CS22, CS23, controlled by switches SC21, SC22, SC23 during operation, the charge transferred by different sampling of capacitor CT2 is stored in different capacitors CS21, CS22, CS23, and finally the switches SC24, SC25, SC26 are connected in parallel with all capacitors. Produces an output voltage V OUT2 . The amplification stage 22 in this embodiment uses a Pseudo Correlated Double Sampling operation mode to input the voltage sampled by the front end circuit in stages, and uses a capacitor to store the error value of the non-ideal characteristic to offset the operational amplifier. Non-ideal characteristics. The amplifier stage 22 includes an operational amplifier 28, switches SW1 SWSW6, and sampling capacitors CA and CB. The positive input terminal of the operational amplifier 28 is connected to a common reference voltage source, the switch SW1 is connected to the input and output voltage V OUT1 of the storage circuit 24, and the switch SW2 is connected to the storage circuit. 26 is used for input and output voltage V OUT2 , and switch SW3 is connected between the negative input terminal and the output terminal of the operational amplifier. One end of the sampling capacitor CA is connected to the negative input terminal of the operational amplifier 28, and the other end is connected to the switches SW1 and SW2. One end of the sampling capacitor CB is connected to the negative input terminal of the operational amplifier 28, and the other end is connected to the switches SW4, SW5, so that the sampling capacitor is connected to the output of the common reference voltage source or the operational amplifier 28, and the switch SW6 is used to reset the sampling capacitor. The potential of CA. In one embodiment, the power supply VSS is used as a common reference voltage source. In another embodiment, (VDD - VSS) / 2 is used as a common reference voltage source. 4A-4C are schematic views showing the operation of the amplification stage 22 of FIG. Initially, as shown in FIG. 4A, the switch SW6 is first turned on, the potential of the sampling capacitor CA is reset, and at the same time, the negative input terminal of the operational amplifier 28 stores the non-ideal error value Verr of the operational amplifier 28 in the sampling capacitor CB, and then As shown in FIG. 4B, the switches SW1 and SW4 are turned on, and the output voltage V OUT1 is sampled by the sampling capacitor CA. Finally, the switches SW2 and SW5 are connected to connect the sampling capacitor CB between the negative input terminal and the output terminal of the operational amplifier 28. The sampling capacitor CA samples the output voltage V OUT2 and is amplified by the amplification stage. At this time, the sampling capacitor CB cross-voltage V CB is [(V OUT1 -V OUT2 )*(CA/CB)+Verr]+(-Verr) The non-ideal error value Verr and the non-ideal effect of the operational amplifier 28 cancel each other out, and the sensed value V SENS =(V OUT1 -V OUT2 )*(CA/CB) is generated, and only the output voltages V OUT1 , V OUT2 The difference between the two is related.

為達到多次取樣分別儲存的目的，電荷儲存電路20可採階層化儲存設計。如圖5所示，係使用二階層電容的電荷儲存電路20之第二實施例。圖中的電荷儲存電路20中的儲存電路24、26具有完全相同的結構，皆為兩階層儲存電容架構。以儲存電路24對電容CT1重複取樣為例(過程如Fig.2a~2b所示)，第一次取樣所轉移之電荷儲存於電容CS111中，第二次取樣所轉移之電荷儲存於電容CS112中，之後導通開關SC113與SC114，將電容CS111與CS112之電荷轉移到電容CS121中儲存，然後導通開關SR111與SR112重置電容CS111、CS112，第三與四次取樣依同一方式分別儲存於電容CS111、CS112中，再將電荷轉移到電容CS122中，第五與六次取樣又依同一方式分別儲存於電容CS1 11、CS112中，再將電荷轉移到電容CS123中，之後導通開關SC124、SC125、SC126，輸出電壓VOUT1 即為2*3=6次取樣後的平均輸出。對CT2電容取樣也是依同一方式進行。對電容CT1與CT2的取樣可交錯 進行，亦對降低雜訊干擾有幫助。The charge storage circuit 20 can adopt a hierarchical storage design for the purpose of storing multiple samples separately. As shown in FIG. 5, a second embodiment of a charge storage circuit 20 using a two-level capacitor is used. The storage circuits 24, 26 in the charge storage circuit 20 of the figure have the same structure, both of which are two-layer storage capacitor architectures. Taking the sampling of the capacitor CT1 by the storage circuit 24 as an example (the process is as shown in Fig. 2a~2b), the transferred charge of the first sampling is stored in the capacitor CS111, and the transferred charge of the second sampling is stored in the capacitor CS112. Then, the switches SC113 and SC114 are turned on, the charges of the capacitors CS111 and CS112 are transferred to the capacitor CS121 for storage, and then the switches SR111 and SR112 are reset to the capacitors CS111 and CS112, and the third and fourth samples are respectively stored in the capacitor CS111 in the same manner. In CS112, the charge is transferred to the capacitor CS122, and the fifth and sixth samples are respectively stored in the capacitors CS1 11 and CS112 in the same manner, and then the charge is transferred to the capacitor CS123, and then the switches SC124, SC125, SC126 are turned on. The output voltage V OUT1 is the average output after 2*3=6 samples. Sampling the CT2 capacitor is also done in the same way. Sampling of capacitors CT1 and CT2 can be interleaved and can also be helpful in reducing noise interference.

以N個第一階電容，M個第二階電容組成的兩階層儲存電容架構對CT1電容重複n=N*M次取樣說明上述多階層儲存電容的操作原理，經由電荷守恆計算，其輸出電壓VOUT1 如下：VOUT1 =((Vn +Vn-1 +Λ+V2 +V1 )/M)×A， 公式4 其中，CS1為所有第一階電容的相同電容值，CS2為所有第二階電容的相同電容值。將公式5、6代入公式4可以看出，此多階層分別儲存轉移電荷的方式，可有效地平均輸入訊號及雜訊，降低雜訊的影響。因此，將電荷儲存電路20設計成多階層的儲存電路，其輸出電壓趨近於進行了多階層內各階層電容數目乘積之取樣次數所得到的平均輸出電壓。在其他實施例中，更可以依此方式將電荷儲存電路20設計成三階層或是三階層以上的儲存電路。The two-stage storage capacitor architecture consisting of N first-order capacitors and M second-order capacitors repeats n=N*M sampling of the CT1 capacitor to illustrate the operation principle of the multi-level storage capacitor, and the output voltage is calculated by the charge conservation calculation. V OUT1 is as follows: V OUT1 = ((V n + V n-1 + Λ + V 2 + V 1 ) / M) × A, Equation 4 Where CS1 is the same capacitance value of all first-order capacitors, and CS2 is the same capacitance value of all second-order capacitors. Substituting the formulas 5 and 6 into the formula 4 can be seen that the multi-level storage of the transferred charge can effectively input the signal and the noise, and reduce the influence of the noise. Therefore, the charge storage circuit 20 is designed as a multi-level storage circuit whose output voltage is close to the average output voltage obtained by sampling the number of times of the capacitance of each layer in the multi-level. In other embodiments, the charge storage circuit 20 can be designed in such a manner as a three-level or three-level storage circuit.

圖6係本發明差動電容感測電路之第三實施例。圖中之感測電路具有切換電路16、電荷儲存電路30以及放大級22，其中電荷儲存電路30同樣是以多個儲存電容進行過取樣的概念進行操作，但是不同於圖3之實施例，該電荷儲存電路30具有三個儲存電路32、34、36，並將多個儲存電容的概念加於 浮接於儲存電路32、34之間的儲存電路36中。此電路以儲存電路32、34中的電容CS1、CS2對電容CT1、CT2取樣(過程如圖2a~2d所示)，第一次取樣之後導通開關SCD1、SCD2，將電荷儲存於電容CD1中，然後重置電容CS1、CS2，以相同操作於第二次取樣之後將電荷儲存於電容CD2中，再重置電容CS1、CS2，接著第三次取樣之後將電荷儲存於電容CD3中，最後，將電容CD1~CD3並聯輸出，達到對輸入及雜訊取樣平均的效果。在其他實施例中，儲存電路32、34同樣具有多個或多階的儲存電容，如圖3或圖5之儲存電路24、26，進而使輸出更為平均。Figure 6 is a third embodiment of the differential capacitance sensing circuit of the present invention. The sensing circuit in the figure has a switching circuit 16, a charge storage circuit 30, and an amplification stage 22, wherein the charge storage circuit 30 is also operated with the concept of oversampling a plurality of storage capacitors, but unlike the embodiment of FIG. The charge storage circuit 30 has three storage circuits 32, 34, 36 and adds the concept of a plurality of storage capacitors to Floating in the storage circuit 36 between the storage circuits 32, 34. The circuit samples the capacitors CT1 and CT2 with the capacitors CS1 and CS2 in the storage circuits 32 and 34 (the process is as shown in FIGS. 2a to 2d). After the first sampling, the switches SCD1 and SCD2 are turned on, and the charge is stored in the capacitor CD1. Then, the capacitors CS1 and CS2 are reset, the charge is stored in the capacitor CD2 after the second sampling, and the capacitors CS1 and CS2 are reset, and then the charge is stored in the capacitor CD3 after the third sampling. Finally, Capacitors CD1~CD3 are output in parallel to achieve an average of input and noise sampling. In other embodiments, the storage circuits 32, 34 also have multiple or multiple orders of storage capacitance, such as the storage circuits 24, 26 of FIG. 3 or FIG. 5, thereby making the output more even.

上述之電荷儲存電路20、30可使用不同放大級作為後端的輸出電路，例如，如圖7所示，以不考慮放大級中運算放大器的非理想效應的情況下，使用圖1之放大級14作為後端的放大輸出產生感測值VSENS 。The above-described charge storage circuits 20, 30 can use different amplification stages as the output circuits of the back end. For example, as shown in FIG. 7, the amplification stage 14 of FIG. 1 is used regardless of the non-ideal effect of the operational amplifier in the amplification stage. generating sensing value V SENS amplified output as the rear end.

以上對於本發明之較佳實施例所作的敘述係為闡明之目的，而無意限定本發明精確地所揭露的形式，基於以上的教導或從本發明的實施例學習而作修改或變化是可能的，實施例係為解說本發明的原理以及讓熟習該項技術者以各種實施例利用本發明在實際應用上而選擇及敘述，本發明的技術思想企圖由以下的申請專利範圍及其均等來決定。The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the present invention. It is possible to make modifications or variations based on the above teachings or learning from the embodiments of the present invention. The embodiments are described and illustrated in the practical application by the skilled person in the various embodiments using the present invention. The technical idea of the present invention is determined by the following claims and their equals. .

10‧‧‧差動電容10‧‧‧Differential Capacitance

12‧‧‧切換式電容前端電路12‧‧‧Switching capacitor front-end circuit

14‧‧‧放大級14‧‧‧Amplification

16‧‧‧切換電路16‧‧‧Switching circuit

18‧‧‧電荷儲存電路18‧‧‧Charge storage circuit

20‧‧‧電荷儲存電路20‧‧‧Charge storage circuit

22‧‧‧放大級22‧‧‧Amplification

24‧‧‧儲存電路24‧‧‧Storage circuit

26‧‧‧儲存電路26‧‧‧Storage circuit

28‧‧‧運算放大器28‧‧‧Operational Amplifier

30‧‧‧電荷儲存電路30‧‧‧Charge storage circuit

32‧‧‧儲存電路32‧‧‧Storage circuit

34‧‧‧儲存電路34‧‧‧Storage circuit

36‧‧‧儲存電路36‧‧‧Storage circuit

圖1係習知量測差動電容的感測電路；圖2a~2e所示係圖1中切換式電容前端電路12的操作示 意圖；圖3係本發明差動電容感測電路之第一實施例；圖4a~4c係圖3中放大級22之操作示意圖；圖5係使用二階層電容的電荷儲存電路20之第二實施例；圖6係本發明差動電容感測電路之第三實施例；以及圖7係本發明差動電容感測電路之第四實施例。1 is a sensing circuit for measuring a differential capacitance; FIG. 2a to FIG. 2e are diagrams showing the operation of the switched capacitor front end circuit 12 of FIG. 3 is a first embodiment of the differential capacitance sensing circuit of the present invention; FIGS. 4a to 4c are schematic diagrams showing the operation of the amplification stage 22 of FIG. 3; FIG. 5 is a second implementation of the charge storage circuit 20 using a two-layer capacitor. 6 is a third embodiment of the differential capacitance sensing circuit of the present invention; and FIG. 7 is a fourth embodiment of the differential capacitance sensing circuit of the present invention.

10‧‧‧差動電容10‧‧‧Differential Capacitance

16‧‧‧切換電路16‧‧‧Switching circuit

20‧‧‧電荷儲存電路20‧‧‧Charge storage circuit

22‧‧‧放大級22‧‧‧Amplification

24‧‧‧儲存電路24‧‧‧Storage circuit

26‧‧‧儲存電路26‧‧‧Storage circuit

28‧‧‧運算放大器28‧‧‧Operational Amplifier

Claims (20)

一種差動電容的感測電路，包含：第一感測端及第二感測端，連接該差動電容之兩端；切換電路，連接該第一感測端及該第二感測端，經由切換使該差動電容之兩端連接於高電壓源、低電壓源或是進行電荷轉移；電荷儲存電路，耦接該切換電路，配合該切換電路的切換，儲存該差動電容所轉移的電荷，包含：第一儲存電路，包含多個第一儲存電容，分次儲存該差動電容之一端的電荷於該不同第一儲存電容中，產生第一輸出電壓；以及第二儲存電路，包含多個第二儲存電容，分次儲存該差動電容之另一端的電荷於該不同第二儲存電容中，產生第二輸出電壓；以及放大級，根據該第一輸出電壓及該第二輸出電壓的差異產生感測值；其中，該多個第一儲存電容被並聯後產生該第一輸出電壓，該多個第二儲存電容被並聯後產生該第二輸出電壓。 A sensing circuit for a differential capacitor includes: a first sensing end and a second sensing end connected to both ends of the differential capacitor; and a switching circuit connecting the first sensing end and the second sensing end, The two ends of the differential capacitor are connected to a high voltage source, a low voltage source or a charge transfer via a switch; the charge storage circuit is coupled to the switching circuit, and the switching of the switching circuit is performed to store the transferred by the differential capacitor. The electric charge includes: a first storage circuit including a plurality of first storage capacitors, storing the charge of one end of the differential capacitor in the different first storage capacitors to generate a first output voltage; and a second storage circuit, including a plurality of second storage capacitors, storing the charge of the other end of the differential capacitor in the different second storage capacitors to generate a second output voltage; and an amplification stage according to the first output voltage and the second output voltage The difference produces a sensed value; wherein the plurality of first storage capacitors are connected in parallel to generate the first output voltage, and the plurality of second storage capacitors are connected in parallel to generate the second output voltage. 如請求項1之感測電路，其中該多個第一儲存電容或該多個第二儲存電容包含：多個第一階電容，分次儲存電荷於該不同第一階電容中；以及多個第二階電容，分次儲存該多個第一階電容並聯後的電荷於該不同第二階電容中。 The sensing circuit of claim 1, wherein the plurality of first storage capacitors or the plurality of second storage capacitors comprise: a plurality of first-order capacitors, storing charges in the different first-order capacitors in stages; and The second-order capacitor stores the charges of the plurality of first-order capacitors in parallel in the different second-order capacitors. 如請求項1之感測電路，其中該電荷儲存電路更包含第三儲存電路，包含至少一第三儲存電容，連接該第一儲存電路及第二 儲存電路，分別儲存該第一儲存電路及第二儲存電路中的電荷於兩端。 The sensing circuit of claim 1, wherein the charge storage circuit further comprises a third storage circuit, including at least one third storage capacitor, connected to the first storage circuit and the second The storage circuit stores the charges in the first storage circuit and the second storage circuit at both ends. 如請求項1之感測電路，其中該切換電路包含：第一開關對，連接該第一感測端，包含第一上下橋開關分別連接高電壓源及低電壓源；第二開關對，連接該第二感測端，包含第二上下橋開關分別連接高電壓源及低電壓源；第三開關對，連接該第一儲存電路，使該第一儲存電路連接於該第一感測端、第二感測端或同時連接，進行電荷轉移；以及第四開關對，連接該第二儲存電路，使該第二儲存電路連接於該第一感測端、第二感測端或同時連接，進行電荷轉移。 The sensing circuit of claim 1, wherein the switching circuit comprises: a first switch pair connected to the first sensing end, wherein the first upper and lower bridge switches are respectively connected to a high voltage source and a low voltage source; and the second switch pair is connected The second sensing terminal includes a second upper and lower bridge switch respectively connected to the high voltage source and the low voltage source; the third switch pair is connected to the first storage circuit, so that the first storage circuit is connected to the first sensing end, The second sensing terminal is connected to the second sensing circuit, and the second storage circuit is connected to the first sensing terminal, the second sensing terminal or the same connection. Carry out charge transfer. 如請求項1之感測電路，其中該放大級包含：運算放大器，其正輸入端連接共同參考電壓源；第一開關，用以輸入該第一輸出電壓；第二開關，用以輸入該第二輸出電壓；第一取樣電容，一端連接於該運算放大器之負輸入端，另一端連接該第一開關及該第二開關；第三開關，連接於該運算放大器之負輸入端及輸出端之間；以及第二取樣電容，一端連接於該運算放大器之負輸入端，另一端藉第四開關連接該共同參考電壓源，或藉第五開關連接該運算放大器之輸出端。 The sensing circuit of claim 1, wherein the amplification stage comprises: an operational amplifier having a positive input terminal connected to a common reference voltage source; a first switch for inputting the first output voltage; and a second switch for inputting the first a second sampling voltage; a first sampling capacitor, one end is connected to the negative input end of the operational amplifier, the other end is connected to the first switch and the second switch; and the third switch is connected to the negative input end and the output end of the operational amplifier And a second sampling capacitor, one end connected to the negative input terminal of the operational amplifier, the other end connected to the common reference voltage source by a fourth switch, or connected to the output end of the operational amplifier by a fifth switch. 如請求項1之感測電路，其中該放大級為多級放大器。 The sensing circuit of claim 1, wherein the amplification stage is a multi-stage amplifier. 如請求項6之感測電路，其中該多級放大器包含：差動放大級，根據該第一輸出電壓及該第二輸出電壓的差異產生 放大信號；以及阻抗轉換級，根據該放大信號產生該感測值。 The sensing circuit of claim 6, wherein the multi-stage amplifier comprises: a differential amplification stage, which is generated according to the difference between the first output voltage and the second output voltage Amplifying the signal; and an impedance conversion stage that generates the sensed value based on the amplified signal. 一種差動電容的感測方法，包含：(a)切換開關使該差動電容之兩端連接於高電壓源、低電壓源或是進行電荷轉移；(b)分次儲存該差動電容之一端的電荷於多個第一儲存電容的不同第一儲存電容中，產生第一輸出電壓；(c)分次儲存該差動電容之另一端的電荷於多個第二儲存電容的不同第二儲存電容中，產生第二輸出電壓；以及(d)根據該第一輸出電壓及該第二輸出電壓的差異產生感測值；其中，該(b)步驟包含並聯該多個第一儲存電容以產生該第一輸出電壓，該(c)步驟包含並聯該多個第二儲存電容以產生該第二輸出電壓。 A sensing method for a differential capacitor includes: (a) switching a switch to connect both ends of the differential capacitor to a high voltage source, a low voltage source, or performing charge transfer; and (b) storing the differential capacitor in stages The charge at one end is generated in a different first storage capacitor of the plurality of first storage capacitors to generate a first output voltage; (c) storing the charge at the other end of the differential capacitor in a second and second different storage capacitors a second output voltage is generated in the storage capacitor; and (d) generating a sensing value according to the difference between the first output voltage and the second output voltage; wherein the step (b) includes paralleling the plurality of first storage capacitors The first output voltage is generated, and the step (c) includes paralleling the plurality of second storage capacitors to generate the second output voltage. 如請求項8之感測方法，其中該(b)或(c)步驟包含：分次儲存電荷於不同第一階電容中；以及分次儲存該多個第一階電容並聯後的電荷於不同第二階電容中。 The sensing method of claim 8, wherein the step (b) or (c) comprises: storing the charges in different first-order capacitors in stages; and storing the charges in parallel after storing the plurality of first-order capacitors in parallel. In the second order capacitor. 如請求項8之感測方法，更包含儲存該第一輸出電壓及該第二輸出電壓的差異於至少一第三儲存電容中。 The sensing method of claim 8, further comprising storing the difference between the first output voltage and the second output voltage in the at least one third storage capacitor. 如請求項8之感測方法，其中該(d)步驟包含：重置第一取樣電容，並同時於運算放大器的負輸入端儲存該運算放大器的非理想誤差值於第二取樣電容中；利用該第一取樣電容對該第一輸出電壓取樣；以及再利用該第一取樣電容對該第二輸出電壓取樣，並使該第二取樣 電容連接於該運算放大器的負輸入端與輸出端之間，產生與該第一輸出電壓及該第二輸出電壓的差異相關的該感測值。 The sensing method of claim 8, wherein the step (d) comprises: resetting the first sampling capacitor, and simultaneously storing the non-ideal error value of the operational amplifier in the second sampling capacitor at a negative input end of the operational amplifier; The first sampling capacitor samples the first output voltage; and the second sampling voltage is further sampled by the first sampling capacitor, and the second sampling is performed A capacitor is coupled between the negative input terminal and the output terminal of the operational amplifier to generate the sensed value associated with the difference between the first output voltage and the second output voltage. 如請求項8之感測方法，其中該(d)步驟包含：根據該第一輸出電壓及該第二輸出電壓的差異產生放大信號；以及根據該放大信號產生該感測值。 The sensing method of claim 8, wherein the step (d) comprises: generating an amplified signal according to the difference between the first output voltage and the second output voltage; and generating the sensed value according to the amplified signal. 一種差動電容的感測電路，包含：第一感測端及第二感測端，連接該差動電容之兩端；切換電路，連接該第一感測端及該第二感測端，經由切換使該差動電容之兩端連接於高電壓源、低電壓源或是進行電荷轉移；電荷儲存電路，耦接該切換電路，配合該切換電路的切換，儲存該差動電容所轉移的電荷，包含：第一儲存電路，儲存該差動電容之一端的電荷於第一儲存電容中；第二儲存電路，儲存該差動電容之另一端的電荷於第二儲存電容中；以及第三儲存電路，包含多個第三儲存電容，其中每一該第三儲存電容之兩端分別連接於該第一儲存電路及第二儲存電路，分次將該第一儲存電路及第二儲存電路中的電荷儲存於該不同第三儲存電容中，並聯時於兩端產生第一輸出電壓及第二輸出電壓；以及放大級，根據該第一輸出電壓及該第二輸出電壓的差異產生感測值。 A sensing circuit for a differential capacitor includes: a first sensing end and a second sensing end connected to both ends of the differential capacitor; and a switching circuit connecting the first sensing end and the second sensing end, The two ends of the differential capacitor are connected to a high voltage source, a low voltage source or a charge transfer via a switch; the charge storage circuit is coupled to the switching circuit, and the switching of the switching circuit is performed to store the transferred by the differential capacitor. The electric charge includes: a first storage circuit storing the charge at one end of the differential capacitor in the first storage capacitor; a second storage circuit storing the charge at the other end of the differential capacitor in the second storage capacitor; and a third The storage circuit includes a plurality of third storage capacitors, wherein two ends of each of the third storage capacitors are respectively connected to the first storage circuit and the second storage circuit, and the first storage circuit and the second storage circuit are respectively divided into The charge is stored in the different third storage capacitors, and the first output voltage and the second output voltage are generated at both ends in parallel; and the amplification stage is generated according to the difference between the first output voltage and the second output voltage Sensing value. 如請求項13之感測電路，其中該切換電路包含： 第一開關對，連接該第一感測端，包含第一上下橋開關分別連接高電壓源及低電壓源；第二開關對，連接該第二感測端，包含第二上下橋開關分別連接高電壓源及低電壓源；第三開關對，連接該第一儲存電路，使該第一儲存電路連接於該第一感測端、第二感測端或同時連接，進行電荷轉移；以及第四開關對，連接該第二儲存電路，使該第二儲存電路連接於該第一感測端、第二感測端或同時連接，進行電荷轉移。 The sensing circuit of claim 13, wherein the switching circuit comprises: The first switch pair is connected to the first sensing end, and the first upper and lower bridge switches are respectively connected to the high voltage source and the low voltage source; the second switch pair is connected to the second sensing end, and the second upper and lower bridge switches are respectively connected a high voltage source and a low voltage source; a third switch pair connected to the first storage circuit, the first storage circuit being connected to the first sensing end, the second sensing end or simultaneously connected to perform charge transfer; The four switch pairs are connected to the second storage circuit, and the second storage circuit is connected to the first sensing end, the second sensing end or the same connection for charge transfer. 如請求項13之感測電路，其中該放大級包含：運算放大器，將其正輸入端連接共同參考電壓源；第一開關，用以輸入該第一輸出電壓；第二開關，用以輸入該第二輸出電壓；第一取樣電容，一端連接於該運算放大器之負輸入端，另一端連接該第一開關及該第二開關；第三開關，連接於該運算放大器之負輸入端及輸出端之間；以及第二取樣電容，一端連接於該運算放大器之負輸入端，另一端藉第四開關連接該共同參考電壓源，或藉第五開關連接該運算放大器之輸出端。 The sensing circuit of claim 13, wherein the amplification stage comprises: an operational amplifier having a positive input terminal connected to a common reference voltage source; a first switch for inputting the first output voltage; and a second switch for inputting the a second output voltage; a first sampling capacitor, one end is connected to the negative input end of the operational amplifier, the other end is connected to the first switch and the second switch; and the third switch is connected to the negative input end and the output end of the operational amplifier And a second sampling capacitor, one end connected to the negative input terminal of the operational amplifier, the other end connected to the common reference voltage source by a fourth switch, or connected to the output end of the operational amplifier by a fifth switch. 如請求項13之感測電路，其中該放大級為多級放大器。 The sensing circuit of claim 13, wherein the amplification stage is a multi-stage amplifier. 如請求項16之感測電路，其中該多級放大器包含：差動放大級，根據差異平均值產生放大信號；以及阻抗轉換級，根據該放大信號產生該感測值。 The sensing circuit of claim 16, wherein the multi-stage amplifier comprises: a differential amplification stage that generates an amplification signal according to a difference average value; and an impedance conversion stage that generates the sensing value according to the amplification signal. 一種差動電容的感測方法，包含：(a)切換開關使該差動電容之兩端連接於高電壓源、低電壓源或 是進行電荷轉移；(b)儲存該差動電容之一端的電荷於第一儲存電容中；(c)儲存該差動電容之另一端的電荷於第二儲存電容中；(d)分次將該第一儲存電容及第二儲存電容中的電荷儲存於不同第三儲存電容中，並聯時於兩端產生第一輸出電壓及第二輸出電壓；以及(e)根據該第一輸出電壓及該第二輸出電壓的差異產生感測值。 A sensing method for a differential capacitor, comprising: (a) switching a switch to connect both ends of the differential capacitor to a high voltage source, a low voltage source, or Carrying out charge transfer; (b) storing the charge at one end of the differential capacitor in the first storage capacitor; (c) storing the charge at the other end of the differential capacitor in the second storage capacitor; (d) The charges in the first storage capacitor and the second storage capacitor are stored in different third storage capacitors, and the first output voltage and the second output voltage are generated at both ends in parallel; and (e) according to the first output voltage and the The difference in the second output voltage produces a sensed value. 如請求項18之感測方法，其中該(e)步驟包含：重置第一取樣電容，並同時於運算放大器的負輸入端儲存該運算放大器的非理想誤差值於第二取樣電容中；利用該第一取樣電容對該第一輸出電壓取樣；以及再利用該第一取樣電容對該第二輸出電壓取樣，並使該第二取樣電容連接於該運算放大器的負輸入端與輸出端之間，產生與該第一輸出電壓及該第二輸出電壓的差異相關的該感測值。 The sensing method of claim 18, wherein the step (e) comprises: resetting the first sampling capacitor, and simultaneously storing the non-ideal error value of the operational amplifier in the second sampling capacitor at a negative input end of the operational amplifier; The first sampling capacitor samples the first output voltage; and the second sampling voltage is further sampled by the first sampling capacitor, and the second sampling capacitor is connected between the negative input terminal and the output terminal of the operational amplifier And generating the sensed value associated with the difference between the first output voltage and the second output voltage. 如請求項18之感測方法，其中該(e)步驟包含：根據該第一輸出電壓及該第二輸出電壓的差異產生放大信號；以及根據該放大信號產生該感測值。 The sensing method of claim 18, wherein the step (e) comprises: generating an amplified signal according to the difference between the first output voltage and the second output voltage; and generating the sensed value according to the amplified signal.
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