TWI489601B - Electronic device packaging structure - Google Patents

Electronic device packaging structure Download PDF

Info

Publication number
TWI489601B
TWI489601B TW100147205A TW100147205A TWI489601B TW I489601 B TWI489601 B TW I489601B TW 100147205 A TW100147205 A TW 100147205A TW 100147205 A TW100147205 A TW 100147205A TW I489601 B TWI489601 B TW I489601B
Authority
TW
Taiwan
Prior art keywords
region
conductive type
electronic component
package structure
component package
Prior art date
Application number
TW100147205A
Other languages
Chinese (zh)
Other versions
TW201246479A (en
Inventor
Ra Min Tain
Ming Ji Dai
John H Lau
Original Assignee
Ind Tech Res Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to US13/411,639 priority Critical patent/US8536701B2/en
Publication of TW201246479A publication Critical patent/TW201246479A/en
Application granted granted Critical
Publication of TWI489601B publication Critical patent/TWI489601B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Bipolar Transistors (AREA)

Description

電子元件封裝結構Electronic component package structure

本發明是有關於一種積體電路，且特別是有關於一種電子元件封裝結構。The present invention relates to an integrated circuit, and more particularly to an electronic component package structure.

傳統的功率元件是採上下電極結構分別設置在晶片的兩個表面上。由於功率晶片的耗能極高，尤其是應用於電動車的功率晶片，多在千瓦等級以上，所以散熱是一大挑戰。現在使用的功率模組還是屬傳統的功率元件是採上下電極的結構，這樣的結構在封裝上同時要使用打線及焊接方式完成模組封裝，其製程步驟較為複雜且其封裝設備成本又相當高。Conventional power components are provided with upper and lower electrode structures respectively disposed on both surfaces of the wafer. Since the power consumption of power chips is extremely high, especially for power chips used in electric vehicles, it is more than kilowatts, so heat dissipation is a big challenge. The power module currently used is still a traditional power component that adopts the structure of the upper and lower electrodes. Such a structure requires the wire bonding and the soldering method to complete the module packaging on the package, and the process steps are complicated and the packaging equipment cost is relatively high. .

本發明提供一種電子元件封裝結構可以利用簡單的方式完成封裝，且具有較多的散熱面積，以提升散熱效能，增加可靠度。The invention provides an electronic component packaging structure that can be packaged in a simple manner and has more heat dissipation area to improve heat dissipation performance and increase reliability.

本發明提出一種電子元件封裝結構，包括半導體元件、第一保護層、第一導體銲墊、第二導體銲墊以及至少一導通結構。半導體元件包括半導體基極、第一導電型基體區、第二導電型摻雜區、第一介電層、第二介電層、射極、集極以及閘極。半導體基極具有第一表面與第二表面，第一表面與第二表面相對。集極位於半導體基極的第二表 面上。第一導電型基體區位於半導體基極之第一表面上。第二導電型摻雜區位於第一導電型基體區中。閘極位於半導體基極的第一表面上，覆蓋部分該第一導電型基體區與部分該第二導電型摻雜區，且閘極以第一介電層與半導體基極的第一表面、第一導電型基體區與第二導電型摻雜區相隔絕。第二介電層覆蓋閘極，第二介電層中具有開口，且開口貫穿第二導電型摻雜區，而延伸至開口的底部裸露出第一導電型基體區。射極位於半導體基極的第二介電層上，並且填充於開口中，電性連接第二導電型摻雜區與第一導電型基體區。第一保護層位於閘極周圍的半導體基極的第一表面上。第一導體銲墊位於第一保護層上。第二導體銲墊位於半導體基極的第二表面上的集極上方。上述導通結構貫穿第一保護層、導體基極的第一表面與第二表面以及集極。導通結構包括導體柱與第二保護層。導體柱電性連接第一導體銲墊與第二導體銲墊。第二保護層位於導體柱與半導體基極之間。The present invention provides an electronic component package structure including a semiconductor component, a first protective layer, a first conductor pad, a second conductor pad, and at least one via structure. The semiconductor component includes a semiconductor base, a first conductive type substrate region, a second conductive type doped region, a first dielectric layer, a second dielectric layer, an emitter, a collector, and a gate. The semiconductor base has a first surface and a second surface, the first surface being opposite the second surface. The second table with the collector at the base of the semiconductor On the surface. The first conductivity type substrate region is on the first surface of the semiconductor base. The second conductive type doped region is located in the first conductive type base region. The gate is located on the first surface of the semiconductor base, covering a portion of the first conductive type substrate region and a portion of the second conductive type doped region, and the gate is a first dielectric layer and a first surface of the semiconductor base, The first conductive type substrate region is isolated from the second conductive type doped region. The second dielectric layer covers the gate, the second dielectric layer has an opening therein, and the opening penetrates the second conductive type doped region, and the bottom portion of the opening extends to expose the first conductive type substrate region. The emitter is located on the second dielectric layer of the semiconductor base and is filled in the opening to electrically connect the second conductive type doped region and the first conductive type base region. A first protective layer is on the first surface of the semiconductor base surrounding the gate. The first conductor pad is located on the first protective layer. A second conductor pad is over the collector on the second surface of the semiconductor base. The conductive structure penetrates through the first protective layer, the first surface and the second surface of the conductor base, and the collector. The conductive structure includes a conductor post and a second protective layer. The conductor post is electrically connected to the first conductor pad and the second conductor pad. The second protective layer is between the conductor post and the semiconductor base.

本發明又提出一種電子元件封裝結構，包括：半導體元件、保護層與導體銲墊。半導體元件包括半導體基極、第一導電型基體區、第二導電型摻雜區、第一介電層、第二介電層、射極、集極以及閘極。半導體基極的第一表面上包括第一區、第二區與第三區，第三區位於第一區與第二區之間。集極位於半導體基極的第二區上。第一導電型基體區位於半導體基極之第一表面上。第二導電型摻雜區位於第一導電型基體區中。閘極位於半導體基極的第一區 上方，覆蓋部分該第一導電型基體區與部分該第二導電型摻雜區。閘極以第一介電層與半導體基極的第一表面、第一導電型基體區與第二導電型摻雜區相隔絕。第二介電層覆蓋閘極，第二介電層中具有開口，且開口貫穿第二導電型摻雜區，而延伸至開口的底部裸露出第一導電型基體區。射極位於半導體基極的第二介電層上，並且填充於開口中，電性連接第二導電型摻雜區與第一導電型基體區。保護層位於第三區上。導體銲墊位於集極上。The invention further provides an electronic component package structure comprising: a semiconductor component, a protective layer and a conductor pad. The semiconductor component includes a semiconductor base, a first conductive type substrate region, a second conductive type doped region, a first dielectric layer, a second dielectric layer, an emitter, a collector, and a gate. The first surface of the semiconductor base includes a first region, a second region, and a third region, and the third region is located between the first region and the second region. The collector is located on the second region of the semiconductor base. The first conductivity type substrate region is on the first surface of the semiconductor base. The second conductive type doped region is located in the first conductive type base region. The gate is located in the first region of the semiconductor base Upper portion covers the first conductive type substrate region and a portion of the second conductive type doped region. The gate is separated from the first surface of the semiconductor base, the first conductive type substrate region, and the second conductive type doped region by the first dielectric layer. The second dielectric layer covers the gate, the second dielectric layer has an opening therein, and the opening penetrates the second conductive type doped region, and the bottom portion of the opening extends to expose the first conductive type substrate region. The emitter is located on the second dielectric layer of the semiconductor base and is filled in the opening to electrically connect the second conductive type doped region and the first conductive type base region. The protective layer is located on the third zone. The conductor pads are located on the collector.

基於上述，本發明之電子元件封裝結構可以利用打線或是銲接方式完成封裝，且具有較多的散熱面積，以提升散熱效能，增加可靠度。Based on the above, the electronic component package structure of the present invention can be packaged by wire bonding or soldering, and has more heat dissipation area to improve heat dissipation performance and increase reliability.

為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

圖1是依照本發明第一實施例所繪示的一種電子元件封裝結構的剖面示意圖。1 is a cross-sectional view showing an electronic component package structure according to a first embodiment of the present invention.

請參照圖1，電子元件封裝結構10a包括半導體元件14、第一保護層16、第一導體銲墊18、第二導體銲墊20、至少一導通結構22、第一凸塊24與第二凸塊26。Referring to FIG. 1 , the electronic component package structure 10 a includes a semiconductor component 14 , a first protective layer 16 , a first conductive pad 18 , a second conductive pad 20 , at least one conductive structure 22 , first bumps 24 and second bumps . Block 26.

半導體元件14包括半導體基極12、射極28、集極30以及閘極32。半導體基極(base)12具有第一表面12a與第二表面12b，第一表面12a與第二表面12b相對。半導體基極12的材料可以是IV族元素、IV-IV族半導體化合物 或III-V族半導體化合物。半導體基極12的材料例如是矽、GaN或SiC。半導體基極12例如是具有第二導電型摻雜的磊晶矽。射極28位於半導體基極12的第一表面12a上。集極30位於半導體基極12的第二表面12b上。The semiconductor component 14 includes a semiconductor base 12, an emitter 28, a collector 30, and a gate 32. The semiconductor base 12 has a first surface 12a and a second surface 12b, the first surface 12a being opposite the second surface 12b. The material of the semiconductor base 12 may be a group IV element or a group IV-IV semiconductor compound. Or a III-V semiconductor compound. The material of the semiconductor base 12 is, for example, germanium, GaN or SiC. The semiconductor base 12 is, for example, an epitaxial germanium having a second conductivity type doping. The emitter 28 is located on the first surface 12a of the semiconductor base 12. The collector 30 is located on the second surface 12b of the semiconductor base 12.

閘極32位於半導體基極12的第一表面12a上，且位於半導體基極12與射極28之間。閘極32以第一介電層34與半導體基極12的第一表面12a相隔絕，且閘極32以第二介電層36與射極28相隔絕。第一介電層34例如是二氧化矽(SiO2 )、氮化矽(Si3 N4 )或氮化鋁(AlN)。第一介電層34的厚度例如是5000埃至20000埃。第二介電層36的材料可以與第一介電層34的材料相同或相異。第二介電層36之材料例如是二氧化矽、氮化矽或氮化鋁。第二介電層36的厚度例如是5000埃至20000埃。The gate 32 is located on the first surface 12a of the semiconductor base 12 and between the semiconductor base 12 and the emitter 28. The gate 32 is isolated from the first surface 12a of the semiconductor base 12 by a first dielectric layer 34, and the gate 32 is isolated from the emitter 28 by a second dielectric layer 36. The first dielectric layer 34 is, for example, hafnium oxide (SiO 2 ), tantalum nitride (Si 3 N 4 ), or aluminum nitride (AlN). The thickness of the first dielectric layer 34 is, for example, 5000 angstroms to 20,000 angstroms. The material of the second dielectric layer 36 may be the same as or different from the material of the first dielectric layer 34. The material of the second dielectric layer 36 is, for example, hafnium oxide, tantalum nitride or aluminum nitride. The thickness of the second dielectric layer 36 is, for example, 5,000 angstroms to 20,000 angstroms.

射極28之材料可以是金屬，例如是鋁、銅或金。集極30的材料例如是具有第一導電型摻雜的磊晶矽。閘極32的材料例如是具有第二導電型摻雜的多晶矽。在一實施例中，本說明書實施例所述的第一導電型/第二導電型例如是P型/N型。在另一實施例中，本說明書實施例所述的第一導電型/第二導電型例如是N型/P型。P型摻雜例如是磷、砷或是銻。N型摻雜例如是硼、銦或鎵。The material of the emitter 28 can be a metal such as aluminum, copper or gold. The material of the collector 30 is, for example, an epitaxial germanium having a first conductivity type doping. The material of the gate 32 is, for example, a polysilicon having a second conductivity type doping. In an embodiment, the first conductivity type/second conductivity type described in the embodiments of the present specification is, for example, a P type/N type. In another embodiment, the first conductivity type/second conductivity type described in the embodiments of the present specification is, for example, an N type/P type. The P-type doping is, for example, phosphorus, arsenic or antimony. The N-type doping is, for example, boron, indium or gallium.

在一實施例中，半導體元件14還包括第一導電型基體區40以及第二導電型摻雜區42。第一導電型基體區40位於半導體基極12的第一表面12a中。閘極32會覆蓋部分第一導電型基體區40與部分第二導電型摻雜區42，且 以第一介電層34與半導體基極12的第一表面12a、第一導電型基體區40與第二導電型摻雜區42相隔絕。此外，半導體元件14還具有開口38，其位於第二介電層36中，且貫穿第二導電型摻雜區42，而延伸至開口38的底部以裸露出第一導電型基體區40。開口38的深度例如是20000埃至40000埃。In an embodiment, the semiconductor component 14 further includes a first conductive type substrate region 40 and a second conductive type doped region 42. The first conductive type substrate region 40 is located in the first surface 12a of the semiconductor base 12. The gate 32 covers a portion of the first conductive type substrate region 40 and a portion of the second conductive type doped region 42, and The first dielectric layer 34 is isolated from the first surface 12a of the semiconductor base 12, the first conductive type substrate region 40, and the second conductive type doped region 42. In addition, the semiconductor component 14 also has an opening 38 that is located in the second dielectric layer 36 and extends through the second conductive type doped region 42 and extends to the bottom of the opening 38 to expose the first conductive type substrate region 40. The depth of the opening 38 is, for example, 20,000 angstroms to 40,000 angstroms.

在第一導電型基體區40與第二導電型掺雜區42及半導體基極12之第一表面12a上依序設置有第一介電層34、閘極32、第二介電層36。其中第一導電型基體區40、第二導電型掺雜區42、第二介電層36中即設置開口38，使射極28可以T字型形狀設置且形成在開口38內，並使射極28分別與開口38底部的第一導電型基體區40、開口38側壁的第二導電型掺雜區42以及第二介電層36直接接觸。A first dielectric layer 34, a gate 32, and a second dielectric layer 36 are sequentially disposed on the first conductive type substrate region 40, the second conductive type doping region 42, and the first surface 12a of the semiconductor base 12. An opening 38 is disposed in the first conductive type substrate region 40, the second conductive type doped region 42, and the second dielectric layer 36, so that the emitter 28 can be disposed in a T-shape and formed in the opening 38, and is caused to be shot. The poles 28 are in direct contact with the first conductive type substrate region 40 at the bottom of the opening 38, the second conductive type doped region 42 of the sidewall of the opening 38, and the second dielectric layer 36, respectively.

第一保護層16設置於閘極32周圍的半導體基極12的第一表面12a上且與第一介電層34連接。第一保護層16之材質可以是介電材料，例如是二氧化矽、氮化矽或氮化鋁。第一保護層16的厚度例如是5000埃至20000埃。The first protective layer 16 is disposed on the first surface 12a of the semiconductor base 12 around the gate 32 and is connected to the first dielectric layer 34. The material of the first protective layer 16 may be a dielectric material such as hafnium oxide, tantalum nitride or aluminum nitride. The thickness of the first protective layer 16 is, for example, 5000 Å to 20,000 Å.

第一導體銲墊18位於半導體基極12的第一表面12a上方的第一保護層16上。第一導體銲墊18包括凸塊下金屬層(UBM)，其材料例如是鎳或金。第二導體銲墊20位於半導體基極12的第二表面12b的集極30上。第二導體銲墊20材料包括金屬或是金屬合金，例如是銅或是鋁。The first conductor pad 18 is located on the first protective layer 16 above the first surface 12a of the semiconductor base 12. The first conductor pad 18 includes a sub-bump metal layer (UBM) of a material such as nickel or gold. The second conductor pad 20 is located on the collector 30 of the second surface 12b of the semiconductor base 12. The second conductor pad 20 material comprises a metal or a metal alloy such as copper or aluminum.

導通結構22位於導通孔19之中，導通孔19貫穿第 一保護層16、半導體基極12的第一表面12a、第二表面12b以及集極30。導通結構22包括導體柱21以及第二保護層17。導體柱21貫穿第一保護層16且分別電性連接第一導體銲墊18與第二導體銲墊20。導體柱21之材料包括金屬或是金屬合金，例如是銅、鎢或鋁或其合金。其中導通結構22與導通孔19可為一或多數個，在圖式中以兩個來表示，但本發明並不以此為限。第二保護層17位於導體柱21與半導體基極12之間。第二保護層17的材料可以與第一保護層16的材料相同或相異。第二保護層17之材料可以是介電材料，例如是二氧化矽、氮化矽或氮化鋁。第二保護層17的厚度例如是5000埃至20000埃。The conductive structure 22 is located in the via hole 19, and the via hole 19 penetrates through the A protective layer 16, a first surface 12a of the semiconductor base 12, a second surface 12b, and a collector 30. The conductive structure 22 includes a conductor post 21 and a second protective layer 17. The conductor post 21 penetrates the first protective layer 16 and is electrically connected to the first conductor pad 18 and the second conductor pad 20, respectively. The material of the conductor post 21 includes a metal or a metal alloy such as copper, tungsten or aluminum or an alloy thereof. The conductive structure 22 and the via 19 may be one or more, and are represented by two in the drawings, but the invention is not limited thereto. The second protective layer 17 is located between the conductor post 21 and the semiconductor base 12. The material of the second protective layer 17 may be the same as or different from the material of the first protective layer 16. The material of the second protective layer 17 may be a dielectric material such as hafnium oxide, tantalum nitride or aluminum nitride. The thickness of the second protective layer 17 is, for example, 5,000 angstroms to 20,000 angstroms.

第一凸塊24設置在第一導體銲墊18上且與其電性連接。第二凸塊26設置在射極28上且與其電性連接。第一凸塊24與第二凸塊26之材質可以是金屬或是金屬合金，例如是金凸塊(Gold bump)、錫鉛凸塊(Solder bump)及銅凸塊(Copper bump)。The first bump 24 is disposed on the first conductor pad 18 and electrically connected thereto. The second bump 26 is disposed on the emitter 28 and electrically connected thereto. The material of the first bump 24 and the second bump 26 may be a metal or a metal alloy, such as a gold bump, a solder bump, and a copper bump.

上述電子元件封裝結構10a可以更包括散熱片(heatsink)50。散熱片50可以設置於第二導體銲墊20的一側。散熱片50之材料可以是金屬或是絕緣材料。若是散熱片50的材料為金屬，在第二導體銲墊20與散熱片50之間可以以導熱膠60連接。若是散熱片50的材料為絕緣材料，例如是陶瓷或是高散熱有機材料，則散熱片50可以與第二導體銲墊20直接接觸。The above electronic component package structure 10a may further include a heatsink 50. The heat sink 50 may be disposed on one side of the second conductor pad 20. The material of the heat sink 50 may be metal or an insulating material. If the material of the heat sink 50 is metal, the second conductive pad 20 and the heat sink 50 may be connected by a heat conductive adhesive 60. If the material of the heat sink 50 is an insulating material, such as ceramic or a highly heat-dissipating organic material, the heat sink 50 may be in direct contact with the second conductor pad 20.

圖2是依照本發明第二實施例所繪示的一種電子元件封裝結構的剖面示意圖。2 is a cross-sectional view showing an electronic component package structure according to a second embodiment of the present invention.

請參照圖2，本實施例之電子元件封裝結構10b之構件與上述第一實施例之電子元件封裝結構10a非常相似，其同樣包括半導體元件14、第一保護層16、第二保護層17、第一導體銲墊18、第二導體銲墊20、至少一導通結構22。電子元件封裝結構10b也可以再包括散熱片50。電子元件封裝結構10b與電子元件封裝結構10a不同處在於：第一導體銲線(conductive bond wire)44與第二導體銲線46分別取代第一凸塊24與第二凸塊26。第一導體銲線44，與導體銲墊18電性連接。第二導體銲線46與射極28電性連接。第一導體銲線(conductive bond wire)44與第二導體銲線46的材料包括金屬或是金屬合金，例如是金、鋁或銅。Referring to FIG. 2, the components of the electronic component package structure 10b of the present embodiment are very similar to the electronic component package structure 10a of the first embodiment described above, and also include the semiconductor component 14, the first protective layer 16, and the second protective layer 17, The first conductor pad 18, the second conductor pad 20, and at least one conductive structure 22. The electronic component package structure 10b may further include a heat sink 50. The electronic component package structure 10b is different from the electronic component package structure 10a in that a first conductive bond wire 44 and a second conductor bond wire 46 replace the first bump 24 and the second bump 26, respectively. The first conductor bond wire 44 is electrically connected to the conductor pad 18. The second conductor bond wire 46 is electrically connected to the emitter 28. The material of the first conductive bond wire 44 and the second conductor bond wire 46 includes a metal or a metal alloy such as gold, aluminum or copper.

圖3是依照本發明第三實施例所繪示的一種電子元件封裝結構的剖面示意圖。3 is a cross-sectional view showing an electronic component package structure according to a third embodiment of the present invention.

請參照圖3，本發明又提出一種電子元件封裝結構110a，包括：半導體元件114、保護層116、導體銲墊118、第一凸塊124與第二凸塊126。Referring to FIG. 3, the present invention further provides an electronic component package structure 110a, including: a semiconductor component 114, a protective layer 116, a conductor pad 118, a first bump 124, and a second bump 126.

半導體元件114包括半導體基極112、射極128、集極130以及閘極132。半導體基極112位於基底100上。基底100例如是矽晶圓。半導體基極112的第一表面112a上包括第一區150、第二區152與第三區154，其中第三區154位於第一區150與第二區152之間。射極128位於半導體基極112的第一表面112a的第一區150上。集極130 位於半導體基極112的第一表面112a的第二區152上。閘極132位於半導體基極112的第一表面112a的第一區150上。閘極132以第一介電層134與半導體基極112的第一表面112a相隔絕，且閘極132以第二介電層136與射極128相隔絕。The semiconductor component 114 includes a semiconductor base 112, an emitter 128, a collector 130, and a gate 132. The semiconductor base 112 is located on the substrate 100. The substrate 100 is, for example, a germanium wafer. The first surface 112a of the semiconductor base 112 includes a first region 150, a second region 152 and a third region 154, wherein the third region 154 is located between the first region 150 and the second region 152. The emitter 128 is located on the first region 150 of the first surface 112a of the semiconductor base 112. Collector 130 Located on the second region 152 of the first surface 112a of the semiconductor base 112. Gate 132 is located on first region 150 of first surface 112a of semiconductor base 112. The gate 132 is isolated from the first surface 112a of the semiconductor base 112 by a first dielectric layer 134, and the gate 132 is isolated from the emitter 128 by a second dielectric layer 136.

在一實施例中，半導體元件114還包括第一導電型基體區140以及第二導電型摻雜區142。第一導電型基體區140位於半導體基極112的第一表面12a的第一區150中。閘極132會覆蓋部分第一導電型基體區140與部分第二導電型摻雜區142，且以第一介電層134與半導體基極112的第一表面112a、第一導電型基體區140與第二導電型摻雜區142相隔絕。此外，半導體元件114還具有開口138，其位於第二介電層136中，且貫穿第二導電型摻雜區142，而延伸至開口138的底部以裸露出第一導電型基體區140。開口138的深度例如是20000埃至40000埃。In an embodiment, the semiconductor component 114 further includes a first conductive type substrate region 140 and a second conductive type doped region 142. The first conductivity type substrate region 140 is located in the first region 150 of the first surface 12a of the semiconductor base 112. The gate 132 covers a portion of the first conductive type substrate region 140 and a portion of the second conductive type doped region 142, and the first dielectric layer 134 and the first surface 112a of the semiconductor base 112 and the first conductive type substrate region 140 Isolated from the second conductivity type doping region 142. In addition, the semiconductor device 114 also has an opening 138 that is located in the second dielectric layer 136 and extends through the second conductive type doped region 142 and extends to the bottom of the opening 138 to expose the first conductive type substrate region 140. The depth of the opening 138 is, for example, 20,000 angstroms to 40,000 angstroms.

換言之，在第一導電型基體區140與第二導電型摻雜區142及半導體基極112之第一表面112a上依序設置有第一介電層134、閘極132、第二介電層136。其中第一導電型基體區140、第二導電型摻雜區142、第二介電層136中即設置開口138，使射極128可以T字型形狀設置且形成在開口138內，並使射極128分別與第一導電型基體區140、第二導電型摻雜區142第二介電層136直接接觸。In other words, a first dielectric layer 134, a gate 132, and a second dielectric layer are sequentially disposed on the first conductive type substrate region 140 and the first conductive type doped region 142 and the first surface 112a of the semiconductor base 112. 136. An opening 138 is disposed in the first conductive type substrate region 140, the second conductive type doped region 142, and the second dielectric layer 136, so that the emitter 128 can be disposed in a T-shape and formed in the opening 138, and is formed. The poles 128 are in direct contact with the first conductive type substrate region 140 and the second conductive type doped region 142, respectively, of the second dielectric layer 136.

保護層116位於第一表面112a的第三區154上，與第一介電層134連接。保護層116之材料包括二氧化矽、 氮化矽或氮化鋁。The protective layer 116 is located on the third region 154 of the first surface 112a and is connected to the first dielectric layer 134. The material of the protective layer 116 includes cerium oxide, Tantalum nitride or aluminum nitride.

導體銲墊118位於集極130上。導體銲墊118包括凸塊下金屬層(UBM)，其材料例如是鎳或金，或其合金。Conductor pads 118 are located on collector 130. The conductor pad 118 includes a sub-bump metal layer (UBM) of a material such as nickel or gold, or an alloy thereof.

第一凸塊124設置於導體銲墊118上且與其電性連接。第二凸塊126設置於射極128上且與其電性連接。The first bump 124 is disposed on the conductive pad 118 and electrically connected thereto. The second bump 126 is disposed on the emitter 128 and electrically connected thereto.

本實施例之半導體元件114的半導體基極112、射極128、集極130以及閘極132、保護層116、導體銲墊118、第一凸塊124和第二凸塊126的材料，可以採用上述實施例之半導體元件14的半導體基極12、射極28、集極30以及閘極32、保護層16、導體銲墊18、第一凸塊24和第二凸塊26的材料，於此不再贅述。The material of the semiconductor base 112, the emitter 128, the collector 130, and the gate 132, the protective layer 116, the conductor pad 118, the first bump 124, and the second bump 126 of the semiconductor device 114 of the present embodiment may be The semiconductor base 12, the emitter 28, the collector 30 and the gate 32, the protective layer 16, the conductor pad 18, the first bump 24, and the second bump 26 of the semiconductor device 14 of the above embodiment are as follows. No longer.

此外，上述電子元件封裝結構110a可以更包括散熱片170。散熱片170可以設置於基底100的表面100a上。若是散熱片170的材料為金屬，在基底100與散熱片170之間可以以導熱膠160連接。若是散熱片170的材料為絕緣材料，例如是陶瓷或是高散熱有機材料，則散熱片170可以與基底100的表面100a直接接觸。In addition, the above electronic component package structure 110a may further include a heat sink 170. The heat sink 170 may be disposed on the surface 100a of the substrate 100. If the material of the heat sink 170 is metal, the heat conductive adhesive 160 may be connected between the substrate 100 and the heat sink 170. If the material of the heat sink 170 is an insulating material such as ceramic or a highly heat-dissipating organic material, the heat sink 170 may be in direct contact with the surface 100a of the substrate 100.

圖4是依照本發明第四實施例所繪示的一種電子元件封裝結構的剖面示意圖。4 is a cross-sectional view showing an electronic component package structure according to a fourth embodiment of the present invention.

請參照圖4，本實施例之電子元件封裝結構110b之構件與上述第三實施例之電子元件封裝結構110a非常相似，其同樣包括半導體元件114、保護層116、第一導體銲墊118。電子元件封裝結構110b也可以再包括散熱片170。 電子元件封裝結構110b與電子元件封裝結構110a不同處在於：第一導體銲線144與第二導體銲線146分別取代第一凸塊124與第二凸塊126。第一導體銲線144，與導體銲墊118電性連接。第二導體銲線146與射極128電性連接。第一導體銲線144與第二導體銲線146的材料例如是金、鋁或銅。Referring to FIG. 4, the components of the electronic component package structure 110b of the present embodiment are very similar to the electronic component package structure 110a of the third embodiment described above, and also include the semiconductor component 114, the protective layer 116, and the first conductor pad 118. The electronic component package structure 110b may further include a heat sink 170. The electronic component package structure 110b is different from the electronic component package structure 110a in that the first conductor bonding wire 144 and the second conductor bonding wire 146 replace the first bump 124 and the second bump 126, respectively. The first conductor bond wire 144 is electrically connected to the conductor pad 118. The second conductor bond wire 146 is electrically connected to the emitter 128. The material of the first conductor bonding wire 144 and the second conductor bonding wire 146 is, for example, gold, aluminum or copper.

本發明改變習知上下電極結構的封裝方式，利用貫穿半導體基極兩個表面的導通結構(TSV)結構，或是將半導體元件的電極設置在晶片的同一面，可以覆晶方式將功率晶片設置在基底上。晶片未設置電極的另一面可以與散熱片連接，使其具有較多散熱設計。與習知的功率模組比較，習知是在晶片的上端以打線方式封裝且用矽膠方式來密封，完全僅以基底底面來散熱，而本發明的結構則有較多的散熱面積，可以提升晶片的可靠度。The invention changes the conventional packaging method of the upper and lower electrode structures, and the power semiconductor wafer can be set in a flip chip manner by using a conductive structure (TSV) structure penetrating the two surfaces of the semiconductor base or by disposing the electrodes of the semiconductor element on the same side of the wafer. On the substrate. The other side of the wafer where no electrodes are provided can be connected to the heat sink to provide more heat dissipation design. Compared with the conventional power module, it is known that the upper end of the wafer is packaged in a wire-bonding manner and sealed by a silicone method, and only the bottom surface of the substrate is used for heat dissipation, and the structure of the present invention has more heat dissipation area, which can be improved. The reliability of the wafer.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10a、10b、110a、110b‧‧‧電子元件封裝結構10a, 10b, 110a, 110b‧‧‧ electronic component package structure

12、112‧‧‧半導體基極12, 112‧‧‧ semiconductor base

12a‧‧‧第一表面12a‧‧‧ first surface

12b‧‧‧第二表面12b‧‧‧ second surface

14、114‧‧‧半導體元件14, 114‧‧‧ semiconductor components

16‧‧‧第一保護層16‧‧‧First protective layer

17‧‧‧第二保護層17‧‧‧Second protective layer

18‧‧‧第一導體銲墊18‧‧‧First Conductor Pad

19‧‧‧導通孔19‧‧‧through holes

20‧‧‧第二導體銲墊20‧‧‧Second conductor pad

21‧‧‧導體柱21‧‧‧Conductor column

22‧‧‧導通結構22‧‧‧Connected structure

24、124‧‧‧第一凸塊24, 124‧‧‧ first bump

26、126‧‧‧第二凸塊26, 126‧‧‧ second bump

28、128‧‧‧射極28, 128‧‧ ‧ emitter

30、130‧‧‧集極30, 130‧‧ ‧ collector

32、132‧‧‧閘極32, 132‧‧‧ gate

34、134‧‧‧第一介電層34, 134‧‧‧ first dielectric layer

36、136‧‧‧第二介電層36, 136‧‧‧ second dielectric layer

38、138‧‧‧開口38, 138‧‧‧ openings

40、140‧‧‧第一導電型基體區40, 140‧‧‧First Conductive Matrix Area

42、142‧‧‧第二導電型摻雜區42, 142‧‧‧Second conductive doped region

44、144‧‧‧第一導體銲線44, 144‧‧‧ first conductor wire

46、146‧‧‧第二導體銲線46, 146‧‧‧ second conductor wire

50、170‧‧‧散熱片50, 170‧‧ ‧ heat sink

60、160‧‧‧導熱膠60,160‧‧‧thermal adhesive

100‧‧‧基底100‧‧‧Base

100a、112a‧‧‧表面100a, 112a‧‧‧ surface

116‧‧‧保護層116‧‧‧Protective layer

118‧‧‧導體銲墊118‧‧‧Conductor pads

150‧‧‧第一區150‧‧‧First District

152‧‧‧第二區152‧‧‧Second District

154‧‧‧第三區154‧‧‧ Third District

圖1是依照本發明第一實施例所繪示的一種電子元件封裝結構的剖面示意圖。1 is a cross-sectional view showing an electronic component package structure according to a first embodiment of the present invention.

圖2是依照本發明第二實施例所繪示的一種電子元件封裝結構的剖面示意圖。2 is a cross-sectional view showing an electronic component package structure according to a second embodiment of the present invention.

圖3是依照本發明第三實施例所繪示的一種電子元件封裝結構的剖面示意圖。3 is a cross-sectional view showing an electronic component package structure according to a third embodiment of the present invention.

圖4是依照本發明第四實施例所繪示的一種電子元件封裝結構的剖面示意圖。4 is a cross-sectional view showing an electronic component package structure according to a fourth embodiment of the present invention.

10a‧‧‧電子元件封裝結構10a‧‧‧Electronic component package structure

12‧‧‧半導體基極12‧‧‧Semiconductor base

12a‧‧‧上表面12a‧‧‧Upper surface

12b‧‧‧下表面12b‧‧‧ lower surface

14‧‧‧半導體元件14‧‧‧Semiconductor components

16‧‧‧第一保護層16‧‧‧First protective layer

17‧‧‧第二保護層17‧‧‧Second protective layer

18‧‧‧第一導體銲墊18‧‧‧First Conductor Pad

19‧‧‧導通孔19‧‧‧through holes

20‧‧‧第二導體銲墊20‧‧‧Second conductor pad

21‧‧‧導體柱21‧‧‧Conductor column

22‧‧‧導通結構22‧‧‧Connected structure

24‧‧‧第一凸塊24‧‧‧First bump

26‧‧‧第二凸塊26‧‧‧second bump

28‧‧‧射極28‧‧ ‧shoot

30‧‧‧集極30‧‧ ‧ Collector

32‧‧‧閘極32‧‧‧ gate

34‧‧‧第一介電層34‧‧‧First dielectric layer

36‧‧‧第二介電層36‧‧‧Second dielectric layer

38‧‧‧開口38‧‧‧ openings

40‧‧‧第一導電型基體區40‧‧‧First Conductive Matrix Area

42‧‧‧第二導電型摻雜區42‧‧‧Second Conductive Doped Area

50‧‧‧散熱片50‧‧‧ Heat sink

60‧‧‧導熱膠60‧‧‧thermal adhesive

Claims (21)

一種電子元件封裝結構，包括：一半導體元件，包括：一半導體基極具有一第一表面與一第二表面，該第一表面與該第二表面相對；一集極位於該半導體基極的該第二表面上；一第一導電型基體區，位於該半導體基極之該第一表面中；一第二導電型摻雜區，位於該第一導電型基體區中；一閘極位於該半導體基極的該第一表面上，覆蓋部分該第一導電型基體區與部分該第二導電型摻雜區，且該閘極以一第一介電層與該半導體基極的該第一表面、該第一導電型基體區與該第二導電型摻雜區相隔絕；一第二介電層覆蓋該閘極，該第二介電層中具有一開口，且該開口貫穿該第二導電型摻雜區，而延伸至該開口的底部以裸露出該第一導電型基體區；以及一射極位於該半導體基極的該第二介電層上，並且填充於該開口中，電性連接該第二導電型摻雜區與該第一導電型基體區；一第一保護層，位於該閘極周圍的該半導體基極的該第一表面上，且與該第一介電層連接；一第一導體銲墊，位於該第一保護層上；一第二導體銲墊，位於該半導體基極的該第二表面上方的該集極上；以及至少一導通結構，貫穿該第一保護層、該半導體基極的該第一表面、該第二表面以及該集極，且電性連接該第一導體銲墊與該第二導體銲墊，該導通結構包括：一導體柱，位於該半導體基極之中；以及一第二保護層，位於該導體柱與該半導體基極之間。An electronic component package structure comprising: a semiconductor component, comprising: a semiconductor base having a first surface and a second surface, the first surface being opposite to the second surface; a collector located at the semiconductor base a second surface of the first conductive type; the first conductive type substrate region is located in the first surface of the semiconductor base; a second conductive type doped region is located in the first conductive type substrate region; and a gate is located at the semiconductor The first surface of the base portion covers a portion of the first conductive type substrate region and a portion of the second conductive type doped region, and the gate has a first dielectric layer and the first surface of the semiconductor base The first conductive type substrate region is isolated from the second conductive type doped region; a second dielectric layer covers the gate, the second dielectric layer has an opening therein, and the opening extends through the second conductive a doped region extending to the bottom of the opening to expose the first conductive type substrate region; and an emitter located on the second dielectric layer of the semiconductor base and filled in the opening, electrical Connecting the second conductive type doped region and the first An first protective layer is disposed on the first surface of the semiconductor base around the gate and connected to the first dielectric layer; a first conductive pad is located in the first protection layer a second conductive pad on the collector above the second surface of the semiconductor base; and at least one conductive structure extending through the first protective layer, the first surface of the semiconductor base, a second surface and the collector, and electrically connecting the first conductive pad and the second conductive pad, the conductive structure comprises: a conductor pillar located in the semiconductor base; and a second protective layer, Located between the conductor post and the semiconductor base. 如申請專利範圍第1項所述之電子元件封裝結構，更包括：一第一凸塊，與該第一導體銲墊電性連接；以及一第二凸塊，與該射極電性連接。The electronic component package structure of claim 1, further comprising: a first bump electrically connected to the first conductor pad; and a second bump electrically connected to the emitter. 如申請專利範圍第2項所述之電子元件封裝結構，其中該第一導體銲墊包括凸塊下金屬層(UBM)。The electronic component package structure of claim 2, wherein the first conductor pad comprises a sub-bump metal layer (UBM). 如申請專利範圍第3項所述之電子元件封裝結構，其中該第一導體銲墊的材料包括鎳或金，或其合金。The electronic component package structure of claim 3, wherein the material of the first conductor pad comprises nickel or gold, or an alloy thereof. 如申請專利範圍第1項所述之電子元件封裝結構，其中該第二導體銲墊的材料包括金屬或是金屬合金。The electronic component package structure of claim 1, wherein the material of the second conductor pad comprises a metal or a metal alloy. 如申請專利範圍第1項所述之電子元件封裝結構，其中該第二導體銲墊的材料包括銅或是鋁，或其合金。The electronic component package structure of claim 1, wherein the material of the second conductor pad comprises copper or aluminum, or an alloy thereof. 如申請專利範圍第1項所述之電子元件封裝結構，更包括：一第一導體銲線(conductive bond wire)，與該第一導體銲墊電性連接；以及一第二導體銲線，與該射極電性連接。The electronic component package structure of claim 1, further comprising: a first conductive bond wire electrically connected to the first conductive pad; and a second conductor bond wire, The emitter is electrically connected. 如申請專利範圍第1項所述之電子元件封裝結構，其中該導體柱之材料包括金屬或是金屬合金。The electronic component package structure of claim 1, wherein the material of the conductor post comprises a metal or a metal alloy. 如申請專利範圍第1項所述之電子元件封裝結構，其中該導體柱之材料包括銅、鎢或鋁，或其合金。The electronic component package structure of claim 1, wherein the material of the conductor post comprises copper, tungsten or aluminum, or an alloy thereof. 如申請專利範圍第1項所述之電子元件封裝結構，其中該第一保護層之材料包括二氧化矽(SiO2 )、氮化矽(Si3 N4 )或氮化鋁(AlN)。The electronic component package structure according to claim 1, wherein the material of the first protective layer comprises cerium oxide (SiO 2 ), cerium nitride (Si 3 N 4 ) or aluminum nitride (AlN). 如申請專利範圍第1項所述之電子元件封裝結構，其中該第二保護層之材料包括二氧化矽、氮化矽或氮化鋁。The electronic component package structure of claim 1, wherein the material of the second protective layer comprises ceria, tantalum nitride or aluminum nitride. 如申請專利範圍第1項所述之電子元件封裝結構，其中該第一導電型基體區包括P型基體區且該第二導電型摻雜區包括N型掺雜區，或該第一導電型基體區包括N型基體區且該第二導電型摻雜區包括P型摻雜區。The electronic component package structure of claim 1, wherein the first conductive type substrate region comprises a P-type base region and the second conductive type doped region comprises an N-type doped region, or the first conductive type The base region includes an N-type base region and the second conductive type doped region includes a P-type doped region. 一種電子元件封裝結構，包括：一半導體元件，包括：一半導體基極，該半導體基極的一第一表面包括一第一區、一第二區與一第三區，該第三區位於該第一區與該第二區之間；一集極，位於該半導體基極的該第二區上；一第一導電型基體區，位於該半導體基極之該第一表面中；一第二導電型摻雜區，位於該第一導電型基體區中；一閘極，位於該半導體基極的該第一區上方，覆蓋部分該第一導電型基體區與部分該第二導電型摻雜區，且該閘極以一第一介電層與該半導體基極的該第一表面、該第一導電型基體區與該第二導電型摻雜區相隔絕；一第二介電層覆蓋該閘極，該第二介電層中具有一開口，且該開口貫穿該第二導電型摻雜區，而延伸至該開口的底部以裸露出該第一導電型基體區；以及一射極位於該半導體基極的該第二介電層上，並且填充於該開口中，電性連接該第二導電型摻雜區與該第一導電型基體區；一保護層，位於該第三區上；以及一導體銲墊，位於該集極上。An electronic component package structure includes: a semiconductor component, comprising: a semiconductor base, a first surface of the semiconductor base includes a first region, a second region and a third region, wherein the third region is located Between the first region and the second region; a collector located on the second region of the semiconductor base; a first conductive type substrate region located in the first surface of the semiconductor base; a second a conductive doped region located in the first conductive type substrate region; a gate located above the first region of the semiconductor base, covering a portion of the first conductive type substrate region and a portion of the second conductive type doping And the gate is separated from the first surface of the semiconductor base by the first dielectric layer, the first conductive type substrate region and the second conductive type doped region; and a second dielectric layer is covered The gate has an opening in the second dielectric layer, and the opening extends through the second conductive type doped region to extend to the bottom of the opening to expose the first conductive type substrate region; and an emitter Located on the second dielectric layer of the semiconductor base and filled in the Mouth, electrically connected to the second conductivity type doped region and the first conductivity type base region; a protective layer disposed on the third region; and a conductive pad, located on the collector. 如申請專利範圍第13項所述之電子元件封裝結構，更包括：一第一凸塊，與該導體銲墊電性連接；以及一第二凸塊，與該射極電性連接。The electronic component package structure of claim 13, further comprising: a first bump electrically connected to the conductor pad; and a second bump electrically connected to the emitter. 如申請專利範圍第14項所述之電子元件封裝結構，其中該導體銲墊包括凸塊下金屬層。The electronic component package structure of claim 14, wherein the conductor pad comprises a sub-bump metal layer. 如申請專利範圍第15項所述之電子元件封裝結構，其中該導體銲墊之材料包括鎳或金，或其合金。The electronic component package structure of claim 15, wherein the material of the conductor pad comprises nickel or gold, or an alloy thereof. 如申請專利範圍第13項所述之電子元件封裝結構，更包括：一第一導體銲線，與該導體銲墊電性連接；以及一第二導體銲線，與該射極電性連接。The electronic component package structure of claim 13 further comprising: a first conductor bond wire electrically connected to the conductor pad; and a second conductor bond wire electrically connected to the emitter. 如申請專利範圍第13項所述之電子元件封裝結構，其中該保護層之材料包括二氧化矽、氮化矽或氮化鋁。The electronic component package structure of claim 13, wherein the material of the protective layer comprises ceria, tantalum nitride or aluminum nitride. 如申請專利範圍第13項所述之電子元件封裝結構，其中該保護層之材料與該第一介電層之材料相同。The electronic component package structure of claim 13, wherein the material of the protective layer is the same as the material of the first dielectric layer. 如申請專利範圍第13項所述之電子元件封裝結構，其中該保護層之材料與該第一介電層之材料相異。The electronic component package structure of claim 13, wherein the material of the protective layer is different from the material of the first dielectric layer. 如申請專利範圍第13項所述之電子元件封裝結構，其中該第一導電型基體區包括P型基體區且該第二導電型摻雜區包括N型摻雜區，或該第一導電型基體區包括N型基體區且該第二導電型摻雜區包括P型摻雜區。The electronic component package structure of claim 13, wherein the first conductive type substrate region comprises a P-type base region and the second conductive type doped region comprises an N-type doped region, or the first conductive type The base region includes an N-type base region and the second conductive type doped region includes a P-type doped region.
TW100147205A 2011-05-03 2011-12-19 Electronic device packaging structure TWI489601B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/411,639 US8536701B2 (en) 2011-05-03 2012-03-05 Electronic device packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201161481750P 2011-05-03 2011-05-03

Publications (2)

Publication Number Publication Date
TW201246479A TW201246479A (en) 2012-11-16
TWI489601B true TWI489601B (en) 2015-06-21

Family

ID=47096342

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100147205A TWI489601B (en) 2011-05-03 2011-12-19 Electronic device packaging structure

Country Status (2)

Country Link
CN (1) CN102769004A (en)
TW (1) TWI489601B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9613843B2 (en) * 2014-10-13 2017-04-04 General Electric Company Power overlay structure having wirebonds and method of manufacturing same
US10522466B1 (en) * 2018-10-05 2019-12-31 Nanya Technology Corporation Semiconductor structure and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008300423A (en) * 2007-05-29 2008-12-11 Sanyo Electric Co Ltd Semiconductor device
US7576410B2 (en) * 2005-09-28 2009-08-18 Infineon Technologies Ag Power transistor
TWI316284B (en) * 2005-09-19 2009-10-21 Taiwan Semiconductor Mfg Semiconductor device, fabrication methods thereof and methods for forming a tungsten-containing layer
US20100032810A1 (en) * 2008-08-08 2010-02-11 Hanyi Ding Through wafer vias and method of making same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2650519B2 (en) * 1991-07-25 1997-09-03 株式会社日立製作所 Horizontal insulated gate transistor
US5795793A (en) * 1994-09-01 1998-08-18 International Rectifier Corporation Process for manufacture of MOS gated device with reduced mask count
JP2007150176A (en) * 2005-11-30 2007-06-14 Sharp Corp Semiconductor device and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI316284B (en) * 2005-09-19 2009-10-21 Taiwan Semiconductor Mfg Semiconductor device, fabrication methods thereof and methods for forming a tungsten-containing layer
US7576410B2 (en) * 2005-09-28 2009-08-18 Infineon Technologies Ag Power transistor
JP2008300423A (en) * 2007-05-29 2008-12-11 Sanyo Electric Co Ltd Semiconductor device
US20100032810A1 (en) * 2008-08-08 2010-02-11 Hanyi Ding Through wafer vias and method of making same

Also Published As

Publication number Publication date
TW201246479A (en) 2012-11-16
CN102769004A (en) 2012-11-07

Similar Documents

Publication Publication Date Title
US10700017B2 (en) Interchip backside connection
TWI395277B (en) Wafer level chip scale packaging
US9362474B2 (en) Vertical LED chip package on TSV carrier
TWI497654B (en) Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance
US11776867B2 (en) Chip package
US20120175755A1 (en) Semiconductor device including a heat spreader
TW201201329A (en) Thermally enhanced electronic package and method of manufacturing the same
US11837528B2 (en) Method of manufacturing a semiconductor device having a bond wire or clip bonded to a bonding pad
US8536701B2 (en) Electronic device packaging structure
US20100123243A1 (en) Flip-chip chip-scale package structure
TW201131829A (en) Thermally-enhanced hybrid LED package components
TWI489601B (en) Electronic device packaging structure
JP2008140894A (en) Semiconductor device and its manufacturing method
JP2022523671A (en) Electronic device flip chip package with exposed clips
TWI718250B (en) Package structures
WO2022080081A1 (en) Semiconductor device
TWI727861B (en) Chip packaging structure and method of manufacturing the same
WO2021193338A1 (en) Semiconductor device
TWM593659U (en) Packaging structure for directly exporting thermal energy of electronic components
JP2011082523A (en) Package for semiconductor device
KR102459361B1 (en) Power module package
TWI828503B (en) Semiconductor power component and semiconductor power package structure
CN102651359A (en) Semiconductor structure with low resistance substrate and low power loss
US11114387B2 (en) Electronic packaging structure
US20100127392A1 (en) Semiconductor die