TWI489440B - Image processing unit, image processing apparatus and image display system - Google Patents

Description

Image processing unit, image processing device, and image display system

The present invention relates to an image processing unit, an image processing apparatus, and an image display system, and more particularly to an image processing unit and an image that can provide lower system power consumption in a power down mode. Processing device and image display system.

As the demand for displays has increased, the industry is fully committed to the development of related displays. A liquid crystal display (LCD) with superior image quality, good space utilization efficiency, low power consumption, and no radiation has gradually become the mainstream of the market. Recently, due to the rise of the concept of green environmental protection, the power saving of liquid crystal displays has become more and more important. According to the application of the liquid crystal display, the operation mode may roughly include an active mode and a power down mode. Among them, in order to meet the power-saving standard, when operating in the power-off mode, the power consumption requirements of the liquid crystal display are strict. In the prior art, even if the power module or adapter of the liquid crystal display is not considered, the liquid crystal display still has a certain power consumption. So how to design an image display system, Further providing lower power consumption is an important issue.

The present invention provides an image processing unit that provides lower system power consumption in a particular mode of operation.

The present invention provides an image processing apparatus comprising the image processing unit described above that provides lower system power consumption in a particular operation.

The present invention provides an image display system comprising the image processing apparatus described above that provides lower system power consumption in a particular operation.

An exemplary embodiment of the present invention provides an image processing unit including a normally open circuit block and a very open circuit block. The normally open circuit block is configured to receive a first bias voltage from a power supply unit. The very open circuit block includes a microcontroller (MCU) of the image processing unit. When the very open circuit block operates in a first mode of operation, the very open circuit block receives a second bias voltage from the power supply unit to perform an image processing operation on an image input signal. When the very open circuit block operates in a second operation mode, the very open circuit block stops receiving the second bias voltage from the power supply unit, and stops the image processing operation, and at least the micro control in the very open circuit block The unit is powered off. One of the normally open circuit block and the very open circuit block, according to a first event trigger signal, the control power supply unit stops supplying the second bias voltage to the very open circuit block, so that the very open circuit block is The first mode of operation enters a second mode of operation.

In an embodiment of the invention, the normally-on circuit block further controls the power supply block to supply the second bias voltage according to a second event trigger signal. The circuit block is opened very much to allow the very open circuit block to enter the first mode of operation from the second mode of operation.

In an embodiment of the invention, the normally-on circuit block controls the power supply block to stop supplying the second bias voltage to the very open circuit block according to the first event trigger signal, so that the very open circuit block is The first mode of operation enters a second mode of operation.

In an embodiment of the invention, the non-open circuit block controls the power supply block to stop supplying the second bias voltage to the very open circuit block according to the first event trigger signal, so that the very open circuit block is The first mode of operation enters a second mode of operation.

In an embodiment of the invention, the normally-on circuit block outputs an operation stop signal to the very open circuit block according to the first event trigger signal. The very open circuit block outputs a power cut signal to the normally open circuit block according to the operation stop signal. The normally open circuit block controls the power supply block to stop supplying the second bias voltage to the very open circuit block according to the power cut signal, so that the very open circuit block enters the second operation mode from the first operation mode.

In an embodiment of the invention, the microcontroller in the non-open circuit block is configured to receive an operation stop signal.

In an embodiment of the invention, the normally-on circuit block outputs a power-off signal to the power supply block according to the first event trigger signal. The power supply block stops supplying the second bias voltage to the very open circuit block according to the power cutoff signal to cause the very open circuit block to enter the second mode of operation from the first mode of operation.

In an embodiment of the invention, the non-open circuit block further includes an input interface of the image processing unit.

An exemplary embodiment of the present invention provides an image processing apparatus for driving a display panel. The image processing device includes a power supply unit and the image processing unit described above. The power supply unit is configured to provide a first bias voltage and a second bias voltage. The image processing unit is coupled to the power supply unit.

In an embodiment of the invention, the power supply unit includes a first power supply block and a second power supply block, respectively providing a first bias voltage and a second bias voltage.

In an embodiment of the invention, the first power supply block is configured to receive a DC voltage to generate a first bias voltage according to the DC voltage. The second power supply block is configured to receive the first bias voltage to generate the second bias voltage according to the first bias voltage.

In an embodiment of the invention, the first bias voltage is less than a DC voltage, and the second bias voltage is less than the first bias voltage.

In an embodiment of the invention, the first power supply block is configured to receive a DC voltage to generate a third bias voltage according to the DC voltage. The second power supply block is configured to receive the third bias voltage to generate the second bias voltage according to the third bias voltage. The power supply unit further includes a voltage dividing unit for dividing the third bias voltage to generate the first bias voltage.

In an embodiment of the invention, the image processing apparatus further includes a power conversion circuit. The power conversion circuit is configured to receive an alternating voltage and convert the alternating voltage into a direct current voltage.

An exemplary embodiment of the present invention provides an image display system including the above image processing device and a display panel. The display panel is configured to receive an image processing device to display an image frame.

An exemplary embodiment of the present invention provides an image processing unit including a normally open circuit block and a very open circuit block. The normally open circuit block is configured to receive a first bias voltage from a power supply unit. The very open circuit block receives a second bias voltage from the power supply unit when the very open circuit block operates in a first mode of operation. When the very open circuit block operates in the second mode of operation, the very open circuit block stops receiving the second bias voltage from the power supply unit. The normally open circuit block outputs an operation stop signal to the very open circuit block according to a first event trigger signal. The very open circuit block outputs a power cut signal to the very open circuit block according to the operation stop signal. The normally open circuit block controls the power supply block to stop supplying the second bias voltage to the very open circuit block according to the power cut signal, so that the very open circuit block enters the second operation mode from the first operation mode.

In an embodiment of the invention, the non-open circuit block includes a microcontroller of an image processing unit. When the very open circuit block operates in the second mode of operation, at least the microcontroller is powered down in the very open circuit block.

In an embodiment of the invention, when the very open circuit block operates in the first mode of operation, the very open circuit block performs an image processing operation on an image input signal. When the very open circuit block operates in the second mode of operation, the very open circuit block stops the image processing operation.

In an embodiment of the invention, the normally-on circuit block further controls the power supply block to supply the second bias voltage to the very open circuit block according to a second event trigger signal, so as to open the circuit area. The block enters the first mode of operation from the second mode of operation.

An exemplary embodiment of the present invention provides an image processing unit including a normally open circuit block and a very open circuit block. Normally open circuit block for use from a power supply The supply unit receives a first bias voltage. When the very open circuit block operates in a first mode of operation, the very open circuit block receives a second bias voltage from the power supply unit, and is very open when the very open circuit block operates in the second mode of operation. The circuit block stops receiving the second bias voltage from the power supply unit. The normally open circuit block outputs a power cutoff signal to the power supply block according to the first event trigger signal, and the power supply block stops supplying the second bias voltage to the very open circuit block according to the power cutoff signal, so as to be very open. The circuit block enters the second mode of operation from the first mode of operation.

In an embodiment of the invention, the non-open circuit block includes a microcontroller of an image processing unit. When the very open circuit block operates in the second mode of operation, at least the microcontroller is powered down in the very open circuit block.

In an embodiment of the invention, when the very open circuit block is operated in the first operation mode, the very open circuit block performs an image processing operation on an image input signal, and when the very open circuit block operates in the first In the second operation mode, the very open circuit block stops the image processing operation.

In an embodiment of the invention, the normally-on circuit block further controls the power supply block to supply the second bias voltage to the very open circuit block according to a second event trigger signal, so as to open the circuit area. The block enters the first mode of operation from the second mode of operation.

The above described features and advantages of the invention will be apparent from the following description.

100, 300, 400, 500‧‧‧ image display system

110, 310, 410, 510‧ ‧ image processing device

111, 311, 411, 511‧‧‧ first power supply block

112, 312, 412, 512‧‧‧ power supply unit

113, 313, 413, 513‧‧‧second power supply block

114, 314, 414, 514‧ ‧ image processing unit

115, 315, 415, 515‧‧‧ normally open circuit blocks

117, 317, 417, 517‧‧‧ very open circuit blocks

119, 319, 419, 519‧‧‧ Microcontrollers

120‧‧‧ display panel

121, 321, 421, 521‧‧‧ input interface

516‧‧‧Power conversion circuit

623‧‧‧Voltage unit

PAO‧‧‧First bias voltage

PS‧‧‧second bias voltage

PAO’‧‧‧3rd bias voltage

PDC‧‧‧ DC voltage

PAC‧‧‧AC voltage

PO‧‧‧ operation stop signal

PD‧‧‧Power cut signal

SI‧‧‧ image input signal

Sctr1‧‧‧ control signal

Str1‧‧‧ first event trigger signal

Str2‧‧‧ second event trigger signal

FIG. 1 is a schematic diagram of an image display system according to an embodiment of the invention.

FIG. 2 is a schematic waveform diagram of a plurality of signals of the image display system of FIG. 1 according to an embodiment of the invention.

3 is a schematic diagram of an image display system according to another embodiment of the present invention.

4 is a schematic diagram of an image display system according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of an image display system according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of a power supply unit according to an embodiment of the present invention.

The invention is illustrated by the following examples, but the invention is not limited to the illustrated embodiments. Further combinations are also allowed between the embodiments. The term "coupled" as used throughout the specification (including the scope of the patent application) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other one or more signals.

In related applications of the present invention, an image display system generally includes a power conversion circuit, an image processing device, and a display panel. The power conversion circuit is, for example, a power module for converting an alternating current voltage into a direct current voltage and supplying a direct current voltage to the image processing device as an operating voltage for image processing. The image processing device is configured to receive the image data, process the image data, and transmit the image data to the display panel to display the image surface. Generally, the image processing apparatus internally includes a power supply unit and an image processing unit, wherein the latter can be implemented as a scaler chip, but is not limited thereto. In addition, the image processing device can be implemented as a system board. In different embodiments, the power conversion circuit and the image processing device may be separately provided or combined. In other applications of the invention, the power conversion circuit may also be an adapter.

In addition, in order to save power, some power-saving circuit structures are designed inside the image processing device. The image processing unit may roughly include an analog circuit block and a digital circuit block depending on the type of power source to which the circuit block is biased. The analog circuit block performs circuit operation under the bias of the analog power supply, and the digital circuit block performs circuit operation under the bias of the digital power supply. In a related art, in order to achieve power saving, the clock generator inside the digital circuit block is selectively controlled to be turned on and off. However, in this example, even if the clock generator is turned off, the digital power source for biasing the digital circuit block is continuously supplied to the digital circuit block, so the power saving effect is limited. In order to solve this problem, another related art further divides the digital circuit block into a first circuit block and a second circuit block. In order to save power, the power supply path of the second circuit block is selectively cut off. However, in this example, since the first circuit block includes a microprocessor, an input processor, a general-purpose input/output (GPIO) interface, a clock generator, and the like, even The power supply path of the second circuit block is cut off, and the first circuit block continues to perform various circuit operations, so the power saving effect is also limited.

In the present disclosure, depending on whether the circuit block is in a low power consumption mode When the power is off, the image processing unit can be roughly divided into a normally open circuit block and a very open circuit block. One of the normally open circuit block and the very open circuit block, according to an event trigger signal, the control power supply unit stops supplying a bias voltage to the very open circuit block, so that the very open circuit block is replaced by a first The operational mode enters a second mode of operation in which the other power consumption is lower. In this second mode of operation with lower power consumption, at least the microcontroller can be scheduled to be powered down to achieve a certain power saving effect. Moreover, the normally open circuit block can further control the power supply block to supply the bias voltage to the very open circuit block according to another event trigger signal, so that the very open circuit block is caused by the low power consumption. The second mode of operation enters the first mode of operation. Some embodiments are then used to illustrate the detailed operational scenarios of the internal circuitry of the disclosed image processing unit operating in different modes.

FIG. 1 is a schematic diagram of an image display system according to an embodiment of the invention. Referring to FIG. 1 , the image display system 100 of the present embodiment includes an image processing device 110 and a display panel 120 . The display panel 120 is configured to receive the driving of the image processing device 110 to display an image frame. The image processing device 110 includes a power supply unit 112 and an image processing unit 114. The image processing unit 114 is coupled to the power supply unit 112. The power supply unit 112 is configured to provide a first bias voltage PAO and a second bias voltage PS to the image processing unit 114. In this example, the image processing unit 114 is, for example, a scaler chip disposed inside the image processing device 110, and the wafer can be used as image frame scaling and update rate conversion. The adjustment of the size and display position of the image frame can be achieved by controlling the magnification of the video scaling chip and the starting position and size of the screen display. In addition, the image processing unit 114 can perform conversion processing between the input interface and the output interface of the image data, that is, the input interface (for example, After receiving and processing the image data of one or more of D-SUB, DVI, HDMI, DP, and MHL, the image data of the output interface (such as LVDS) is transferred to the display panel of the latter stage. It should be noted that in the present disclosure, the image processing unit 114 is not limited to being a video zooming chip.

Specifically, the image processing unit 114 includes a normally open circuit block 115 and a very open circuit block 117. Preferably, the normally open circuit block 115 includes at least an event detection circuit, and may also include a clock generator, such as a resistor-capacitor oscillator (RC Oscilator). In addition, it is preferable that the very open circuit block 117 includes at least a microprocessor, and further includes at least one of an input device, a general-purpose input/output interface, a clock generator, and a synchronous processor.

The power supply unit 112 includes a first power supply block 111 and a second power supply block 113, respectively providing a first bias voltage PAO and a second bias voltage PS to the normally open circuit block 115 and the very open circuit block 117. . In an embodiment, the first power supply block 111 can receive the DC voltage PDC to generate the first bias voltage PAO according to the DC voltage PDC. For example, the DC voltage PDC is, for example, 12 volts, and the first bias voltage PAO is, for example, 5 volts, but the invention is not limited thereto. In some implementations of such an embodiment, the first power supply block 111 includes a step-down circuit structure for stepping down the 12 volt DC voltage PDC to a 5 volt first bias voltage PAO. In the same or different embodiments, the second power supply block 113 can receive the first bias voltage PAO to generate the second bias voltage PS according to the first bias voltage PAO. For example, the voltage value of the second bias voltage PS is, for example, one of 1.2 volts, 1.8 volts, 2.5 volts, and 3.3 volts, and the size thereof is determined according to actual design requirements, and the invention is not limited thereto. In one of such embodiments In some implementations, the second power supply block 113 includes another buck circuit structure for bucking the 5 volt first bias voltage PAO to the second bias voltage PS. In other words, the first bias voltage PAO can be arranged to be smaller than the direct current voltage PDC, and the second bias voltage PS is smaller than the first bias voltage PAO.

In the present embodiment, the normally open circuit block 115 is configured to receive the first bias voltage PAO from the first power supply block 111. The very open circuit block 117 includes at least the microcontroller 119 of the image processing unit 114, and may further include an input interface 121. The input interface 121 is configured to receive the image input signal SI, and the microcontroller 119 is configured to perform image processing operations on the image input signal SI. When the very open circuit block 117 operates in a first mode of operation, such as an active mode, the very open circuit block 117 receives the second bias voltage PS from the second power supply block 113 to the image. Input signal SI for image processing operations. In addition, in the first operation mode, the image processing unit 114 is in a normal operation state, and each circuit block in the very open circuit block 117 performs a corresponding image processing operation on the received image input signal SI. It should be noted that the first mode of operation of the present disclosure includes, but is not limited to, an active mode.

On the other hand, when the very open circuit block 117 operates in a second mode of operation, such as a power down mode, the very open circuit block 117 stops receiving the second bias from the second power supply block 113. Pressing the voltage PS stops the image processing operation on the image input signal SI. In the second mode of operation, the image processing unit 114 is in a state of low power consumption. Therefore, in order to reduce the power consumption of the image processing unit 114, at least the microcontroller 119 of the very open circuit block 117 can be arranged to be powered down. Preferably, in the second mode of operation, the input processor, the general purpose input/output interface, the clock generator, and the same in the very open circuit block 117 At least one of the circuit devices such as the step processor is also powered off at the same time. It should be noted that the second mode of operation of the present disclosure includes, but is not limited to, a power off mode.

In this embodiment, the normally open circuit block 115 can control the second power supply block 113 to stop supplying the second bias voltage PS to the very open circuit block 117 according to the first event trigger signal Str1, so that the circuit is very open. Block 117 enters the second mode of operation from the first mode of operation. For example, in the present embodiment, the normally open circuit block 115 outputs the operation stop signal PO to the microcontroller 119 of the very open circuit block 117 according to the first event trigger signal Str1. Then, the very open circuit block 117 returns the power cut signal PD to the normally open circuit block 115 according to the operation stop signal PO. Thereafter, the normally-on circuit block 115 outputs a control signal Sctr1 to the second power supply block 113 according to the power-off signal PD to control the second power supply block 113 to stop supplying the second bias voltage PS to the very open circuit block. 117, thereby causing the very open circuit block 117 to enter the second mode of operation from the first mode of operation. In this embodiment, the first event refers to, for example, that the image display system 100 is turned off. Therefore, the first event trigger signal Str1 may be from one of the one or more power keys of the image display system 100, or from the display. The data bus (SDA) of the data channel (DDC) or the clock bus (SCL) from the data channel.

On the other hand, in the embodiment, the normally open circuit block 115 can also output the control signal Sctr1 to the second power supply block 113 according to the second event trigger signal Str2 to control the second power supply block 113 to start supplying the second. The bias voltage PS is applied to the very open circuit block 117 to cause the very open circuit block 117 to enter the first mode of operation from the second mode of operation. In this embodiment, the second event refers to, for example, that the image display system 100 is powered on. Therefore, the second event trigger signal Str2 may be from one of the one or more power keys of the image display system 100, or from the display. Data pass The data bus of the track, or the clock bus from the display data channel.

In addition, in this embodiment, a possible implementation manner in which the second power supply block 113 stops supplying the second bias voltage PS to the very open circuit block 117 includes that the second power supply block 113 itself is controlled by the control signal. Sctr1 is powered off, thus stopping generating and stopping the supply of the second bias voltage PS to the very open circuit block 117, or including the second power supply block 113 itself being controlled by the control signal Sctr1, although according to the first bias The voltage PAO generates the second bias voltage PS, but stops outputting the generated second bias voltage PS to the very open circuit block 117. In such an embodiment in which the second bias voltage PS is generated but the output of the generated second bias voltage PS to the very open circuit block 117 is stopped, the second power supply block 113 may include a power control block. The operation of the very open circuit block 117 to stop outputting the generated second bias voltage PS is controlled.

2 is a schematic waveform diagram of a plurality of signals of the image display system of FIG. 1 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in the embodiment, it is assumed that the image processing unit 114 is initially in the first operation mode. In the first operation mode, when the first event is triggered, the normally open circuit block 115 first receives the first event trigger signal Str1, and the normally open circuit block 115 performs a first event trigger signal Str1. Filter or debounce processing. The first event trigger signal Str1 is, for example, a high-level pulse signal, but in other embodiments, the first event trigger signal Str1 does not exclude a low-level pulse signal. Then, after the first event trigger signal Str1 is filtered or debounced in the normally open circuit block 115, and the receiver is confirmed to be the first event trigger signal Str1, the normally open circuit block 115 outputs a low level operation. The stop signal PO is applied to the microcontroller 119 in the very open circuit block 117. The normally open circuit block 115 here is the input The low stop operation stop signal PO is given to the microcontroller 119 as an example, but in other embodiments, the normally open circuit block 115 does not exclude the output high level operation stop signal PO to the microcontroller 119 at this time. . After the very open circuit block 117 receives the low level operation stop signal PO, a power cut signal PD is generated and returned to the normally open circuit block 115. The power-off signal PD here is, for example, a high-level pulse signal, but in other embodiments, the power-off signal PD does not exclude a low-level pulse signal. Then, after the normally open circuit block 115 receives the high-level power-off signal PD, the normally-on circuit block 115 outputs a low-level control signal Sctr1 to the second power supply block 113 to control the second. The power supply block 113 stops supplying the second bias voltage PS to the very open circuit block 117. The normally open circuit block 115 here is an example of outputting the low level control signal Sctr1 to the second power supply block 113. However, in other embodiments, the normally open circuit block 115 does not exclude the output at this time. The high level control signal Sctr1 is supplied to the second power supply block 113. So far, the image processing unit 114 enters the second operation mode, and at least the microcontroller 119 is powered off among the very open circuit blocks 117.

Then, in the second operation mode, when the second event is triggered, the normally open circuit block 115 first receives the second event trigger signal Str2. The second event trigger signal Str2 is also a pulse signal of a high level, but in other embodiments, the second event trigger signal Str2 does not exclude a pulse signal that is a low level. After the normally open circuit block 115 confirms that the second event trigger signal Str2 is received, the normally open circuit block 115 outputs a high level operation stop signal PO to the microcontroller 119, and outputs a low level control signal Sctr1 to The second power supply block 113 starts to supply the second bias voltage PS to the very open circuit block 117 by the control power supply block 113. to Therefore, the very open circuit block 117 returns to the first operation mode from the second operation mode, and the image processing operation of the image input signal SI can be started.

In this embodiment, the normally open circuit block 115 and the very open circuit block 117 communicate with the operation stop signal PO and the power cut signal PD, and the very open circuit block 117 can record each event trigger. The power on state or the power off state, but the present invention is not limited thereto. In another embodiment, the channel communication number may not exist between the normally open circuit block 115 and the very open circuit block 117, that is, the operation stop signal PO and the power cut signal PD are not included between the two.

3 is a schematic diagram of an image display system according to another embodiment of the present invention. Referring to FIG. 1 and FIG. 3, the image display system 300 of the present embodiment is similar to the image display system 100 of FIG. 1. However, the main difference between the two is, for example, that the normally open circuit block 315 of the present embodiment is directly based on The first event trigger signal Str1 outputs the power-off signal PD to the power supply block 313 to control the power supply block 313 to stop supplying the second bias voltage PS to the very open circuit block 317 according to the power-off signal PD, thereby The very open circuit block 317 is brought into the second mode of operation from the first mode of operation. In other words, in this example, the communication between the normally open circuit block 115 and the very open circuit block 117 without the operation stop signal PO and the power cut signal PD can control the power supply block 313 to stop supplying the second. The bias voltage PS is to the very open circuit block 317.

In addition, in the embodiment, the normally open circuit block 315 can output the control signal Sctr1 to the second power supply block 313 according to the second event trigger signal Str2 to control the second power supply. Block 313 begins to supply the second The bias voltage PS is to the very open circuit block 317.

In the present embodiment, the second power supply block 313 determines to supply or stop supplying the second bias voltage PS to the very open circuit block 317 which is controlled by the normally open circuit block 315, but the present invention is not limited thereto. . In another embodiment, the second power supply block 113 can also be controlled by the very open circuit block 317 to stop supplying the second bias voltage PS to the very open circuit block 317.

4 is a schematic diagram of an image display system according to another embodiment of the present invention. Referring to FIG. 3 and FIG. 4, the image display system 400 of the present embodiment is similar to the image display system 300 of FIG. 3, but the main difference between the two is, for example, that the very open circuit block 417 of the embodiment is directly according to the first An event trigger signal Str1 controls the power supply block 413 to stop supplying the second bias voltage PS to the very open circuit block 417 to cause the very open circuit block 417 to enter the second mode of operation from the first mode of operation.

In this embodiment, when the very open circuit block 417 enters the second operation mode, the circuit block that does not need to be operated inside is turned off to achieve the purpose of power cut. Therefore, in this embodiment, the control is performed. The operation of the second power supply block 413 to supply the second bias voltage PS to the very open circuit block 417 is still performed by the normally open circuit block 415.

In the embodiment of FIG. 1, the image processing device 110 directly receives the DC voltage PDC, so that the first power supply block 111 of the power supply unit 112 generates the first bias voltage PAO according to the DC voltage PDC, but the present invention Not limited to this. FIG. 5 is a schematic diagram of an image display system according to another embodiment of the present invention. Referring to FIG. 5, the image processing apparatus 510 of the embodiment further includes a power conversion circuit 516. The power conversion circuit 516 is configured to receive the AC voltage PAC and the AC voltage PAC Converted to DC voltage PDC. In this example, power conversion circuit 516 is, for example, a power module or adapter in a monitor system architecture. It should be noted that in other embodiments, the image processing device 510 does not need to internally include a power conversion circuit, but is externally coupled to the power conversion circuit.

Next, an embodiment will be used to explain different implementation architectures of the internal circuits of the power supply unit of the present disclosure.

FIG. 6 is a schematic diagram of a power supply unit according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 6. In the embodiment of FIG. 1, the power supply unit 112 includes a first power supply block 111 for receiving the DC voltage PDC to generate a first bias voltage PAO according to the DC voltage PDC, and directly providing the first bias voltage. The PAO is given to the normally open circuit block 115. In this embodiment, the power supply unit 612 further includes a voltage dividing unit 623 for dividing the third bias voltage PAO' to generate the first bias voltage PAO. Specifically, the first power supply block 611 receives the DC voltage PDC to generate a third bias voltage PAO' according to the DC voltage PDC. The second power supply block receives the third bias voltage PAO' to generate the second bias voltage PS in accordance with the third bias voltage PAO'.

In summary, in an exemplary embodiment of the present invention, one of the normally open circuit block and the very open circuit block controls the power supply unit to stop supplying the bias voltage to the very open circuit area according to the event trigger signal. The block is such that the very open circuit block enters from another mode of operation into another mode of operation with lower power consumption. In this mode of low power consumption, at least the microcontroller is powered down to achieve power savings, such as system power consumption up to 1 mW.

Although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. The scope of the present invention is defined by the scope of the appended claims, which are defined by the scope of the appended claims, without departing from the spirit and scope of the invention. quasi.

100‧‧‧Image display system

110‧‧‧Image processing device

111‧‧‧First power supply block

112‧‧‧Power supply unit

113‧‧‧Second power supply block

114‧‧‧Image Processing Unit

115‧‧‧Normally Open Circuit Blocks

117‧‧‧ Very open circuit block

119‧‧‧Microcontroller

120‧‧‧ display panel

121‧‧‧Input interface

PAO‧‧‧First bias voltage

PS‧‧‧second bias voltage

PDC‧‧‧ DC voltage

PO‧‧‧ operation stop signal

PD‧‧‧Power cut signal

SI‧‧‧ image input signal

Sctr1‧‧‧ control signal

Str1‧‧‧ first event trigger signal

Str2‧‧‧ second event trigger signal

Claims (24)

An image processing unit includes: a normally open circuit block for receiving a first bias voltage from a power supply unit; and a very open circuit block including a microcontroller of the image processing unit, when When the very open circuit block is operated in a first operation mode, the very open circuit block receives a second bias voltage from the power supply unit to perform an image processing operation on an image input signal. When the circuit block operates in a second operation mode, the very open circuit block stops receiving the second bias voltage from the power supply unit, and stops the image processing operation, and at least the non-open circuit block The microcontroller is powered off; wherein one of the normally open circuit block and the very open circuit block controls the power supply unit to stop supplying the second bias voltage to the one according to a first event trigger signal The circuit block is opened so that the very open circuit block enters the second mode of operation from the first mode of operation. The image processing unit of claim 1, wherein the normally open circuit block further controls the power supply block to supply the second bias voltage to the very open circuit area according to a second event trigger signal. Blocking to cause the very open circuit block to enter the first mode of operation from the second mode of operation. The image processing unit of claim 2, wherein the normally open circuit block controls the power supply block to stop supplying the second bias voltage to the very open circuit block according to the first event trigger signal. So that the very open circuit block enters the second mode of operation from the first mode of operation. The image processing unit of claim 2, wherein the The open circuit block controls the power supply block to stop supplying the second bias voltage to the very open circuit block according to the first event trigger signal, so that the very open circuit block enters the first operation mode. The second mode of operation. The image processing unit of claim 2, wherein the normally open circuit block outputs an operation stop signal to the very open circuit block according to the first event trigger signal, the very open circuit block according to the operation The stop signal outputs a power cut signal to the normally open circuit block, and the normally open circuit block controls the power supply block to stop supplying the second bias voltage to the very open circuit block according to the power cut signal So that the very open circuit block enters the second mode of operation from the first mode of operation. The image processing unit of claim 5, wherein the microcontroller in the very open circuit block is configured to receive the operation stop signal. The image processing unit of claim 2, wherein the normally open circuit block outputs a power cutoff signal to the power supply block according to the first event trigger signal, and the power supply block is cut according to the power supply. The stop signal stops supplying the second bias voltage to the very open circuit block to cause the very open circuit block to enter the second mode of operation from the first mode of operation. The image processing unit of claim 1, wherein the very open circuit block further comprises an input interface of the image processing unit. An image processing device for driving a display panel, the image processing device comprising: a power supply unit for providing a first bias voltage and a second bias voltage; and as described in claim 1 An image processing unit coupled to the power source Supply unit. The image processing device of claim 9, wherein the power supply unit comprises a first power supply block and a second power supply block, respectively providing the first bias voltage and the second bias Voltage. The image processing device of claim 10, wherein the first power supply block is configured to receive a DC voltage to generate the first bias voltage according to the DC voltage, and the second power supply a block for receiving the first bias voltage to generate the second bias voltage according to the first bias voltage. The image processing device of claim 11, wherein the first bias voltage is less than the DC voltage, and the second bias voltage is less than the first bias voltage. The image processing device of claim 10, wherein the first power supply block is configured to receive a DC voltage to generate a third bias voltage according to the DC voltage, the second power supply region a block for receiving the third bias voltage to generate the second bias voltage according to the third bias voltage, and the power supply unit further includes a voltage dividing unit for dividing the third bias voltage A voltage is generated to generate the first bias voltage. The image processing device of claim 11, further comprising: a power conversion circuit for receiving an alternating voltage and converting the alternating voltage to the direct current voltage. An image display system comprising: the image processing device according to claim 9; A display panel is configured to receive a driving of the image processing device to display an image frame. The image display system of claim 15, further comprising: a power conversion circuit for receiving an alternating current voltage and converting the alternating current voltage to a direct current voltage for providing to the image processing device Power supply unit is used. An image processing unit includes: a normally open circuit block for receiving a first bias voltage from a power supply unit; and a very open circuit block, wherein the very open circuit block operates in a first operation In the mode, the very open circuit block receives a second bias voltage from the power supply unit, and when the very open circuit block operates in the second operation mode, the very open circuit block stops from the power supply The unit receives the second bias voltage; wherein the normally open circuit block outputs an operation stop signal to the very open circuit block according to a first event trigger signal, and the very open circuit block outputs a signal according to the operation. The power-off signal is sent to the normally-on circuit block, and the normally-on circuit block controls the power supply block to stop supplying the second bias voltage to the non-open circuit block according to the power-off signal, so that the The very open circuit block enters the second mode of operation from the first mode of operation. The image processing unit of claim 17, wherein the very open circuit block comprises a microcontroller of the image processing unit, and when the very open circuit block operates in the second mode of operation, At least the microcontroller is powered down in the very open circuit block. The image processing unit of claim 17, wherein When the very open circuit block is operated in the first operation mode, the very open circuit block performs an image processing operation on an image input signal, when the very open circuit block operates in the second operation mode, The very open circuit block stops the image processing operation. The image processing unit of claim 17, wherein the normally open circuit block further controls the power supply block to supply the second bias voltage to the very open circuit area according to a second event trigger signal. Blocking to cause the very open circuit block to enter the first mode of operation from the second mode of operation. An image processing unit includes: a normally open circuit block for receiving a first bias voltage from a power supply unit; and a very open circuit block, wherein the very open circuit block operates in a first operation In the mode, the very open circuit block receives a second bias voltage from the power supply unit, and when the very open circuit block operates in the second operation mode, the very open circuit block stops from the power supply The unit receives the second bias voltage; wherein the normally open circuit block outputs a power-off signal to the power supply block according to the first event trigger signal, and the power supply block stops supplying the power according to the power-off signal The second bias voltage is applied to the very open circuit block to cause the very open circuit block to enter the second mode of operation from the first mode of operation. The image processing unit of claim 21, wherein the very open circuit block comprises a microcontroller of the image processing unit, and when the very open circuit block operates in the second mode of operation, At least the microcontroller is powered down in the very open circuit block. The image processing unit of claim 21, wherein When the very open circuit block is operated in the first operation mode, the very open circuit block performs an image processing operation on an image input signal, when the very open circuit block operates in the second operation mode, The very open circuit block stops the image processing operation. The image processing unit of claim 21, wherein the normally open circuit block further controls the power supply block to supply the second bias voltage to the very open circuit area according to a second event trigger signal. Blocking to cause the very open circuit block to enter the first mode of operation from the second mode of operation.