TWI488418B - Constant on-time controller - Google Patents

Description

Fixed on-time controller

The present invention relates to a fixed on-time controller, and more particularly to a fixed on-time controller with ripple compensation.

The synchronous buck converter of the current fixed on-time (COT) architecture, in line with the trend of the operating voltage drop of the integrated circuit, the demand for the ripple of the output voltage is more and more rigorous. In order to achieve low output ripple ripple, synchronous buck converters typically use a low-equivalent series resistance (ESR) multilayer ceramic capacitor (MLCC) as the output capacitor. However, the use of a multilayer ceramic capacitor reduces the ripple of the output voltage, but it also brings stability problems. Therefore, additional ripple is required to improve the stability of the application of the laminated ceramic capacitor. The method of introducing ripple can be divided into two types: the external introduction of the controller and the internal introduction of the controller, wherein the introduction of the controller has a better cost advantage.

Please refer to the first figure for the application circuit diagram of the traditional fixed on-time controller with ripple compensation. Fixed on-time controller control The circulating DC step-down conversion circuit converts an input voltage Vin into an output voltage Vout. The DC-to-DC buck conversion circuit includes an upper arm transistor Q1, a lower arm transistor Q2, an inductor L, and an output capacitor Cout. The output capacitor Cout has an equivalent resistance Rc. The upper arm transistor Q1 and the lower arm transistor Q2 are connected to each other via a phase node P, and the other end of the upper arm transistor Q1 is connected to the input voltage Vin, and the other end of the lower arm transistor Q2 is grounded. One end of the inductor L is connected to the phase node P, and the other end is connected to the output capacitor Cout to generate an output voltage Vout.

The fixed on-time controller is coupled to the phase node P of the upper arm transistor Q1 and the lower arm transistor Q2. The fixed on-time controller includes a pulse width modulation controller 11 and a driver 17. The pulse width modulation controller 11 includes a synchronous signal generating circuit 13 and a pulse width modulation comparing circuit 15. The sync signal generating circuit 13 includes a low pass filter 3 and an error amplifier 5. The low-pass filter 3 includes a resistor R4 and a capacitor C4, and is connected to the phase node P to filter out the high-frequency component of the voltage signal Vp of the phase node P, and generates a signal Slp of a similar triangular wave at a node X. One non-inverting terminal of the error amplifier 5 receives a reference voltage signal Vref1, and an inverting terminal receives the signal Slp to generate an error amplification signal S12. The pulse width modulation comparison circuit 15 includes an adder 7 and a comparator 9. The adder 7 adds the error amplification signal S12 to a reference voltage signal Vref2 to generate an addition signal S13. The output voltage Vout outputted by the DC-to-DC buck converter circuit is divided by a voltage detecting circuit 1 to generate a voltage detecting signal Vfb. A non-inverting terminal of the comparator 9 receives the summing signal S13, and an inverting terminal receives the voltage detecting signal Vfb to generate a pulse width modulation signal S9 to the driver 17. Driver 17 according to pulse width modulation signal S9 controls the upper arm transistor Q1 and the lower arm transistor Q2 to stabilize the output voltage Vout.

The disadvantage of the conventional fixed on-time controller is that in different application environments, such as input voltage Vin, output voltage Vout or operating frequency, the amplitude and duty cycle of the voltage signal Vp of the phase node P may vary greatly. The amount of ripple on the resulting addition signal S13 also varies with the application environment. This causes the deviation of the actual output voltage from the ideal output voltage to be different in different application environments.

Since the deviation between the actual output voltage and the ideal output voltage in the prior art may vary depending on the application environment, the fixed on-time controller of the present invention can provide a substantially constant amount of ripple that does not change with the application environment, and avoids the actual The deviation of the output voltage from the ideal output voltage varies with the application environment.

To achieve the above object, the present invention provides a fixed on-time controller for controlling switching of a switching circuit to generate an output voltage. The fixed on-time controller includes a ripple generator, a comparison circuit, and a logic control circuit. The ripple generator generates a ripple signal according to a first signal of one of the current components flowing through one of the inductances of the conversion circuit and a current component containing a second signal or an inductor of the output voltage component, wherein the second signal When the signal contains the current component of the inductor, the amplitude of one of the second signals is less than the amplitude of the first signal. The ripple generator includes a level adjustment circuit for adjusting the levels of the first signal and the second signal according to one of the ripple signals. Comparison circuit receiving ripple signal a reference voltage signal and a voltage detection signal representing one of the output voltages, and adjusting one of the reference voltage signal and the voltage detection signal according to the ripple signal to generate a ripple with ripple information of one of the ripple signals The signal is adjusted, and the comparison circuit compares the ripple adjustment signal with the reference voltage signal and the voltage detection signal to generate a comparison result signal. The logic control circuit generates a control signal having a fixed pulse width to control switching of the conversion circuit according to the comparison result signal.

The present invention also provides a fixed on-time controller for controlling switching of a conversion circuit to generate an output voltage. The fixed on-time controller includes a ripple generator, a comparison circuit, and a logic control circuit. The ripple generator generates a ripple signal according to a first signal of one of the current components flowing through one of the inductances of the conversion circuit and a second signal containing a large component of the output voltage component or the current of the inductor, wherein When the second signal contains the current component of the inductor, the amplitude of one of the second signals is less than the amplitude of the first signal. The ripple generator includes a level adjustment circuit for adjusting the amplitude of the ripple signal according to the output voltage and a control signal or according to one of the ripple signals. The comparison circuit receives the ripple signal, a reference voltage signal, and a voltage detection signal representing the output voltage, and adjusts one of the reference voltage signal and the voltage detection signal according to the ripple signal to generate one of the ripple signals. A ripple adjustment signal of the wave information, the comparison circuit compares the ripple adjustment signal with another of the reference voltage signal and the voltage detection signal to generate a comparison result signal. The logic control circuit generates a control signal having a fixed pulse width to control the conversion circuit according to the comparison result signal Switching.

The present invention further provides a fixed on-time controller for controlling switching of a conversion circuit to generate an output voltage. The fixed on-time controller includes a ripple generator, a comparison circuit, and a logic control circuit. The ripple generator generates a ripple signal according to a first signal of one of the current components flowing through one of the inductances of the conversion circuit and a second signal containing a current component of the output voltage component or the inductor, wherein the second signal When the signal contains the current component of the inductor, the amplitude of one of the second signals is less than the amplitude of the first signal. The ripple generator includes a level adjustment circuit that generates an adjustment signal based on the output voltage and a control signal or according to one of the ripple signals. The comparison circuit receives the ripple signal, a reference voltage signal, and a voltage detection signal representing the output voltage, and adjusts one of the reference voltage signal and the voltage detection signal according to the ripple signal to generate one of the ripple signals. A ripple adjustment signal of the wave information, the comparison circuit compares the ripple adjustment signal with another of the reference voltage signal and the voltage detection signal to generate a comparison result signal. The comparison circuit includes a signal introduction circuit for adjusting the amplitude of the ripple adjustment signal according to the adjustment signal. The logic control circuit generates a control signal having a fixed pulse width according to the comparison result signal to control switching of the conversion circuit.

The above summary and the following detailed description are exemplary in order to further illustrate the scope of the claims. Other objects and advantages of the present invention will be described in the following description and drawings.

Prior art:

1‧‧‧Voltage detection circuit

3‧‧‧Low-pass filter

5‧‧‧Error amplifier

7‧‧‧Adder

9‧‧‧ comparator

11‧‧‧ Pulse width modulation controller

13‧‧‧Synchronous signal generation circuit

15‧‧‧ Pulse width modulation comparison circuit

17‧‧‧ drive

C4‧‧‧ capacitor

Cout‧‧‧ output capacitor

L‧‧‧Inductance

P‧‧‧ phase node

Q1‧‧‧Upper arm transistor

Q2‧‧‧ Lower arm transistor

R4‧‧‧ resistance

Rc‧‧‧ equivalent resistance

S3‧‧‧ ripple signal

S9‧‧‧ pulse width modulation signal

S12‧‧‧Error amplification signal

S13‧‧‧ Adding signals

Slp‧‧‧ signal

Vfb‧‧‧ voltage detection signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vp‧‧‧ voltage signal

Vref1‧‧‧ reference voltage signal

Vref2‧‧‧ reference voltage signal

X‧‧‧ node

this invention:

1‧‧‧Voltage detection circuit

100, 200, 300‧‧ ‧ level adjustment circuit

101, 102‧‧‧ low pass filter

103‧‧‧Amplifier

104, 204, 304‧‧‧ signal introduction circuit

105‧‧‧Absolute value circuit

106‧‧‧ Filter

107, 207, 307‧‧‧ voltage detection circuit

108, 208, 308, 408, 508, 608‧‧‧ sampling detection circuit

109, 209‧‧‧voltage drop generation circuit

110‧‧‧Ripple generator

111‧‧‧ comparator

115, 215, 315‧‧‧ comparison circuit

120‧‧‧Logic Control Circuit

203‧‧‧Transduction amplifier

205‧‧‧ ripple amplitude sampling circuit

206‧‧‧Error amplifier

303‧‧‧Controllable amplifier

305‧‧‧current absolute value circuit

BS‧‧‧ bootstrap circuit

C11‧‧‧ capacitor

C12‧‧‧ capacitor

C13‧‧‧ capacitor

CL1, CL2‧‧‧ counter

COM1, COM2‧‧‧ comparator

Cout‧‧‧ output capacitor

CP1‧‧‧ first count signal

CP2‧‧‧ second count signal

Cr‧‧‧ capacitor

DL1~DL2‧‧‧D type flip-flop

I1, I2‧‧‧ controlled current source

IDC1, IDC2‧‧‧ constant current source

IL‧‧‧Inductor Current

IN1‧‧‧Inverter

Ir‧‧‧ Current

L‧‧‧Inductance

LG, UG‧‧‧ control signals

M1~M4‧‧‧O crystal

NG_C‧‧‧Error signal

NOR1~NOR3‧‧‧Anti-gate

OR1~OR3‧‧‧ or gate

OS‧‧‧pulse generator

P‧‧‧ phase node

Q1‧‧‧Upper arm transistor

Q2‧‧‧ Lower arm transistor

R1, R2‧‧‧ resistance

R11‧‧‧ resistance

R12‧‧‧ resistance

R13‧‧‧resistance

R14‧‧‧ resistance

R205‧‧‧resistance

S0‧‧‧ quasi-square wave signal

S1‧‧‧ first signal

S2‧‧‧ second signal

S3‧‧‧ ripple signal

S4‧‧‧ ripple adjustment signal

S5‧‧‧ voltage signal

S6‧‧‧DC signal

S11‧‧‧ comparison result signal

SC4‧‧‧Adjustment start signal

SH1‧‧‧ first comparison signal

SH2‧‧‧ second comparison signal

Si3‧‧‧ current ripple signal

Si5‧‧‧current signal

SSE‧‧‧Adjustment termination signal

SW, SWA, SWB‧‧‧ control signals

T0, t1, t2‧‧‧ time points

Vbs‧‧‧ bootstrap voltage

Vfb‧‧‧ voltage detection signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vp‧‧‧ voltage

Vref‧‧‧reference voltage signal

VrefL‧‧‧ minimum reference voltage

VrefH‧‧‧Maximum reference voltage

The first figure shows the application circuit diagram of a conventional fixed on-time controller with ripple compensation.

The second figure is an application circuit diagram of a fixed on-time controller according to a first preferred embodiment of the present invention.

The third figure is a circuit diagram of a level adjustment circuit according to a first preferred embodiment of the present invention.

The fourth figure is the signal waveform diagram of the level adjustment circuit shown in the third figure.

Figure 5 is a partial circuit diagram of a fixed on-time controller in accordance with a second preferred embodiment of the present invention.

Figure 6 is a circuit diagram of a level adjustment circuit in accordance with a second preferred embodiment of the present invention.

Figure 7 is a circuit diagram of a voltage detecting circuit in accordance with a preferred embodiment of the present invention.

The eighth figure is a signal waveform diagram of the embodiment shown in the sixth and seventh figures.

Figure 9 is a partial circuit diagram of a fixed on-time controller in accordance with a third preferred embodiment of the present invention.

Figure 11 is a circuit diagram of a level adjustment circuit in accordance with a third preferred embodiment of the present invention.

Figure 11 is a partial circuit diagram of a fixed on-time controller in accordance with a fourth preferred embodiment of the present invention.

Figure 12 is a solid view of a fifth preferred embodiment of the present invention A schematic diagram of a partial circuit for the on-time control.

Figure 13 is a partial circuit diagram showing the fixed on-time control according to a sixth preferred embodiment of the present invention.

Figure 14 is a partial circuit diagram showing the fixed on-time control according to a seventh preferred embodiment of the present invention.

Figure 15 is a circuit diagram showing a portion of a fixed on-time control in accordance with an eighth preferred embodiment of the present invention.

Referring to the second figure, there is shown an application circuit diagram of a fixed on-time controller according to a first preferred embodiment of the present invention. The fixed on-time controller controls switching of a switching circuit to generate an output voltage. In this embodiment, the conversion circuit is a DC-DC converter circuit that converts an input voltage Vin into an output voltage Vout. The DC-to-DC buck conversion circuit includes an upper arm transistor Q1, a lower arm transistor Q2, an inductor L, and an output capacitor Cout. The upper arm transistor Q1 and the lower arm transistor Q2 are coupled to each other via a phase node P, and the other end of the upper arm transistor Q1 is coupled to the input voltage Vin, and the other end of the lower arm transistor Q2 is coupled to the ground. One end of the inductor L is coupled to the phase node P, and the other end is coupled to the output capacitor Cout to generate an output voltage Vout. The DC-to-DC buck converter circuit can additionally add a bootstrap circuit BS for providing a bootstrap voltage Vbs higher than the input voltage Vin to a fixed on-time controller, so that the fixed on-time controller can correctly control the upper arm transistor Switching of Q1. One end of the bootstrap circuit BS is coupled to the phase node P. When the upper arm transistor Q1 is turned off and the lower arm transistor Q2 is turned on, the phase node P is turned on. The voltage Vp is approximately equal to a ground voltage level, at which time a capacitor (not shown) inside the bootstrap circuit BS is charged. When the upper arm transistor Q1 is turned on and the lower arm transistor Q2 is turned off, the voltage Vp of the phase node P is approximately equal to a voltage level of the input voltage Vin, and the bootstrap voltage Vbs provided by the capacitor inside the bootstrap circuit BS is approximately equal to two. Double the input voltage. A voltage detecting circuit 1 detects the output voltage Vout to generate a voltage detecting signal Vfb. In this embodiment, the voltage detecting circuit 1 has resistors R1 and R2 connected in series to divide the output voltage Vout to generate a voltage detecting signal Vfb.

The fixed on-time controller includes a ripple generator 110, a comparison circuit 115, and a logic control circuit 120. The ripple generator 110 includes a level adjustment circuit 100, low pass filters 101 and 102, and an amplifier 103 for generating a ripple signal S3. The level adjustment circuit 100 is coupled to the phase node P or the bootstrap circuit BS, and generates a quasi-square wave signal S0 according to the voltage Vp of the phase node P or the bootstrap voltage Vbs. The low pass filter 101 includes a resistor R11 and a capacitor C11 connected in series, and generates a first signal S1 of an approximate triangular wave at a connection point thereof. The other end of the resistor R11 is coupled to the level adjusting circuit 100, and the other end of the capacitor C11 is grounded. The first signal S1 is synchronized with an inductor current IL flowing through the inductor L, and thus can represent the inductor current IL. In practical applications, the first signal S1 can be replaced by a detection signal of the inductor current IL or other signal that can be used to contain the inductor current IL component. The low pass filter 102 includes a resistor R12 and a capacitor C12 connected in series to generate an approximate DC signal or a second signal S2 having a ripple component at a connection point thereof. In this embodiment, the other end of the resistor R12 is coupled to the low pass filter 101 to receive the first Signal S1, and the other end of capacitor C12 is grounded. The second signal S2 is an approximate DC signal or a signal having a ripple component (but the amplitude is smaller than the amplitude of the first signal S1) depending on the capacitance value (filtering capability) of the capacitor C12. In practical applications, the low-pass filter 102 can be directly coupled to the level adjustment circuit 100 to receive the quasi-square wave signal S0 to generate the second signal S2, and the amplitude of the second signal S2 is smaller than the amplitude of the first signal S1. For the adjustment of the above circuit application, for example, when the first signal S1 and the second signal S2 are all composed of the inductor current IL, or the first signal S1 and the second signal S2 are respectively composed of the inductor current IL and contain the output voltage Vout The components other than the components have the same size, and can be mutually eliminated afterwards, without affecting the function of the present invention. In this implementation, the second signal S2 is an approximate DC signal containing the output voltage Vout component. In practical application, the second signal S2 may be a detection signal such as the output voltage Vout or the output voltage Vout, which may represent the output voltage Vout or the signal containing the output voltage Vout component; or the signal representing the magnitude of the inductor current, but The amplitude of the amplitude is different from the magnitude of the amplitude of the first signal S1. The amplifier 103 receives the first signal S1 and the second signal S2 to generate the ripple signal S3 according to the level difference between the first signal S1 and the second signal S2. In this embodiment, the amplifier 103 is a voltage amplifier, an inverting terminal receives the first signal S1, and a non-inverting terminal receives the second signal S2, thereby amplifying (or reducing) the first signal S1 and the second signal. The level difference of S2 becomes the output of the ripple signal S3. At this time, the ripple signal S3 is synchronized with the inductor current IL in an inverted phase. The level adjustment circuit 100 is coupled to an output end of the amplifier 103 to sample the amplitude of the ripple signal S3, and adjusts a level of the quasi-square wave signal S0 according to the sampling result, thereby achieving the adjustment first. The role of the signal S1 and the second signal S2. When the magnitude of the amplitude of the ripple signal S3 is affected by different application environments, the ripple generator 110 can correct the amplitude of the ripple signal S3 by using such a circuit design to reduce the amplitude of the amplitude in different application environments. The difference is even a fixed magnitude and is not affected by the application environment.

The comparison circuit 115 includes a signal introduction circuit 104 and a comparator 111. In this embodiment, the signal introduction circuit 104 is an adder that adds the ripple signal S3 and a reference voltage signal Vref to generate a ripple adjustment signal S4. An inverting terminal of the comparator 111 receives the voltage detecting signal Vfb, and a non-inverting terminal receives the ripple adjusting signal S4 to generate a comparison result signal S11. When the level of the ripple adjustment signal S4 is higher than the voltage detection signal Vfb, the comparison result signal S11 is a high level; when the level of the ripple adjustment signal S4 is lower than the voltage detection signal Vfb, the comparison result signal S11 is a low level.

In actual application, the signal introduction circuit 104 can receive the ripple signal S3 and the voltage detection signal Vfb to introduce the ripple information of the ripple signal S3 into the voltage detection signal Vfb to generate the ripple adjustment signal S4. At this time, the non-inverting terminal of the comparator 111 is changed to receive the voltage detecting signal Vfb, and the non-inverting terminal is changed to receive the ripple adjusting signal S4. In addition, the amplifier 103 in the ripple generator 110 is correspondingly adjusted, and the non-inverting terminal is instead received the first signal S1, and the inverting terminal is changed to receive the second signal S2. In this way, the same effect as the embodiment shown in the second figure can be achieved.

As described above, the correspondence between the input of the amplifier 103 in the ripple generator 110 and the comparator 111 of the comparison circuit 115 and the received signal can be The same effect is achieved with the corresponding adjustment. In the following embodiments, the correspondence between the input terminal and the acceptance signal will not be specifically described.

The logic control circuit 120 receives the comparison result signal S11 to generate a control signal UG having a fixed pulse width to control the switching of the upper arm transistor Q1 according to the comparison result signal S11, so that the conversion circuit converts the input voltage Vin into the output voltage Vout. In the synchronous buck application, the logic control circuit 120 generates another control signal LG to control the switching of the lower arm transistor Q2. When the upper arm transistor Q1 and the lower arm transistor Q2 are both N-type MOS field-effect transistors, a high logic level of the control signal UG must be higher than the input voltage Vin to turn on the upper arm transistor Q1. At this time, the logic control circuit 120 can receive the bootstrap voltage Vbs such that the high logic level of the control signal UG is higher than the input voltage Vin. By switching the upper arm transistor Q1 and the lower arm transistor Q2, the ratio of the on-time to the off-time is adjusted to achieve a stable output voltage Vout.

Next, please refer to the third figure, which is a circuit diagram of a level adjustment circuit according to a first preferred embodiment of the present invention. The level adjustment circuit 100 includes a sample detection circuit 108 and a voltage drop generation circuit 109. The amplitude of the first signal S1 and the second signal S2 is confirmed according to the amplitude of the ripple signal S3, and then the phase node P is The voltage Vp or the level of the bootstrap voltage Vbs is shifted, so that the level of the quasi-square wave signal S0 is adjusted to achieve the function of adjusting the levels of the first signal S1 and the second signal S2.

The sampling detection circuit 108 includes an absolute value circuit 105, a filter 106, and a voltage detecting circuit 107. Since the ripple signal S3 is a DC The triangular wave voltage signal is divided into zero, so the ripple signal S3 passes through the absolute value circuit 105 in the sampling detection circuit 108, and a voltage signal S5 having twice the frequency and a DC component greater than zero is generated. The filter 106 includes a resistor R13 and a capacitor C13 for filtering the high frequency signal. The voltage signal S5 passes through the filter 106 to generate a constant current signal S6. Then, the voltage detecting circuit 107 detects the magnitude of the direct current signal S6 to determine whether the magnitude of the direct current signal S6 is equal to a predetermined target value or is within a predetermined target range, and generates a control signal SW accordingly. In this embodiment, the voltage detecting circuit 107 can be an amplifier for scaling the difference between the DC signal S6 and the predetermined target value to become the control signal SW. In the present invention, the predetermined target value may be zero without affecting the function of the substantially fixed ripple amount of the present invention. A level of the control signal SW represents the difference between the DC signal S6 and a predetermined target value or a predetermined target range.

The voltage drop generating circuit 109 receives the voltage Vp of the phase node P or the bootstrap voltage Vbs at one end, and generates a quasi-square wave signal S0 at the other end, and the voltage across the voltage is controlled by the control signal SW. The voltage drop generating circuit 109 is also controlled by the control signal UG. The control signal UG is generated to represent that the fixed on-time controller is in the On Time period, so the voltage drop generating circuit 109 operates only during the on period. If the application environment of the fixed on-time controller is typical (ie, it conforms to the preset application environment), the voltage drop generating circuit 109 does not have a voltage across the two ends, and the signals at both ends: the voltage Vp of the phase node P or the bootstrap voltage Vbs, the quasi-square The level of the wave signal S0 is synchronous and consistent. If the application environment of the fixed on-time controller is not typical, the amplitude of the ripple signal S3 will be shifted by a predetermined target value or a predetermined target range. Wai. At this time, the voltage detecting circuit 107 adjusts the voltage across the voltage drop generating circuit 109 through the control signal SW. Thereby, the level of the quasi-square wave signal S0 is adjusted to adjust the amplitude of the ripple signal S3 to a predetermined value or a predetermined range.

Please refer to the fourth figure, which is the signal waveform diagram of the level adjustment circuit shown in the third figure. At the time point t0 to t1, the application environment of the fixed on-time controller is a typical case. At this time, the amplitude of the ripple signal S3 is equal to a predetermined value, and the voltage detecting circuit 107 does not generate the control signal SW. Therefore, the voltage drop generating circuit 109 does not generate a voltage across, and the level of the quasi-square wave signal S0 is synchronized with and coincides with the voltage Vp of the phase node P or the bootstrap voltage Vbs. Please also refer to the second figure. At time t1, the frequency of the new application environment of the fixed on-time controller is lower, which is not typical. This causes the amplitude of the ripple signal S3 to also become larger and shift by a predetermined value. At this time, the magnitudes of the voltage signal S5 and the direct current signal S6 also become larger. At time t2, the voltage detecting circuit 107 detects that the magnitude of the direct current signal S6 is higher than a predetermined value, and generates the control signal SW to cause the voltage drop generating circuit 109 to form a voltage across the voltage, so that the level of the quasi-square wave signal S0 is lower than the voltage of the phase node P. Vp or the level of the bootstrap voltage Vbs. The level of the quasi-square wave signal S0 will return to the same size as the typical case. Therefore, the amplitude of the ripple signal S3 is also corrected to be the same as the typical case. Therefore, during the period from time t1 to time t2, the ripple of the ripple adjustment signal S4 generated by the signal introduction circuit 104 is large, but after the adjustment at the time point t2, the ripple of the ripple adjustment signal S4 is restored to The typical situation is the same. Therefore, in the typical case and the atypical case, the ripple adjustment signal S4 has substantially the same ripple size, and avoids the conventional fixed on-time controller, and the deviation between the actual output voltage and the ideal output voltage varies with the application. The problem of environmental change.

From the perspective of system stability, the traditional non-fixed ripple circuit architecture, when the system frequency is small or the output voltage Vout is high, the system has better stability due to its large ripple amplitude, but at the frequency. When the output voltage Vout is large or the output voltage Vout is low, the stability of the system becomes poor due to the small ripple amplitude. In contrast, the present invention utilizes a fixed-ripple circuit architecture that maintains good stability regardless of the external environment.

From the perspective of the ability of transient response, the traditional non-fixed ripple circuit architecture, when the system frequency is small or the output voltage Vout is high, because the ripple amplitude is large, when the load is pulled or pumped, the system cannot Operation at the maximum duty cycle results in a slower reaction rate of the system and a worse transient back strain. In contrast, the circuit structure of the fixed ripple of the present invention provides a better transient response during loading or unloading regardless of the external environment.

In addition, in the conventional non-fixed ripple circuit architecture, the comparison point between the voltage detection signal Vfb representing the output voltage Vout and the addition signal S13 (see the first figure) varies with the application, directly resulting in the output voltage Vout. It will vary with the application, making the accuracy of the output voltage Vout greatly reduced. The above comparison point refers to the level of the voltage detection signal Vfb and the addition signal S13 when the comparator 9 generates the pulse width modulation signal S9. However, in the circuit structure of the fixed ripple of the present invention, regardless of the external environment, the comparison point between the voltage detection signal Vfb and the ripple adjustment signal S4 is fixed, and the output voltage Vout has a fixed deviation, and the fixed deviation can be very Simple elimination, thus greatly improving the output The accuracy of the voltage Vout.

Referring to FIG. 5, it is a partial circuit diagram of a fixed on-time controller according to a second preferred embodiment of the present invention. Compared with the embodiment shown in FIG. 2, a level adjustment circuit 200 receives the output voltage Vout and the control signal UG to determine the adjustment amount of the amplitude of the ripple signal S3, instead of the phase adjustment circuit 100. The voltage Vp of P or the bootstrap voltage Vbs determines the adjustment amount of the amplitude of the ripple signal S3. Since the control signal UG is used to control the on and off of the upper arm transistor Q1, the control signal UG can be filtered to represent the current of the inductor L. The level adjustment circuit 200 generates a quasi-square wave signal S0 according to the output voltage Vout and the control signal UG. The circuit operations of the low-pass filters 101 and 102, the amplifier 103, and the comparison circuit 115 are the same as those of the embodiment shown in the second figure, and are not described herein again.

6 is a circuit diagram of a level adjustment circuit according to a second preferred embodiment of the present invention. The level adjustment circuit includes a sample detection circuit 208 and a voltage drop generation circuit 209 for generating a quasi-square wave signal S0 according to the output voltage Vout or the bootstrap voltage Vbs and the control signal UG. The sampling detection circuit 208 includes a ripple amplitude sampling circuit 205, a filter 106 and a voltage detecting circuit 207, and generates a control signal SWA or SWB according to the output voltage Vout and the control signal UG. The ripple amplitude sampling circuit 205 includes transistors M1 to M4, an error amplifier 206, a resistor R205, and a capacitor Cr. The transistor M3, the error amplifier 206 and the resistor R205 constitute a voltage to current converter. The transistor M3 is connected in series with the resistor R205, and the other end of the resistor R205 is grounded. One of the error amplifiers 206 is non-inverting The input terminal receives the output voltage Vout, and an inverting input terminal is connected to a connection point of the transistor M3 and the resistor R205. The error amplifier 206 will adjust an equivalent on-resistance of the transistor M3 such that the voltage across the resistor R205 coincides with the output voltage Vout. Therefore, the magnitude of the current flowing through the transistor M3 will be proportional to the output voltage Vout, which is generated by the current mirror formed by the transistors M1 and M2, and generates a current Ir to charge the capacitor Cr. The transistor M4 is connected in parallel with the capacitor Cr. When the upper arm transistor Q1 of the fixed on-time controller is turned on and enters the On Time period, the control signal UG is at a high level to turn on the transistor M4. At this time, the capacitor Cr is discharged, so that a level of the generated voltage signal S5 is zero. When the upper arm transistor Q1 of the fixed on-time controller is turned off and enters the off time period, the control signal UG is at a low level to turn off the transistor M4. At this time, the capacitor Cr is charged by the current Ir to generate a voltage signal S5 that rises with time, and its slope is proportional to the output voltage Vout. The filter 106 receives the voltage signal S5 and filters it to generate a DC signal S6. The voltage detecting circuit 207 generates the control signals SWA, SWB based on the direct current signal S6, so that the voltage drop generating circuit 209 adjusts its crossover voltage accordingly.

The voltage drop generating circuit 209 includes a current circuit and a resistor R14, and the current circuit has constant current sources IDC1 and IDC2 and controlled current sources I1 and I2. The constant current sources IDC1 and IDC2 and the controlled current sources I1 and I2 are controlled by the control signal UG, so that the constant current sources IDC1 and IDC2 and the controlled current sources I1 and I2 operate only during the on period. If the application environment of the fixed on-time controller is typical, the currents of the constant current source IDC1 and IDC2 and the controlled current sources I1 and I2 are equal, so there is no voltage across the resistor R14, and the signal across the resistor R14: The voltage Vp of the phase node P or the level of the bootstrap voltage Vbs and the quasi-square wave signal S0 are synchronized and coincident. If the application environment of the fixed on-time controller is not typical, the amplitude of the ripple signal S3 will be shifted by a predetermined target value or a predetermined target range. At this time, the voltage detecting circuit 207 adjusts a voltage across the voltage drop generating circuit 209 through the control signals SWA, SWB. Thereby, the level of the quasi-square wave signal S0 is adjusted to adjust the amplitude of the ripple signal S3 to a predetermined value or a predetermined range.

Referring to the seventh figure, there is shown a circuit diagram of a voltage detecting circuit in accordance with a preferred embodiment of the present invention. The voltage detection circuit includes comparators COM1 and COM2, D-type flip-flops DL1 to DL2, an inverter IN1, an inverse gate NOR1 to NOR3, or gates OR1 to OR3, a pulse generator OS, and counters CL1 and CL2. A non-inverting terminal of the comparator COM1 receives a minimum reference voltage VrefL, and an inverting terminal receives the DC signal S6. When the DC signal S6 is lower than the minimum reference voltage VrefL, a first comparison signal SH1 is generated. An inverting terminal of the comparator COM2 receives a maximum reference voltage VrefH, and a non-inverting terminal receives the DC signal S6. When the DC signal S6 is higher than the maximum reference voltage VrefH, a second comparison signal SH2 is generated. Wherein, the maximum reference voltage VrefH and the minimum reference voltage VrefL are maximum and minimum values of the direct current signal S6 that are allowed to deviate from the typical application, and the maximum reference voltage VrefH is higher than the minimum reference voltage VrefL. By the setting of the maximum reference voltage VrefH and the minimum reference voltage VrefL, it is ensured that the ripple signal S3 is adjusted to within a predetermined range corresponding to the maximum reference voltage VrefH and the minimum reference voltage VrefL. The inverse OR gate NOR1 receives an adjustment start signal SC4, an adjustment termination signal SSE, and an error signal NG_C. The error signal NG_C is representative The periodic signal of the on-time controller is described by the control signal LG in this embodiment. The initial value of the adjustment start signal SC4 is a low level, and is turned to a high level when a predetermined time is started after the soft start of the fixed on time controller starts. The initial value of the adjustment termination signal SSE is a low level, and when the soft start ends, it changes to a high level. The main function of the adjustment start signal SC4 and the adjustment termination signal SSE is to confirm whether the system is approaching or entering a stable operation state. In addition to the above-mentioned soft start determination, it is also possible to judge whether the output voltage Vout reaches a predetermined voltage value. For example, the adjustment start signal SC4 represents the output voltage Vout to a first target value, and the adjustment termination signal SSE represents the output voltage Vout to a second target value, wherein the first target value is less than a predetermined stable output voltage of the output voltage Vout, And the second target value is greater than the first target value and less than or equal to the preset stable output voltage. When the fixed on-time controller is in normal operation, when the adjustment start signal SC4 is at the high level until the adjustment termination signal SSE is turned to the high level, whenever the error signal NG_C is at the low level, that is, the lower arm transistor Q2 is turned off. , reverse or gate NOR1 outputs a high level signal. During this adjustment, the voltage detection circuit performs voltage detection and judgment in accordance with the state of the lower arm transistor Q2.

The D-type flip-flops DL1~DL2, the pulse generator OS, and the OR gate OR1 form a detection and clear circuit. The detection and clearing circuit is responsible for determining whether the first comparison signal SH1 and the second comparison signal SH2 have a high level during the adjustment period. When the adjustment start signal SC4 is turned to the high level, the inverter IN1 outputs a low level signal to activate the counters CL1~CL2. When the error signal NG_C is at a low level, the inverse OR gate NOR1 generates a high level signal, and the pulse generator is touched. The OS generates a pulse width signal having a predetermined pulse width to OR gate OR1, so that the output signals of the D-type flip-flops DL1 DL DL2 are low-level (return to zero). When the control signal LG is at a high level, during each period of the adjustment period, the DC signal S6 is lower than the minimum reference voltage VrefL, and the comparator COM1 generates the first comparison signal SH1, so that the D-type flip-flop DL1 outputs a first A counting signal CP1. Similarly, during each period of the adjustment period, the DC signal S6 is higher than the maximum reference voltage VrefH, and the comparator COM2 generates the second comparison signal SH2, so that the D-type flip-flop DL2 outputs a second count signal CP2. The counter CL1 is responsible for detecting whether the number of consecutive high-level occurrences of the first count signal CP1 reaches a predetermined value. The counter CL2 is responsible for detecting whether the number of consecutive high-level occurrences of the second count signal CP2 reaches a preset value. During any period of the adjustment period, the direct current signal S6 is within the range of the maximum reference voltage VrefH and the minimum reference voltage VrefL, so that the first count signal CP1 and the second count signal CP2 are re-counted. Such a circuit design can effectively avoid misjudgment caused by noise interference. The counter CL1 determines whether or not to reduce the current of the controlled current sources I1 and I2 based on whether the result of the counting reaches a predetermined value. Thus, the resistor R14 will have a bias current flowing from the right side to the left side, so that the quasi-square wave signal S0 is higher than the voltage Vp of the phase node P or the bootstrap voltage Vbs. Thereby, the amplitude of the ripple signal S3 can be raised upwards and the DC signal S6 is returned to the minimum reference voltage VrefL. Similarly, the counter CL2 determines whether or not to increase the current of the controlled current sources I1 and I2 based on whether the result of the counting reaches a predetermined value. Thus, the resistor R14 will have a bias current flowing from the left side to the right side, so that the quasi-square wave signal S0 is lower than the voltage Vp of the phase node P or the bootstrap voltage Vbs. Thereby, the amplitude of the ripple signal S3 can be adjusted downwards. Let the DC signal S6 return to the maximum reference voltage VrefH.

Of course, in addition to the two comparison levels of the maximum reference voltage VrefH and the minimum reference voltage VrefL, the present invention can add other comparison levels according to requirements to achieve more order adjustment capability.

Please refer to the eighth figure, which is a signal waveform diagram of the embodiment shown in the sixth figure and the seventh figure. At the time point t0 to t1, the application environment of the fixed on-time controller is a typical case. At this time, the amplitude of the ripple signal S3 is equal to a predetermined value, and the voltage detecting circuit 207 does not generate the control signals SWA and SWB. Therefore, the voltage drop generating circuit 209 does not generate a voltage across, and the level of the quasi-square wave signal S0 is synchronized with and coincides with the voltage Vp of the phase node P or the bootstrap voltage Vbs. At time t1, the lower frequency of the new application environment of the fixed on-time controller is not typical. At this time, the magnitudes of the voltage signal S5 and the direct current signal S6 also become larger. This causes the direct current signal S6 to be higher than the maximum reference voltage VrefH. The voltage detecting circuit 207 generates the control signal SWA or SWB to adjust the controlled current sources I1 and I2, so that the ripple signal S3, the voltage signal S5, the direct current signal S6, and the ripple adjustment signal S4 are adjusted to a predetermined interval. The DC signal S6 is adjusted to be within the range of the maximum reference voltage VrefH and the minimum reference voltage VrefL until the time point t2 after the adjustment period has elapsed.

Referring to FIG. 9, a partial circuit diagram of a fixed on-time controller according to a third preferred embodiment of the present invention. In contrast to the embodiment shown in the second figure, the voltage amplifier of amplifier 103 is changed to a transconductance amplifier 203. The transconductance amplifier 203 receives the first signal S1 and the second signal S2 to generate a current ripple signal Si3 according to the level difference between the first signal S1 and the second signal S2. One The level adjustment circuit 300 is coupled to an output end of the transconductance amplifier 203 to sample the amplitude of the current ripple signal Si3, and adjust the level of the quasi-square wave signal S0 according to the sampling result, thereby adjusting the first signal S1 and The second signal S2. When the amplitude of the ripple signal S3 is affected by different application environments, the fixed on-time controller can correct the amplitude of the ripple signal S3 by such a circuit design to reduce the amplitude of the amplitude in different application environments. The difference is even a fixed magnitude and is not affected by the application environment. A comparison circuit 215 includes a signal introduction circuit 204 and a comparator 111. In this embodiment, the signal introduction circuit 204 is a resistor, and the current ripple signal Si3 flows through the signal introduction circuit 204 to generate a bias voltage, so that the reference voltage signal Vref is biased to generate a ripple adjustment signal S4 input comparator. The non-inverting terminal of the 111, and the inverting terminal of the comparator 111 receives the voltage detecting signal Vfb. The comparator 111 compares the voltage detection signal Vfb and the ripple adjustment signal S4 to generate a comparison result signal S11. When the level of the ripple adjustment signal S4 is higher than the voltage detection signal Vfb, the comparison result signal S11 is a high level; when the level of the ripple adjustment signal S4 is lower than the voltage detection signal Vfb, the comparison result signal S11 is Low level. Of course, the signal introduction circuit 204 can also be changed to introduce the current ripple signal Si3 into the voltage detection signal Vfb to become the ripple adjustment signal S4. At this time, the comparator 111 receives the reference voltage signal Vref from the non-inverting terminal, and inverts. The end receiving the ripple adjustment signal S4 can achieve the same effect as described above.

Referring to the tenth figure, there is shown a circuit diagram of a level adjusting circuit according to a third preferred embodiment of the present invention. The level adjustment circuit includes a sampling detection circuit 308 and a voltage drop generation circuit 209, according to the current ripple signal Si3 The amplitude of the adjustment of the level of the first signal S1 and the second signal S2 is confirmed, and then the voltage of the phase node P or the level of the bootstrap voltage Vbs is offset, so that the level of the quasi-square wave signal S0 is adjusted. The function of adjusting the first signal S1 and the second signal S2 is achieved.

The sample detection circuit 308 includes a current absolute value circuit 305, a filter 106, and a voltage detection circuit 207. Since the current ripple signal Si3 is a triangular wave current signal with a zero DC component, the current ripple signal Si3 passes through the current absolute value circuit 305 in the sampling detection circuit 308, and generates a current having twice the frequency and a DC component greater than zero. Signal Si5. The current signal Si5 is converted into a voltage signal S5 via a resistor. The filter 106 includes a resistor R13 and a capacitor C13 for filtering the high frequency signal. The voltage signal S5 passes through the filter 106 to generate a DC signal S6. Then, the voltage detecting circuit 207 detects the magnitude of the direct current signal S6 to determine whether the magnitude of the direct current signal S6 is equal to a predetermined target value or is located in a predetermined target range, and generates control signals SWA, SWB accordingly. For the voltage detection circuit 207 and the voltage drop generation circuit 209, refer to the description of the corresponding embodiment, and details are not described herein again.

Referring to FIG. 11 , it is a partial circuit diagram of a fixed on-time controller according to a fourth preferred embodiment of the present invention. Compared with the embodiment shown in FIG. 9 , the level adjustment circuit 300 is changed to the level adjustment circuit 200 for receiving the output voltage Vout and the control signal UG to determine the adjustment amount of the amplitude of the ripple signal S3. The level adjustment circuit 300 determines the adjustment amount of the amplitude of the ripple signal S3 by the voltage Vp of the phase node P or the bootstrap voltage Vbs. The level adjustment circuit 200 generates a quasi-square wave signal according to the output voltage Vout and the control signal UG. S0. The circuit operations of the low-pass filters 101 and 102, the transconductance amplifier 203, and the comparison circuit 215 are the same as those of the embodiment shown in FIG. 9, and are not described herein again.

Referring to FIG. 12, a partial circuit diagram of a fixed on-time controller according to a fifth preferred embodiment of the present invention. Compared to the embodiment shown in the second figure, the amplifier 103 is changed to a controllable amplifier 303, and the voltage drop generating circuit 109 in the level adjusting circuit is omitted. The controllable amplifier 303 receives the control signal SW generated by the sampling detection circuit 108, and raises or lowers the gain value of the controllable amplifier 303 according to the control signal SW. The controllable amplifier 303 receives the first signal S1 and the second signal S2 to generate a ripple signal S3 according to the level difference of the first signal S1 and the second signal S2 and the gain value thereof, thereby adjusting the amplitude of the ripple signal S3. effect.

Referring to a thirteenth aspect, a partial circuit diagram of a fixed on-time control according to a sixth preferred embodiment of the present invention. Compared with the embodiment shown in FIG. 12, the sampling detecting circuit 108 is changed to a sampling detecting circuit 408 for generating the control signal SW according to the output voltage Vout and the control signal UG. The sampling detection circuit 408 includes a ripple amplitude sampling circuit 205, a filter 106, and a voltage detecting circuit 307. The voltage detecting circuit 307 can be an inverse function circuit, that is, its operation conforms to K=Y*X, where K is a constant, X is an input signal, and Y is an output signal. Therefore, when the level of the direct current signal S6 is higher, the level of the control signal SW is smaller; For the rest of the circuit operation, refer to the description of the corresponding circuit in other embodiments, and details are not described herein again.

Please refer to the fourteenth figure, which is a seventh preferred embodiment according to the present invention. A schematic diagram of a partial circuit of the fixed on-time control of the embodiment. Compared with the embodiment shown in Fig. 12, the controllable amplifier 303 is changed to the transconductance amplifier 403, and the sampling detection circuit 108 is changed to a sampling detection circuit 508. In addition, a comparison circuit 315 includes a signal introduction circuit 304 and a comparator 111. The sampling detection circuit 508 includes a current absolute value circuit 305, a filter 106, and a voltage detection circuit 307. For the circuit operation, refer to the description of the corresponding circuit in other embodiments, and details are not described herein again. The sampling detection circuit 508 generates a control signal SW according to the amplitude of the current ripple signal Si3. The signal introduction circuit 304 includes an adjustable resistance circuit for adjusting or lowering the impedance value according to the control signal SW. The current ripple signal Si3 flows through the signal introduction circuit 304, and generates a bias voltage according to the impedance value, so that the reference voltage signal Vref is biased to generate the ripple adjustment signal S4 to be input to the non-inverting terminal of the comparator 111. The inverting terminal of the comparator 111 receives the voltage detecting signal Vfb. The comparator 111 compares the voltage detection signal Vfb and the ripple adjustment signal S4 to generate a comparison result signal S11. Of course, the signal introduction circuit 304 can also be changed to introduce the current ripple signal Si3 into the voltage detection signal Vfb to become the ripple adjustment signal S4. At this time, the comparator 111 receives the reference voltage signal Vref by the non-inverting terminal, and inverts. The end receiving the ripple adjustment signal S4 can achieve the same effect as described above.

Referring to a fifteenth diagram, there is shown a partial circuit diagram of a fixed on-time control according to an eighth preferred embodiment of the present invention. The sample detection circuit 508 is changed to a sample detection circuit 608 as compared to the embodiment shown in FIG. The sampling detection circuit 608 includes a ripple amplitude sampling circuit 205, a filter 106, and a voltage detecting circuit 307, and generates control according to the output voltage Vout and the control signal UG. Signal SW. The comparison circuit 315 generates a bias voltage according to the control signal SW and the current ripple signal Si3, so that the reference voltage signal Vref or the voltage detection signal Vfb is biased to adjust its level, thereby achieving the actual output voltage and the ideal output of the present invention. The value of the voltage deviation varies with the application environment.

In summary, the present invention determines the amplitude of the ripple based on the amplitude or output voltage of the ripple signal and the control signal, and adjusts the amplitude of the ripple accordingly. In this way, the fixed on-time controller of the present invention can control the ripple amplitude in a predetermined value or a predetermined range in different application environments, so as to avoid the deviation between the actual output voltage and the ideal output voltage as the application environment changes. problem.

As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial applicability. The present invention has been disclosed in the foregoing, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the present invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

1‧‧‧Voltage detection circuit

100‧‧‧ level adjustment circuit

101, 102‧‧‧ low pass filter

103‧‧‧Amplifier

104‧‧‧Signal introduction circuit

110‧‧‧Ripple generator

111‧‧‧ comparator

115‧‧‧Comparative circuit

120‧‧‧Logic Control Circuit

BS‧‧‧ bootstrap circuit

C11‧‧‧ capacitor

C12‧‧‧ capacitor

Cout‧‧‧ output capacitor

IL‧‧‧Inductor Current

L‧‧‧Inductance

LG, UG‧‧‧ control signals

P‧‧‧ phase node

Q1‧‧‧Upper arm transistor

Q2‧‧‧ Lower arm transistor

R1, R2‧‧‧ resistance

R11‧‧‧ resistance

R12‧‧‧ resistance

S0‧‧‧ quasi-square wave signal

S1‧‧‧ first signal

S2‧‧‧ second signal

S3‧‧‧ ripple signal

S4‧‧‧ ripple adjustment signal

S11‧‧‧ comparison result signal

Vbs‧‧‧ bootstrap voltage

Vfb‧‧‧ voltage detection signal

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

Vp‧‧‧ voltage

Vref‧‧‧reference voltage signal

Claims (13)

A fixed on-time controller for controlling switching of a conversion circuit to generate an output voltage, the fixed on-time controller comprising: a ripple generator, wherein a current component flows according to an inductance including one of the conversion circuits a first signal and a second signal including the output voltage component or the current component of the inductor to generate a ripple signal, wherein the second signal includes the current component of the inductor, the second signal One of the amplitudes is smaller than the amplitude of the first signal, and the ripple generator includes a level adjustment circuit for adjusting the level of the first signal and the second signal according to the amplitude of the ripple signal; a comparison circuit, receiving the ripple signal, a reference voltage signal, and a voltage detection signal representing the output voltage, and adjusting one of the reference voltage signal and the voltage detection signal according to the ripple signal to generate One of the ripple information of the ripple signal is a ripple adjustment signal, and the comparison circuit compares the ripple adjustment signal with the reference voltage signal and the voltage detection signal. Generating a comparison result signal; and a control logic circuit having one of a fixed pulse width control signal for controlling the switching circuit of the switching signal generated based on the comparison result. The fixed on-time controller of claim 1, wherein the level adjustment circuit receives an adjustment start signal, and adjusts the level of the first signal and the second signal after receiving the adjustment start signal, and The adjustment start signal To represent the fixed on-time controller after starting A. for a predetermined time; or B. the output voltage reaches a predetermined voltage. The fixed on-time controller of claim 1 or 2, wherein the ripple generator further comprises a voltage detecting circuit for comparing the ripple signal with a predetermined range or a predetermined value, The level adjustment circuit adjusts the levels of the first signal and the second signal according to the comparison result. The fixed on-time controller according to claim 3, wherein the level adjusting circuit comprises a resistor and a current circuit, and the current circuit adjusts a current flowing through the resistor according to the comparison result of the voltage detecting circuit. . A fixed on-time controller for controlling switching of a conversion circuit to generate an output voltage, the fixed on-time controller comprising: a ripple generator, wherein a current component flows according to an inductance including one of the conversion circuits a first signal and a second signal including the output voltage component or the current component of the inductor to generate a ripple signal, wherein the second signal includes the current component of the inductor, the second signal One of the amplitudes is smaller than the amplitude of the first signal, and the ripple generator includes a level adjustment circuit for adjusting the ripple signal according to the output voltage and a control signal or according to one of the ripple signals The amplitude of the amplitude; a comparison circuit that receives the ripple signal, a reference voltage signal, and represents the input And outputting a voltage detection signal according to the ripple signal, and adjusting one of the reference voltage signal and the voltage detection signal according to the ripple signal to generate a ripple adjustment signal having a ripple information of the ripple signal, Comparing the ripple adjustment signal with the reference voltage signal and the voltage detection signal to generate a comparison result signal, and a logic control circuit for generating the control with a fixed pulse width according to the comparison result signal Signal to control the switching of the conversion circuit. The fixed on-time controller of claim 5, wherein the ripple generator comprises an amplifier, and the ripple signal is generated according to a level difference between the first signal and the second signal, and the level is generated. The adjustment circuit adjusts the gain value of one of the amplifiers. The fixed on-time controller of claim 5, wherein the ripple generator comprises an amplifier, the level adjustment circuit adjusts the level of the first signal and the second signal, and the amplifier according to the The ripple signal is generated by the difference between the first signal and the second signal. The fixed on-time controller of claim 5, wherein the level adjustment circuit receives an adjustment start signal, and adjusts the level of the first signal and the second signal after receiving the adjustment start signal, and The adjustment start signal is A. for a predetermined time after the start of the fixed on-time controller; or B. The output voltage reaches a predetermined voltage. The fixed on-time controller of claim 5 or 8, wherein the ripple generator further comprises a voltage detecting circuit for comparing the ripple signal with a predetermined range or a predetermined value, The level adjustment circuit adjusts the levels of the first signal and the second signal according to the comparison result. The fixed on-time controller according to claim 9, wherein the level adjusting circuit comprises a resistor and a current circuit, and the current circuit adjusts a current flowing through the resistor according to the comparison result of the voltage detecting circuit. . A fixed on-time controller for controlling switching of a conversion circuit to generate an output voltage, the fixed on-time controller comprising: a ripple generator, wherein a current component flows according to an inductance including one of the conversion circuits a first signal and a second signal including the output voltage component or the current component of the inductor to generate a ripple signal, wherein the second signal includes the current component of the inductor, the second signal One of the amplitudes is smaller than the amplitude of the first signal, and the ripple generator includes a level adjustment circuit for generating an adjustment signal according to the output voltage and a control signal or according to one of the ripple signals; a comparison circuit receives the ripple signal, a reference voltage signal, and a voltage detection signal representing the output voltage, and adjusts the parameter according to the ripple signal Testing one of the voltage signal and the voltage detection signal to generate a ripple adjustment signal having a ripple information of the ripple signal, the comparison circuit comparing the ripple adjustment signal with the reference voltage signal and the voltage Detecting another signal to generate a comparison result signal, wherein the comparison circuit includes a signal introduction circuit for adjusting an amplitude of the ripple adjustment signal according to the adjustment signal; and a logic control circuit, according to the comparison result signal The control signal having a fixed pulse width is generated to control the switching of the conversion circuit. The fixed on-time controller of claim 11, wherein the ripple generator comprises a transduction amplifier, and the ripple signal is generated according to the first signal and the second signal, wherein the signal introduction circuit comprises a The adjustable resistance circuit is coupled to the ripple signal and the reference voltage signal and the voltage detection signal to generate the ripple adjustment signal, and an impedance value of the adjustable resistance circuit is adjusted according to the adjustment signal . The fixed on-time controller of claim 11, wherein the level adjustment circuit receives an adjustment start signal, and generates the adjustment signal after receiving the adjustment start signal, and the adjustment start signal is representative of the fixed conduction. After the time controller is started, A. reaches a predetermined time; or B. The output voltage reaches a predetermined voltage.