TWI463768B - Dc-to-dc converter - Google Patents

Description

DC to DC Buck Converter

The present invention relates to an electrical energy conversion technique, and more particularly to a DC-to-DC buck converter.

Today's DC-to-DC buck converters are implemented in a variety of ways, such as voltage mode control, current mode control, and constant on time mode control. ), etc., in order to improve the stability of the output voltage, reduce the jitter during voltage switching, and improve the conversion efficiency. 1 is a schematic diagram of a DC-to-DC buck converter 100 employing a fixed on-time control mode.

The DC-to-DC buck converter 100 (or the buck converter 100) is provided with a driving circuit 110, an upper bridge element (for example, a transistor Qp), a lower bridge element (for example, a transistor Qn), an output inductor L, For example, a voltage dividing circuit 120 composed of resistors R1 and R2, a comparator 130, a fixed on-time controller 140, and an output capacitor 150. There is an inductor current I _L flowing through the output inductor L. In an ideal case, the buck converter 100 can know whether the externally supplied output voltage Vout is stable through the change of the inductor current I _L , thereby automatically adjusting the external output energy, but currently there is little way to directly measure the inductor current I. The change of _L. Therefore, the buck converter 100 senses the change of the inductor current I _L through the output voltage Vout, thereby determining whether to continue to provide the output energy. In other words, the buck converter 100 divides the output voltage Vout by the voltage dividing circuit 120 to form a feedback voltage V _FB related to the change in the inductor current I _L . The comparator 130 receives the reference voltage V _REF and the feedback voltage V _FB to detect whether the output voltage Vout is lower than the reference voltage V _REF and triggers the fixed on-time controller 140 when the output voltage Vout is lower than the reference voltage V _REF .

After the fixed on-time controller 140 is triggered, a pulse wave having a fixed on-time is output to the reset terminal of the driving circuit 110, so that the driving circuit 110 turns on the upper bridge element (the transistor Qp) and turns off the lower bridge element (the transistor) Qn), energy is supplied to the output of the buck converter 100 through the input voltage Vin and the output inductor L. When the pulse of the fixed on-time provided by the fixed on-time controller 140 ends, the drive circuit 110 turns off the upper bridge element (transistor Qp) and turns on the lower bridge element (transistor Qn) to stop supplying energy to its output.

Therefore, the buck converter 100 adopting the fixed on-time control mode captures the change of the inductor current I _L through the output voltage Vout, and the output terminal expects that the output capacitor 150 can have a large equivalent series resistance (equivalent series) The ESR)R _ESR and the smaller equivalent series inductance (ESL) L _ESL enable the time constant of the product of the output capacitor value C _OUT and its equivalent series resistance R _ESR in the output capacitor 150 to be sufficient The value avoids the stability of the system to the subharmonic oscillation and increases the noise tolerance.

FIG. 2 is a diagram showing the influence of the equivalent series resistance R _ESR on the output voltage Vout in the time domain with the same output capacitance value. In simple terms, the upper inductor current I _{L in} Figure 2 is the ideal triangular waveform, while the left sequential signals V _ESL , V _ESR and V _CO represent the equivalent series inductance L _ESL , equivalent series resistance, respectively. R _ESR and the schematic voltage component of the output capacitance value C _OUT . The signals V _ESL , V _ESR and V _CO will be proportionally changed according to the magnitudes of the equivalent series inductance L _ESL , the equivalent series resistance R _ESR and the output capacitance value C _OUT , respectively, and will be combined with each other as the output voltage Vout. . As can be seen from the left side of Fig. 2, the inductor current I _L and the waveform of the signal V _ESR are linear with each other, but the inductor current I _L is integral and differential with the signal V _ESL and the signal V _CO , respectively.

Therefore, when the output capacitance values C _{OUT are} set to be the same, the output voltages Vout1 to Vout3 shown on the right side of FIG. 2 will have different output ripples due to the large and small resistance values of the equivalent series resistance R _ESR . This leads to poor system stability. When considering the delay of the output voltage, the influence of V _ESL can be ignored. When the resistance value of the equivalent series resistance R _ESR is too small, the output voltage (for example, Vout1~Vout3) is mainly determined by V _CO , so the feedback mechanism is adopted. The obtained output voltages Vout1 VVout3 and current I _L have a phase difference of time delay, resulting in system instability. If the problem of noise interference is considered, the excessive component of the signal V _ESL will cause the output voltages Vout1 VVout3 to generate discontinuous waveforms, as shown by the vertical dotted lines C and D on the right side of FIG. 2, and the discontinuous waveform changes. It will make the feedback system interfere and thus unstable. Wherein, when the feedback voltage V _FB corresponding to the output voltages Vout1 VVout3 is lower than the reference voltage V _REF (the horizontal dotted line appearing in the waveforms of the output voltages Vout1 VVout3), the fixed on-time controller of FIG. 1 can be correctly triggered at the broken line C 140.

Therefore, the equivalent series resistance R _ESR having a small resistance value will easily cause a judgment error in the comparator 130 of FIG. 1 and reduce the system stability of the buck converter 100. In the past, manufacturers will select an equivalent series resistance R _ESR with sufficient value to make the output voltage Vout have significant chopping to ensure the stability of the buck converter 100. However, in recent years, manufacturers have gradually adopted low-cost capacitors with low equivalent series resistance as output capacitors, such as multi-layer ceramic capacitors (MLCC), thereby reducing the stability of the buck converter 100. Degrees and tolerance of noise, leading to the above problems. At present, many manufacturers usually ignore the influence of the output capacitor and its equivalent series resistance on the buck converter, or use other circuit implementation methods to expect better results.

The invention provides a DC-to-DC buck converter, which can increase the system stability of the buck converter, reduce the numerical limit on the output capacitor and its equivalent series resistance, and improve the tolerance of the buck converter to noise. At the same time, reduce the effects of the series-connected inductance on the output to the output capacitor path.

The invention provides a DC-to-DC buck converter comprising a drive circuit, at least one pair of upper and lower bridge components, an output capacitor, a phase lead-in unit, and a constant on-time (COT) control unit. The upper bridge component and the lower bridge component are connected to each other and controlled by a pulse width modulation signal generated by the driving circuit, which alternately switches and provides an output voltage according to the input voltage to transmit the output inductor and the output capacitor. The phase lead-in unit receives the first differential signal generated according to the output voltage and the reference voltage, and performs phase advancement of the first differential signal to provide the second differential signal. The fixed on-time control unit is coupled to the phase lead-in unit, and receives and determines whether the energy of the output voltage is sufficient according to the second differential signal, thereby outputting a pulse wave signal with a fixed on-time to the driving circuit, so that A drive circuit generates the pulse width modulation signal.

In an embodiment of the invention, the DC-DC buck converter further includes a margin enhancement unit coupled to the drive circuit and the phase lead unit. The boundary enhancement unit receives the feedback voltage generated according to the output voltage, and adjusts the feedback voltage according to the specific period of the pulse width modulation signal, and generates the first according to the adjusted feedback voltage and the reference voltage. Differential signal.

In an embodiment of the invention, the boundary enhancement unit includes a step booster. The step booster boosts the feedback voltage by an offset voltage during the turn-on of the lower bridge element to provide an adjusted feedback voltage in accordance with the pulse width modulation signal. The first differential signal of the positive phase terminal is an adjusted feedback voltage, and the first differential signal of the inverting terminal is a reference voltage.

In an embodiment of the invention, the step booster includes a bias generating circuit and a control switch. The negative terminal of the bias generating circuit receives the feedback voltage and produces an adjusted feedback voltage at the positive terminal of the bias generating circuit. The control terminal of the control switch receives the pulse width modulation signal, the first end of the control switch receives the feedback voltage, and the second end of the control switch is coupled to the positive terminal of the bias generation circuit. The control switch conducts its second end and its output during conduction of the lower bridge component to deliver the adjusted feedback voltage. Also, the control switch conducts its first end and its output during the non-conduction of the upper bridge element to deliver the feedback voltage.

In an embodiment of the invention, the boundary enhancement unit further includes a noise canceller that receives the first differential signal to filter out the noise portion of the first differential signal.

In an embodiment of the invention, the boundary enhancement unit further includes a noise synchronizer, and the first end receives the adjusted feedback voltage. The noise is the same The second end of the stepper receives the reference voltage to add a noise portion of the adjusted feedback voltage to the reference voltage. The phase lead-in unit receives the adjusted feedback voltage and the reference voltage, and transmits the adjusted feedback voltage and the noise portion of the reference voltage through the differential input.

In an embodiment of the invention, the phase lead-in unit includes a zero compensation circuit that provides zero offset and phase advances the first differential signal to generate a second differential signal.

In an embodiment of the invention, the zero point compensation circuit comprises a band pass filter. The inverting input of the band pass filter receives the first differential signal of the positive phase terminal, the positive phase input terminal of the band pass filter receives the first differential signal of the inverting terminal, and the two output ends of the band pass filter The second differential signal is separately provided. In another embodiment of the invention, the zero point compensation circuit described above is implemented as a high pass filter.

In an embodiment of the invention, the fixed on-time control unit includes a comparator and a fixed on-time controller. A comparator is coupled to the phase lead unit. The non-inverting input terminal and the inverting input terminal of the comparator respectively receive the second differential signal of the positive phase terminal and the inverting terminal to generate a comparison signal according to the comparison result. The fixed on-time controller is triggered by the comparison signal to output a pulse wave signal with a fixed on-time to the driving circuit, so that the driving circuit generates a pulse width modulation signal.

Based on the above, the DC-to-DC buck converter disclosed in the embodiment of the present invention increases the phase leading unit in the front stage of the comparator, thereby adjusting the output voltage so that the waveform is restored in phase lead manner to the same phase similar to the inductor current. Waveform. In addition, the boundary strengthening unit raises the feedback voltage during the conduction of the lower bridge component, and differentially applies the feedback voltage and the reference voltage. And high-frequency filtering to reduce common-mode noise, in order to avoid false triggering of the fixed on-time control unit. As such, the DC-to-DC buck converter increases the system stability of the buck converter, increases the buck converter's tolerance for noise, and reduces the numerical limits on the output capacitor and its equivalent series resistance.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 3A. FIG. 3A is a functional block diagram showing a DC-to-DC buck converter 300 according to an embodiment of the invention. As shown in FIG. 3A, the DC-DC buck converter 300 proposed in the present application can be applied to various power supplies for DC-to-DC conversion, for example, in consumer electronic devices, mobile phones, cameras, and the like. The buck converter 300 includes a drive circuit 310, at least one pair of upper and lower bridge elements, an output inductor L, an output capacitor 360, a phase lead-in unit 330, and a constant on-time (COT) control unit 340. In the embodiment, the buck converter 300 further includes a voltage dividing circuit 350.

The upper bridge element and the lower bridge element of the embodiment of the present invention are exemplified by a transistor Qp and a transistor Qn, respectively. The first end of the transistor Qp (eg, the source terminal) receives the input voltage Vin, the second end of the transistor Qp (eg, the 汲 terminal) and the first end of the transistor Qn (eg, the 汲 terminal) pass through the junction E Connected, and the second end of the transistor Qn (eg, the source terminal) is grounded. The receiving ends of the transistor Qp and the transistor Qn respectively receive the pulse width modulation signals Gh and G1 provided by the driving circuit 310, so that the transistor Qp and the transistor Qn are controlled by the pulse width modulation signal Gh of the driving circuit 310 and Gl. The first end of the output inductor L is coupled to the upper bridge component (the second end of the transistor Qp) through the contact point E and Lower bridge element (first end of transistor Qn). The second end of the output inductor L acts as the output of the DC-to-DC buck converter 300 and produces an output voltage Vout. In addition, the first end of the output capacitor 360 is coupled to the output of the buck converter 300, and the other end of the output capacitor 360 is grounded to maintain a voltage drop of the output voltage Vout.

Therefore, the driving circuit 310 generates the pulse width modulation signals Gh and G1 according to the pulse signal Sp having the fixed on-time provided by the fixed on-time (COT) control unit 340, thereby alternately switching the transistors Qp and Qn. The charge and discharge effects of the output inductor L provide an output voltage Vout to other wafers or devices that require electrical energy supply.

In general, if the time constant obtained by multiplying the output capacitance value C _OUT of the output capacitor 360 by its equivalent series resistance R _ESR can reach a sufficient value, the buck converter 300 can be reduced to encounter the subharmonic. Concussive stability issues and increased noise tolerance. For example, if a solid capacitor (SP-CAP) is selected as the output capacitor 360, since the equivalent series resistance R _{ESR is} large, the waveform of the output voltage Vout can be more chopped, so that the COT control unit 340 can directly receive the output. When the output voltage Vout determines whether the energy of the inductor current I _L in the output capacitor L is sufficient, the accuracy of the judgment can be improved.

However, based on factors such as cost, manufacturers are hoping to use a multilayer ceramic capacitor (MLCC) with a low equivalent series resistance R _ESR as the output capacitor 360, resulting in the above-mentioned system instability and mismatch in the entire buck converter 300. Signal interference and other phenomena. Herein, the embodiment of the present invention adds a phase lead-in unit 330 to the previous stage of the COT time control unit 340 of FIG. 3A, and adjusts the output voltage Vout so as to be similar to the waveform characteristic of the capacitor current I _L , thereby increasing the buck converter. The system stability of the 300 itself reduces the numerical limit on the output capacitor and its equivalent series resistance, and improves the tolerance of the buck converter 300 to the noise in the output voltage Vout, while reducing the output to the output capacitor path. The effect of series inductance.

Referring to FIG. 3A in detail, the voltage dividing circuit 350, the phase leading unit 330, and the COT control unit 340 will be described in detail below. The voltage dividing circuit 350 includes resistors R1 and R2, and one end of the resistor R1 is coupled to the output of the buck converter 300. The other end of the resistor R1 is coupled to one end of the resistor R2 to form a feedback terminal F, and the other end of the resistor R2 is grounded. Thereby, the voltage dividing circuit 350 divides the output voltage Vout to supply the feedback voltage V _FB from the feedback terminal F to the first differential input terminal of the phase leading unit 330. That is, the first differential signal V _{DIFF_1} of the positive phase terminal of the present embodiment is the feedback voltage V _FB .

The phase lead unit 330 is coupled to the voltage dividing circuit 350. The phase lead unit 330 receives the feedback voltage V _FB from its first differential input terminal as the first differential signal V _{DIFF_1 of the} positive phase terminal and the reference voltage V _REF from its second differential input terminal by means of differential processing. The second differential signal V _{DIFF_2} as the inverting terminal is used to reduce the common mode noise of the first differential signal V _{DIFF_1} . And, the phase leading unit 330 performs phase-leading of the first differential signal V _{DIFF_1} to provide a signal second differential signal V _{DIFF_2} synchronized with the inductor current I _L , so that the processed second differential signal V _{DIFF_2} can be restored back to the waveform in phase with the inductor current I _L during the turn-on of the lower bridge element. The fixed on-time control unit 340 is coupled to the phase lead-in unit 330, which receives the second differential signal V _{DIFF_2} and determines whether the energy of the output voltage Vout is sufficient according to the second differential signal V _{DIFF_2} , thereby outputting a pulse wave with a fixed on-time. The signal Sp is applied to the driving circuit 310 to cause the driving circuit 310 to generate the pulse width modulation signals Gh and G1.

In the ideal case, the buck converter 300 of the present invention can be implemented in FIG. 3A. However, in the process of actually implementing the above embodiment, some components may cause undesired noise interference to the first differential signal V _{DIFF_1} . If the noise interference is acceptable, the circuit of FIG. 3A can be used. However, if the noise interference causes the system to still be unstable, the embodiment of the present invention can be added in the previous stage of the phase leading unit 330. The boundary strengthening unit 320 is used to reduce noise interference, as shown in FIG. 3B. FIG. 3B is a functional block diagram illustrating another DC-to-DC buck converter 300 in accordance with an embodiment of the present invention.

Referring to FIG. 3B, the difference between FIG. 3A and FIG. 3B is that the boundary enhancement unit 320 is added to FIG. 3B. The boundary strengthening unit 320 is coupled to the driving circuit 310, the phase leading unit 330, and the voltage dividing circuit 350. Feedback voltage V _FB, and based on the PWM signal Gh or Gl conduction / non-conduction period (so-called specific period) through the boundary strengthening unit 320 receives according to the output voltage Vout is generated to adjust the feedback voltage V _FB The magnitude of the level is determined, and the first differential signal V _{DIFF_1 is} generated according to the adjusted feedback voltage V _FB and the reference voltage V _REF to make the buck converter 300 more stable.

4A is a detailed circuit diagram of the DC-DC buck converter 300 of FIG. 3B, some of which have been disclosed in the above embodiments, and are not described below. The boundary enhancement unit 320 mainly includes a step booster 410. In this embodiment, the boundary enhancement unit 320 further includes a noise canceller 440 and a buffer 450. The step booster 410 boosts the offset voltage Vos according to the pulse width modulation signal G1 to provide the adjusted feedback voltage V _{FB_1} during the turn-on of the lower bridge element. However, it can be easily seen by the embodiment that the step booster 410 can also be changed to a step-down buck, and the pulse width modulation signal Gh or the conduction/non-conduction period of the G1 can be reversed or elasticized. Adjustments can also achieve the desired effects of the embodiments of the present invention.

In addition, in the embodiment of the present invention, the step booster 410 is disposed on the path between the feedback voltage V _FB and the feedback voltage V _{FB — N of the} filtered high frequency noise, but other embodiments may also _adopt the step. The booster 410/step buck is implemented on a path between the reference voltages V _REF to V _{REF — N} . Since the phase lead-in unit 330 is a differential input type, if the step-down voltage regulator is used to lower the reference voltage V _REF during the on-time of the pulse width modulation signal G1, the effect of raising the feedback voltage V _FB can also be formed. . Therefore, the embodiment of the present invention is not limited to the above circuit aspect, and the boundary strengthening unit 320 can be flexibly implemented by referring to the above method by applying the embodiment. For example, the step booster or the step buck can be flexibly replaced according to whether the pulse width modulation signal G1 is turned on or off during the non-conduction period, and the installation position of the step booster or the step buck can also be fed back. The voltage V _FB or the reference voltage V _REF is elastically replaced in an alternative manner. The boundary enhancement unit 320 uses the adjusted feedback voltage V _{FB_1} and the reference voltage V _REF as the third differential signal V _{DIFF —} 3 of the positive phase terminal and the inverting terminal, _respectively .

The step booster 410, the noise canceller 440, and the buffer 450 in the boundary enhancement unit 320 of FIG. 4A are described in detail herein. The step booster 410 includes a bias generating circuit 420 and a control switch 430. The negative terminal of the bias generating circuit 420 receives the feedback voltage V _FB , and the bias generating circuit generates the adjusted feedback voltage V _{FB_1} at the positive terminal _thereof . In this embodiment, the adjusted feedback voltage V _{FB_1} is also referred to as a positive phase. The third differential signal V _{DIFF_3 at the end} . The control terminal of the control switch 430 receives the pulse width modulation signal G1, and the first terminal N1 of the control switch 430 receives the feedback voltage V _FB , and the second terminal N2 of the control switch is coupled to the positive terminal of the bias generation circuit 420 to receive the adjustment. feedback voltage V _{FB_1,} the control output of the switch 430 is coupled to a first input of the noise elimination 440.

Thereby, the control switch 430 turns on the second terminal N2 and its output terminal N3 during the conduction of the lower bridge element to transmit the adjusted feedback voltage V _{FB_1} as the third differential signal V _{DIFF_3 of the} positive phase terminal. In contrast, when the control switch 430 is in the non-conduction period of the lower bridge element, its first terminal N1 and its output terminal N3 are turned on to transmit the feedback voltage V _FB as the third differential signal V _{DIFF_3 of the} positive phase terminal, thereby When the upper bridge element is turned on, the feedback voltage V _FB is raised to become the adjusted feedback voltage V _{FB_1} .

The first input of the noise canceller 440 receives the adjusted feedback voltage V _{FB_1} through the step booster 410 , and the second input of the noise canceller 440 receives the reference voltage V _REF . Therefore, the noise canceller 440 can receive the third differential signal V _{DIFF_3} to filter the common mode and high frequency noise of the adjusted feedback voltage V _{FB_1} , and filter the feedback voltage V of the high frequency noise. _{FB_N} and the reference voltage V _{REF_N} serve as the first differential signal V _{DIFF_1 of the} positive phase terminal and the inverting terminal, _respectively .

In other embodiments, the noise canceller 440 can also be implemented using other circuit structures. 4B is a detailed circuit diagram of the DC-to-DC buck converter 300 of FIG. 3B in other embodiments. Referring to FIG. 4B, the embodiment of the present invention uses the noise synchronizer 445 to eliminate the noise portion of the feedback voltage V _{FB_1} , and the other components are the same as FIG. 4A . In detail, the first end of the noise synchronizer 445 receives the adjusted feedback voltage V _{FB_1} , and the second end of the noise synchronizer 445 receives the reference voltage V _REF . Thereby, the noise synchronizer 445 can add the noise portion of the adjusted feedback voltage V _{FB_1} to the reference voltage V _REF such that the reference voltage V _REF also has the noise portion of the feedback voltage V _{FB_1} . The phase lead-in unit 330 using the differential input receives the adjusted feedback voltage V _REF and the reference voltage V _{REF having the} noise portion, and transmits the differential input to eliminate the feedback voltage V _{FB_1} and the same V _{REF of} the reference voltage. The noise part, which indirectly eliminates noise.

In the embodiment of the present invention, the boundary enhancement unit 320 of FIG. 4A and FIG. 4B respectively includes a noise canceller 440 and a noise synchronizer 445 to enable the feedback voltage V _{FB — N} and the reference voltage V _{REF — N} to stabilize the buck converter 300 . However, in the embodiment, the noise canceller 440 and the noise synchronizer 445 may be omitted in the boundary enhancement unit 320, and the third differential signal V _{DIFF_3 is} directly regarded as the first differential signal V _{DIFF_1} and output to The phase lead unit 330 can also implement the embodiment.

Referring to FIG. 4A, one end (input) of the buffer 450 receives the reference voltage V _REF , and the output of the buffer 450 is coupled to the second input of the noise canceller 440 . Further, the buffer 450 may be omitted in the boundary enhancement unit 320 of some embodiments.

Phase lead unit 330 primarily utilizes a bandpass filter (BPF) 460 as its implementation. The inverting input terminal of the band pass filter 460 receives the first differential signal V _{DIFF_1 of the} positive phase terminal (the feedback voltage V _{FB_N of the} high frequency noise is filtered out), and the positive phase input terminal of the band pass filter 460 receives the inverted phase The first differential signal V _{DIFF_1 of the terminal} (the reference voltage V _{REF — N of the} high frequency noise is filtered out), and the two outputs of the band pass filter 460 respectively provide the second differential signal of the positive phase end and the opposite phase end V _{DIFF_2} . In other embodiments, the phase lead-in unit 330 can also use a high-pass filter as its implementation. However, since the high-pass filter cannot filter high-frequency noise, the buck converter 300 of the present invention may be degraded for high-frequency noise. Tolerance.

With continued reference to FIG. 4A, the COT control unit 340 includes a comparator 470 and a fixed on-time controller 480. The comparator 470 is coupled to the phase lead unit 460. The non-inverting input terminal and the inverting input terminal of the comparator 470 receive the second differential signal V _{DIFF_2 of the} positive phase terminal and the inverting terminal, _respectively , to generate a comparison signal Vs according to the comparison result. The fixed on-time controller 480 is triggered by the comparison signal Vs to output the pulse signal Sp with a fixed on-time to the driving circuit 310, so that the driving circuit 310 generates the pulse width modulation signals Gh and G1. The COT control unit 340 is an element that is provided in the buck converter 300 using the fixed on-time control mode, and therefore will not be described again.

In view of this, based on the hardware components of the buck converter 300 of FIG. 4A, the present embodiment can explain in detail how the buck converter 300 can maintain the stability of the system through the correlation waveforms of FIGS. 5-8. FIG. 5 is a waveform diagram of the inductor current I _L , the output voltage Vout , and the differential signals V _{DIFF_1} VV _{DIFF_3} of FIG. _4A . Referring to FIG. 4A and FIG. 5 simultaneously, the inductor current I _L in FIG. 5 is an ideal triangular waveform, and the output voltage Vout is a waveform generated when the equivalent series resistance R _{ESR of the} output capacitor 360 is small. The feedback voltage V _FB is generated based on the divided voltage of the output voltage Vout, so the waveforms of the two are similar. During the period T _Gh is the period during which the upper bridge element is turned on, at this time, the lower bridge element is turned off, and the output inductor L is connected to the input voltage Vin through the upper bridge element at this time to gradually increase the current value of the inductor current I _L . In contrast, the period T _G1 is the period during which the lower bridge element is turned on. At this time, the upper bridge element is turned off, and the inductor current I _L gradually decreases the current value of the inductor current I _L due to the connection of the lower bridge element to the ground. In addition, since the above waveforms all have a problem of phase delay with respect to the inductor current I _L , the phase delay is difficult to explain, and thus the phase delay is not clearly shown in FIG. 5 .

Therefore, when transitioning from the period T _Gh to the period T _G1 (dashed line H), the boundary enhancement unit 320 synchronizes with the lower bridge element on-time according to the pulse width modulation signal G1, and uses the step booster 410 to output the basis. The feedback voltage V _FB generated by the voltage Vout is raised, that is, when the lower bridge element is turned on, the feedback voltage V _FB is raised by the offset voltage Vos. Since the step booster 410 uses the control switch 430 to control the rise of the feedback voltage V _FB , the third differential signal V _{DIFF — 3} produces a surge generation as indicated by reference numerals 510, 520. This embodiment facilitates the use of the noise canceller 440 to filter out the _glitch of the third differential signal V _{DIFF_3} as indicated by reference numerals 510 and 520 to provide a relatively smooth first differential signal V _{DIFF_1} to increase the noise suppression capability.

The phase lead unit 330 receives the first differential signal V _{DIFF_1} and generates a second synchronization with the inductor current I _L by means of a differential processing and a phase lead by means of a band pass filter (GPF) 460 with a zero point compensation function. Differential signal V _{DIFF_2} . Thereby, when the comparator 470 compares between the positive differential phase and the inverted phase second differential signal V _{DIFF_2} , it is less likely to _cause an error.

For example, if the waveform of the second differential signal V _{DIFF_2} of FIG. 5 is in contact with the broken line LL (at the intersection of the dotted lines I and LL), it means that the value of the second differential signal V _{DIFF_2} is lower than 0, thus triggering the comparator 470 to make The comparison signal Vs is in a transition state, causing the fixed on-time controller 480 to switch the upper and lower bridge elements to each other through the pulse signal Sp to switch from the period T _G1 to the period T _GH to start charging the inductor, and vice versa.

6 is a schematic diagram of gain vs. frequency before and after the phase lead-in unit 330 of the DC-to-DC buck converter 300 of FIG. 4A. The gain GAIN1 at the top of FIG. 6 is a gain curve of the buck converter without the phase lead unit, and the gain GAIN2 at the bottom of FIG. 6 is the gain curve of the buck converter 300 with the phase lead unit 330. As can be seen in Figure 6, the use of phase lead-in unit 330 allows buck converter 300 to achieve better gain benefits at relatively low frequency conditions (e.g., frequency fz).

7 is a schematic diagram of phase versus frequency before and after the phase lead-in unit 330 of the DC-to-DC buck converter 300 of FIG. 4A. The buck converter before the phase leader unit is used is represented by the solid line segment L1, so the buck converter needs to be at a (-14) degree phase, that is, a relatively high frequency pulse width modulation signal is required to reach stability. During the period of Tstable1. The buck converter 300 using the phase lead unit 330 is represented by a broken line segment L2, and the buck converter 300 only needs to reach the stable period Tstable2 at about (-90) degrees, so the buck conversion using the phase lead unit 330 is employed. The device 300 can achieve a stable power supply output when a relatively low frequency pulse width modulation signal is generated.

FIG. 8 is a waveform diagram of the DC-DC buck converter 300 of FIG. 4A before and after the step booster 410 is employed. Case 1 of Fig. 8 is a waveform of a correlation signal when a DC-to-DC buck converter that does not employ a step booster is affected by a smaller noise margin. From arrow 810, the output voltage Vout and The second differential signal V _{DIFF_2} touches the dotted line LL only when the period T _Gh transitions to the period T _G1 , that is, the value of the second differential signal V _{DIFF_2} is only slightly lower than 0. Case 2 is the waveform of the related signal when the DC-to-DC buck converter that does not use the step booster is affected by a large noise boundary. The second differential signal V _{DIFF_2 is} known by the arrow 820 in Case 2. The value should be lower than 0 in the case that the period T _Gl (that is, the inductor L should still be discharged), causing the pulse signal Sp to be triggered again to cause the inductor L to be recharged and enter the period T _Gh , thereby causing a judgment error. Case.

Case 3 of FIG. 8 is the DC buck converter 300 of FIG. 3B. After using the step booster 410, if there is a large noise boundary, the step booster 410 will be based on the output voltage Vout. The generated feedback voltage V _FB is raised so that the second differential signal V _{DIFF_2} does not occur as in the case of the arrow 2 of the case 2 and its value is lower than 0, so that the comparator 470 does not cause an error.

In summary, the DC-to-DC buck converter disclosed in the embodiment of the present invention adds a phase lead-in unit to the front stage of the comparator, thereby adjusting the output voltage so that the waveform is restored in a phase-leading manner to be similar to the inductor current. Waveforms of the same phase. In addition, the boundary strengthening unit raises the feedback voltage during the conduction of the lower bridge component, and reduces the common mode noise by means of differential and high frequency filtering, etc., to avoid false triggering of the fixed on-time control unit. As such, the DC-to-DC buck converter increases the system stability of the buck converter, increases the buck converter's tolerance for noise, and reduces the numerical limits on the output capacitor and its equivalent series resistance.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 300‧‧‧DC to DC Buck Converter

110, 310‧‧‧ drive circuit

120, 350‧‧ ‧ voltage divider circuit

130, 470‧‧‧ comparator

140, 340‧‧‧ Fixed On-Time (COT) Control Unit

150, 360‧‧‧ output capacitor

320‧‧‧Boundary Enhancement Unit

330‧‧‧ Phase Leading Unit

410‧‧‧step booster

420‧‧‧Pressure generating circuit

430‧‧‧Control switch

440‧‧‧ Noise canceller

445‧‧‧ Noise Synchronizer

450‧‧‧buffer

460‧‧‧Bandpass Filter (BPF)

480‧‧‧Fixed on-time controller

510, 520‧ ‧ label

810~820‧‧‧ arrow

End points of N1, N2, N3‧‧‧ control switches

A, B, C, D, I, H, LL‧‧‧ dotted lines

E‧‧‧Contact

F‧‧‧reporting end

Vin‧‧‧Input voltage

Vout, Vout1~Vout3‧‧‧ output voltage

R _ESR ‧‧‧Equivalent series resistance

L _ESL ‧‧‧Equivalent series inductance

C _OUT ‧‧‧output capacitance value

L‧‧‧Output inductor

I _L ‧‧‧Inductor current

Qp, Qn‧‧‧ transistor

Gh, Gl‧‧‧ pulse width modulation signal

V _FB ‧‧‧Responsive voltage

V _{FB_1 ‧‧‧Adjusted} feedback voltage

V _{FB_N} ‧‧‧ has filtered out the feedback voltage of high frequency noise

V _REF ‧‧‧reference voltage

V _{REF_N} ‧‧‧ has filtered out the reference voltage of high frequency noise

V _{DIFF_1} , V _{DIFF_2} , V _{DIFF_3 ‧‧‧Differential} signal

Vs‧‧‧ comparison signal

Vos‧‧‧ offset voltage

Sp‧‧‧ pulse signal

R1, R2‧‧‧ resistance

T _Gh , T _Gl ‧‧‧

GAIN1, GAIN2‧‧‧ Gain

L1‧‧‧solid line

L2‧‧‧dotted section

Tstable1, Tstable2‧‧‧ stable period

Fz‧‧‧ frequency

Figure 1 is a schematic diagram of a DC-to-DC buck converter employing a fixed on-time control mode.

Figure 2 is a graph showing the effect of the equivalent series resistance on the output voltage in the time domain with the same output capacitance value.

3A is a functional block diagram illustrating a DC-to-DC buck converter in accordance with an embodiment of the present invention.

FIG. 3B is a functional block diagram showing another DC-to-DC buck converter according to an embodiment of the invention.

4A is a detailed circuit diagram of the DC-to-DC buck converter of FIG. 3B.

4B is a detailed circuit diagram of the DC-to-DC buck converter of FIG. 3B in other embodiments.

FIG. 5 is a waveform diagram of the inductor current I _L , the output voltage Vout, and the differential signals V _{DIFF_1} VV _{DIFF_3} of FIG. _4A .

6 is a schematic diagram of the gain versus frequency of the DC-to-DC buck converter of FIG. 4A before and after the phase lead-in unit is employed.

7 is a schematic diagram of phase versus frequency of the DC-to-DC buck converter of FIG. 4A before and after employing a phase lead-in unit.

Figure 8 is a waveform diagram of the DC-to-DC buck converter of Figure 4A before and after the step booster is employed.

300‧‧‧DC to DC Buck Converter

310‧‧‧Drive circuit

320‧‧‧Boundary Enhancement Unit

330‧‧‧ Phase Leading Unit

340‧‧‧Fixed On-Time (COT) Control Unit

350‧‧‧voltage circuit

360‧‧‧ output capacitor

E‧‧‧Contact

F‧‧‧reporting end

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

R _ESR ‧‧‧Equivalent series resistance

L _ESL ‧‧‧Equivalent series inductance

C _OUT ‧‧‧output capacitance value

L‧‧‧Output inductor

I _L ‧‧‧Inductor current

Qp, Qn‧‧‧ transistor

Gh, Gl‧‧‧ pulse width modulation signal

V _FB ‧‧‧Responsive voltage

V _REF ‧‧‧reference voltage

V _{DIFF_1} , V _{DIFF_2 ‧‧‧Differential} signal

Sp‧‧‧ pulse signal

R1, R2‧‧‧ resistance

Claims (9)

A DC-to-DC buck converter includes: a driving circuit, at least one pair of upper and lower bridge elements, and an output capacitor, the upper bridge element and the lower bridge element being connected to each other and controlled by a pulse generated by the driving circuit a wide-modulation signal that alternately switches and provides an output voltage according to an input voltage through an output inductor and an output capacitor; a phase lead-in unit that receives a first differential signal generated according to the output voltage and a reference voltage, and the first a differential signal is phase-lead to provide a second differential signal; a fixed on-time control unit is coupled to the phase lead-in unit, and receives and determines whether the energy of the output voltage is sufficient according to the second differential signal, thereby Outputting a pulse wave signal with a fixed on-time to the driving circuit, so that the driving circuit generates the pulse width modulation signal; and a boundary strengthening unit coupled to the driving circuit and the phase leading unit, and receiving is generated according to the output voltage Retrieving the voltage and adjusting the feedback voltage according to the specific period of the pulse width modulation signal, and adjusting according to The feedback voltage and a reference voltage to generate the first differential signal. The DC-to-DC buck converter of claim 1, wherein the boundary enhancement unit comprises: a step booster, according to the pulse width modulation signal, to be used during the conduction of the lower bridge component The voltage is raised by an offset voltage to provide the adjusted feedback voltage, wherein the first differential signal of the positive phase terminal is the adjusted feedback voltage, and the first differential signal of the inverting terminal is the reference Voltage. The DC-to-DC buck converter of claim 2, wherein the step booster comprises: a bias generating circuit, the negative terminal receiving the feedback voltage, and the positive terminal of the bias generating circuit generates the adjusted feedback voltage; and a control switch, the control terminal receiving the pulse width modulation signal, the control switch The first end receives the feedback voltage, and the second end of the control switch is coupled to the positive terminal of the bias generating circuit, and the control switch conducts the second end of the control terminal with the output end thereof during the conduction of the lower bridge component to transmit the adjustment The feedback voltage is applied, and the control switch conducts its first end and its output during the non-conduction of the upper bridge element to transmit the feedback voltage. The DC-DC buck converter of claim 2, wherein the boundary enhancement unit further comprises: a noise canceller that filters out the noise portion of the first differential signal. The DC-DC buck converter according to claim 2, wherein the boundary enhancement unit further comprises: a noise synchronizer, wherein the first end receives the adjusted feedback voltage, and the noise synchronizer The second terminal receives the reference voltage to add the noise portion of the adjusted feedback voltage to the reference voltage, wherein the phase leading unit receives the adjusted feedback voltage and the reference voltage, and transmits the differential voltage through the differential input The feedback voltage of the adjustment and the noise portion of the reference voltage are eliminated. The DC-to-DC buck converter of claim 1, wherein the phase lead-in unit comprises: a zero-point compensation circuit that provides zero-point compensation and phase-leads the first differential signal to generate the second Differential signal. The DC-to-DC buck converter of claim 6, wherein the zero-point compensation circuit comprises: a band pass filter having an inverting input receiving the first differential signal of the positive phase terminal, the positive phase input terminal of the band pass filter receiving the first differential signal of the inverting terminal, the band pass filter The two outputs provide the second differential signal of the positive phase terminal and the inverting terminal, respectively. The DC-to-DC buck converter of claim 6, wherein the zero-point compensation circuit is implemented by a high-pass filter. The DC-DC buck converter according to claim 1, wherein the fixed on-time control unit comprises: a comparator coupled to the phase lead-in unit, a positive-phase input terminal and an inverting input terminal of the comparator Receiving the second differential signal of the positive phase end and the inverting end respectively to generate a comparison signal according to the comparison result; and fixing the on-time controller, being triggered by the comparison signal to output a pulse wave signal having a fixed on-time The driving circuit causes the driving circuit to generate the pulse width modulation signal.