TWI488285B - Dual metal oxide semiconductor field effect transistors integrating a capacitor - Google Patents

Description

Bimetal oxide semiconductor field effect transistor integrated with a capacitor

The present invention generally relates to a metal oxide semiconductor field effect transistor, and more particularly to a metal oxide semiconductor field effect transistor integrated with a capacitor and a method of fabricating the same.

In a power device, a bypass capacitor is typically connected between the power supply of the DC-DC power switching and the ground (GND). There is pulsation in the working circuit current, such as the synchronous frequency of the digital circuit, which is easy to cause the ripple of the power supply voltage. This is an AC noise. A small-capacity non-polar capacitor can bypass this noise to the ground. In addition, the working voltage of the electronic product It is decreasing continuously, which requires a DC-DC converter with low voltage and high current output. In DC-DC converters, a capacitor is often used as a filter capacitor. In order to improve stability, the above capacitors are essential for improving the performance of the device. .

A design scheme for integrating a capacitor in a DC-DC converter is to simultaneously seal a separate capacitor and a metal oxide semiconductor field effect transistor (MOSFET) through an epoxy resin in a chip package structure, and the capacitor is not Directly integrated with the MOS FET, but independent. The electrical connection between the MOS FET and the capacitor depends on the connection of the wafer particles forming the MOS field effect transistor to the capacitor through the bond alloy wire or the grounding of the capacitor (GND).

A design scheme for integrating a capacitor in a dual MOSFET including a low-side MOSFET and a high-side MOSFET, as shown in FIG. 1A, in which the source S _{1 of the} N-type high-side MOSFET _{1 is} connected to the N-type low-side MOSFET 2 A drain ₃ is connected between the drain D ₂ , the drain D _{1 of the} high side MOSFET ₁ and the source S _{2 of the} low side MOSFET ₂ .

Correspondingly, the schematic diagram of the structure of the wafer of FIG. 1B is a schematic diagram of the structure of the wafer in which the low-side MOSFET and the high-side MOSFET corresponding to the circuit structure diagram of FIG. 1A in the prior art are integrated in one wafer and combined with one capacitor. The wafer particles 10 in Fig. 1B constitute the high side MOSFET 1 in Fig. 1A, and the wafer particles 20 in Fig. 1B constitute the low side MOSFET 2 in Fig. 1A. The size of the wafer particles 10 is smaller than the size of the wafer particles 20, and the wafer particles 10 are stacked on the wafer particles 20. The wafer particles 10 and the wafer particles 20 are packaged in a stacked chip package (Stack Die). Assembly), the wafer particles 20 are bonded to the metal lead frame 30. Wherein, the gate bonding region 11 of the wafer particle 10 is connected to the gate pin 11b through the gate bonding wire 11a; the source bonding region 12 of the wafer particle 10 is connected to the lead frame 30 through the bonding wire 12a. The drain (not shown) at the bottom of the wafer particle 10 is bonded to the drain metal layer 13 by a conductive silver paste (Epoxy) while the drain metal layer 13 is connected to the drain pin through the bonding wire 13a. 13b. The size of the drain metal layer 13 is larger than the size of the wafer particles 10. The gate bonding region 21 of the wafer particle 20 is connected to the gate pin 21b through the gate bonding wire 21a; the source metal layer 22 of the wafer particle 20 is provided with a source bonding region 22a, a source. The bonding region 22a is connected to the source pin 22c through the bonding wire 22b; the drain (not shown) at the bottom of the wafer particle 20 is bonded to the lead frame 30 by conductive silver paste (Epoxy), and then the wafer The drain of the particles 20 is electrically connected to the source bonding region 12 of the wafer particles 10. Wherein, a drain dielectric layer 13 of the wafer particles 10 and a source metal layer 22 of the wafer particles 20 have a dielectric layer (not shown) and are bonded and bonded together, and the drain metal layer 13 is The structure of the source metal layer 22 can exist as a capacitor. Unfortunately, the capacitance value is insufficient to meet the actual requirements of the power device, and if necessary, the capacitance between the electrode metal layer 13 and the source metal layer 22 is increased. The value needs to be additionally connected between the source pin 22c (ie, the source S ₂ of the low-side MOSFET in FIG. 1A) and the drain pin 13b (ie, the drain D ₁ of the high-side MOSFET in FIG. 1A). Set the capacitor. However, the fact is that the negative effect of the bond alloy wire used to connect the capacitor or other external lead wires is the discrete inductance, which has a significant impact on the switching speed of the MOSFET.

An example of a dual MOSFET integrating a high side MOSFET and a low side MOSFET is shown in Figures 1C and 1D of the accompanying drawings. The design and fabrication of a dual MOSFET comprising a low side MOSFET and a high side MOSFET can be found in U.S. Patent Application Serial No. US 2008/0067584 A1. Specifically, the 1C, 1D diagram is a cross-sectional view and a circuit diagram of an integrated combined buck converter using an iT-FET device as a top FET device function and a Schottky FET device as a bottom device function. The iT-FET device and the Schottky FET are supported on a common substrate 150 that functions as the source of the it-FET device and the drain of the Schottky FET device. The Schottky FET device includes a trench gate 120' surrounded by a source region 145' proximate the top surface, and is also enclosed within the body region 110. Source region 145' is in electrical contact with source metal layer 170'. The trench gate 120' of the Schottky FET device is padded with a gate oxide layer 125' and electrically coupled to the gate metal 180'. The present application provides an example of integrating a capacitor in a bimetal oxide semiconductor field effect transistor.

On the other hand, wafer granules are derived from Wafer dicing, as a need to reduce wafer grain substrate resistance or other desired thinning of wafers, and wafer back grinding that is extremely relevant to wafer fabrication processes ( Wafer Backside Grinding's process control is extremely important, and wafers or wafer pellets are more likely to break when the wafer back is thinner. Further, in the process steps of thin wafer particles through a die attach to a lead frame or a substrate such as a PCB, the wafer crack is easily generated. The chip functionality failed, and this is not what we want to see.

In view of this, in order to overcome the above limitations and problems, an aspect of the present invention is to provide a MOS field effect transistor integrated with a capacitor, which has a capacitor directly integrated on the MOS field effect transistor, and is enhanced by the integrated capacitor. An effective way of mechanical strength of MOS field effect transistors.

The invention provides a dual MOS field effect transistor integrated with a capacitor. The double MOS field effect transistor is integrated with a bypass capacitor, wherein: a top surface of a substrate is provided with a structure a first gate metal layer forming a first transistor gate electrode and a drain metal layer constituting the first transistor drain electrode, and a second gate metal layer constituting the second transistor gate electrode and forming a second a source metal layer of the source electrode of the transistor; a multilayer capacitor plate including a plurality of first type capacitor plates and a plurality of second type capacitor plates parallel to the cymbal substrate disposed above the top surface of the cymbal substrate And a dielectric layer is filled between a top surface of the cymbal substrate and a capacitor plate above the top surface of the cymbal substrate and between two adjacent capacitor plates; the first type of capacitor plate and the second type of capacitor The plates are alternately spaced apart from each other, and the first type of capacitor plates are electrically connected to the drain metal layer for forming one electrode of the bypass capacitor, and the second type of capacitor plates are electrically connected to the source metal layer. The other electrode used to form the bypass capacitor.

The above-mentioned dual MOS field effect transistor integrated with a capacitor, wherein a source of the first transistor is formed on a bottom surface of the enamel substrate, and a drain and a gate of the first transistor are formed on a top of the cymbal substrate The drain of the second transistor is formed on the bottom surface of the enamel substrate, and the source and the gate of the second transistor are formed on the top surface of the cymbal substrate.

The above-mentioned dual-MOS field-effect transistor integrated with a capacitor, wherein a layer of the capacitor plate of any one of the layers is provided with a first stacked gate metal layer above the first gate metal layer; A first stacked gate metal layer is electrically connected to the first gate metal layer to derive a gate of the first transistor.

The above-mentioned dual MOS field effect transistor integrated with a capacitor, wherein a layer of the capacitor plate of any one of the layers is provided with a second stacked gate metal layer above the second gate metal layer; A second stacked gate metal layer is electrically connected to the second gate metal layer to derive a gate of the second transistor.

The dual MOS field effect transistor integrated with a capacitor, wherein the drain metal layer is provided with a first extension structure, and the layer of any one of the capacitor plates is disposed above the first extension structure There is a first layered extension structure; wherein the first layer extension structure is electrically connected to the first extension structure to lead the first transistor drain.

The above-mentioned dual MOS field effect transistor integrated with a capacitor, the source metal layer a second extension structure, and any one of the layers of the capacitor plate is disposed with a second layered extension structure above the second extension structure; the second layer extension structure is used for the second extension The structure is electrically connected to derive the second transistor source.

The above dual MOS field effect transistor integrated with a capacitor, in a dielectric layer between adjacent first stacked extension structures and a dielectric layer between the first stacked extension structure and the first extended structure adjacent to the first extended structure A plurality of through holes are formed in the middle, and the first layer extending structure is electrically connected to the drain of the first transistor through the metal injected into the through holes.

The above dual MOS field effect transistor integrated with one capacitor, in a dielectric layer between adjacent second stacked extension structures and a dielectric layer between the second stacked extension structure and the second extended structure adjacent to the second extended structure A plurality of through holes are formed in the middle, and the second laminated extension structure is electrically connected to the source of the second transistor through the metal injected into the through holes.

The above-mentioned dual MOS field effect transistor integrated with a capacitor, wherein the first type of capacitor plate and the second type of capacitor plate are longitudinally staggered for the first type of capacitor between adjacent second type of capacitor plates a second type of connection layer insulated from the first type of capacitor plate is disposed in the layer where the plate is located; between the second type of capacitor plate and the second type of connection layer, and between the source metal layer and the source metal layer A through hole is formed in the dielectric layer between the two types of capacitor plates, and the second type of capacitor plates are electrically connected to each other through the metal injected into the through hole, and the second type of capacitor plate and the source metal layer are electrically connected. connection.

The above-mentioned dual MOS field effect transistor integrated with a capacitor, wherein the first type of capacitor plate and the second type of capacitor plate are longitudinally staggered for use between adjacent first type of capacitor plates and the first type of capacitor a first type of connection layer insulated from the second type of capacitor plate is disposed in a layer of the second type of capacitor plate between the plate and the drain metal layer; between the first type of capacitor plate and the first type of connection layer a via hole is disposed in the dielectric layer between the drain metal layer and the first type of connection layer adjacent to the drain metal layer, and the first type of capacitor plates are electrically connected to each other through the metal injected into the via hole, and the first The capacitor-like plate is electrically connected to the drain metal layer.

The above-mentioned dual MOS field effect transistor integrated with a capacitor, wherein any one layer The first type of capacitor plates are connected to the first layer extension structure of the layer of the first type of capacitor plates of the layer.

The above-mentioned dual MOS field effect transistor integrated with a capacitor, wherein the source metal layer is provided with a second extension structure, and the layer of any one of the capacitor plates is disposed above the second extension structure There is a second layered extension structure, wherein the first type of capacitor plates of any one of the layers are separated from the second layer of the extension structure of the layer of the first type of capacitor plates.

The above-mentioned dual MOS field effect transistor integrated with a capacitor, wherein the second type of capacitor plate of any one of the layers is connected with the second layer extension structure of the layer of the second type of capacitor plate of the layer.

The dual MOS field effect transistor integrated with a capacitor, wherein the drain metal layer is provided with a first extension structure, and the layer of any one of the capacitor plates is disposed above the first extension structure There is a first layered extension structure, wherein the second type of capacitor plates of any one of the layers are separated from the first layer of the extension structure of the layer of the second type of capacitor plates.

The above-mentioned dual MOS field effect transistor integrated with a capacitor, wherein the first gate metal layer, the drain metal layer, the source metal layer and the second gate metal layer are separated and separated from each other by a partition, and the partition is filled with Dielectric; the layer on which any one of the capacitor plates is located contains an insulating partition and the insulating partition is filled with a dielectric.

The above-mentioned MOS field effect transistor integrated with a capacitor, wherein the first transistor is a high-end MOS field effect transistor, and the second transistor is a low-end MOS field effect transistor.

The invention also provides a method for integrating a capacitor on a dual MOS field effect transistor, comprising the steps of: depositing a dielectric layer multiple times on the top surface of the enamel substrate on which the first transistor and the second transistor are located; Depositing a metal layer to form a multilayer dielectric layer and a plurality of metal layers alternately between a dielectric layer and a metal layer on a top surface of the ruthenium substrate; wherein, after depositing the dielectric layer, etching the dielectric layer for forming a plurality of vias in the dielectric layer Hole; in which the metal layer is deposited after gold The genus layer is etched and divided to divide the metal layer into different metal regions, a part of the metal region forms a capacitor plate, and the metal layer is filled with a metal to fill the via hole included in the dielectric layer; After the dividing, a first layer extending structure and a second layer extending structure of the layer where the metal layer is formed are formed, and the first stacked gate metal layer and the second stacked gate metal layer are formed.

The above method, wherein the top surface of the cymbal substrate comprises a drain metal layer constituting the drain electrode of the first transistor, and a first gate metal layer constituting the gate electrode of the first transistor to constitute a second transistor source a source metal layer of the electrode, a second gate metal layer constituting the second transistor gate electrode; the drain metal layer includes a first extension structure, and the source metal layer includes a second extension structure.

The above method, wherein the first layered extension structure is located above the first extension structure, the second layered extension structure is located above the second extension structure; and the first layer of stacked gate metal A layer is above the first gate metal layer, and a second stacked gate metal layer is above the second gate metal layer.

The above method, wherein the multi-layer metal layer is etched and divided to form a plurality of capacitor plates including a plurality of first type capacitor plates and a plurality of second type capacitor plates at different levels; the first type of capacitor plates and The second type of capacitor plates are alternately spaced apart from each other.

In the above method, the second type of connection layer insulated from the first type of capacitor plate is formed in the layer of the first type of capacitor plate between the adjacent second type of capacitor plates after the multilayer metal layer is etched and divided. Etching the dielectric layer to etch a plurality of vias in the dielectric layer between the second type of capacitor plates and the second type of connection layer, and by implanting a dielectric layer between the second type of capacitor plates and the second type of connection layer The metal in the middle via hole electrically connects the second type of capacitor plates to each other.

In the above method, the multilayer metal layer is etched and divided to form an insulation layer between the adjacent first type of capacitor plates and the second type of capacitor plates between the first type of capacitor plates and the drain metal layer. a first type of connection layer of a second type of capacitor plate; an etch dielectric layer between the first type of capacitor plate and the first type of connection layer and the first type of connection between the drain metal layer and the drain metal layer A plurality of via holes are etched in the dielectric layer between the layers, and the first type of capacitor plates are electrically connected to each other by injecting metal in the via holes in the dielectric layer between the first type of capacitor plates and the first type of connection layer Connecting, electrically connecting the first type of connection layer and the drain metal layer by implanting a metal in a via hole in the dielectric layer between the first type of connection layer and the drain metal layer adjacent to the drain metal layer.

The above method, wherein the etching dielectric layer etches a plurality of via holes in the dielectric layer between the source metal layer and the second type of capacitor plates adjacent to the source metal layer, and by implanting the source metal layer and the proximity source The metal in the via hole in the dielectric layer between the second type of capacitor plates of the polar metal layer electrically connects the second type of capacitor plate to the source metal layer.

The above method, wherein the etching dielectric layer etches a plurality of passes in the dielectric layer between the adjacent first stacked extension structures and between the first stacked extension structure and the first extended structure of the first extended structure a hole, the metal in the through hole in the dielectric layer between the adjacent first stacked extension structures and between the first laminate extension structure and the first extension structure adjacent to the first extension structure The layered extension structure is electrically connected, and the first layer extension structure is electrically connected to the first extension structure.

The above method, wherein the etching dielectric layer etches a plurality of passes in the dielectric layer between the adjacent second stacked extension structures and between the second stacked extension structure and the second extended structure of the second extended structure a hole, the metal in the via hole in the dielectric layer between the adjacent second stacked extension structure and the second laminate extension structure and the second extension structure adjacent to the second extension structure The two-layer extension structure is electrically connected, and the second layer extension structure is electrically connected to the second extension structure.

The above method, wherein the etching dielectric layer is between the adjacent first stacked gate metal layers and between the first stacked gate metal layer and the first gate metal layer adjacent to the first gate metal layer a plurality of via holes are etched in the dielectric layer by implanting a first stacked gate metal layer and a first gate metal layer between adjacent first stacked gate metal layers and adjacent to the first gate metal layer The metal in the via hole in the dielectric layer electrically connects the adjacent first stacked gate metal layer, and electrically connects the first stacked gate metal layer and the first gate metal layer.

The above method, wherein the etching dielectric layer is between the adjacent second stacked gate metal layers and between the second stacked gate metal layer and the second gate metal layer adjacent to the second gate metal layer a plurality of via holes are etched into the dielectric layer by implanting a second stacked gate metal layer and a second gate metal layer between adjacent second stacked gate metal layers and adjacent to the second gate metal layer The metal in the via hole in the dielectric layer electrically connects the adjacent second stacked gate metal layer while electrically connecting the second stacked gate metal layer and the second gate metal layer.

In the above method, the first type of capacitor plates of any one of the layers are connected to the first layer of the layer of the first type of capacitor plates, and the layer of the layer of the first type of capacitor plates is The two-layer extension structure divides the insulation.

In the above method, the second type of capacitor plates of any one of the layers are connected to the second layer of the layer of the second type of capacitor plates, and the layer of the second type of capacitor plates of the layer is The layered extension structure divides the insulation.

The above method, wherein the drain metal layer, the first gate metal layer, the source metal layer, and the second gate metal layer are separated from each other by a partition, and the dielectric layer is deposited for filling the dielectric in the partition; depositing the dielectric layer The insulating partition formed by etching the divided metal layer is filled with a dielectric. These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;

GND‧‧‧capacitor grounding

S ₁ /S ₂ ‧‧‧ source

D ₁ /D ₂ ‧‧‧Drain

10/20‧‧‧ wafer pellets

11/21‧‧‧Gate bonding zone

11a/21a‧‧‧Gate bonding wire

11b/21b‧‧‧ gate pin

12/22a‧‧‧Source Bonding Zone

12a/13a/22b‧‧‧bonding wire

13/531/631/103/1130‧‧‧Drain metal layer

13b‧‧‧Drain pin

22/130/170’/230/330/430/53/632/730/93/104/1140‧‧‧ source metal layer

22c‧‧‧Source pin

30‧‧‧ lead frame

10/200/300/400‧‧‧MOS field effect transistor

110/210/310/410/510/610/710/810/910/1010/1110‧‧‧ 矽 substrate

120/220/320/420/720/920‧‧‧Gate metal layer

120’‧‧‧ Groove gate

120a/220a/320a/420a‧‧‧Layered gate metal layer

120b/140b/150b/220b/240b/250b/320b/340b/350b/420b/435b/450b/521b//522b/535b/536b/540b/550b/621b/622b/635b/636b‧‧Metal

135/235/335/435‧‧‧Extended structure

135a/235a/335a/435a‧‧‧Layer extension structure

140/240/340/440/540/640‧‧‧First type of capacitive plates

140a/240a/340a/540a‧‧‧Type 1 connection layer

145’‧‧‧ source area

150/250/350/450/550/650‧‧‧Second type capacitor plates

150a/250a/350a/450a/550a‧‧‧Second type of connection layer

180’‧‧‧Gate metal

500/600‧‧‧Double MOS field effect transistor

521/1020/1120‧‧‧First gate metal layer

521a/621a‧‧‧First laminated gate metal layer

522/6/1150‧‧‧second gate metal layer

522a/622a‧‧‧Second laminated gate metal layer

535‧‧‧First extension structure

535a/635a‧‧‧First layer extension structure

536/636‧‧‧Second extension structure

536a/636a‧‧‧Second layer extension structure

711/713/715/811/813/815/817/911/913/915/1011/1013/1015/1111/1113/1115‧‧‧Multiple deposition of dielectric layers

711a713a/715a/811a/813a/815a/817a/911a/913a/915a/1011a/1013a/1015a/1111a/1113a/1115a‧‧‧through holes

712/714/716/812/814/816/818/912/914/916/1012/1014/1016/1112/1114/1116‧‧ ‧ multiple deposition of metal layers

712a/712b/712c/714a/714b/714c/716a/716b/812a/812b/814a/814b/814c/816a/816b/816c/818a/818b/912a/912b/914a/914b/914c/916a/916b/ 1012a/1012b/1012c/1012d/1014a/1014b/1014c/1014d/1016a/1016b/1016c/1112a/1112b/1112c/1114a/1114b/1114c/1116a/1116b/1116c‧‧‧Metal area

725/925/1025/1125‧‧‧ partition

Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.

Figure 1A is a schematic diagram of the circuit structure of a low-side MOSFET and a high-side MOSFET connected to a capacitor.

1B is a top plan view of a wafer in which a low-side MOSFET and a high-side MOSFET corresponding to the circuit diagram in FIG. 1A are integrated in a single wafer in the prior art.

1C and 1D are respectively an iT-FET used in US 2008/0067584 A1. A cross-sectional view and circuit diagram of an integrated combined buck converter that functions as a top FET device and a Schottky FET device as a bottom device.

Fig. 2A is a perspective view showing the structure of the first embodiment of the present invention.

2B is a plan view showing an extended structure of a gate metal layer, a source metal layer, and a source metal layer on a top surface of a corresponding cymbal substrate in a schematic perspective view of the first embodiment of the present invention.

FIG. 2C-2F is a plan view showing a corresponding layer of each layer of the capacitor plates in the bottom view of the first embodiment of the present invention.

Fig. 3A is a perspective view showing the structure of the second embodiment of the present invention.

FIG. 3B is a plan view showing the extension structure of the gate metal layer, the source metal layer and the source metal layer on the top surface of the corresponding cymbal substrate in the schematic view of the two-dimensional structure of the second embodiment of the present invention.

3C-3F is a plan view schematically showing a level of a corresponding bottom-up capacitor layer of each layer in the schematic view of the two-dimensional structure of the second embodiment of the present invention.

4A is a schematic perspective view showing a third embodiment of the present invention.

FIG. 4B is a plan view showing the extended structure of the gate metal layer, the source metal layer and the source metal layer on the top surface of the corresponding cymbal substrate in the three-dimensional structure diagram of the third embodiment of the present invention.

4C-4E is a plan view showing the level of the corresponding bottom-up capacitor layer of each layer in the three-dimensional structure diagram of the third embodiment of the present invention.

Fig. 5A-1 is a schematic view showing the front side three-dimensional structure of the fourth embodiment of the present invention.

5A-2 is a schematic perspective view of the rear side of the fourth embodiment of the present invention.

FIG. 5B is a plan view showing the extension structure of the gate metal layer, the source metal layer and the source metal layer on the top surface of the corresponding cymbal substrate in the four-dimensional structure diagram of the fourth embodiment of the present invention.

FIG. 5C-5E is a plan view showing the level of the corresponding bottom-up capacitor layer of each layer in the schematic view of the four-dimensional structure of the fourth embodiment of the present invention.

Fig. 6A-1 is a schematic view showing the front side three-dimensional structure of the fifth embodiment of the present invention.

6A-2 is a schematic perspective view of the rear side of the fifth embodiment of the present invention.

FIG. 6B is a plan view showing the extended structure of the gate metal layer, the source metal layer and the source metal layer on the top surface of the corresponding cymbal substrate in the schematic diagram of the three-dimensional structure of the fifth embodiment of the present invention.

6C-6E is a corresponding bottom-up view in the schematic diagram of the three-dimensional structure of the fifth embodiment of the present invention A schematic plan view of the layer where each layer of capacitive plates is located.

Fig. 7A-1 is a schematic view showing the front side three-dimensional structure of the sixth embodiment of the present invention.

7A-2 is a schematic perspective view of the rear side of the sixth embodiment of the present invention.

FIG. 7B is a plan view showing the extension structure of the gate metal layer, the source metal layer and the source metal layer on the top surface of the corresponding cymbal substrate in the three-dimensional structure diagram of the sixth embodiment of the present invention.

7C-7E is a plan view showing the level of the corresponding bottom-up capacitor layer of each layer in the three-dimensional structure diagram of the sixth embodiment of the present invention.

8A-8L are preparation methods for carrying out Examples 1 and 3 of the present invention.

Fig. 9 is a view showing a production method for carrying out the second embodiment of the present invention.

Fig. 10 is a view showing a production method for carrying out the fourth embodiment of the present invention.

Fig. 11 is a view showing a production method for carrying out the fifth embodiment of the present invention.

Fig. 12 is a view showing a production method for carrying out the sixth embodiment of the present invention.

According to the disclosure of the patent application and the content of the invention, the technical solution of the present invention is specifically as follows:

Embodiment 1:

Referring to FIG. 2A (schematic diagram of the three-dimensional structure) and FIG. 2B-2F (a schematic plan view of the layer of each of the corresponding bottom-up capacitor plates in the schematic view of the three-dimensional structure), the substrate 110 is shown in FIG. A gate metal layer 120 (referred to as a second electrode metal layer) constituting a gate electrode (referred to as a second electrode) of a low side (Low Side) MOS field effect transistor 100 is disposed on the top surface, and a MOS field effect is formed. A source metal layer 130 (referred to as a first electrode metal layer) of a source electrode (referred to as a first electrode) of the transistor 100, and a source metal layer 130 includes an extension structure 135. A drain (not shown) of the MOS field effect transistor 100 is formed on the bottom surface of the NMOS substrate 110, and a source (not shown) and a gate (not shown) of the MOS field effect transistor 100 are formed on the ruthenium. The top surface of the substrate 110. A plurality of capacitor plates including a plurality of first type capacitor plates 140 and a plurality of second type capacitor plates 150 are disposed parallel to the cymbal substrate 110 above the top surface of the cymbal substrate 110.

Referring to FIGS. 2A and 2B-2F, a capacitor plate (the second type of capacitor plate 150 in this embodiment) is mounted between the top surface of the cymbal substrate 110 and the top surface of the cymbal substrate 110. a dielectric layer (not shown), a first type of capacitor plate 140 and a second type of capacitor plate 150 are filled with a dielectric layer (not shown); the first type of capacitor plate 140 and the second type of capacitor plate 150 are mutually Alternately spaced, and the first type of capacitor plates 140 are electrically connected to the source metal layer 130 for forming one electrode of the bypass capacitor, and the second type of capacitor plates 150 are electrically connected to each other for forming a bypass capacitor. Another electrode. The first type of capacitor plates 140 are longitudinally staggered with the second type of capacitor plates 150 for insulating the first layer of the first type of capacitor plates 140 between the adjacent second type of capacitor plates 150. The second type of connection layer 150a of the capacitor-like plate 140 is provided with a through hole (not shown) in the dielectric layer between the second type of capacitor plate 150 and the second type of connection layer 150a, and is injected into the through hole. The metal 150b electrically connects the second type of capacitor plates 150 to each other. The first type of capacitor plate 140 and the second type of capacitor plate 150 are longitudinally staggered for use between the adjacent first type of capacitor plates 140 and between the first type of capacitor plates 140 and the source metal layer 130. A first type of connection layer 140a insulated from the second type of capacitor plate 150 is disposed in a layer of the second type of capacitor plate 150. A through hole is disposed in the dielectric layer between the first type of capacitor plate 140 and the first type of connection layer 140a and between the source metal layer 130 and the first type of connection layer 140 adjacent to the source metal layer 130 (not shown) And electrically connecting the first type of capacitor plates 140 to each other through the metal 140b injected into the through holes, and electrically connecting the first type of capacitor plates 140 and the source metal layer 130.

A layer of the capacitor plate of any one layer is provided with a stacked gate metal layer 120a over the gate metal layer 120. The stacked gate metal layer 120a is electrically connected to the gate metal layer 120 to connect the gate. Extremely exported. A plurality of via holes are provided in the dielectric layer between the adjacent stacked gate metal layers 120a and in the dielectric layer between the stacked gate metal layer 120a and the gate metal layer 120 adjacent to the gate metal layer 120 (not The laminated gate metal layer 120a is electrically connected to the gate metal layer 120 by the metal 120b implanted in the via hole, that is, the stacked gate metal layer 120a is electrically connected to the gate. In the second B-2F, similar to the manner in which the gate metal layer 120 and the stacked gate metal layer 120a are connected, the layer of the capacitor plate of any one layer is provided with a layered extension structure 135a above the extension structure 135; The laminated extension structure 135a is used for electrical connection with the extension structure 135 Connect to export the source. A plurality of through holes (not shown) are provided in the dielectric layer between the adjacent lamination extension structures 135a and in the dielectric layer between the lamination extension structures 135a and the extension structures 135 adjacent to the extension structure 135, and are passed through the injection holes. A metal (not shown) in the hole electrically connects the laminated extension structure 135a to the extension structure 135, that is, the laminated extension structure 135a is electrically connected to the source.

In the second B-2F, the gate metal layer 120 and the source metal layer 130 are separated from each other, and the divided region between the gate metal layer 120 and the source metal layer 130 is filled with a dielectric; the layer where any one of the capacitor plates is located Each includes an insulating partition for insulating isolation of device structures (such as a capacitor plate, a stacked extension structure, and a stacked gate metal layer) that are electrically connected to each other in the layer, and the insulating partitions are filled with a dielectric. The first type of capacitor plate 140 and the second type of capacitor plate 150 are not limited to the number described in FIG. 2A-2F, and the corresponding stacked gate metal layer 120a and the layered extension structure 135a are not limited to the first The number described in Figure 2A-2F. In addition, in this embodiment, the gate metal layer 120 constituting the gate electrode of the MOS field effect transistor 100 and the source metal layer 130 constituting the source electrode are disposed on the top surface of the cymbal substrate 110, and the drain is disposed on the cymbal sheet. On the bottom surface of the substrate 110, the MOS field effect transistor 100 is a bottom drain type vertical device. The structure of the integrated capacitor of this embodiment can also be applied to other embodiments of MOS field effect transistors. In the bottom-source top-drain MOSFET vertical device of another integrated capacitor, the gate of the bottom-source top-drain MOSFET The electrode and the drain electrode are disposed on the top surface of the cymbal substrate, and the source is disposed on the bottom surface of the cymbal substrate; in other words, in the MOSFET 100 shown in FIG. 2A of the embodiment, the gate metal constituting the second electrode In another embodiment, layer 120 is converted to the gate electrode of another bottom-source drain-type MOSFET whose source metal layer 130 constituting the first electrode is converted to another bottom-source drain type in another embodiment. The drain electrode of the MOSFET, the drain (not shown) formed on the bottom surface of the NMOS substrate 110, is converted in another embodiment to the source of another bottom-source drain-type MOSFET.

Embodiment 2:

Referring to FIG. 3A (schematic diagram of the three-dimensional structure) and FIG. 3B-3F (a schematic plan view of the layer of each of the corresponding bottom-up capacitor plates in the three-dimensional structure diagram), the substrate substrate 210 is shown. A gate metal layer 220 (referred to as a second electrode metal layer) constituting a low side (Low Side) MOS field effect transistor 200 gate electrode (referred to as a second electrode) is disposed on the top surface, and A source metal layer 230 (referred to as a first electrode metal layer) of a MOS field effect transistor 200 source electrode (referred to as a first electrode), and a source metal layer 230 includes an extension structure 235. A drain (not shown) of the MOS field effect transistor 200 is formed on the bottom surface of the 210 wafer substrate, and a source (not shown) and a gate (not shown) of the MOS field effect transistor 200 are formed on the wafer. The top surface of the substrate 210. A plurality of capacitor plates including a plurality of first type capacitor plates 240 and a plurality of second type capacitor plates 250 are disposed parallel to the ruthenium substrate 210 above the top surface of the ruthenium substrate 210.

Referring to FIGS. 3A, 3B-3F, a capacitor plate (in this embodiment, the first type of capacitor plate 240) is mounted between the top surface of the cymbal substrate 210 and the top surface of the cymbal substrate 210. a dielectric layer (not shown), a first type of capacitor plate 240 and a second type of capacitor plate 250 are filled with a dielectric layer (not shown); the first type of capacitor plate 240 and the second type of capacitor plate 250 are mutually Alternately spaced, and the first type of capacitor plates 240 are electrically connected to the source metal layer 230 for forming one electrode of the bypass capacitor, and the second type of capacitor plates 250 are electrically connected to each other for forming a bypass capacitor. Another electrode. The first type of capacitor plate 240 and the second type of capacitor plate 250 are longitudinally staggered, and are arranged to be insulated first in the layer of the first type of capacitor plate 240 between the adjacent second type of capacitor plates 250. The second type of connection layer 250a of the capacitor-like plate 240 is provided with a through hole (not shown) in the dielectric layer between the second type of capacitor plate 250 and the second type of connection layer 250a, and is injected into the through hole. The metal 250b electrically connects the second type of capacitor plates 250 to each other. The first type of capacitor plate 240 and the second type of capacitor plate 250 are longitudinally staggered for providing insulation in the layer of the second type of capacitor plate 250 between the adjacent first type of capacitor plates 240. The first type of connection layer 240a of the capacitor-like plate 250. A through hole is disposed in the dielectric layer between the first type of capacitor plate 240 and the first type of connection layer 240a and between the source metal layer 230 and the first type of capacitor plate 240 adjacent to the source metal layer 230 (not shown) The first type of capacitor plates 240 are electrically connected to each other through the metal 240b injected into the through holes, and the first type of capacitor plates 240 are electrically connected to the source metal layer 230.

In the 3A, 3B-3F, the layer of the capacitor plate of any one layer is provided with a stacked gate metal layer 220a above the gate metal layer 220; wherein the stacked gate metal layer 220a is used for the gate The metal layer 220 is electrically connected to derive the gate. Adjacent gate metal layer 220a A plurality of through holes (not shown) are disposed in the dielectric layer between the dielectric layer and the gate metal layer 220a and the gate metal layer 220 adjacent to the gate metal layer 220, and are inserted into the via holes. The metal 220b electrically connects the stacked gate metal layer 220a and the gate metal layer 220, that is, electrically connects the stacked gate metal layer 220a and the gate. In the 3A, 3B-3F, similar to the manner in which the gate metal layer 220 and the stacked gate metal layer 220a are connected, the layer of the capacitor plate of any one layer is provided with a layered extension structure 235a above the extension structure 235. Wherein, the laminated extension structure 235a is used to electrically connect with the extension structure 235 to derive the source. A plurality of through holes (not shown) are provided in the dielectric layer between the adjacent lamination extension structures 235a and in the dielectric layer between the lamination extension structures 235a and the extension structures 235 adjacent to the extension structure 235, and are passed through the injection holes. A metal (not shown) in the hole electrically connects the layered extension structure 235a to the extension structure 235, that is, the layer extension structure 235a is electrically connected to the source.

In the 3B-3F diagram, the gate metal layer 220 and the source metal layer 230 are separated from each other, and the divided region between the gate metal layer 220 and the source metal layer 230 is filled with a dielectric; the layer where any one of the capacitor plates is located Each includes an insulating partition (eg, a gate metal layer 220, a layer) for insulatingly isolating device structures (such as a capacitor plate, a stacked extension structure, and a stacked gate metal layer) that are electrically connected to each other in the layer. The extension structure 235a, the second type of connection layer 250a, and the division region between the first type of capacitor plates 240) and the insulating division regions are filled with a dielectric. The first type of capacitor plate 240 and the second type of capacitor plate 250 are not limited to the number described in FIGS. 3A, 3B-3F, and the corresponding stacked gate metal layer 220a and the layered extension structure 235a are not limited. The number described in Figures 3A, 3B-3F. In addition, in this embodiment, the gate metal layer 220 constituting the gate electrode of the MOS field effect transistor 200 and the source metal layer 230 constituting the source electrode are disposed on the top surface of the cymbal substrate 210, and the drain is disposed on the cymbal sheet. The bottom surface of the substrate 210, the MOS field effect transistor 200 is a bottom drain type vertical device. The structure of the integrated capacitor of this embodiment can also be applied to other embodiments of MOS field effect transistors. In the bottom-source top-drain MOSFET vertical device of another integrated capacitor, the gate of the bottom-source top-drain MOSFET The electrode and the drain electrode are disposed on the top surface of the cymbal substrate, and the source is disposed on the bottom surface of the cymbal substrate; in other words, in the MOSFET 200 illustrated in FIG. 3A of the embodiment, the gate metal constituting the second electrode Layer 220 is converted in another embodiment The gate electrode of another bottom-drain-type MOSFET, the source metal layer 230 constituting the first electrode is converted into the drain electrode of another bottom-source drain-type MOSFET in another embodiment, which is formed The drain (not shown) on the bottom surface of the germanium substrate 210 is converted in another embodiment to the source of another bottom-source drain-type MOSFET.

Embodiment 3:

In fact, as the dielectric constant of the dielectric applied to the capacitor is continuously increased, the above embodiment is slightly noisy, and the general capacitor does not require the multilayer capacitor plate of the first embodiment or the second embodiment as a further improvement of the above embodiment. The following will provide a more concise implementation.

Referring to FIG. 4A (schematic diagram of the three-dimensional structure) and FIG. 4B-4E (a schematic plan view of the layer of each of the corresponding bottom-up capacitor plates in the three-dimensional structure diagram), the MOS field effect transistor 300 is integrated. There is a bypass capacitor in which a gate metal layer 320 constituting a gate electrode (referred to as a second electrode) of a low side (Low Side) MOS field effect transistor 300 is disposed on a top surface of a germanium substrate 310. (referred to as a second electrode metal layer), and a source metal layer 330 (referred to as a first electrode metal layer) constituting a source electrode (referred to as a first electrode) of the MOS field effect transistor 300, and the source metal layer 330 includes An extension structure 335. Above the top surface of the cymbal substrate 310 is disposed a multilayer capacitor plate including a first type of capacitor plate 340 and two second type of capacitor plates 350 parallel to the cymbal substrate 310. On the top surface of the cymbal substrate 310 and a capacitor plate above the top surface of the cymbal substrate 310 (Fig. 4A is regarded as the second type of capacitor plate 350) and adjacent two capacitor plates (4A) The figure is considered to be filled with a dielectric layer between the first type of capacitor plate 340 and the second type of capacitor plate 350). The first type of capacitor plate 340 and the second type of capacitor plate 350 are alternately spaced apart from each other, and the first type of capacitor plate 340 is electrically connected to the source metal layer 330 for forming an electrode of the bypass capacitor, and the second type The capacitor plates 350 are electrically connected to each other to form another electrode of the bypass capacitor. A drain (not shown) of the MOS field effect transistor 300 is formed on the bottom surface of the NMOS substrate 310, and a source (not shown) and a gate (not shown) of the MOS field effect transistor 300 are formed on the ruthenium. The top surface of the substrate 310.

Referring to FIGS. 4A, 4B-4E, the top surface of the cymbal substrate 310 and the cymbal substrate 310 are shown. A capacitor plate (in this embodiment, the second type of capacitor plate 350) is filled with a dielectric layer (not shown), and the first type of capacitor plate 340 and the second type of capacitor plate 350 are filled. There is a dielectric layer (not shown); the first type of capacitor plate 340 and the second type of capacitor plate 350 are alternately spaced apart from each other, and the first type of capacitor plate 340 is electrically connected to the source metal layer 330 for forming a side One electrode of the capacitance of the circuit, and the second type of capacitor plates 350 are electrically connected to each other to form another electrode of the bypass capacitor. The first type of capacitor plate 340 and the second type of capacitor plate 350 are longitudinally staggered, and are arranged to be insulated first in the layer of the first type of capacitor plate 340 between the adjacent second type of capacitor plates 350. A second type of connection layer 350a of the capacitor-like plate 340, and a through hole (not shown) is disposed in the dielectric layer between the second type of capacitor plate 350 and the second type of connection layer 350a, and is inserted into the through hole. The metal 350b electrically connects the second type of capacitor plates 350 to each other. The first type of capacitor plate 340 and the second type of capacitor plate 350 are longitudinally staggered for providing insulation in a layer where the second type of capacitor plate 350 between the first type of capacitor plate 340 and the source metal layer 330 is located. The first type of connection layer 340a of the second type of capacitor plate 350. A through hole is disposed in the dielectric layer between the first type of capacitor plate 340 and the first type of connection layer 340a and between the source metal layer 330 and the first type of connection layer 340 adjacent to the source metal layer 330 (not shown) And electrically connecting the first type of capacitor plate 340 and the source metal layer 330 through the metal 340b injected into the via. In the 4A, 4B-4E, the layer of the capacitor plate of any one layer is provided with a stacked gate metal layer 320a above the gate metal layer 320; wherein the stacked gate metal layer 320a is used for the gate The metal layer 320 is electrically connected to lead the gate. A plurality of via holes are provided in the dielectric layer between the adjacent stacked gate metal layers 320a and in the dielectric layer between the stacked gate metal layer 320a and the gate metal layer 320 adjacent to the gate metal layer 320 (not The stacked gate metal layer 320a is electrically connected to the gate metal layer 320 by the metal 320b implanted in the via hole, that is, the stacked gate metal layer 320a is electrically connected to the gate.

4A, 4B-4E, similar to the manner in which the gate metal layer 320 and the stacked gate metal layer 320a are connected, the layer of the capacitor plate of any one layer is provided with a layered extension structure 335a above the extension structure 335. Wherein, the laminated extension structure 335a is used to electrically connect with the extension structure 335 to derive the source. Provided in the dielectric layer between the adjacent lamination extension structures 335a and in the dielectric layer between the lamination extension structures 335a and the extension structures 335 adjacent to the extension structure 335 a plurality of through holes (not shown), and electrically connecting the laminated extension structures 335a to each other through a metal (not shown) injected into the through holes, and the laminated extension structure 335a is electrically connected to the extension structure 335 at the same time, that is, The laminated extension structure 335a will be electrically connected to the source.

In FIG. 4B-4E, the gate metal layer 320 and the source metal layer 330 are separated from each other, and the divided region between the gate metal layer 320 and the source metal layer 330 is filled with a dielectric; the layer where any one of the capacitor plates is located Each includes an insulating partition for insulating isolation of device structures (such as a capacitor plate, a stacked extension structure, and a stacked gate metal layer) that are electrically connected to each other in the layer, and the insulating partitions are filled with a dielectric. In addition, in this embodiment, the gate metal layer 320 constituting the gate electrode of the MOS field effect transistor 300 and the source metal layer 330 constituting the source electrode are disposed on the top surface of the cymbal substrate 310, and the drain is disposed on the cymbal sheet. The bottom surface of the substrate 310, the MOS field effect transistor 300 is a bottom drain type vertical device. The structure of the integrated capacitor of this embodiment can also be applied to other embodiments of MOS field effect transistors. In the bottom-source top-drain MOSFET vertical device of another integrated capacitor, the gate of the bottom-source top-drain MOSFET The electrode and the drain electrode are disposed on the top surface of the cymbal substrate, and the source is disposed on the bottom surface of the cymbal substrate; in other words, in the MOSFET 300 illustrated in FIG. 4A of the embodiment, the gate metal constituting the second electrode Layer 320 is converted in another embodiment to the gate electrode of another bottom-source drain-type MOSFET whose source metal layer 330 constituting the first electrode is converted to another bottom-source drain type in another embodiment The drain electrode of the MOSFET, the drain (not shown) formed on the bottom surface of the NMOS substrate 310, is converted in another embodiment to the source of another bottom-source drain-type MOSFET.

Embodiment 4:

The above embodiments are based on connecting the first type of capacitor plates to each other through the first type of connection layer, or connecting the first type of capacitor plates to the source metal layer through the first type of connection layer. As a further simplification, another embodiment described below is disclosed.

See FIGS. 5A-1 and 5A-2 (5A-1 is a schematic view of the front side of the reticle substrate 410, 5A-2 is a schematic view of the rear side of the reticle substrate 410), and FIG. 5B-5E ( A schematic plan view of the corresponding layer of the bottom-up capacitor layer of each layer in the three-dimensional structure diagram) A gate metal layer 420 (referred to as a second electrode metal layer) constituting a gate electrode (referred to as a second electrode) of the low-side MOS field effect transistor 400 is disposed on a top surface of the substrate 410. A source metal layer 430 (referred to as a second electrode metal layer) constituting a source electrode (referred to as a first electrode) of the MOS field effect transistor 400, and a source metal layer 430 includes an extension structure 435. A plurality of first type capacitor plates 440 are disposed above the top surface of the cymbal substrate 410 in parallel with the substrate of the cymbal 410. As a simplification measure, the first type of capacitor plate of the first type includes a first type of capacitor. The plate 440) and the plurality of capacitor plates of the second type of capacitor plate 450. Between the top surface of the cymbal substrate 410 and a capacitor plate (the second type of capacitor plate 450) above the top surface of the cymbal substrate 410 and the adjacent two capacitor plates (the first type of capacitor plate 440) A dielectric layer (not shown) is filled between the second type of capacitor plates 450). The first type of capacitor plates 440 and the second type of capacitor plates 450 are alternately spaced apart from each other, and the first type of capacitor plates 440 are electrically connected to the source metal layer 430 for forming an electrode of the bypass capacitor, and second The capacitor-like plates 450 are electrically connected to each other to form another electrode of the bypass capacitor. A drain (not shown) of the MOS field effect transistor 400 is formed on the bottom surface of the cymbal substrate 410, and a source (not shown) and a gate (not shown) of the MOS field effect transistor are formed on the lining of the cymbal lining The top of the bottom 410.

Referring to FIG. 5A-1, any layer of the capacitor plate is provided with a stacked gate metal layer 420a over the gate metal layer 420; the stacked gate metal layer 420a is used for electrical connection with the gate metal layer 420. Connect to export the gate. A plurality of via holes are provided in the dielectric layer between the adjacent stacked gate metal layers 420a and in the dielectric layer between the stacked gate metal layer 420a and the gate metal layer 420 adjacent to the gate metal layer 420 (not The grounded gate metal layer 420a is electrically connected to the gate metal layer 420, that is, electrically connected to the gate, by the metal 420b implanted in the via. Referring to FIG. 5A-2, the source metal layer 430 is provided with an extension structure 435, and the layers of the capacitor plates of any one layer are provided with a layered extension structure 435a above the extension structure 435; the layer extension structure 435a is used for The extension structure 435 is electrically connected to derive the source. A plurality of through holes (not shown) are provided in the dielectric layer between the adjacent lamination extension structures 435a and in the dielectric layer between the lamination extension structures 435a and the extension structures 435 of the extension structure 435, and are passed through the injection holes. The metal 435b in the hole electrically connects the layer extension structure 435a to the source.

Referring to FIGS. 5A-1 and 5A-2, the first type of capacitor plates 440 and the second type of capacitor plates 450 are longitudinally staggered for use in the first type of capacitor poles between adjacent second type of capacitor plates 450. A second type of connection layer 450a insulated from the first type of capacitor plate 440 is disposed in the layer where the board 440 is located, and a through hole is disposed in the dielectric layer between the second type of capacitor plate 450 and the second type of connection layer 450a ( Not shown), and the second type of capacitor plates 450 are electrically connected to each other through the metal 450b injected into the via holes. Referring to FIG. 5A-2, any of the first type of capacitor plates 440 is connected to the layered extension structure 435a of the layer of the first type of capacitor plates 440. Therefore, the first type of capacitor plates 440 are electrically connected to the layer extension structure 435a, and the layer extension structure 435a is electrically connected to the source metal layer 430, so that the first type of capacitor plates 440 are both source metal and source metal. Layer 430 is electrically connected.

In the 5B-5E, the gate metal layer 420 and the source metal layer 430 are separated from each other, and the partition between the gate metal layer 420 and the source metal layer 430 is filled with a dielectric; the layer where any one of the capacitor plates is located Each includes an insulating partition for insulating isolation of device structures (such as a capacitor plate, a stacked extension structure, and a stacked gate metal layer) that are electrically connected to each other in the layer, and the insulating partitions are filled with a dielectric. In addition, in this embodiment, the gate metal layer 420 constituting the gate electrode of the MOS field effect transistor 400 and the source metal layer 430 constituting the source electrode are disposed on the top surface of the cymbal substrate 410, and the drain is disposed on the ruthenium. The bottom surface of the substrate 410, the MOS field effect transistor 400 is a bottom drain type vertical device. The structure of the integrated capacitor of this embodiment can also be applied to other embodiments of MOS field effect transistors. In the bottom-source top-drain MOSFET vertical device of another integrated capacitor, the gate of the bottom-source top-drain MOSFET The electrode and the drain electrode are disposed on the top surface of the cymbal substrate, and the source is disposed on the bottom surface of the cymbal substrate; in other words, in the MOSFET 400 shown in FIGS. 5A-1 and 5A-2 of the embodiment, The gate metal layer 420 constituting the second electrode is converted into a gate electrode of another bottom-source top-drain MOSFET in another embodiment, and the source metal layer 430 constituting the first electrode is converted in another embodiment The drain electrode of another bottom drain type MOSFET, the drain (not shown) formed on the bottom surface of the cymbal substrate 410 is converted into another bottom drain type MOSFET in another embodiment. The source.

Embodiment 5:

The above embodiments all integrate a capacitor with a single-chip low-side MOSFET, including one The specific design of the integrated capacitor in the low MOSFET and the high MOSFET's dual MOSFET is as follows. A design and fabrication of a dual MOSFET comprising a low side MOSFET and a high side MOSFET can be found in U.S. Patent Application Serial No. US 2008/0067584 A1.

See Figure 6A-1 (schematic diagram of the front side of the slab substrate 510), and Figure 6B-6E (the schematic diagram of the corresponding layer of the bottom-up capacitor layer of each layer in the schematic view of the three-dimensional structure) The dual MOS field effect transistor 500 is integrated with a bypass capacitor, wherein a first gate metal layer 521 constituting the first transistor gate electrode and a first electrode are disposed on a top surface of the NMOS substrate 510. A drain metal layer 531 of the crystal drain electrode, a second gate metal layer 522 constituting the second transistor gate electrode, and a source metal layer 532 constituting the second transistor source electrode. The first transistor is a high-end MOS field effect transistor, and the second transistor is a low-end MOS field effect transistor.

A plurality of first type capacitor plates (such as a first type capacitor plate 540 in this embodiment) and a plurality of second type capacitors are disposed above the top surface of the cymbal substrate 510 parallel to the cymbal substrate 510. a multi-layer capacitor plate of the plate 550, and between a top surface of the cymbal substrate 510 and a capacitor plate above the top surface of the cymbal substrate 510 (such as the second type of capacitor plate 550 in this embodiment) and A dielectric layer (not shown) is filled between two adjacent capacitor plates (such as the second type of capacitor plate 550 and the first type of capacitor plate 540). The first type of capacitor plates 540 and the second type of capacitor plates 550 are alternately spaced apart from each other, and the first type of capacitor plates 540 are electrically connected to the drain metal layer 531 for forming an electrode of the bypass capacitor, and second The capacitor-like plates 550 are each electrically connected to the source metal layer 532 for forming the other electrode of the bypass capacitor. A source (not shown) of the first transistor is formed on a bottom surface of the cymbal substrate 510, and a drain and a gate (not shown) of the first transistor are formed on a top surface of the cymbal substrate 510; A drain (not shown) of the crystal is formed on the bottom surface of the ruthenium substrate 510, and a source and a gate (not shown) of the second transistor are formed on the top surface of the ruthenium substrate 510. A layer of the capacitor plate of any one layer is disposed above the first gate metal layer 521 with a first stacked gate metal layer 521a; wherein the first stacked gate metal layer 521a is used for the first gate metal Layer 521 is electrically connected to derive the gate of the first transistor. A layer of the capacitor plate of any one layer is provided with a second stacked gate metal layer 522a above the second gate metal layer 522; wherein the second stacked gate metal layer 522a is used for The second gate metal layer 522 is electrically connected to derive the gate of the second transistor.

Refer to FIG. 6A-2 (a schematic view of the rear side of the slab substrate 510), and FIG. 6B-6E (a schematic plan view of the corresponding bottom-up layer of each of the capacitor plates in the schematic view of the three-dimensional structure) The drain metal layer 531 is provided with a first extension structure 535, and a layer of any one of the capacitor plates is disposed above the first extension structure 535 with a first layer extension structure 535a; wherein, the first layer extension structure 535a is used to electrically connect with the first extension structure 535 to lead the first transistor drain. Refer to FIG. 6A-2 (a schematic view of the rear side of the slab substrate 510), and FIG. 6B-6E (a schematic plan view of the corresponding bottom-up layer of each of the capacitor plates in the schematic view of the three-dimensional structure) The source metal layer 532 is provided with a second extension structure 536, and a layer of any one of the capacitor plates is disposed above the second extension structure 536 with a second layer extension structure 536a; wherein the second layer extension structure 536a is for electrically connecting with the second extension structure 536 to derive the second transistor source.

Referring to FIG. 6A-1, in the dielectric layer between adjacent first stacked gate metal layers 521a and in the first stacked gate metal layer 521a and the first gate adjacent to the first gate metal layer 521 A plurality of through holes (not shown) are disposed in the dielectric layer between the electrode metal layers 521, and the first stacked gate metal layers 521a are electrically connected to each other through the metal 521b injected into the through holes, and the first layer is simultaneously The gate metal layer 521a is electrically connected to the first gate metal layer 521, that is, the first stacked gate metal layer 521a is electrically connected to the gate of the first transistor. Referring to FIG. 6A-1, the dielectric layer between the adjacent second stacked gate metal layers 522a and the second stacked gate metal layer 522a and the second gate adjacent to the second gate metal layer 522. A plurality of through holes (not shown) are disposed in the dielectric layer of the inter-metal layer 522, and the second stacked gate metal layers 522a are electrically connected to each other through the metal 522b injected into the via holes, and the second layer is stacked The gate metal layer 522a is electrically connected to the second gate metal layer 522, that is, the second stacked gate metal layer 522a is electrically connected to the gate of the second transistor.

Referring to FIG. 6A-2, the dielectric layer between the adjacent first stacked extension structures 535a and the dielectric layer between the first extended extension structures 535a and the first extended structures 535 adjacent to the first extended structures 535. A plurality of through holes (not shown) are provided, and the first stacked extension structures 535a are electrically connected to each other through the metal 535b injected into the through holes, and the first laminated extension structure 535a is The electrical connection between the first extension structure 535 and the first extension structure 535a is electrically connected to the drain of the first transistor. Referring to FIG. 6A-2, the dielectric layer between the adjacent second stacked extension structures 536a and the dielectric layer between the second extended extension structures 536a and the second extended structures 536 adjacent to the second extended structures 536. A plurality of through holes (not shown) are provided, and the second stacked extension structures 536a are electrically connected to each other through the metal 536b injected into the through holes, and the second laminated extension structure 536a and the second extended structure are The electrical connection 536 is electrically connected to the second laminated extension 536a and the source of the second transistor.

Referring to FIG. 6A-1 and FIG. 6B-6E (a schematic plan view of a layer of each of the corresponding bottom-up capacitor plates in the schematic view of the three-dimensional structure), the first type of capacitor plates 540 and the second The capacitor-like plate 550 is longitudinally staggered and configured to provide a second type of connection insulated from the first type of capacitor plate 540 in a layer of the first type of capacitor plate 540 between adjacent second type of capacitor plates 550. a layer 550a; a via hole is disposed in the dielectric layer between the second type of capacitor plate 550 and the second type of connection layer 550a and between the source metal layer 532 and the second type of capacitor plate 550 adjacent to the source metal layer 532 (not shown), and the second type of capacitor plate 550 is electrically connected to the second type of connection layer 550a through the metal 550b injected into the through hole, and the second type of capacitor plates 550 are electrically connected to each other. The second type of capacitor plate 550 is electrically connected to the source metal layer 532. Referring to FIG. 6A-1 and FIG. 6B-6E (a schematic plan view of a layer of each of the corresponding bottom-up capacitor plates in the schematic view of the three-dimensional structure), the first type of capacitor plates 540 and the second The capacitor-like plates 550 are arranged in a longitudinally staggered manner for the adjacent first type of capacitor plates (the first type of capacitor plates may have multiple layers, and the first type of capacitor plates of the present embodiment comprise a first type of capacitor plates 540). a first type of connection layer 540a insulated from the second type of capacitor plate 550 is disposed in a layer between the first type of capacitor plate 540 and the second type of capacitor plate 550 between the drain metal layer 531; A through hole (not shown) is disposed in the dielectric layer between the capacitor-like plate 540 and the first type of connection layer 540a and between the drain metal layer 531 and the first type of connection layer 540a adjacent to the drain metal layer 531, and The first type of capacitor plates 540 are electrically connected to each other through the metal 540b injected into the through holes (if the first type of capacitor plates have multiple layers), and the first type of capacitor plates 540 and the drain metal layer 531 are electrically connected. .

In FIG. 6B-6E, the first gate metal layer 521, the drain metal layer 531, and the source metal The layer 532 and the second gate metal layer 522 are separated and separated from each other by the dividing region, and the dividing region is filled with a dielectric; the layer where any one of the capacitor plates is located includes a device structure for insulating and isolating the mutually non-electrical connection in the layer. (such as capacitor plate, first layer extension structure, second layer extension structure, first layer of stacked gate metal layer, second layer of stacked gate metal layer, first type of connection layer, second type of connection layer) The insulating partition and the insulating partition are filled with a dielectric.

If it is desired to obtain a larger capacitance value, the number of layers of the first type of capacitor plate 540 and the second type of capacitor plate 550 in Embodiment 5 may not be limited to those described in FIGS. 6A-1, 6A-2, and 6B-6E. The number of the first stacked gate metal layer 521a, the second stacked gate metal layer 522a, the first stacked extension structure 535a, and the second stacked extension structure 536a are also not limited to the 6A-1. , the number described in the figures 6A-2, 6B-6E.

Example 6:

The fifth embodiment is based on electrically connecting the first type of capacitor plates to the drain metal layer through the first type of connection layer, and connecting the second type of capacitor plates to each other or to the source metal through the second type of connection layer. On the floor. As a further simplification, a more concise embodiment of the following will be disclosed without departing from the spirit of the invention.

See Fig. 7A-1 (schematic diagram of the front side of the reticle substrate 610), Fig. 7A-2 (schematic view of the rear side of the cymbal substrate 610), and Fig. 7B-7E (corresponding to the three-dimensional structure The double MOS field effect transistor 600 is integrated with a bypass capacitor, wherein the top surface of the substrate 610 is disposed on the top surface of the substrate 610. a first gate metal layer 621 of the transistor gate electrode, a drain metal layer 631 constituting the first transistor drain electrode, and a second gate metal layer 622 constituting the second transistor gate electrode and a second structure A source metal layer 632 of the transistor source electrode. The first transistor is a high-end MOS field effect transistor, and the second transistor is a low-end MOS field effect transistor. A plurality of first type capacitor plates (such as a first type capacitor plate 640 in this embodiment) and a plurality of second type capacitors are disposed above the top surface of the cymbal substrate 610 parallel to the cymbal substrate 610. a multi-layer capacitor plate of the plate 650, and a capacitor plate on the top surface of the cymbal substrate 610 and the top surface of the cymbal substrate 610 (such as The second type of capacitor plates 650) in the embodiment and between two adjacent capacitor plates (such as the second type of capacitor plates 650 and the first type of capacitor plates 640) are filled with a dielectric layer (not shown). ). The first type of capacitor plates 640 and the second type of capacitor plates 650 are alternately spaced apart from each other, and the first type of capacitor plates 640 are electrically connected to the drain metal layer 631 for forming an electrode of the bypass capacitor, and second The capacitor-like plates 650 are electrically connected to the source metal layer 632 for forming the other electrode of the bypass capacitor. A source (not shown) of the first transistor is formed on a bottom surface of the cymbal substrate 610, and a drain and a gate (not shown) of the first transistor are formed on a top surface of the cymbal substrate 610; A drain (not shown) of the crystal is formed on the bottom surface of the ruthenium substrate 610, and a source and a gate (not shown) of the second transistor are formed on the top surface of the ruthenium substrate 610. A layer of the capacitor plate of any one layer is disposed above the first gate metal layer 621 with a first stacked gate metal layer 621a; wherein the first stacked gate metal layer 621a is used for the first gate metal Layer 621 is electrically connected to derive the gate of the first transistor. A layer of the capacitor plate of any one layer is disposed on the second gate metal layer 622 with a second stacked gate metal layer 622a; wherein the second stacked gate metal layer 622a is used for the second gate metal Layer 622 is electrically connected to derive the gate of the second transistor.

See Figure 7A-2 (schematic diagram of the rear side of the slab substrate 610), and Figure 7B-7E (the schematic diagram of the corresponding layer of the bottom-up capacitor layer of each layer in the schematic view of the three-dimensional structure) The drain metal layer 631 is provided with a first extension structure 635, and a layer of any one of the capacitor plates is disposed above the first extension structure 635 with a first layer extension structure 635a; wherein, the first layer extension structure 635a is for electrically connecting with the first extension structure 635 to lead the first transistor drain. See Figure 7A-2 (schematic diagram of the rear side of the slab substrate 610), and Figure 7B-7E (the schematic diagram of the corresponding layer of the bottom-up capacitor layer of each layer in the schematic view of the three-dimensional structure) The source metal layer 632 is provided with a second extension structure 636, and a layer of any one of the capacitor plates is disposed above the second extension structure 636 with a second layer extension structure 636a; wherein the second layer extension structure 636a is for electrically connecting with the second extension structure 636 to derive the second transistor source.

Referring to FIG. 7A-1, in the dielectric layer between adjacent first stacked gate metal layers 621a and in the first stacked gate metal layer 621a and the first gate adjacent to the first gate metal layer 621 A plurality of through holes (not shown) are disposed in the dielectric layer between the epitaxial metal layers 621, and the first stacked gate metal layers 621a are electrically connected to each other through the metal 621b injected into the via holes, and the first layer is simultaneously The gate metal layer 621a is electrically connected to the first gate metal layer 621, that is, the first stacked gate metal layer 621a is electrically connected to the gate of the first transistor. Referring to FIG. 7A-1, in the dielectric layer between adjacent second stacked gate metal layers 622a and in the second stacked gate metal layer 622a and second gate adjacent to the second gate metal layer 622 A plurality of through holes (not shown) are disposed in the dielectric layer of the inter-metal layer 622, and the second stacked gate metal layers 622a are electrically connected to each other through the metal 622b implanted in the via holes, and the second layer is stacked The gate metal layer 622a is electrically connected to the second gate metal layer 622, that is, the second stacked gate metal layer 622a is electrically connected to the gate of the second transistor.

Referring to FIG. 7A-2, the dielectric layer between the adjacent first stacked extension structures 635a and the dielectric layer between the first extended extension structures 635a and the first extended structures 635 adjacent to the first extended structures 635. a plurality of through holes (not shown) are provided, and the first layer extension structures 635a are electrically connected to each other through the metal 635b injected into the through holes, and the first layer extension structure 635a and the first extension structure are The electrical connection 635 is electrically connected, thereby electrically connecting the first stacked extension structure 635a to the drain of the first transistor. Referring to FIG. 7A-2, the dielectric layer between the adjacent second stacked extension structures 636a and the second extended structure 636a and the second extended structure 636 adjacent to the second extended structure 636. A plurality of through holes (not shown) are provided, and the second laminated extension structures 636a are electrically connected to each other through the metal 636b injected into the through holes, and the second laminated extension structure 636a and the second extended structure are The electrical connection 636 is electrically connected, thereby electrically connecting the second laminated extension structure 636a to the source of the second transistor.

See Figure 7A-2, Figure 7B-7E (the schematic diagram of the layer of the corresponding bottom-up capacitor layer in the three-dimensional structure diagram), any one of the first type of capacitor plates 640 Connected to the first layer extension structure 635a of the layer of the first type of capacitor plate 640 of the layer. The second type of capacitor plates 650 of any one of the layers are connected to the second layer extension structure 636a of the layer of the second type of capacitor plates 650. Therefore, the first type of capacitor plates 640 are electrically connected to the first layer extension structure 635a, and the first layer extension structure 635a is electrically connected to the drain metal layer 631, so that the first type of capacitor plates 640 are Electrical properties with the drain metal layer 631 The second type of capacitor plate 650 is electrically connected to the second layer extension structure 636a, and the second layer extension structure 636a is electrically connected to the source metal layer 632. The source metal layer 632 is electrically connected.

In FIG. 7B-7E, the first gate metal layer 621, the drain metal layer 631, the source metal layer 632, and the second gate metal layer 622 are separated and separated from each other by a division region, and the division region is filled with a dielectric; any layer The layers on which the capacitor plates are located include device structures for insulating and isolating each other from each other (eg, a capacitor plate, a first layer extension structure, a second layer extension structure, and a first layer stack gate) The insulating partition of the metal layer and the second stacked gate metal layer and the insulating partition are filled with a dielectric.

If it is desired to obtain a larger capacitance value, the number of layers of the first type of capacitor plate 640 and the second type of capacitor plate 650 in Embodiment 6 may not be limited to those described in FIGS. 7A-1, 7A-2, and 7B-7E. The number of the first stacked gate metal layer 621a, the second stacked gate metal layer 622a, the first stacked extension structure 635a, and the second stacked extension structure 636a are also not limited to the 7A-1. , the number described in the figures 7A-2, 7B-7E.

Based on the technical solution of the above embodiment, a method of preparing an integrated capacitor on a metal oxide semiconductor field effect transistor (MOSFET) is now provided.

Referring to Figures 8A-8L and 4A-4E, the capacitor structure of the technical solution disclosed in Embodiment 3 (Fig. 4A-4E) will be described. Referring to Figures 8A-8L, the preparation method is as follows: in a MOS field The dielectric layer 711, 713, 715 and the plurality of deposited metal layers 712, 714, 716 are deposited on the top surface of the cymbal substrate 710 where the effect transistor is located to form a dielectric layer and a metal layer on the top surface of the cymbal substrate 710. An alternating multilayer dielectric layer and a plurality of metal layers. The dielectric layers 711, 713, and 715 are etched after depositing the dielectric layers 711, 713, and 715 for forming a plurality of via holes in the dielectric layer (such as 711a, 713a, and 715a and through holes not shown in the drawing). The following will be mentioned; wherein, after depositing the metal layers 712, 714, 716, the metal layers 712, 714, 716 are etched and divided for dividing the metal layers 712, 714, 716 into different metal regions (such as 712a). , 712b, 712c, 714a, 714b, 714c, 716a, 716b and metal regions not shown in the figure, the following will be mentioned And a part of the metal region forms a capacitor plate, and the metal layer is filled with a metal to fill the via holes included in the dielectric layer (such as 711a, 713a, 715a and a through hole not shown in the figure, the following content will be Mention). After any one of the metal layers is etched and divided, a layered extension structure (not shown) and a stacked gate metal layer (such as 712a, 714a, 716a) on the layer where the metal layer is formed are formed.

A dielectric layer 711 is deposited on the top surface of the NMOS substrate 710 where the MOS field effect transistor is located, and a plurality of through holes 711a are formed in the dielectric layer 711 by etching the dielectric layer 711; FIG. 8A-8L is a cross-sectional view of FIG. 4A. In the 8A-8L diagram, the metal layers 712, 714, and 716 are etched and divided to form the metal cut patterns shown in the fourth C, 4D, and 4E drawings. A metal layer 712 is deposited on the dielectric layer 711 and the metal layer 712 is divided by etching to divide the metal layer 712 into different metal regions, and the metal layer 712 is deposited while filling the via hole included in the dielectric layer 711 with metal. 711a. The dielectric layer and the metal layer are repeatedly deposited a plurality of times to form a plurality of dielectric layers and a plurality of metal layers alternately between the dielectric layers 711, 713, 515 and the metal layers 712, 714, 716 on the top surface of the ruthenium substrate. Specific steps are as follows:

Referring to FIG. 8A, the top surface of the cymbal substrate 710 includes a gate metal layer 720 constituting a MOS field effect transistor gate electrode, a source metal layer 730 constituting a MOS field effect transistor source electrode, and a source metal layer 730. An extension structure (not shown, refer to FIG. 4B). A dielectric layer 711 is deposited on the top surface of the gusset substrate 710. The gate metal layer 720 and the source metal layer 730 are separated from each other, and the dielectric layer 711 is deposited to fill the dielectric between the gate metal layer 720 and the source metal layer 730. Referring to FIG. 8B, a plurality of via holes 711a are formed in the dielectric layer 711 by etching the dielectric layer 711. The via 711a is selectively etched into the dielectric over the gate metal layer 720 over the extended structure, and patterned in the dielectric layer 711 in the dielectric below the first type of connection layer 712b mentioned below. Through hole 711a. Referring to FIG. 8C, a metal layer 712 is formed on the dielectric layer 711. During the formation of the metal layer 712, metal is implanted into the via hole 711a. Referring to FIG. 8D, the etched metal layer 712 is etched to form metal regions 712a, 712b, and 712c, wherein the metal region 712a constitutes a stacked gate metal layer over the gate metal layer 720, and the metal region 712b constitutes a first type of connection layer. The metal region 712c constitutes a second type of capacitor plate, and the etched divided metal layer 712 also forms a layer extension over the extended structure. Stretching structure (not shown). Referring to FIG. 8E, a dielectric layer 713 is deposited on the top surface of the metal layer 712. The deposition dielectric layer 712 is simultaneously used to fill the dielectric contained in the metal layer 712 with a dielectric region. Referring to FIG. 8F, a plurality of via holes 713a are formed in the dielectric layer 713 by etching the dielectric layer 713. The via 713a is selectively etched into the dielectric above the metal region 712a, the metal region 712b, and the metal region 712c. The metal layer 712 includes a via hole 713a formed above the layered extension structure. Referring to FIG. 8G, a metal layer 714 is formed on the dielectric layer 713. During the formation of the metal layer 714, metal is implanted into the via 713a. Referring to FIG. 8H, the etched metal layer 714 is etched to form metal regions 714a, 714b, and 714c, wherein the metal region 714a constitutes a stacked gate metal layer over the gate metal layer 720, and the metal region 714b constitutes a first type of capacitor plate. The metal region 714c constitutes a second type of connection layer, and the etched metal layer 714 also forms a layered extension structure (not shown) over the extension structure. During the etching of the divided metal layer 714, the first type of capacitor plates are longitudinally staggered with the second type of capacitor plates. Referring to FIG. 8I, a dielectric layer 715 is deposited on the top surface of the metal layer 714. The deposited dielectric layer 715 is also used to fill the dielectric contained in the metal layer 714 with a dielectric. Referring to FIG. 8J, a plurality of vias 715a are formed in the dielectric layer 715 by etching the dielectric layer 715. The via 715a is selectively etched into the dielectric above the metal region 714a and the metal region 714c, and the via 713a is also formed over the layered extension structure of the metal layer 714. Referring to FIG. 8K, a metal layer 716 is formed on the dielectric layer 715. During the formation of the metal layer 716, metal is implanted into the via 715a. Referring to FIG. 8L, the etched metal layer 716 is etched to form metal regions 716a, 716b, wherein the metal region 716a constitutes a stacked gate metal layer over the gate metal layer 720, and the metal region 716b constitutes a second type of capacitor plate, etched The split metal layer 716 also forms a lamination extension structure over the extension structure (not shown in the figure, as shown in the third embodiment of FIGS. 4C, 4D, 4E). Fig. 8L is a cross-sectional view shown in Fig. 4A. In the eighth embodiment, the metal layers 712, 714, and 716 are etched and divided to form metal cut patterns shown in Figs. 4C, 4D, and 4E.

During the process of etching the divided metal layer 716, the first type of capacitor plates are longitudinally staggered with the second type of capacitor plates, so that the metal region 714c can inject a second type of capacitor by injecting a metal between the second type of capacitor plates and the metal region 714c. The plates are connected to each other.

In the above method, if the dielectric layer is further deposited on the metal layer 716 to redeposit the metal layer, as described above, the structure shown in the first embodiment 1A, 1B-1F can be formed, and the difference is only the metal layer and The number of layers of the dielectric layer can be unlimited. In the above method, any one metal layer (such as 712, 714, 716 or more metal layers) is etched and divided to form a stacked extension structure over the extended structure and a stacked gate metal layer over the gate metal layer. . a plurality of metal layers (such as 712, 714, 716 or more metal layers) are etched and divided to form a plurality of capacitor plates comprising a plurality of first type capacitor plates and a plurality of second type capacitor plates at different levels; The first type of capacitor plate and the second type of capacitor plate are alternately arranged at intervals. In the above method, a plurality of metal layers (such as 712, 714, 716 or more metal layers) are etched and divided to form an insulation layer in a layer of the first type of capacitor plates between adjacent second type of capacitor plates. The second type of connection layer of the first type of capacitor plate. Etching a dielectric layer (such as 713, 715 or more dielectric layers) to etch a plurality of vias in the dielectric layer between the second type of capacitor plates and the second type of connection layer, and by implanting a second type of capacitor The metal in the via hole in the dielectric layer between the board and the second type of connection layer electrically connects the second type of capacitor plates to each other. In the above method, after the multilayer metal layer is etched and divided, between the adjacent first type of capacitor plates (if a plurality of first type capacitor plates are formed) and the second type of capacitor plates between the first type of capacitor plates and the source metal layer A first type of connection layer insulated from the second type of capacitor plates is formed in the layer. Etching the dielectric layer to etch a plurality of via holes in the dielectric layer between the first type of capacitor plate and the first type of connection layer and between the source metal layer and the first type of connection layer adjacent to the source metal layer, and pass through The metal in the via hole in the dielectric layer between the first type of capacitor plate and the first type of connection layer electrically connects the first type of capacitor plates to each other through the first type of connection layer adjacent to the source metal layer The metal in the via hole in the dielectric layer between the source metal layers electrically connects the first type of connection layer to the source metal layer. In the above method, the etch dielectric layer etches a plurality of via holes between the adjacent lamination extension structures and the dielectric layer between the lamination extension structure and the extension structure of the extension structure, by implanting adjacent lamination extension structures The metal in the through hole in the dielectric layer between the layered extension structure and the extension structure between the extension structure and the extension structure electrically connects adjacent layer extension structures, and electrically connects the layer extension structure and the extension structure . In the above method, the etching dielectric layer etches a plurality of via holes in the dielectric layer between the adjacent stacked gate metal layers and between the stacked gate metal layer and the gate metal layer of the gate metal layer. Injecting adjacent stacked gate gold The metal in the via hole in the dielectric layer between the layer and between the gate metal layer and the gate metal layer electrically connects the adjacent stacked gate metal layers, and The stacked gate metal layer is electrically connected to the gate metal layer. In the above method, the gate metal layer and the source metal layer are separated from each other, and the dielectric layer is deposited to fill the dielectric between the gate metal layer and the source metal layer; and the dielectric layer is deposited to etch the divided metal layer. The formed insulating partition fills the dielectric.

Referring to Fig. 9, the preparation method for the implementation of the second (Fig. 3A, 3B-3F) is similar to the above steps 8A-8L, and the specific steps are not described again. The preparation method comprises: depositing a dielectric layer 811, 813, 815, 817 and a plurality of deposited metal layers 812, 814, 816, 818 on the top surface of the cymbal substrate 810 where a MOS field effect transistor is located to form a cymbal. A plurality of dielectric layers and a plurality of metal layers having alternating dielectric layers and metal layers on the top surface of the substrate 810. The dielectric layers 811, 813, 815, and 817 are etched after the dielectric layers 811, 813, 815, and 817 are deposited, and are used to form a plurality of via holes (811a, 813a, 815a, and 817a) in the dielectric layer and are not shown. Out through holes, which will be mentioned below). Wherein, the metal layers 812, 814, 816, and 818 are etched and divided by depositing metal layers (812, 814, 816, and 818 in the figure) for dividing the metal layers 812, 814, 816, and 818 into different layers. Different metal regions (812a, 812b, 814a, 814b, 814c, 816a, 816b, 816c, 818a, 818b and metal regions not shown in the figure, as will be mentioned below), part of the metal region A capacitor plate is formed, and a metal layer is filled while filling a via hole (such as 811a, 813a, 815a, 817a and a via hole not shown in the drawing) included in the dielectric layer, which will be mentioned later.

Referring to FIG. 9, the top surface of the cymbal substrate 810 includes a gate metal layer 820 constituting a MOS field effect transistor gate electrode, a source metal layer 830 constituting a MOS field effect transistor source electrode, and a source metal layer 830. An extension structure (not shown in the figure, refer to the second embodiment of FIG. 3B). A dielectric layer 811 is deposited on the top surface of the NMOS substrate 810 where the MOS field effect transistor is located, and a plurality of via holes 811a are formed in the dielectric layer 811 by etching the dielectric layer 811; FIG. 9 is a cross-sectional view of FIG. 3A. A metal layer 812 is deposited on the dielectric layer 811 and the metal layer 812 is divided by etching to divide the metal layer 812 into different metal regions, and the metal layer 812 is deposited. At the same time, the via hole 811a included in the dielectric layer 811 is filled with metal. The dielectric layer and the metal layer are repeatedly deposited a plurality of times to form a plurality of dielectric layers and a plurality of metal layers in which the dielectric layers 811, 813, 815, and 817 and the metal layers 812, 814, 816, and 818 are alternately on the top surface of the ruthenium substrate 810. If the dielectric layer is further deposited on the metal layer 818 to redeposit the metal layer, and thus looped, the number of layers of the metal layer and the dielectric layer can be formed without limitation. Fig. 9 is a cross-sectional view shown in Fig. 3A. In Fig. 9, the metal layers 812, 814, 816, and 818 are etched and divided to form metal cut patterns shown in Figs. 3C, 3D, 3E, and 3F. The top surface of the cymbal substrate 810 includes a gate metal layer 820 constituting a MOS field effect transistor gate electrode, a source metal layer 830 constituting a MOS field effect transistor source electrode, and an extension structure of the source metal layer (not Shown, refer to the second embodiment of FIG. 3B).

Any one of the metal layers is etched and divided to form a stacked extension structure over the extended structure (not shown, refer to the second embodiment 3C-3F of the second embodiment) and the stacked gate metal above the gate metal layer 820. Layers 812a, 814a, 816a, 818a. The multilayer metal layer is etched and divided to form a plurality of capacitor plates including a plurality of first type capacitor plates 812b and 816c and a plurality of second type capacitor plates 814b and 818b at different levels; the first type of capacitor plates 812b and 816c The second type of capacitor plates 814b and 818b are alternately arranged at intervals. After the multilayer metal layer is etched and divided, a second type of connection layer 816b insulated from the first type of capacitor plate 816c is formed in a layer of the first type of capacitor plate 816 between adjacent second type capacitor plates 814b and 818b. . Etching the dielectric layer to etch a plurality of vias 815a, 817a in the dielectric layer between the second type of capacitor plates 814b, 818b and the second type of connection layer 816b, and by injecting the second type of capacitor plates 814b, 818b and The metal in the vias 815a, 817a in the dielectric layer between the two types of connection layers 816b electrically connects the second type of capacitor plates 814b, 818b to each other. After the multilayer metal layer is etched and divided, a first type of connection layer 814c insulated from the second type of capacitor plate 814b is formed in a layer of the second type of capacitor plate 814b of the adjacent first type of capacitor plates 812b, 816c. . An etch dielectric layer is formed in the dielectric layer between the first type of capacitor plates 812b, 816c and the first type of connection layer 814c and between the source metal layer 830 and the first type of capacitor plate 812b adjacent to the source metal layer 830. There are a plurality of through holes 815a, 813a, 811a, and between the first type of capacitor plates 812b, 816c and the first type of connection layer 814c and the source metal The metal in the via 815a, 813a, 811a in the dielectric layer between the layer 830 and the first type of capacitor plate 812b adjacent to the source metal layer 830 electrically connects the first type of capacitor plates 812b, 816c to each other while The first type of capacitor plates 812b, 816c are electrically connected to the source metal layer 830.

The etch dielectric layer etches a plurality of vias (not shown) in the dielectric layer between adjacent lamination extension structures (not shown) and between the lamination extension structure and the extension structure of the extension structure, through the implantation Metals (not shown) in the via holes in the dielectric layers between adjacent stacked extension structures and adjacent to the extended structure and the extension structure electrically connect adjacent layer extension structures, At the same time, the laminated extension structure is electrically connected to the extension structure. The etch dielectric layer is etched in the dielectric layer between adjacent stacked gate metal layers 812a, 814a, 816a, 818a and between the stacked gate metal layer 812a and the gate metal layer 820 of the gate metal layer 820. A plurality of via holes 811a, 813a, 815a, and 817a are formed by implanting a stacked gate metal layer 812a and a gate between adjacent stacked gate metal layers 812a, 814a, 816a, and 818a and adjacent to the gate metal layer 820. The metal in the vias 811a, 813a, 815a, 817a in the dielectric layer between the epitaxial metal layers 820 electrically connects the adjacent stacked gate metal layers 812a, 814a, 816a, 818a while the stacked gates are The metal layers 812a, 814a, 816a, 818a are electrically connected to the gate metal layer 820. The gate metal layer 820 and the source metal layer 830 are separated from each other, and the dielectric layer is deposited to fill the dielectric region between the gate metal layer and the source metal layer; the dielectric layer is deposited to etch the divided metal layer. The formed insulating partition fills the dielectric.

Referring to Fig. 10, the preparation method of the fourth embodiment (Fig. 5A-1, 5A-2, 5B-5E) is similar to the above steps 8A-8L, and the specific steps are not described again. A dielectric layer 911, 913, 915 and a plurality of deposited metal layers 912, 914, 916 are deposited a plurality of times on the top surface of the cymbal substrate 910 where a MOS field effect transistor is located to form a dielectric on the top surface of the cymbal substrate 910. a multilayer dielectric layer and a plurality of metal layers alternating between a layer and a metal layer. The dielectric layers 911, 913, and 915 are etched after depositing the dielectric layers 911, 913, and 915 for forming a plurality of via holes in the dielectric layer (such as 911a, 913a, 915a and through holes not shown in the drawing). The following will be mentioned). The metal layers 912, 914, and 916 are etched and divided after the metal layers 912, 914, and 916 are deposited, and the metal layers 912, 914, and 916 are divided into different metal regions (such as 912a, 912b, and 914a, 914b, 914c, 916a, 916b and a metal region not shown in the drawing, which will be mentioned later), and depositing a metal layer while filling a via hole (911a, 913a, 915a) included in the dielectric layer with a metal A through hole not shown in the drawing will be mentioned below).

Referring to FIG. 10, the top surface of the cymbal substrate 910 includes a gate metal layer 920 constituting a MOS field effect transistor gate electrode, a source metal layer 930 constituting a MOS field effect transistor source electrode, and a source metal layer 930. An extension structure (not shown). A dielectric layer 911 is deposited on the top surface of the NMOS substrate 910 where the MOS field effect transistor is located, and a plurality of through holes 911a are formed in the dielectric layer 911 by etching the dielectric layer 911; FIG. 10 is a 5A-1, 5A A cross-sectional view of the -2 diagram. A metal layer 912 is deposited on the dielectric layer 911 and the metal layer 912 is divided by etching to divide the metal layer 912 into different metal regions, and the metal layer 912 is deposited while filling the via hole included in the dielectric layer 911 with metal. 911a. The dielectric layer and the metal layer are repeatedly deposited a plurality of times to form a plurality of dielectric layers and a plurality of metal layers in which the dielectric layers 911, 913, 915 and the metal layers 912, 914, and 916 are alternately on the top surface of the ruthenium substrate 910. Fig. 10 is a cross-sectional view shown in Fig. 5A-1. In Fig. 10, the metal layers 912, 914, and 916 are etched and divided to form metal cut patterns shown in Figs. 5C, 5D, and 5E.

If the dielectric layer is further deposited on the metal layer 916 to re-deposit the metal layer, and thus looped, a structure in which the number of layers of the metal layer and the dielectric layer is not limited can be formed.

The top surface of the cymbal substrate 910 includes a gate metal layer 920 constituting a MOS field effect transistor gate electrode, a source metal layer 930 constituting a MOS field effect transistor source electrode, and an extension structure of the source metal layer (not show). Any one of the metal layers is etched and divided to form a stacked extension structure (not shown) over the extended structure and a stacked gate metal layer 912a, 914a, 916a over the gate metal layer 920. The multi-layer metal layer is etched and divided to form a plurality of first-type capacitor plates (including a first-type capacitor plate 914b in the embodiment) and a plurality of second-type capacitor plates at different levels (as shown in FIG. 912b, The multilayer capacitor plate of 916b); the first type of capacitor plates 914b and the second type of capacitor plates 912b, 916b are alternately spaced apart from each other. After the multilayer metal layer is etched and divided, a second type of connection layer 914c insulated from the first type of capacitor plate 914b is formed in a layer of the first type of capacitor plate 914b between adjacent second type capacitor plates 912b and 916b. . Etching the dielectric layer A plurality of via holes 913a, 915a are etched in the dielectric layer between the second type of capacitor plates 912b, 916b and the second type of connection layer 914c, and are connected to the second type by injecting the second type of capacitor plates 912b, 916b. The metal in the vias 913a, 915a in the dielectric layer between the layers 914c electrically connects the second type of capacitor plates 912b, 916b to each other. The first type of capacitor plates of any of the layers (including a first type of capacitor plates 914b in this embodiment) are connected to a layered extension (not shown) of the layer of the first type of capacitor plates of the layer. That is to say, the first type of capacitor plate 914b is electrically connected to the source metal layer 930 through a layered extension structure connecting the layers of the first type of capacitor plates 914b.

The etch dielectric layer etches a plurality of vias (not shown) in the dielectric layer between adjacent lamination extension structures (not shown) and between the lamination extension structure and the extension structure of the extension structure, through the implantation Metals (not shown) in the via holes in the dielectric layers between adjacent stacked extension structures and adjacent to the extended structure and the extension structure electrically connect adjacent layer extension structures, At the same time, the laminated extension structure is electrically connected to the extension structure. The etch dielectric layer is etched more in the dielectric layer between the adjacent stacked gate metal layers 912a, 914a, 916a and between the stacked gate metal layer 912a and the gate metal layer 920 of the gate metal layer 920. The via holes 911a, 913a, 915a are formed by implanting between the stacked gate metal layers 912a, 914a, 916a and between the stacked gate metal layer 912a and the gate metal layer 920 near the gate metal layer 920. The metal in the vias 911a, 913a, 915a in the dielectric layer electrically connects the adjacent stacked gate metal layers 912a, 914a, 916a while laminating the gate metal layers 912a, 914a, 916a and the gate The metal layer 920 is electrically connected.

The gate metal layer 920 and the source metal layer 930 are separated from each other, and the dielectric layer is deposited to fill the dielectric between the gate metal layer and the source metal layer; the dielectric layer is used to etch the divided metal layer. The formed insulating partition fills the dielectric.

Referring to Fig. 11, the preparation method of the fifth embodiment (Fig. 6A-1, 6A-2, 6B-6E) is the same as the above steps 8A-8L, and the specific steps are not described again. The preparation method comprises: depositing a dielectric layer 1011, 1013, 1015 and a plurality of deposited metal layers 1012, 1014, 1016 on the top surface of the enamel substrate 1010 where the first transistor and the second transistor are located to form a lining. Bottom 1010 A multilayer dielectric layer and a plurality of metal layers in which the dielectric layers 1011, 1013, and 1015 on the top surface are alternated with the metal layers 1012, 1014, and 1016. The dielectric layers 1011, 1013, and 1015 are etched after depositing the dielectric layers 1011, 1013, and 1015, and are used to form a plurality of via holes 1011a, 1013a, and 1015a in the dielectric layers 1011, 1013, and 1015, and are not shown in the drawings. Through holes; after the metal layers 1012, 1014, and 1016 are deposited, the metal layers 1012, 1014, and 1016 are etched and divided to divide the metal layers 1012, 1014, and 1016 into different metal regions (as shown in FIG. 1012a, 1012b, 1012c, 1012d, 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c and a metal region not shown), and depositing the metal layers 1012, 1014, 1016 while filling the via holes 1011a, 1013a included in the dielectric layer with metal , 1015a and through holes not shown in the figure. Fig. 11 is a cross-sectional view shown in Fig. 6A-1. In Fig. 11, the metal layers 1012, 1014, and 1016 are etched and divided to form metal cut patterns shown in Figs. 6C, 6D, and 6E. The top surface of the cymbal substrate 1010 includes a drain metal layer 1030 constituting a first transistor drain electrode, and a first gate metal layer 1020 constituting a first transistor gate electrode, constituting a source of the second transistor source electrode. The epitaxial metal layer 1040 and the second gate metal layer 1050 constituting the second transistor gate electrode. The drain metal layer 1030 includes a first extension structure (not shown in the drawings, refer to Embodiment 5, FIG. 6B), and the source metal layer 1040 includes a second extension structure (not shown in the drawing, refer to the embodiment). 5th 6B)). Any one of the metal layers 1012, 1014, and 1016 is etched and divided to form a first layered extension structure above the first extension structure (not shown in the drawing, refer to Embodiment 5, 6C-6E) and located at the a second layered extension structure over the second extension structure (not shown in the figure, refer to Embodiment 5, 6C-6E); and a first stacked gate metal layer 1012a over the first gate metal layer 1020 And 1014a, 1016a and a second stacked gate metal layer 1012d, 1014d, 1016c over the second gate metal layer 1050.

The multilayer metal layers 1012, 1014, and 1016 are etched and divided to form a plurality of layers of a plurality of first type capacitor plates (1014b in the figure) and a plurality of second type capacitor plates (1012c, 1016b in the figure) at different levels. The capacitor plate; the first type of capacitor plate 1014b and the second type of capacitor plates 1012c, 1016b are alternately spaced apart from each other. The first type of capacitor plates 1014b between the adjacent second type of capacitor plates 1012c, 1016b are etched and divided by the multilayer metal layers 1012, 1014, and 1016. A second type of connection layer 1014c insulated from the first type of capacitor plates 1014b is formed in the layer. Etching the dielectric layer to etch a plurality of via holes in the dielectric layer between the second type of capacitor plates 1012c, 1016b and the second type of connection layer 1014c (such as 1013a, 1015a in the figure and through holes not shown in the figure), The second type of capacitor plates 1012c, 1016b are electrically connected to each other by injecting metal (not shown) in the via holes in the dielectric layer between the second type of capacitor plates 1012c, 1016b and the second type of connection layer 1014c. After the multilayer metal layer is etched and divided, the adjacent first type of capacitor plates (the first type of capacitor plates may have multiple layers, and the first type of capacitor plates 1014b are included in the embodiment) and the first type of capacitor plates 1014b A first type of connection layer 1012b insulated from the second type of capacitor plate 1012c is formed in a layer of the second type of capacitor plate 1012c between the drain metal layer 1030.

Etching the dielectric layer to etch a plurality of dielectric layers between the first type of capacitor plate 1014b and the first type of connection layer 1012b and between the drain metal layer 1030 and the first type of connection layer 1012b adjacent to the drain metal layer 1030 Through holes (1011a, 1013a in the figure and through holes not shown in the figure), and by injecting metal in the through holes in the dielectric layer between the first type of capacitor plates 1014b and the first type of connection layer 1012b (not The first type of capacitor plates 1014b are electrically connected to each other by implanting metal in the via holes in the dielectric layer between the first type of connection layer 1012b and the drain metal layer 1030 of the drain metal layer 1030 ( The first type of connection layer 1012b is electrically connected to the drain metal layer 1030. Etching the dielectric layer to etch a plurality of vias in the dielectric layer between the source metal layer 1040 and the second type of capacitor plate 1012c adjacent to the source metal layer 1040 (as shown in FIG. 1011a and through holes not shown in the drawing) And the second type of capacitor plate 1012c is coupled to metal (not shown) in the via hole in the dielectric layer between the source metal layer 1040 and the second type of capacitor plate 1012c adjacent to the source metal layer 1040. The source metal layer 1040 is electrically connected.

Etching the dielectric layer between the adjacent first stacked extension structures (not shown in FIG. 11 and referring to Embodiment 5, FIG. 6A-2) and the first layered extension structure adjacent to the first extension structure and the first A plurality of via holes are etched into the dielectric layer between the extension structures by implanting a dielectric between the adjacent first layer extension structures and between the first layer extension structure and the first extension structure of the first extension structure The metal in the via hole in the layer electrically connects the adjacent first layer extension structures, and electrically connects the first layer extension structure to the first extension structure. Etching the dielectric layer in the adjacent a two-layer extension structure (not shown in FIG. 11, which is referred to in Embodiment 5, FIG. 6A-2) and in a dielectric layer between the second layer extension structure and the second extension structure adjacent to the second extension structure Etching a plurality of via holes by implanting metal in vias in the dielectric layer between adjacent second stacked extension structures and adjacent to the second layered extension structure of the second extension structure and the second extension structure The adjacent second layer extension structures are electrically connected, and the second layer extension structure is electrically connected to the second extension structure. Etching the dielectric layer between the adjacent first stacked gate metal layers (1012a, 1014a, 1016a in the figure) and the first stacked gate metal layer 1012a and the first gate adjacent to the first gate metal layer 1020 A plurality of via holes (such as 1011a, 1013a, 1015a and through holes not shown in the figure) are etched into the dielectric layer between the metal layer 1020 by implanting adjacent first stacked gate metal layers. The metal (not shown) in the via hole in the dielectric layer between the first stacked gate metal layer 1012a and the first gate metal layer 1020 adjacent to the first gate metal layer 1020 will be adjacent to the first The stacked gate metal layers (1012a, 1014a, 1016a in the figure) are electrically connected, and the first gate metal layer 1020 and the first stacked gate metal layer (1012a, 1014a, 1016a in the figure) are electrically connected. Sexual connection.

Etching the dielectric layer between the adjacent second stacked gate metal layers (1012d, 1014d, 1016c in the figure) and the second stacked gate metal layer 1012d and the second gate adjacent to the second gate metal layer 1050 A plurality of via holes (such as 1011a, 1013a, 1015a and through holes not shown in the figure) are etched into the dielectric layer between the metal layer 1050 by implanting an adjacent second stacked gate metal layer ( Metal in the via hole in the dielectric layer between 1012d, 1014d, 1016c) and between the second stacked gate metal layer 1012d and the second gate metal layer 1050 of the second gate metal layer 1050 (not shown) electrically connecting adjacent second stacked gate metal layers (1012d, 1014d, 1016c in the figure) while the second gate metal layer 1050 and the second stacked gate metal layer ( 1012d, 1014d, 1016c) are electrically connected as shown. The drain metal layer 1030, the first gate metal layer 1020, the source metal layer 1040, and the second gate metal layer 1050 pass through the division region (for example, the drain metal layer 1030 and the first gate metal layer 1020) 1025) Separating from each other, depositing a dielectric layer for filling the dielectric in the partition; and depositing a dielectric layer for filling the dielectric spacer formed by etching the split metal layer into the dielectric.

Referring to Fig. 12, the preparation method of the sixth embodiment (Fig. 7A-1, 7A-2, 7B-7E) is similar to the above steps 8A-8L, and the specific steps are not described again. The preparation method: depositing dielectric layers 1111, 1113, 1115 and multiple deposition metal layers 1112, 1114, 1116 on the top surface of the enamel substrate 1110 where the first transistor and the second transistor are located to form a lining. A dielectric layer 1111, 1113, 1115 on the top surface of the bottom 1110 and a plurality of metal layers 1112, 1114, 1116 alternate with a plurality of dielectric layers and a plurality of metal layers. The dielectric layers 1111, 1113, and 1115 are etched after depositing the dielectric layers 1111, 1113, and 1115, and are used to form a plurality of via holes 1111a, 1113a, and 1115a in the dielectric layers 1111, 1113, and 1115, and are not shown in the drawings. Through holes; after the metal layers 1112, 1114, and 1116 are deposited, the metal layers 1112, 1114, and 1116 are etched and divided to divide the metal layers 1112, 1114, and 1116 into different metal regions (such as 1112a, 1112b, and 1112c in the figure). 1114a, 1114b, 1114c, 1116a, 1116b, 1116c and metal regions not shown), and depositing metal layers 1112, 1114, 1116 while filling the via holes 1111a, 1113a, 1115a and the layers included in the dielectric layer with metal A through hole not shown. Fig. 12 is a cross-sectional view shown in Fig. 7A-1. In Fig. 12, the metal layers 1112, 1114, and 1116 are etched and divided to form metal cut patterns shown in Figs. 7C, 7D, and 7E.

The top surface of the cymbal substrate 1110 includes a drain metal layer 1130 constituting a drain electrode of the first transistor, a first gate metal layer 1120 constituting a gate electrode of the first transistor, and a source constituting a source electrode of the second transistor. A polar metal layer 1140, a second gate metal layer 1150 constituting a second transistor gate electrode. The drain metal layer 1130 includes a first extension structure (not shown in FIG. 12, refer to Embodiment 6 and FIG. 7B), and the source metal layer 1140 includes a second extension structure (not shown in FIG. 12, Refer to Figure 6B of Example 6). Any one of the metal layers 1112, 1114, and 1116 is etched and divided to form a first layered extension structure (not shown in the figure, which is not shown in the figure, and is referred to in the sixth embodiment of the seventh embodiment, and is located in the second extension). a second stacked extension structure above the structure (not shown in the figure, refer to Embodiment 6 7C-7E); and a first stacked gate metal layer 1112a, 1114a over the first gate metal layer 1120 And 1116a and a second stacked gate metal layer 1112c, 1114c, 1116c over the second gate metal layer 1150. The multilayer metal layers 1112, 1114, and 1116 are etched and divided to form a plurality of first-type capacitor plates at different levels (this is For example, a first type of capacitor plate 1114b is taken as an example) and a plurality of second type capacitor plates (such as 1112b and 1116b in the figure) are used; the first type of capacitor plate 1114b and the second type The capacitor-like plates 1112b and 1116b are alternately arranged at intervals. Etching the dielectric layer between the adjacent first layer extension structures (not shown in FIG. 12, refer to Embodiment 6 7A-2) and the first layer extension structure adjacent to the first extension structure and the first A plurality of via holes are etched into the dielectric layer between the extension structures by implanting a dielectric between the adjacent first layer extension structures and between the first layer extension structure and the first extension structure of the first extension structure The metal in the through hole in the layer electrically connects the adjacent first layer extension structure, and electrically connects the first layer extension structure to the first extension structure, that is, the first layer extension structure and the drain The electrode metal layer 1130 is electrically connected.

Etching the dielectric layer between the adjacent second stacked extension structures (not shown in FIG. 12, refer to Embodiment 6 7A-2) and the second laminated extension structure and the second adjacent to the second extended structure A plurality of via holes are etched into the dielectric layer between the extension structures by implanting a dielectric between the adjacent second layer extension structures and between the second layer extension structure and the second extension structure of the second extension structure The metal in the via hole in the layer electrically connects the adjacent second layer extension structure, and electrically connects the second layer extension structure to the second extension structure, that is, the second layer extension structure and the source The electrode metal layer 1140 is electrically connected. Etching the dielectric layer between the adjacent first stacked gate metal layers (such as 1112a, 1114a, 1116a in the figure) and the first stacked gate metal layer 1112a and the first gate adjacent to the first gate metal layer 1120 A plurality of via holes (such as 1111a, 1113a, 1115a and through holes not shown in the drawing) are etched into the dielectric layer between the metal layer 1120 by implanting adjacent first stacked gate metal layers. The metal (not shown) in the via hole in the dielectric layer between the first stacked gate metal layer 1112a and the first gate metal layer 1120 adjacent to the first gate metal layer 1120 will be adjacent to the first The stacked gate metal layers (1112a, 1114a, 1116a in the figure) are electrically connected, and the first stacked gate metal layer (1112a, 1114a, 1116a in the figure) and the first gate metal layer 1120 are electrically connected. Sexual connection.

Etching the dielectric layer between the adjacent second stacked gate metal layers (such as 1112c, 1114c, 1116c) and the second stacked gate metal layer 1112c and the second gate adjacent to the second gate metal layer 1150 A plurality of through holes are etched in the dielectric layer between the metal layer 1150 (as shown in FIG. 1111a, 1113a, 1115a and through holes not shown in the drawing), by injecting adjacent second stacked gate metal layers (such as 1112c, 1114c, 1116c in the figure) and near the second gate metal layer 1150 A metal (not shown) in the via hole in the dielectric layer between the two-layered gate metal layer 1112c and the second gate metal layer 1150 will be adjacent to the second stacked gate metal layer (as shown in FIG. 1112c) , 1114c, 1116c) electrically connected, while electrically connecting the second gate metal layer 1150 and the second stacked gate metal layer (1112c, 1114c, 1116c in the figure).

Any one of the first type of capacitor plates (such as the first type of capacitor plates 1114b in the present embodiment) is located at the level of the first type of capacitor plates (such as the first type of capacitor plates 1114b in the present embodiment). a first layer of extension structure (not shown) is connected; any one of the second type of capacitor plates (such as the first type of capacitor plates 1112b, 1116b in the present embodiment) and the second type of capacitor plate of the layer ( A second layered extension (not shown) of the layer of the first type of capacitor plates 1112b, 1116b) is connected as in the present embodiment. Therefore, the first type of capacitor plates 1114b are electrically connected to the first layer extension structure, and the first layer extension structure is electrically connected to the drain metal layer 1130, so that the first type of capacitor plates 1114b are both leaked and drained. The metal layer 1130 is electrically connected; the second type of capacitor plates 1112b and 1116b are electrically connected to the second layer extension structure, and the second layer extension structure is electrically connected to the source metal layer 1140, so that the second layer The capacitor-like plates 1112b and 1116b are electrically connected to the source metal layer 1140. The drain metal layer 1130, the first gate metal layer 1120, the source metal layer 1140, and the second gate metal layer 1150 pass through a partition (eg, a drain region between the drain metal layer 1130 and the first gate metal layer 1120) 1125) Separating from each other, depositing a dielectric layer for filling the dielectric in the divided region; and depositing a dielectric layer for filling the dielectric spacer formed by etching the divided metal layer with a dielectric.

The technical solutions disclosed in the above embodiments have many forms of deformations without departing from the spirit of the present invention, for example, the increase or decrease of the metal layer and the dielectric layer, and the different ways of adjusting the lead-out source and the source. Or variations in the type of wafer, these variants are considered by the inventors as an integral part of the invention without any doubt.

The above embodiments are based on, but not limited to, Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs). Among them, the low side (MOSFET) MOSFET can also be referred to by the skilled person in the art as a low side metal oxide. Semiconductor field effect transistors; high side MOSFETs can also be referred to by those skilled in the art as high side metal oxide semiconductor field effect transistors.

An obvious advantage is that the capacitor is directly integrated into the MOSFET, replacing the way the bond MOSFET and the external capacitor are connected by a bond alloy wire, which greatly eliminates the on-line discrete inductance. Another beneficial effect is that, due to the presence of the capacitor plate and the dielectric layer, the thickness and mechanical strength of the ruthenium substrate are increased, and the ruthenium substrate is in the process step of wafer back grinding (Wafer Backside Grinding), The suppression of the stress of the ruthenium substrate itself, or the control of the warpage of the entire wafer, is extremely effective. According to this advantage, the MOSFET substrate can be thinned to achieve a lower MOSFET on-resistance. .

Based on the thinness and good heat dissipation performance of semiconductor devices, the Mold Cap of semiconductor devices also tends to be thinned. However, the extremely thin plastic package thickness will inevitably cause surface encapsulation of epoxy resin in the molding process (Package). The emergence of Void), even to expose Die Exposed, a direct and effective measure to avoid this defect is to thin the wafer. Therefore, another outstanding achievement in the IC assembly process obtained by the increase in the mechanical strength of the wafer of the present invention is also visible.

Exemplary embodiments of specific structures of the specific embodiments are given by way of illustration and drawings. Although the above invention proposes a prior preferred embodiment, these are not intended to be limiting. It will be appreciated by those skilled in the art that the present invention may be embodied in various other specific forms without departing from the scope of the invention. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; For example, the present invention is described by taking a MOS transistor as an example. According to the same inventive concept, the present invention is also applicable to a bipolar transistor circuit. Accordingly, the appended claims are intended to cover all such modifications and Any and all equivalent ranges and contents within the scope of the claims are intended to be within the spirit and scope of the invention.

500‧‧‧Optoelectronics

510‧‧‧矽 substrate

521‧‧‧First gate metal layer

521a‧‧‧First laminated gate metal layer

521b/522b/536b/540b/550b‧‧‧Metal

522‧‧‧Second gate metal layer

522a‧‧‧Second laminated gate metal layer

531‧‧‧Drain metal layer

532‧‧‧ source metal layer

535a‧‧‧First layer extension structure

536‧‧‧Second extension structure

536a‧‧‧Second layer extension structure

540‧‧‧The first type of capacitor plate

540a‧‧‧first type of connection layer

550‧‧‧Second type capacitor plate

550a‧‧‧Second type of connection layer

Claims (28)

A dual MOS field effect transistor integrated with a capacitor, wherein the double MOS field effect transistor is integrated with a bypass capacitor, wherein a top surface of a 衬底 substrate is provided with a first transistor gate electrode a gate metal layer and a drain metal layer constituting a first transistor drain electrode, and a second gate metal layer constituting a second transistor gate electrode and a second transistor source electrode a source metal layer; a multilayer capacitor plate including a plurality of first type capacitor plates and a plurality of second type capacitor plates parallel to the cymbal substrate disposed above the top surface of the cymbal substrate And a dielectric layer is filled between a top surface of the cymbal substrate and a capacitor plate above the top surface of the cymbal substrate and between two adjacent capacitor plates; the first type of capacitor plate and the second The capacitor-like plates are alternately spaced apart from each other, and the first type of capacitor plates are electrically connected to the drain metal layer for forming an electrode of the bypass capacitor, and the second type of capacitor plates are connected to the source metal layer. Electrically connecting another electrode constituting the bypass capacitor; the first transistor a source is formed on a bottom surface of the enamel substrate, a drain and a gate of the first transistor are formed on a top surface of the cymbal substrate; and a drain of the second transistor is formed on a bottom surface of the cymbal substrate a source and a gate of the second transistor are formed on a top surface of the enamel substrate; the drain metal layer is provided with a first extension structure, and any layer of the capacitor plate is at the first extension A first layered extension structure is disposed above the structure; wherein the first layer extension structure is electrically connected to the first extension structure to derive the first transistor drain. The dual MOS field effect transistor integrated with a capacitor according to claim 1, wherein any one of the layers of the capacitor plate is provided with a first stacked gate above the first gate metal layer. Metal layer The first stacked gate metal layer is electrically connected to the first gate metal layer to derive the gate of the first transistor. The dual MOS field effect transistor integrated with a capacitor according to claim 1, wherein any layer of the capacitor plate is provided with a second stacked gate above the second gate metal layer. a metal layer; wherein the second stacked gate metal layer is electrically connected to the second gate metal layer to derive the gate of the second transistor. The dual MOS field effect transistor integrated with a capacitor according to claim 1, wherein the source metal layer is provided with a second extension structure, and any layer of the capacitor plate is at the second layer. A second layered extension structure is disposed above the extension structure; wherein the second layer extension structure is electrically connected to the second extension structure to derive the second transistor source. The dual MOS field effect transistor integrated with a capacitor according to claim 1, wherein the dielectric layer adjacent to the first stacked extension structure and the first layer adjacent to the first extension structure a plurality of through holes are formed in the dielectric layer between the layer extending structure and the first extending structure, and the first layer extending structure and the drain of the first transistor are electrically connected by metal injected into the through hole Sexual connection. The dual MOS field effect transistor integrated with a capacitor according to claim 4, wherein the dielectric layer adjacent to the second stacked extension structure and the first layer adjacent to the second extension structure a plurality of through holes are formed in the dielectric layer between the two-layer extension structure and the second extension structure, and the second layer extension structure and the source of the second transistor are electrically connected by metal injected into the through hole Sexual connection. The dual MOS field effect transistor integrated with a capacitor according to claim 1, wherein the first type of capacitor plate and the second type of capacitor plate are longitudinally staggered for adjacent a second type of connection layer insulated from the first type of capacitor plate is disposed in a layer of the first type of capacitor plate between the second type of capacitor plates; and the second type of capacitor plate and the first type a through hole is disposed in the dielectric layer between the two types of connection layers and between the source metal layer and the second type of capacitor plate adjacent to the source metal layer, and the second hole is inserted through the metal in the through hole The capacitor-like plates are electrically connected to each other, and the second type of capacitor plates are electrically connected to the source metal layer. The dual MOS field effect transistor integrated with a capacitor according to claim 1, wherein the first type of capacitor plate and the second type of capacitor plate are longitudinally staggered for use in adjacent ones a first type of connection layer insulated from the second type of capacitor plate is disposed in a layer between the capacitor plates and the second type of capacitor plates between the first type of capacitor plates and the drain metal layer; Providing a through hole in the dielectric layer between the first type of capacitor plate and the first type of connection layer and between the drain metal layer and the first type of connection layer adjacent to the drain metal layer, and passing through The metal injected into the via hole electrically connects the first type of capacitor plates to each other, and electrically connects the first type of capacitor plate to the drain metal layer. The dual MOS field effect transistor integrated with a capacitor according to claim 1, wherein any one of the first type of capacitor plates and the first layer of the layer of the first type of capacitor plates The extension structure is connected. The dual MOS field effect transistor integrated with a capacitor according to claim 9, wherein the source metal layer is provided with a second extension structure, and any layer of the capacitor plate is at the second layer. A second layered extension structure is disposed above the extension structure, and any one of the first type of capacitor plates is divided and insulated from the second layer extension structure of the layer of the first type of capacitor plate. The dual MOS field effect transistor integrated with a capacitor according to claim 4, wherein any one of the second type of capacitor plates and the second layer of the layer of the second type of capacitor plate The extension structure is connected. The dual MOS field effect transistor integrated with a capacitor according to claim 11, wherein the drain metal layer is provided with a first extension structure, and the layer of the capacitor plate of any one of the layers is A first layered extension structure is disposed above the first extension structure, and any one of the second type of capacitor plates is divided and insulated from the first layer extension structure of the layer of the second type of capacitor plate. The dual MOS field effect transistor integrated with a capacitor according to claim 1, wherein the first gate metal layer, the drain metal layer, the source metal layer, and the second gate metal layer The partition is isolated and separated by a partition, and the partition is filled with a dielectric; any layer of the capacitor plate includes an insulating partition and the insulating partition is filled with a dielectric. The dual MOS field effect transistor integrated with a capacitor according to claim 1, wherein the first transistor is a high-end MOS field effect transistor, and the second transistor is a low-end MOS field effect transistor. Crystal. A method for integrating a capacitor on a dual MOS field effect transistor includes the steps of: depositing a dielectric layer and multiple times on a top surface of a substrate of a first transistor and a second transistor; Depositing a metal layer to form a plurality of dielectric layers and a plurality of metal layers alternately between the dielectric layer and the metal layer on the top surface of the enamel substrate; wherein, after depositing the dielectric layer, etching the dielectric layer for forming the dielectric layer a plurality of through holes; wherein, after depositing the metal layer, the metal layer is etched and divided to divide the metal layer into different metal regions, a part of the metal regions form a capacitor plate, and the metal layer is deposited Filling a via hole included in the dielectric layer with a metal; A first layer of metal layer is etched and divided to form a first layer extension structure and a second layer extension structure of the layer where the metal layer is located, and a first stacked gate metal layer and a second stacked gate metal layer . The method of claim 15, wherein the top surface of the cymbal substrate comprises a drain metal layer constituting the drain electrode of the first transistor, and a first electrode constituting the gate electrode of the first transistor a gate metal layer, a source metal layer constituting the second transistor source electrode, and a second gate metal layer constituting the second transistor gate electrode; the drain metal layer includes a first extension The structure, the source metal layer comprises a second extension structure. The method of claim 16, wherein the first layered extension structure is above the first extension structure, the second layer extension structure is above the second extension structure; and the first layer is stacked The gate metal layer is above the first gate metal layer, and the second stacked gate metal layer is above the second gate metal layer. The method of claim 15, wherein the multi-layer metal layer is etched and divided to form a plurality of capacitor plates including a plurality of first-type capacitor plates and a plurality of second-type capacitor plates at different levels; The first type of capacitor plate and the second type of capacitor plate are alternately arranged at intervals. The method of claim 18, wherein the multi-layer metal layer is etched and formed, and the insulating layer is formed in a layer of the first type of capacitor plate between the adjacent second type of capacitor plates. a second type of connection layer of the first type of capacitor plate; etching the dielectric layer to etch a plurality of via holes in the dielectric layer between the second type of capacitor plate and the second type of connection layer, and injecting The metal in the via hole in the dielectric layer between the second type of capacitor plate and the second type of connection layer electrically connects the second type of capacitor plates to each other. The method of claim 18, wherein the multi-layer metal layer is etched and divided between adjacent ones of the first type of capacitor plates and between the first type of capacitor plates and the drain metal layer Forming a first type of connection layer insulated from the second type of capacitor plate in the layer of the second type of capacitor plate; etching the dielectric layer between the first type of capacitor plate and the first type of connection layer A plurality of via holes are etched into the dielectric layer between the drain metal layer and the first type of connection layer adjacent to the drain metal layer, and the first type of capacitor plate and the first type of connection layer are implanted The first type of capacitor plates are electrically connected to each other through a metal in the via hole in the dielectric layer, and the dielectric is interposed between the first type of connection layer and the drain metal layer adjacent to the drain metal layer. The metal in the vias in the layer electrically connects the first type of connection layer to the drain metal layer. The method of claim 18, wherein etching the dielectric layer etches a plurality of the dielectric layer between the source metal layer and the second type of capacitor plate adjacent to the source metal layer a via hole, and the second type of capacitor plate and the source are formed by implanting a metal in a via hole in the dielectric layer between the source metal layer and the second type of capacitor plate adjacent to the source metal layer The metal layer is electrically connected. The method of claim 17, wherein etching the dielectric layer between the adjacent first stacked extension structures and the first laminate extension structure adjacent to the first extension structure and the first Having a plurality of vias etched into the dielectric layer between the extension structures by implanting the first layer extension structure between the adjacent first layer extension structures and adjacent to the first extension structure and the first extension The metal in the via hole in the dielectric layer between the structures electrically connects the adjacent first layer extension structure, and electrically connects the first layer extension structure to the first extension structure. The method of claim 17, wherein etching the dielectric layer between the adjacent second stacked extension structures and the second stacked extension structure adjacent to the second extension structure and the second A plurality of through holes are etched into the dielectric layer between the extension structures through the injection phase The metal in the through hole in the dielectric layer between the adjacent second stacked extension structure and the second extended structure adjacent to the second extended structure and the second extended structure will be adjacent to the metal The second layer of the extension structure is electrically connected, and the second layer of the extension structure is electrically connected to the second extension structure. The method of claim 17, wherein etching the dielectric layer between the adjacent first stacked gate metal layers and the first stacked gate adjacent to the first gate metal layer a plurality of via holes are etched into the dielectric layer between the metal layer and the first gate metal layer by implanting between adjacent first stacked gate metal layers and adjacent to the first gate metal layer The metal in the via hole in the dielectric layer between the first stacked gate metal layer and the first gate metal layer electrically connects the adjacent first stacked gate metal layer while The first stacked gate metal layer is electrically connected to the first gate metal layer. The method of claim 17, wherein etching the dielectric layer between the adjacent second stacked gate metal layers and the second stacked gate adjacent to the second gate metal layer a plurality of via holes are etched into the dielectric layer between the metal layer and the second gate metal layer by implanting between adjacent second stacked gate metal layers and adjacent to the second gate metal layer The metal in the via hole in the dielectric layer between the second stacked gate metal layer and the second gate metal layer electrically connects the adjacent second stacked gate metal layer, and The second stacked gate metal layer is electrically connected to the second gate metal layer. The method of claim 18, wherein any one of the first type of capacitor plates is connected to the first layer of the layer of the layer of the first type of capacitor plates, and the layer is The second layered extension structure of the layer of the first type of capacitor plate is divided and insulated. The method of claim 18, wherein any one of the second type of capacitor plates is connected to the second layer of the layer of the layer of the second type of capacitor plates, and the layer The first layer of the extension structure of the second type of capacitor plate is divided and insulated. The method of claim 16, wherein the drain metal layer, the first gate metal layer, the source metal layer, and the second gate metal layer are separated from each other by a partition, and deposited A dielectric layer is used to fill the dielectric region with a dielectric layer; the dielectric layer is deposited for filling an insulating partition region dielectric formed by etching the metal layer.