TWI487038B - Thin film transistor substrate and method fabricating the same - Google Patents

Description

Thin film transistor substrate and method of manufacturing same

The present invention relates to a circuit substrate, and more particularly to a thin film transistor substrate.

In recent years, since a transistor made of a metal oxide semiconductor has a high carrier mobility (Mobility) and has a better electrical performance, and the manufacturing method is simpler than that of a conventional thin film transistor, it has high efficiency. The application of oxidized metal semiconductor thin film transistors has developed rapidly.

Generally, a thin film transistor is made of tantalum nitride (SiNx) as a material of a gate insulator and a barrier layer. However, in the oxidized metal semiconductor transistor, due to the leakage problem of the component, it is necessary to limit the high-temperature film-forming yttrium oxide (SiOx) as the material of the gate insulating layer and the low-temperature film-forming yttrium oxynitride (SiOxNy). The material of the sheath.

However, due to the low-temperature film formation of yttrium oxynitride (SiOxNy) as a protective layer, the structure is relatively loose, so there is a potential defect of the pore hole, so that water vapor may enter the contact with the signal line through the film hole. Causes the line to corrode and cause a broken wire.

In view of this, there is still a need for a technique that overcomes the problems in the structure and process of the above-mentioned thin film transistor substrate.

Therefore, an aspect of the present invention provides a thin film transistor substrate including a display region and a non-display region, and the display region includes a thin film transistor, a scan line, and a signal line, and the non-display area includes a scan line, a signal line, and a connection. Wire and contact metal. The scan line is located on the first patterned metal layer on the substrate and electrically connected to the gate of the thin film transistor. The signal line is located on the second patterned metal layer on the gate insulating layer, and is electrically connected to the source and the drain of the thin film transistor. The connecting line is located on the first patterned metal layer. The gate insulating layer covers at least a portion of the scan lines and the connecting lines of the first patterned metal layer. The signal line and the connecting line in the non-display area are electrically connected to the first through hole of the gate insulating layer, and the connecting line and the contact metal are electrically connected to the second through hole in the insulating layer.

According to an embodiment of the invention, the gate insulating layer is yttrium oxide (SiOx) or yttrium oxynitride (SiOxNy), and the film forming temperature of the gate insulating layer ranges from about 350 ° C to about 400 ° C.

According to another embodiment of the present invention, a thin film transistor includes at least a metal oxide semiconductor, and the material of the metal oxide semiconductor is indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), or zinc oxide ( ZnO).

According to another embodiment of the present invention, the cover layer is yttrium oxide (SiOx) or yttrium oxynitride (SiOxNy), and the film forming temperature of the cover layer ranges from about 100 ° C to about 200 ° C.

According to still another embodiment of the present invention, a cover layer is further disposed on the second patterned metal layer and the gate insulating layer.

Another aspect of the present invention provides a method of preparing the above-described thin film transistor substrate, the steps comprising the following. A substrate is provided, the substrate including a display area and a non-display area, and the non-display area is located around the display area. The first metal layer is formed on the substrate. The first metal layer includes a gate, a scan line and a connection line. The gate is formed on the display area, the scan line is formed on the display area and the non-display area, and the connection line is formed in the non-display area. The gate insulating layer is formed to cover the first patterned metal layer, and the gate insulating layer of the non-display region has a first through hole and a second through hole to respectively expose a part of the connecting lines. A patterned oxidized metal semiconductor is formed over the gate insulating layer and the oxidized metal semiconductor is patterned relative to the gate. Forming a second patterned metal layer on the patterned metal oxide semiconductor and the gate insulating layer, wherein the second patterned metal layer comprises a source, a drain, a signal line and a contact metal, wherein the signal line is connected by the first through hole and the connecting line Electrically connected, the contact metal is connected to the signal line through the second through hole. The protective layer covers the second patterned metal layer and the gate insulating layer, and the protective layer of the display region has a contact window to expose a portion of the drain, and the non-display region of the protective layer has an opening to expose a portion of the contact pad. A pixel electrode is formed on the cover layer to electrically connect to the drain electrode through the contact window.

According to an embodiment of the invention, the material for forming the gate insulating layer comprises silane (SiH ₄ ) and Nitros oxide (N ₂ O), and the film forming temperature of the gate insulating layer is about 350 ° C. To about 400 ° C, preferably from about 370 ° C to about 380 ° C.

According to another embodiment of the present invention, the material for forming the metal oxide semiconductor is indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), or zinc oxide (ZnO).

According to still another embodiment of the present invention, the material for forming the sheath layer comprises cerium methane and nitrous oxide, and the film forming temperature for forming the sheath layer ranges from about 100 ° C to about 200 ° C, preferably from about 150 ° C to about 180 ° C.

Therefore, by applying the disclosure, the signal line and the contact pad can be connected by the connecting line to reduce the generation of film holes, and effectively avoid the external water and gas from entering the line to cause corrosion.

The description of the embodiments of the present invention is intended to be illustrative and not restrictive. The embodiments disclosed herein may be combined or substituted with each other in an advantageous manner, and other embodiments may be added to an embodiment without further description or description.

In the following description, numerous specific details are set forth However, embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are only schematically shown in the drawings in order to simplify the drawings.

1 is a plan view of a thin film transistor substrate 300 in accordance with an embodiment of the present invention. Fig. 11 is a schematic cross-sectional view showing the line segments A-A', B-B' and C-C' taken along the first drawing. Please also refer to Figures 1 and 11.

The above-mentioned thin film transistor substrate 300 includes a substrate 310, a scanning line 324, a connecting line 322, signal lines 360, 360', an array of thin film transistors 345, and a pixel electrode 380. The substrate 310 includes a display area 314 and a non-display area 312, and the non-display area 312 is located around the display area 314. In the display area 314, the scan line 324, the signal line 360, the thin film transistor 345 and the pixel electrode 380 are included, and the thin film transistor 345 and the pixel electrode 380 are located in a region surrounded by the scan line 324 and the signal line 360. Within the non-display area 312, a scan line 324, a signal line 360', and a connection line 322 are included.

The first patterned metal layer is disposed on the substrate 310 to form a gate 320, a scan line 324, and a connection line 322. The scan line 324 is electrically connected to the gate 320 of the thin film transistor 345. The gate insulating layer 330 is disposed on the first patterned metal layer, covering the gate 320, the scan line 324, and the connection line 322. In the non-display area 312, the gate insulating layer 330 has a first via 332 and a second via 334. The connecting lines 322 of the portion of the first patterned metal layer are respectively exposed. The second patterned metal layer is disposed on the gate insulating layer 330 to form a source 352, a drain 350 and a connection line 322. The signal line 360 is electrically connected to the source 352 and the drain 350 of the thin film transistor 345. As shown in FIG. 1 , the connection line 322 is electrically connected to the signal line 360 ′ by the first through hole 332 , and the contact metal 390 is electrically connected to the connection line 322 by the second through hole 334 of the insulating layer 330 . The description of Fig. 1 above can be referred to Fig. 11.

2 is a flow chart showing a method of manufacturing a thin film transistor substrate 300 according to an embodiment of the present invention, and FIGS. 3-8 are schematic cross-sectional views showing respective process stages of an embodiment of the above manufacturing method.

In step 210, a first patterned metal layer is formed on the substrate 310 as shown in FIG. The substrate 310 includes a display area 314 and a non-display area 312, and the non-display area 312 is located around the display area 314. Referring to FIG. According to an embodiment of the invention, the material of the substrate 310 is made of glass, quartz, plastic or other polymer materials.

The first patterned metal layer can be formed using any conventional method. In one embodiment, a first layer of the first metal layer is deposited on the substrate 310, and then the gate 320, the scan line 324, and the connection line 322 are defined using a photolithography process. The gate 320 is formed in the display region 314, the scan line 324 is formed in the display region 314 and the non-display region 312, and the connection line 322 is formed in the non-display region 312. Referring to FIG.

The first patterned metal layer may be a single layer structure or a multilayer metal layer structure. In one embodiment, the material forming the first patterned metal layer is tungsten (Wu), chromium (Cr), copper (Cu), molybdenum (Mo), aluminum (Al), niobium (Nd), titanium (Ti). Or a combination of the above or an alloy as described above.

In step 220, a gate insulating layer 330 is formed to cover the first patterned metal layer, as shown in FIG. In the non-display area 312, the gate insulating layer 330 has at least one first through hole 332 and at least one second through hole 334 to respectively expose a portion of the first patterned metal connecting line 322. The first through hole 332 exposes a portion of the connection line 322 as a contact pad.

In one embodiment, a plasma-assisted chemical vapor deposition (PECVD) is used to form a gate insulating layer, and a reaction gas is introduced into the reaction chamber, and the reaction gas may be, for example, methane and mono-oxidation. The dinitrogen is then chemically reacted at a suitable temperature and the gate insulating layer 330 is deposited as cerium oxide (SiOx) or cerium oxynitride (SiOxNy). In the present embodiment, the film formation temperature of the gate insulating layer 330 ranges from about 350 ° C to about 400 ° C, preferably from about 360 ° C to about 390 ° C, more preferably from about 370 ° C to about 380 ° C.

In step 230, a patterned oxidized metal semiconductor layer 340 is formed over the gate insulating layer 330. As shown in FIG. 5, the oxidized metal semiconductor layer 340 is patterned relative to the gate 320.

The patterned metal oxide semiconductor layer 340 can be formed using any conventional method. In one embodiment, the method of forming the patterned metal oxide semiconductor layer 340 is a radio frequency magnetron sputtering method or a direct current sputtering method. The material of the patterned oxidized metal semiconductor 340 is indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), zinc oxide (ZnO) or the like.

In step 240, a second patterned metal layer is formed on the patterned metal oxide semiconductor layer 340 and the gate insulating layer 330. As shown in FIG. 6, the second patterned metal layer includes a source 352, a drain 350, and a signal. The line 360, 360', and the signal line 360' of the second patterned metal layer is electrically connected to the first metal layer connection line 322 by the first via 332.

In one embodiment, a second layer of a second metal layer is deposited over the gate insulating layer 330, and then source 352, drain 350, and signal lines 360, 360' are defined using a photolithographic etching process. Source 352 and drain 350 are formed in display area 314, and signal lines 360, 360' are formed in display area 314 and non-display area 312.

The material of the second patterned metal layer may be the same as or different from the material of the first patterned metal layer. The material of the second patterned metal layer may be, for example, tungsten (Wu), chromium (Cr), copper (Cu), molybdenum (Mo), aluminum (Al), niobium (Nd), titanium (Ti) or a combination thereof. The above alloy.

In step 250, a capping layer 370 is formed over the second patterned metal layer and the gate insulating layer 330. In one embodiment, the cap layer 370 is formed on the source 352, the drain 350, the signal line 360, and the gate insulating layer 330 of the second patterned metal layer of the display region 314, and has a contact window 372 to expose a portion of the drain. 350, as shown in Figure 7A. In another embodiment, the cap layer 370 covers the source 352 of the second patterned metal layer, the drain 350, the signal lines 360, 360', and the gate insulating layer 330. And in the display area 314, the cover layer 370 has a contact window 372 to expose a portion of the drain 350, and the cover layer 370 in the non-display area 312 has an opening 374 exposing a portion of the first patterned metal layer connection line 322 as Contact pads, as shown in Figure 7B.

In one embodiment, a plasma-assisted chemical vapor deposition (PECVD) is used to form a sheath 370, and methane and nitrous oxide are introduced as reaction gases into the reaction chamber. In one embodiment, the film forming temperature of the protective layer 370 is from about 100 ° C to about 200 ° C, preferably from about 150 ° C to about 180 ° C, more preferably from about 160 ° C to about 170 ° C, followed by a chemical reaction and deposition. A protective layer 370 of cerium oxide (SiOx) or cerium oxynitride (SiOxNy).

In step 260, a pixel electrode 380 is formed on the sheath 370 to be electrically connected to the drain 350 through the contact window 372, as shown in FIG.

In another embodiment, the implementation of steps 210 to 230 is the same as the above embodiment. In step 240, a second patterned metal layer is formed on the patterned metal oxide semiconductor layer 340 and the gate insulating layer 330. As shown in FIG. 9, the second patterned metal layer includes a source 352, a drain 350, and a signal. The wires 360, 360' and the contact metal 390, and the contact metal 390 is electrically connected to the first patterned metal layer via the second via 334, and the signal line 360' is patterned by the first via 332 and the first pattern. The connection lines 322 of the metal layers are electrically connected.

In step 250, a capping layer 370 is formed over the second patterned metal layer and the gate insulating layer 330. In one embodiment, the cap layer 370 is formed on the source 352, the drain 350, the signal line 360, and the gate insulating layer 330 of the second patterned metal layer of the display region 314, and has a contact window 372 to expose a portion of the drain. 350, as shown in Figure 10A. In another embodiment, the cap layer 370 covers the source 352 of the second patterned metal layer, the drain 350, the signal lines 360, 360', the gate insulating layer 330, and the contact metal 390, and has a contact window 372 in the display region 314. To expose a portion of the drain 350, and having an opening 374 in the non-display area 312, the exposed portion contacts the metal 390 as a contact pad as shown in FIG. 10B.

In step 260, a pixel electrode 380 is formed on the sheath 370 to be electrically connected to the drain 350 through the contact window 372, as shown in FIG. The specific embodiments and features of the second patterned metal layer, the protective layer 370, and the pixel electrode 380 of the present embodiment can be the same as those of the above-described embodiment.

In the prior art, the upper layer of the non-display area is covered only by a single layer of the protective layer, and the temperature is formed in the range of about 150 ° C to about 200 ° C. The low temperature film forming property makes the protective layer structure loose, so it is easy to cause the film. The phenomenon of holebreaking. According to an embodiment of the present invention, the gate of the non-display area may be covered with a single layer of the gate insulating layer or the double layer of the gate insulating layer and the protective layer, and the gate insulating layer is at about 350 ° C compared to the low temperature forming condition of the protective layer. The film is formed at a high temperature of about 400 ° C, so the structure is relatively dense, and it is more effective to avoid damage caused by external moisture or air to the thin film transistor substrate, and further reduce the possibility of RF failure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

300. . . Thin film transistor substrate

310. . . Substrate

312. . . Non-display area

314. . . Display area

320. . . Gate

322. . . Cable

324. . . Scanning line

330. . . Brake insulation

332. . . First through hole

334. . . Second through hole

340. . . Oxidized metal semiconductor layer

345. . . Thin film transistor

350. . . Bungee

352. . . Source

360, 360’. . . Signal line

370. . . Cover

372. . . First opening

374. . . Second opening

380. . . Pixel electrode

390. . . Contact metal

210, 220, 230, 240, 250, 260. . . step

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

1 is a plan view showing a thin film transistor substrate according to an embodiment of the present invention.

2 is a flow chart showing a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention.

Fig. 3-11 are schematic cross-sectional views showing the respective stages of the manufacturing process of the embodiment of the present invention, and along the line segments A-A', B-B' and C-C' of Fig. 1.

310. . . Substrate

312. . . Non-display area

314. . . Display area

320. . . Gate

322. . . Cable

324. . . Scanning line

330. . . Brake insulation

340. . . Oxidized metal semiconductor layer

350. . . Bungee

352. . . Source

360, 360’. . . Signal line

370. . . Cover

374. . . Opening

380. . . Pixel electrode

390. . . Contact metal

Claims (20)

A thin film transistor substrate comprising: a substrate comprising a display area and a non-display area, wherein the non-display area is located around the display area; at least one thin film transistor is disposed on the substrate and disposed in the display area At least one scan line is disposed on the first patterned metal layer on the substrate, electrically connected to at least one gate of the at least one thin film transistor, and disposed in the display area and the non-display area; a signal line, which is a second patterned metal layer on the insulating layer of the gate, electrically connected to at least one source and at least one drain of the at least one thin film transistor, and disposed on the display area and the non-display And at least one connecting line is disposed in the first patterned metal layer and disposed in the non-display area; wherein the gate insulating layer is at least a portion of the at least one portion of the first patterned metal layer a line and the at least one connecting line, wherein the at least one connecting line and the at least one signal line are in the non-display area, and at least one first pass located in the gate insulating layer Electrically connected, and which is located in the non-display having at least one contact metal region, the at least one contact metal and the at least one line is connected to the gate insulating layer to be located in at least one of the second through-hole electrical connection. The thin film transistor substrate of claim 1, wherein the gate is The edge layer is yttrium oxide (SiOx) or yttrium oxynitride (SiOxNy). The thin film transistor substrate of claim 1, wherein the gate insulating layer has a film forming temperature ranging from about 350 ° C to about 400 ° C. The thin film transistor substrate of claim 1, wherein the thin film transistor comprises at least a metal oxide semiconductor. The thin film transistor substrate according to claim 4, wherein the material of the metal oxide semiconductor is indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO) or zinc oxide (ZnO). The thin film transistor substrate of claim 1, further comprising a cover layer covering the second patterned metal layer and the gate insulating layer. The thin film transistor substrate of claim 6, wherein the sheath is cerium oxide (SiOx) or cerium oxynitride (SiOxNy). The thin film transistor substrate of claim 6, wherein the coating layer has a film forming temperature ranging from about 100 ° C to about 200 ° C. The thin film transistor substrate of claim 1, wherein the material of the contact metal is a metal of the second patterned metal layer. A method for preparing a thin film transistor substrate, comprising: providing a substrate, the substrate comprising a display area and a non-display area, wherein the non-display area is located around the display area; forming a first patterned metal layer on the substrate The first patterned metal layer includes at least one gate, at least one scan line, and at least one connection line, wherein the gate is formed in the display area, and the scan line is formed on the display area and the non-display area, the connection a gate is formed on the non-display area; a gate insulating layer is formed to cover the first patterned metal layer, wherein the gate insulating layer of the non-display region has at least one first via and at least one second via to expose a portion of the gate a connecting line of the first patterned metal layer, the second via hole exposing the portion of the connecting line of the first patterned metal layer as a contact pad; forming a patterned oxidized metal semiconductor layer on the gate insulating layer Wherein the patterned oxidized metal semiconductor layer is opposite to the gate; forming a second patterned metal layer on the patterned oxidized metal semiconductor layer and the On the insulating layer, the second patterned metal layer includes at least one source, at least one drain, and at least one signal line, and the signal line of the second patterned metal layer is formed by the first through hole and the first through hole The connecting line of a patterned metal layer is electrically connected; a protective layer is formed on the second patterned metal layer of the display region and the gate insulating layer, wherein the protective layer has at least one contact window to expose a portion of the a drain electrode; and forming a pixel electrode on the sheath to electrically connect to the drain through the contact window. The method of claim 10, wherein the protective layer further comprises the second patterned metal layer and the gate insulating layer covering the non-display area, and the protective layer has at least one opening to expose a portion of the contact pad. A method for preparing a thin film transistor substrate, comprising: providing a substrate, the substrate comprising a display area and a non-display area, wherein the non-display area is located around the display area; forming a first patterned metal layer on the substrate The first patterned metal layer includes at least one gate, at least one scan line, and at least one connection line, wherein the gate is formed in the display area, and the scan line is formed on the display area and the non-display area, the connection a gate is formed on the non-display area; a gate insulating layer is formed to cover the first patterned metal layer, wherein the gate insulating layer of the non-display region has at least one first via and at least one second via to expose a portion of the gate a connecting line of the first patterned metal layer; forming a patterned oxidized metal semiconductor on the gate insulating layer, wherein the patterned oxidized metal semiconductor is opposite to the gate; forming a second patterned metal layer for the patterning The oxidized metal semiconductor and the gate insulating layer, wherein the second patterned metal layer comprises at least one source, at least one drain, at least one signal a wire and at least one contact metal, and the signal line of the second patterned metal layer is electrically connected to the connection line of the first patterned metal layer by the first via hole, and the second patterned metal layer The contact metal is electrically connected to the connection line of the first patterned metal layer by the second via hole; forming a cover layer covering at least the second patterned metal layer and the gate insulating layer of the display region, Where the sheath has at least one contact window to expose a portion of the drain electrode; and forming a pixel electrode on the sheath to electrically connect to the drain through the contact window. The preparation method of claim 12, wherein the material forming the gate insulating layer comprises germanium methane and nitrous oxide. The preparation method of claim 12, wherein the film forming temperature of the gate insulating layer is from about 350 ° C to about 400 ° C. The preparation method of claim 12, wherein the film forming temperature of the gate insulating layer is from about 370 ° C to about 380 ° C. The preparation method according to claim 12, wherein the material for forming the patterned oxidized metal semiconductor is indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO) or zinc oxide (ZnO). The method of claim 12, wherein the protective layer further comprises the second patterned metal layer covering the non-display area and the gate insulating layer, and the protective layer has at least one opening to expose a portion of the contact pad. The preparation method according to claim 12, wherein the material forming the sheath layer comprises methane methane and nitrous oxide. The preparation method according to claim 12, wherein the film forming temperature of the sheath layer is from about 100 ° C to about 200 ° C. The preparation method of claim 12, wherein the film forming temperature of the sheath is from about 150 ° C to about 180 ° C.