TWI485995B - Portable computing device with a saw-less transceiver - Google Patents

Description

Portable computing device

The present invention relates to the field of wireless communications, and more particularly to a radio transceiver.

Communication systems are known to support wireless and wireline communication between wireless and/or wired connected communication devices. These communication systems range from national and/or international cellular telephone systems to the Internet and even to point-to-point home wireless networks. Various types of communication systems can be created separately and operate in accordance with one or more communication standards. For example, a wireless communication system can operate in accordance with one or more standards including, but not limited to, IEEE 802.11, Bluetooth, Advanced Mobile Phone Service (AMPS), Digital AMPS, Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA) ), local multipoint decentralized system (LMDS), multi-channel multi-point decentralized system (MMDS), radio frequency identification (RFID), enhanced packet radio communication service (EDGE), general packet radio service (GPRS), WCDMA, long-term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX) and/or variants thereof.

Depending on the type of wireless communication system, wireless communication devices (such as cellular phones, two-way radios, personal digital assistants (PDAs), personal computers (PCs), laptops, home entertainment devices, RFID readers, RFID tags, etc.) and other wireless devices The communication device communicates directly or indirectly. For direct communication (also known as point-to-point communication), participating wireless communication devices tune their receivers and transmitters to the same channel (eg, one or some of the system-specific RF frequencies of a plurality of radio frequency carriers of a wireless communication system) And communicate through these channels. For indirect wireless communication, each wireless communication device is associated with The base station (e.g., for cellular services) and/or communicates directly with associated access points (e.g., for use in a wireless network within a home or building) through assigned channels. In order to complete the communication link between the wireless communication devices, the relevant base stations and/or associated access points communicate directly with each other through the system controller, through the public switched telephone network, over the Internet, and/or through some other wide area network.

For each wireless communication device participating in wireless communication, it includes a built-in radio transceiver (ie, a receiver and a transmitter) or is connected to an associated radio transceiver (eg, a base station for a home and/or in-building wireless communication network, RF data machine, etc.). Receivers are known to be connected to an antenna and include a low noise amplifier, one or more intermediate frequency stages, a filtering stage, and a data recovery stage. The low noise amplifier receives the inbound RF signal through the antenna and then amplifies it. The one or more intermediate frequency stages mix the amplified RF signal with one or more local oscillations to convert the amplified RF signal to a baseband signal or an intermediate frequency signal. The filter stage filters the baseband signal or the intermediate frequency signal to attenuate unwanted out-of-band signals to generate a filtered signal. The data recovery stage recovers the data in the filtered signal according to a particular wireless communication standard.

Known transmitters include a data modulation stage, one or more intermediate frequency stages, and a power amplifier. The data modulation stage converts the data to a baseband signal according to a particular wireless communication standard. One or more intermediate frequency stages mix the baseband signal with one or more local oscillations to produce an RF signal. The power amplifier amplifies the RF signal and then transmits it through the antenna.

In order to implement a radio transceiver, the wireless communication device includes a plurality of integrated circuits and a plurality of discrete components. Figure 1 shows an example of a wireless communication device supporting 2G and 3G cellular telephone protocols. As shown, the wireless communication device includes a baseband processing IC, a power management IC, a radio transceiver IC, a transmit/receive (T/R) switch, an antenna, and a plurality of discrete components. Discrete components include surface acoustic wave (SAW) filters, power amplifiers, duplexers, inductors, and capacitors. These discrete components increase the material cost of wireless communication devices, but they are not required to achieve the precise performance requirements of the 2G and 3G protocols.

With the development of integrated circuit technology, wireless communication device manufacturers hope that there is no Line transceiver IC manufacturers update their ICs based on advances in IC manufacturing processes. For example, wireless transceiver ICs are redesigned for newer manufacturing processes due to changes in the manufacturing process (eg, using smaller transistor models). Since most digital circuits shrink with the IC manufacturing process, the redesign of the digital portion of the IC is a relatively simple process. However, since most analog circuits (such as inductors, capacitors, etc.) do not shrink with IC processes, the redesign of the analog part is not a simple task. As a result, wireless transceiver IC manufacturers have put a lot of effort into producing ICs that use the updated IC manufacturing process.

The present invention provides a device and method of operation, and further description is given in the following description of the drawings and the detailed description of the embodiments and claims.

According to an aspect of the invention, a portable computing device is provided, comprising: a front end module for connecting to an antenna portion and for separating one or more outputs from one or more inbound radio frequency signals Station radio frequency signal; a surfaceless acoustic wave (less-SAW) receiver for: converting the one or more inbound radio frequency signals into one or more inbound IF signals by: Responding to at least one of an intermediate frequency filter response and an RF filter response; filtering the one or more inbound radio frequencies according to the RF filter response when the baseband filter responds to the RF filter response And filtering the one or more inbound intermediate frequency signals according to the intermediate frequency filter response when the baseband filter is responsive to the intermediate frequency filter response; and Converting the one or more inbound IF signals into one or more inbound symbol streams; a surface acoustic wave transmitter for converting one or more outbound symbol streams into the one or more outbounds And a baseband processing unit for: converting outbound data into the one or more outbound symbol streams; and converting the one or more inbound symbol streams into inbound data.

Preferably, the portable computing device further includes: the front end module further configured to separate one or more second outbound radio frequency signals from the one or more second inbound radio frequency signals, wherein the one Or a plurality of inbound and outbound radio frequency signals are located in a first frequency band, and the one or more second inbound radio frequency signals are located in a second frequency band; the surface acoustic wave receiver is further configured to: Converting the plurality of second inbound radio frequency signals into one or more second inbound intermediate frequency signals, wherein: converting the second baseband filter response to at least one of a second intermediate frequency filter response and a second RF filter response Filtering the one or more second inbound radio frequency signals according to the second radio frequency filter response when the second baseband filter responds to the second radio frequency filter response; and when the second The baseband filter response frequency transforms the one or more second inbound intermediate frequency signals according to the second intermediate frequency filter response when the second intermediate frequency filter responds; and the one or more Two-input IF signal conversion One or more second inbound symbol streams; the surfaceless acoustic wave transmitter is further configured to convert one or more second outbound symbol streams into the one or more second outbound radio frequency signals; and the baseband processing The unit is also used to: Converting the second outbound data to the one or more second outbound symbol streams; and converting the one or more second inbound symbol streams to the second inbound material.

Advantageously, the front end module includes an antenna tuning unit coupled to the antenna portion and tuned for providing an impedance matching the impedance of the antenna portion; one or more power amplifiers for amplifying the Deriving one or more outbound radio frequency signals to generate one or more amplified outbound radio frequency signals; a separation module coupled to the surfaceless wave receiver, the antenna tuning unit, and the one or more power amplifiers The separation module is configured to: output the one or more amplified outbound radio frequency signals to the antenna tuning unit; and attenuate the connection between the separation module and the surfaceless wave receiver One or more amplified outbound radio frequency signals thereby separating the one or more inbound radio frequency signals from the one or more outbound radio frequency signals.

Preferably, the baseband processing unit is further configured to generate at least one of: an antenna tuning unit control signal, configured to adjust an impedance of the antenna tuning unit according to an impedance change of the antenna portion; and separate a control signal for adjusting the Determining attenuation of one or more outbound RF signals; and power amplifier control signals for adjusting one or more parameters of the one or more power amplifiers.

Preferably, the surface-free wave transmitter comprises: an up-conversion mixing module, configured to convert the one or more outbound symbol streams into one or more up-converted signals; and transmit a variable-frequency band-pass filter, In: converting the second baseband filter response to a second RF bandpass filter response; Filtering the one or more upconverted signals in response to the second RF bandpass filter to generate one or more filtered upconverted signals; and outputting a module for conditioning the one or more The filtered upconverted signal to produce one or more adjusted upconverted signals; and a power amplifier driver for amplifying the one or more adjusted upconverted signals to generate the one or more outbound radio frequency signals.

Preferably, the baseband processing unit is further configured to: generate a transmitter control signal, where the transmitter control signal is used to adjust at least one of: the second baseband filter response, the second RF bandpass filter Response and parameters of the power amplifier driver.

Advantageously, said surfaceless wave receiver comprises: a radio frequency-intermediate frequency receiver portion comprising: a low noise amplifier for amplifying said one or more inbound radio frequency signals to produce one or more amplified inbound stations a radio frequency signal; an intermediate frequency down conversion module for converting the one or more amplified inbound radio frequency signals into the one or more inbound intermediate frequency signals; and having the radio frequency band pass filter response a variable frequency band pass filter for filtering the one or more inbound radio frequency signals or filtering the one or more inbound intermediate frequency signals; and an intermediate frequency-baseband receiver portion for using the one or more The inbound IF signals are converted to one or more inbound symbol streams.

Preferably, the baseband processing unit is further configured to: generate a receiver control signal, where the receiver control signal is used to adjust at least one of: the baseband filter response, the radio frequency bandpass filter response, and the Low noise amplifier parameters.

Preferably, the portable computing device further includes: a first integrated circuit for supporting the baseband processing unit, the surfaceless wave receiver, and the surfaceless wave emitter; The second integrated circuit is configured to support the front end module.

Preferably, the portable computing device further includes at least one of: a processing module, configured to: execute one or more portable computing device functions to generate the outbound data; and execute the one or more The portable computing device functions to process the input data; and a power management unit for performing one or more power management functions of the portable computing device.

According to another aspect, a portable computing device is provided, comprising: a front end module, the front end module comprising: a plurality of power amplifiers, wherein a power amplifier of the plurality of power amplifiers amplifies a plurality of outbound RF signals a first outbound radio frequency signal; a plurality of separation modules, wherein the separation module of the plurality of separation modules separates the first inbound of the plurality of inbound radio frequency signals from the first outbound radio frequency signal a radio frequency signal; and at least one antenna tuning unit for providing an impedance matching the impedance of the antenna portion according to the control signal, wherein the antenna tuning unit receives the first inbound radio frequency signal from the antenna portion, and The antenna portion outputs the first outbound radio frequency signal; the surface acoustic wave receiver is configured to convert the plurality of inbound radio frequency signals into a plurality of inbound symbol streams; and the surface acoustic wave transmitter is configured to Converting an outbound symbol stream into the plurality of outbound radio frequency signals; and a baseband processing unit configured to: generate the control signal according to an impedance change of the antenna portion; convert a plurality of outbound data The plurality of outbound symbol stream; and the plurality of inbound symbol stream into a plurality of inbound data.

Preferably, the portable computing device further includes: a second power amplifier of the plurality of power amplifiers amplifying a second outbound radio frequency signal of the plurality of outbound radio frequency signals, wherein the first outbound radio frequency signal Located in the first frequency band, the second outbound radio frequency signal is located in the second frequency band; the second separation module of the plurality of separation modules separates the plurality of inbound radio frequencies from the second outbound radio frequency signal a second inbound radio frequency signal in the signal; a band switch coupled to the antenna portion and the at least one antenna tuning unit; and a second antenna tuning unit in the at least one antenna tuning unit for The control signal provides a second impedance that matches the impedance of the antenna portion, wherein the second antenna tuning unit receives the second inbound radio frequency signal from the antenna portion through the band switch and passes the frequency band The switch outputs the second outbound radio frequency signal to the antenna portion.

Preferably, the separation module is further configured to: output the first outbound radio frequency signal to the at least one antenna tuning unit; and attenuate the connection between the separation module and the surface waveless receiver Deriving the first outbound radio frequency signal to separate the first inbound radio frequency signal from the first outbound radio frequency signal.

Preferably, the portable computing device further includes: the baseband processing module generates a separation control signal; and the separation module adjusts the attenuation of the outbound radio frequency signal.

Preferably, the surface-free wave transmitter comprises: an up-conversion mixing module, configured to convert the one or more outbound symbol streams into one or more up-converted signals; and transmit a variable-frequency band-pass filter, In: converting the second baseband filter response to a second RF bandpass filter response; Filtering the one or more upconverted signals in response to the second RF bandpass filter to generate one or more filtered upconverted signals; and outputting a module for conditioning the one or more The filtered upconverted signal to produce one or more adjusted upconverted signals; and a power amplifier driver for amplifying the one or more adjusted upconverted signals to generate the one or more outbound radio frequency signals.

Preferably, the baseband processing unit is further configured to: generate a transmitter control signal, where the transmitter control signal is used to adjust at least one of: the second baseband filter response, the second RF bandpass filter Response and parameters of the power amplifier driver.

Preferably, the surface-free wave receiver comprises: a radio frequency-intermediate frequency receiver unit, comprising: a low noise amplifier unit, configured to amplify the plurality of inbound radio frequency signals to generate a plurality of amplified inbound radio frequency signals; An intermediate frequency down conversion module for converting the plurality of amplified inbound radio frequency signals into a plurality of inbound intermediate frequency signals; and a variable frequency band pass filter having the RF band pass filter response for filtering The plurality of inbound radio frequency signals or filtering the plurality of inbound intermediate frequency signals; and an intermediate frequency-baseband receiver unit for converting the plurality of inbound intermediate frequency signals into a plurality of inbound symbol streams.

Preferably, the baseband processing unit is further configured to: generate a receiver control signal, where the receiver control signal is used to adjust at least one of: the baseband filter response, the radio frequency bandpass filter response, and the Low noise amplifier parameters.

Preferably, the portable computing device further includes: a first integrated circuit for supporting the first baseband processing unit, the surfaceless wave receiver and the surfaceless wave transmitter; and a second product a body circuit for supporting the front end module.

Preferably, the portable computing device further includes at least one of: a processing module, configured to: execute one or more portable computing device functions to generate the outbound data; and execute the one or more The portable computing device functions to process the input; and a power management unit for performing one or more power management functions of the portable computing device.

The various advantages, aspects, and features of the invention, as well as the details of the specific embodiments, are described in the following description and drawings.

10‧‧‧Portable computing communication device

12‧‧‧System on a Chip (SOC)

14‧‧‧ Front End Module (FEM)

16‧‧‧Antenna

18‧‧‧No surface acoustic wave receiver

20‧‧‧No surface acoustic wave transmitter

22‧‧‧Baseband processing unit

24‧‧‧Processing module

26‧‧‧Power Management Unit

28‧‧‧ Receiver (RX) Radio Frequency (RF) - Intermediate Frequency (IF) Department

30‧‧‧Receiver (RX) IF-Baseband (BB)

32‧‧‧Variable Bandpass Filter (FTBPF)

34-36‧‧‧Power Amplifier (PA)

38-40‧‧‧Receiver-transmitter (RX-TX) separation module

42-44‧‧‧Antenna Tuning Unit (ATU)

46‧‧‧Band (FB) switcher

50‧‧‧ Front End Module (FEM)

52‧‧‧System on Chip (SOC)

54‧‧‧Antenna Tuning Unit (ATU)

60‧‧‧ Front End Module (FEM) Network

62-68‧‧‧ Front End Module (FEM)

70‧‧‧RF connection

78‧‧‧RF connection

80‧‧‧ Front End Module (FEM) Network

82‧‧‧Inverter Module

86‧‧‧RF-RF inverter module

90‧‧‧RF connection

100‧‧‧System on Chip (SOC)

110‧‧‧System on Chip (SOC)

112‧‧‧Intermediate (IF)-Baseband (BB) Receiver Unit

114‧‧‧BB-IF Transmitter Department

120‧‧‧ Front End Module (FEM) Network

122‧‧‧RF connection

124-130‧‧‧RX RF-IF Department

132-138‧‧‧TX IF-RF Department

140‧‧‧System on a Chip (SOC)

142‧‧‧ Front End Module (FEM) Network

144‧‧‧Intermediate (IF)-Baseband (BB) Receiver Unit

146‧‧‧BB-IF Transmitter Department

148‧‧‧RX RF-IF Department

150‧‧‧TX IF-RF Department

152-154‧‧‧RF connection

160‧‧‧System on Chip (SOC)

162‧‧‧ Front End Module (FEM) Network

164‧‧‧No SAW Receiver (RX) Downconverting Unit

166‧‧‧No SAW Transmitter (TX) Upconverting Unit

168-174‧‧‧FEM

176‧‧‧RF connection

180‧‧‧System on a Chip (SOC)

182‧‧‧ Front End Module (FEM)

190‧‧‧System on a Chip (SOC)

192‧‧‧ Front End Module (FEM)

200‧‧‧System on Chip (SOC)

202‧‧‧No SAW Transmitter Department

204‧‧‧RF-IF Receiver Division

206‧‧‧Low Noise Amplifier Module (LNA)

208‧‧‧mixing module

210-212‧‧‧mixing register

214-220‧‧‧ register

222‧‧‧Variable Bandpass Filter (FTBPF)

224‧‧‧ Receiver IF-BB

230‧‧‧System on Chip (SOC)

232‧‧‧RF-IF Receiver Division

234‧‧‧Variable Bandpass Filter (FTBPF)

236, 238‧‧‧ filter

240‧‧‧System on a Chip (SOC)

242‧‧‧RF-IF Receiver Division

244-246‧‧‧Low Noise Amplifier Module (LNA)

248‧‧‧mixing module

250-252‧‧‧Transimpedance Amplifier (TIA)

254-256‧‧‧impedance (Z)

258-260‧‧‧ register

270‧‧‧System on Chip (SOC)

271‧‧‧RF-IF Receiver Division

272‧‧‧RF variable frequency bandpass filter (FTBPF)

274-276‧‧‧Low Noise Amplifier Module (LNA)

278‧‧‧mixing module

280-282‧‧‧Transimpedance Amplifier (TIA)

284-286‧‧‧ Impedance (Z)

288‧‧‧IF FTBPF

290‧‧‧System on Chip (SOC)

292‧‧‧RF-IF Receiver Division

294‧‧‧IF FTBPF

300‧‧‧System on a Chip (SOC)

302‧‧‧Dual Band RF-IF Receiver Unit

304‧‧‧Variable Bandpass Filter (FTBPF)

306-308‧‧‧Low Noise Amplifier Module (LNA)

310-312‧‧‧ Mixing Module

314-320‧‧‧mixer register

322-328‧‧‧Filter

330‧‧‧System on Chip (SOC)

332‧‧‧RF-IF Receiver Division

334‧‧‧RF variable frequency bandpass filter (FTBPF)

336‧‧‧Low Noise Amplifier Module (LNA)

338‧‧‧Variable Bandpass Filter (FTBPF)

340‧‧‧mixing module

342-344‧‧‧mixer register

346-348‧‧‧Filter

350‧‧‧System on a Chip (SOC)

352‧‧‧RF-IF Receiver Division

354‧‧‧Variable Bandpass Filter (FTBPF)

356‧‧‧Low Noise Amplifier Module (LNA)

360‧‧‧System on Chip (SOC)

362‧‧‧Upconversion Mixing Module

364‧‧‧Transmitter Local Oscillation Module (LO)

366‧‧‧Variable Bandpass Filter (FTBPF)

368-370‧‧‧Capacitor array

372‧‧‧Power Amplifier Driver (PAD)

380‧‧‧System on Chip (SOC)

382‧‧‧Transmitter Department

390‧‧‧FEM

392‧‧‧LNA

394‧‧‧ Single-Ended Frequency Bandpass Filter (FTBPF)

396-402‧‧‧baseband impedance (Z _BB(s) )

404‧‧‧clock generator

410‧‧‧Single-ended FTBPF

412‧‧‧Differential FTBPF

414-420‧‧‧baseband impedance (Z _BB(s) )

422‧‧‧clock generator

430‧‧‧Single-ended FTBPF

432‧‧‧Complex baseband filter

434‧‧‧clock generator

440‧‧‧Different FTBPF

442‧‧‧Complex baseband filter

444‧‧‧clock generator

450-456‧‧‧baseband impedance (Z _BB(s) )

458‧‧‧ positive gain stage (Gm)

460‧‧‧negative gain stage (-GM)

470‧‧‧Control Module

476‧‧‧clock generator

480-486‧‧‧ Adjustable baseband impedance

488‧‧‧Adjustable positive gain stage

490‧‧‧Adjustable negative gain stage

492‧‧‧Optional Capacitor Network

494‧‧‧Programmable switched capacitor network

496‧‧‧Programmable switched capacitor filter

500‧‧‧Q RF-IF Mixer

502‧‧‧mixing register

504‧‧‧I mixer

510‧‧‧clock generator

522‧‧‧I mixing register

523‧‧‧Q Mixing Register

530‧‧‧IF FTBPF (frequency conversion bandpass filter) module

532, 534, 536, 538, 540, 542, 544, 546‧‧‧ baseband impedance (Z _BBz(s) )

550‧‧‧clock generator

560‧‧‧Single-ended FTBPF

562, 564, 566, 568‧‧‧ baseband impedance (Z _BB(s) )

572‧‧‧clock generator

580‧‧‧Differential FTBPF

582‧‧‧clock generator

590‧‧‧Dual Band Variable Frequency Bandpass Filter (FTBPF)

592, 594, 596, 598‧‧‧ baseband impedance (Z _BB (s))

600‧‧‧clock generator

610‧‧‧Dual Band Differential Frequency Bandpass Filter (FTBPF)

612, 614, 616, 618‧‧‧ baseband impedance (Z _BB (s))

622, 624‧‧‧Transimpedance Amplifier (TIA)

626, 628‧‧‧related impedance (Z)

630‧‧Differential I

632‧‧‧Differential Q

634‧‧‧clock generator

640, 642‧‧‧corresponding impedance (Z)

670‧‧‧Low Noise Amplifier (LNA)

650, 672, 674, 678‧‧‧FTBPF

680‧‧‧4 phase FTBPF

682, 684, 686, 688‧‧‧baseband impedance Z _BB (s)

690‧‧‧Superimposed signal harmonics

692‧‧‧Signal feedthrough harmonics

700‧‧‧3-phase FTBPF (frequency conversion bandpass filter)

702, 704, 706‧‧‧ baseband impedance Z _BB (s)

708‧‧‧Signal feedthrough harmonics

710‧‧‧Superimposed signal harmonics

712‧‧‧4 phase FTBPF (frequency conversion bandpass filter)

714‧‧‧4-phase FTBPF (frequency conversion bandpass filter)

716‧‧‧4-phase FTBPF (frequency conversion bandpass filter)

720‧‧‧4-phase FTBPF (frequency conversion bandpass filter)

722‧‧‧Complex baseband impedance Z _BB,C (ω)

726‧‧‧Complex baseband impedance

730‧‧‧Low Q baseband filter

732‧‧‧m phase FTBPF (frequency bandpass filter)

734‧‧‧m phase FTBPF (frequency conversion bandpass filter)

736‧‧‧m phase FTBPF (frequency conversion bandpass filter)

738‧‧‧m phase FTBPF (frequency conversion bandpass filter)

740‧‧‧m phase FTBPF (frequency conversion bandpass filter)

750‧‧‧clock generator

752, 754, 756‧‧‧ triggers (DFF)

758, 760, 762‧‧ ‧ pulse narrower

770‧‧‧clock generator

772, 774, 776‧‧‧ triggers (DFF)

790‧‧‧clock generator

792‧‧‧ Ring Oscillator

800‧‧‧clock generator

810‧‧‧clock generator

812, 814, 816‧‧‧ clock signals 1-3

818, 820, 822‧‧‧ clock signal 4-6

830‧‧‧ Front End Module (FEM)

832‧‧‧SOC

836‧‧‧Power Amplifier Module (PA)

838‧‧‧Duplexer

840‧‧‧Antenna Tuning Unit (ATU)

842‧‧‧Balanced network

844‧‧‧ Lookup Table (LUT)

846‧‧‧Processing module

848‧‧‧peak detector

850‧‧‧Tune Engine

852‧‧‧Low Noise Amplifier Module (LNA)

860‧‧‧ Front End Module (FEM)

862‧‧‧SOC

866‧‧‧Power Amplifier Module (PA)

872‧‧‧peak detector

874‧‧‧Tune Engine

876‧‧‧Switch and Low Noise Amplifier Module (LNA)

880‧‧‧Small signal balancing network

882‧‧‧ Large Signal Balancing Network

890‧‧‧ Front End Module (FEM)

892‧‧‧SOC

896‧‧‧Power Amplifier Module (PA)

898‧‧‧Duplexer

900‧‧‧Balanced network

902‧‧‧peak detector

904‧‧‧Tune Engine

906‧‧‧Discharge detection

908‧‧‧Module and Low Noise Amplifier Module (LNA)

910‧‧‧ Front End Module (FEM)

912‧‧‧SOC

916‧‧‧Power Amplifier Module (PA)

918‧‧‧Duplexer

920‧‧‧Balanced network

922‧‧‧peak detector

924‧‧‧Low Noise Amplifier Module (LNA)

926‧‧‧Processing module

930‧‧‧ Front End Module (FEM)

932‧‧‧SOC

936‧‧‧Power Amplifier Module (PA)

938‧‧‧Duplexer

940‧‧‧Balanced network

950‧‧‧ Front End Module (FEM)

952‧‧‧LNA

954‧‧‧Power Amplifier Module (PA)

956‧‧‧Duplexer

958‧‧‧Balanced network

960‧‧‧ Front End Module (FEM)

962‧‧‧SOC

970‧‧‧Balanced network

972‧‧‧ Single-Ended Low Noise Amplifier Module (LNA)

974‧‧‧peak detector

976‧‧‧Processing module

990‧‧‧ Front End Module (FEM)

992‧‧‧SOC

994‧‧‧Power Amplifier Module (PA)

996‧‧‧Duplexer

998‧‧‧ tone injection module

1000‧‧‧Balanced network

1002‧‧‧peak detector

1004‧‧‧Processing module

1006‧‧‧Low Noise Amplifier Module (LNA)

1010‧‧‧ Front End Module (FEM)

1012‧‧‧SOC

1014‧‧‧Power Amplifier Module (PA)

1016‧‧‧Duplexer

1018‧‧‧Balanced network

1020‧‧‧Processing module

1022‧‧‧Low Noise Amplifier Module (LNA)

1030‧‧‧Balanced network

1032‧‧‧impedance upconverter

1034‧‧‧baseband impedance (Zbb)

1042, 1044‧‧‧ impedance upconverter

1046, 1048‧‧‧baseband impedance (Zbb)

1050‧‧‧negative impedance

1052‧‧‧Anti-up converter

1060‧‧‧Polarization Receiver

1062‧‧‧ phase processing module

1064, 1066‧‧• Analog to Digital Converter (ADC)

1068‧‧‧ phase-locked loop (PLL)

1070‧‧‧peak detector

1072‧‧‧Amplitude Processing Module

1082‧‧‧PLL

1086‧‧‧Weaving connection

1100‧‧‧ Interwoven connection

1112‧‧‧MN

1126, 1128‧‧‧Transimpedance Amplifier (TIA)

1 is a schematic block diagram of a prior art wireless communication device; FIG. 2 is a schematic block diagram of a portable computing communication device in accordance with one embodiment of the present invention; and FIG. 3 is a portable computing communication in accordance with another embodiment of the present invention. 4 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention; and FIG. 5 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention; 6 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention; FIG. 7 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention; A schematic block diagram of a portable computing communication device of another embodiment; FIG. 9 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention; 10 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention; FIG. 11 is a schematic block diagram of a portable computing communication device in accordance with another embodiment of the present invention; FIG. 13 is a schematic block diagram of a portable computing communication device according to another embodiment of the present invention; FIG. 14 is a block diagram of a portable computing communication device according to another embodiment of the present invention; A schematic block diagram of a portable computing communication device; FIG. 15 is a schematic block diagram of an RF-IF receiver portion of a SOC according to an embodiment of the present invention; and FIG. 16 is an RF-IF receiving of a SOC according to another embodiment of the present invention. FIG. 17 is a schematic block diagram of an RF-IF receiver section of a SOC according to another embodiment of the present invention; FIG. 18 is an RF-IF receiver section of a SOC according to another embodiment of the present invention. FIG. 19 is a schematic block diagram of an RF-IF receiver section of a SOC according to another embodiment of the present invention; FIG. 20 is a schematic diagram of an RF-IF receiver section of a SOC according to another embodiment of the present invention. Block diagram; Figure 21 is a SOC in accordance with another embodiment of the present invention A schematic block diagram of an RF-IF receiver section; FIG. 22 is a schematic block diagram of an RF-IF receiver section of a SOC according to another embodiment of the present invention; and FIG. 23 is a transmitter section of a SOC according to an embodiment of the present invention. Schematic block diagram; 24 is a schematic block diagram of a transmitter portion of a SOC according to an embodiment of the present invention; and FIG. 25 is a schematic diagram of a portion of an RF-IF receiver portion including an FTBPF (Frequency Bandpass Filter) according to an embodiment of the present invention. Figure 26 is a schematic block diagram of a clock generator for an RF-IF receiver section in accordance with one embodiment of the present invention; Figure 27 is a frequency response of an RF-IF receiver section in accordance with one embodiment of the present invention. 28 is a schematic block diagram of an FTBPF according to an embodiment of the present invention; FIG. 29 is a schematic diagram of phase and frequency response of a baseband component of an FTBPF according to an embodiment of the present invention; Schematic diagram of the phase and frequency response of the RF component of the FTBPF; FIG. 31 is a schematic block diagram of a portion of an RF-IF receiver component including an FTBPF (Frequency Bandpass Filter) in accordance with another embodiment of the present invention; A schematic block diagram of a clock generator for an RF-IF receiver component in accordance with another embodiment of the present invention; and FIG. 33 is a schematic diagram of frequency response of an RF-IF receiver component in accordance with another embodiment of the present invention; According to this issue A schematic block diagram of a portion of an RF-IF receiver portion including an FTBPF (Frequency Bandpass Filter) of another embodiment; FIG. 35 is a clock generation for an RF-IF receiver component in accordance with another embodiment of the present invention. FIG. 36 is a schematic diagram of frequency response of an RF-IF receiver component in accordance with another embodiment of the present invention; FIG. 37 is a diagram including an FTBPF (Frequency Bandpass Filter) according to another embodiment of the present invention. A schematic block diagram of a portion of an RF-IF receiver portion; FIG. 38 is a timing for an RF-IF receiver portion in accordance with another embodiment of the present invention. A schematic block diagram of a clock generator; FIG. 39 is a schematic diagram of frequency response of an RF-IF receiver section according to another embodiment of the present invention; and FIG. 40 is a diagram showing an FTBPF (frequency band pass filter) according to another embodiment of the present invention. A schematic block diagram of a portion of an RF-IF receiver portion; FIG. 41 is a schematic block diagram of a clock generator for an RF-IF receiver portion in accordance with another embodiment of the present invention; FIG. 42 is another Schematic diagram of the frequency response of the RF-IF receiver section of one embodiment; FIG. 43 is a schematic block diagram of a portion of an RF-IF receiver section including an FTBPF (Frequency Bandpass Filter) in accordance with another embodiment of the present invention; 44 is a schematic block diagram of a clock generator for an RF-IF receiver section according to another embodiment of the present invention; and FIG. 45 is an RF including an FTBPF (Frequency Bandpass Filter) according to another embodiment of the present invention. -a schematic block diagram of a portion of an IF receiver portion; Figure 46 is a schematic block diagram of a clock generator for an RF-IF receiver portion in accordance with another embodiment of the present invention; Figure 47 is a diagram of a clock generator for an RF-IF receiver portion in accordance with one embodiment of the present invention; A schematic block diagram of a complex baseband (BB) filter; Figure 48 is based on this A schematic diagram of converting a complex BB filter frequency response to a high Q RF filter frequency response in accordance with one embodiment of the invention; and FIG. 49 is an RF-IF reception including an FTBPF (Frequency Variable Bandpass Filter) in accordance with another embodiment of the present invention. FIG. 50 is a schematic block diagram of a clock generator for an RF-IF receiver section in accordance with another embodiment of the present invention; FIG. 51 is an RF-in accordance with another embodiment of the present invention. Schematic diagram of the frequency response of the IF receiver section; FIG. 52 is a diagram showing the inclusion of FTBPF (inverter bandpass filter) according to another embodiment of the present invention. A schematic block diagram of a portion of an RF-IF receiver portion of a wave filter; FIG. 53 is a schematic block diagram of a clock generator for an RF-IF receiver portion according to another embodiment of the present invention; A schematic block diagram of a portion of an RF-IF receiver portion including an FTBPF (Frequency Bandpass Filter) of another embodiment of the invention; FIG. 55 is a clock for an RF-IF receiver portion in accordance with another embodiment of the present invention. A schematic block diagram of a generator; FIG. 56 is a schematic block diagram of a negative resistance according to an embodiment of the present invention; and FIG. 57 is an RF-IF receiver including an FTBPF (Frequency Bandpass Filter) according to another embodiment of the present invention. A schematic block diagram of a portion of a portion; FIG. 58 is a schematic block diagram of a clock generator for an RF-IF receiver portion in accordance with another embodiment of the present invention; and FIG. 59 is a diagram showing an FTBPF (including an FTBPF) according to another embodiment of the present invention. A schematic block diagram of a portion of an RF-IF receiver portion of a variable frequency band pass filter; FIG. 60 is a schematic block diagram of a clock generator for an RF-IF receiver portion in accordance with another embodiment of the present invention; Is the frequency response of the first LO of the RF-IF receiver section in accordance with one embodiment of the present invention FIG. 62 is a schematic diagram showing the frequency response of the second LO of the RF-IF receiver section according to an embodiment of the present invention; FIG. 63 is an RF including an FTBPF (Frequency Bandpass Filter) according to another embodiment of the present invention. -a schematic block diagram of a portion of an IF receiver portion; Figure 64 is a schematic block diagram of a portion of an RF-IF receiver portion including a mixer in accordance with another embodiment of the present invention; Figure 65 is another embodiment in accordance with the present invention A schematic block diagram of a clock generator of an RF-IF receiver section of the example; FIG. 66 is a schematic block diagram of a transimpedance amplifier (TIA) in accordance with one embodiment of the present invention; 67 is a schematic block diagram of a low noise amplifier (LNA) including an FTBPF according to an embodiment of the present invention; and FIG. 68 is a schematic block diagram of a 4-phase FTBPF (frequency conversion band pass filter) according to an embodiment of the present invention; Figure 69 is a schematic diagram showing the frequency response of a 4-phase FTBPF according to an embodiment of the present invention; Figure 70 is a schematic block diagram of a 3-phase FTBPF (frequency conversion band pass filter) according to another embodiment of the present invention; A schematic diagram of a clock signal of a 3-phase FTBPF inventing an embodiment; FIG. 72 is a schematic diagram of a frequency response of a 3-phase FTBPF according to an embodiment of the present invention; and FIG. 73 is a schematic block diagram of a 4-phase FTBPF according to another embodiment of the present invention. Figure 74 is a schematic block diagram of a 4-phase FTBPF in accordance with another embodiment of the present invention; Figure 75 is a schematic block diagram of a 4-phase FTBPF in accordance with another embodiment of the present invention; Figure 76 is another embodiment in accordance with the present invention; Schematic block diagram of a 4-phase FTBPF; FIG. 77 is a schematic block diagram of complex baseband impedance of an FTBPF according to an embodiment of the present invention; FIG. 78 is a schematic block diagram of a 4-phase FTBPF according to an embodiment of the present invention; m according to an embodiment of the present invention FIG. 80 is a schematic block diagram of an m-phase FTBPF according to an embodiment of the present invention; FIG. 81 is a schematic block diagram of an m-phase FTBPF according to an embodiment of the present invention; FIG. 82 is a schematic diagram of a m-phase FTBPF according to an embodiment of the present invention; A schematic block diagram of an m-phase FTBPF of an embodiment; FIG. 83 is a schematic block diagram of an m-phase FTBPF according to an embodiment of the present invention; and FIG. 84 is a schematic diagram of a frequency response of an m-phase FTBPF according to an embodiment of the present invention; Is a schematic block diagram of a clock generator of an m-phase FTBPF in accordance with one embodiment of the present invention; 86 is a schematic block diagram of a clock generator of an m-phase FTBPF according to another embodiment of the present invention; FIG. 87 is a schematic block diagram of a clock generator of an m-phase FTBPF according to another embodiment of the present invention; FIG. A schematic block diagram of a clock generator of a 3-phase FTBPF according to an embodiment of the present invention; FIG. 89 is a schematic block diagram of a clock generator of a 3-phase FTBPF according to another embodiment of the present invention; FIG. 90 is an embodiment of the present invention. FIG. 91 is a schematic block diagram of a portion of each of a front end module (FEM) and a SOC according to another embodiment of the present invention; FIG. 92 is a schematic block diagram of a portion of each of a front end module (FEM) and a SOC according to another embodiment of the present invention; FIG. 93 is a front end module (FEM) in a 2G TX mode according to an embodiment of the present invention. And a schematic block diagram of a portion of each of the SOCs; FIG. 94 is a schematic block diagram of a portion of each of the Front End Module (FEM) and the SOC in the 2G TX mode, in accordance with one embodiment of the present invention; Small signal level of one embodiment of the present invention A schematic block diagram of a balanced network; Figure 96 is a schematic block diagram of a large signal balancing network in accordance with one embodiment of the present invention; and Figure 97 is a front end module (FEM) and SOC each in accordance with another embodiment of the present invention. FIG. 98 is a schematic block diagram of a portion of each of a front end module (FEM) and a SOC according to another embodiment of the present invention; FIG. 99 is a front end according to another embodiment of the present invention. a schematic block diagram of a portion of each of the modules (FEM) and the SOC; 100 is a schematic block diagram of a portion of each of a front end module (FEM) and an LNA in accordance with another embodiment of the present invention; FIG. 101 is a front end module (FEM) and an LNA in accordance with one embodiment of the present invention. A schematic block diagram of an equivalent circuit of a portion of FIG. 102 is a schematic block diagram of a portion of each of a front end module (FEM) and an LNA in accordance with another embodiment of the present invention; FIG. 103 is a diagram in accordance with the present invention. A schematic block diagram of a transformer balun of an embodiment; FIG. 104 is a schematic diagram of a transformer balun implementation in accordance with one embodiment of the present invention; and FIG. 105 is a transformer balun in accordance with another embodiment of the present invention. Schematic diagram of implementation of (transformer balun); FIG. 106 is a schematic block diagram of a portion of each of a front end module (FEM) and an LNA according to another embodiment of the present invention; FIG. 107 is a front end according to another embodiment of the present invention. A schematic block diagram of a portion of each of a module (FEM) and an LNA; FIG. 108 is a schematic block diagram of impedance in accordance with one embodiment of the present invention; and FIG. 109 is an impedance in accordance with another embodiment of the present invention. Figure 110 is a schematic block diagram of a balanced network in accordance with one embodiment of the present invention; Figure 111 is a schematic block diagram of a balanced network in accordance with another embodiment of the present invention; Figure 112 is an embodiment in accordance with the present invention FIG. 113 is a schematic block diagram of a polarization receiver according to an embodiment of the present invention; FIG. 114 is a schematic block diagram of a register circuit according to an embodiment of the present invention; FIG. A schematic block diagram of a weaved connection of one embodiment of the present invention; and Figure 116 is a schematic block diagram of a receiver in accordance with one embodiment of the present invention.

2 is a portable meter including a system on chip (SOC) 12 and a front end module (FEM) 14. A schematic block diagram of an embodiment of a communication device 10 in which the SOC 12 and the FEM 14 are implemented on separate integrated circuits. The portable computing communication device 10 can be any device that can be carried by an individual, at least partially powered by a battery, including a radio transceiver (eg, radio frequency and/or millimeter wave (MMW)) and executing one or more software applications. For example, portable computing communication device 10 can be a cellular, laptop, personal digital assistant, video game joystick, video game player, personal entertainment unit, desktop computer, and the like.

The SOC 12 includes a surfaceless acoustic wave receiver portion 18, a surfaceless acoustic wave transmitter portion 20, a baseband processing unit 22, a processing module 24, and a power management unit 26. The surface acoustic wave receiver 18 includes a receiver (RX) radio frequency (RF)-intermediate frequency (IF) portion 28 and a receiver (RX) IF-baseband (BB) portion 30. The RX RF-IF section 28 also includes one or more variable frequency bandpass filters (FTBPF) 32.

Processing module 24 and baseband processing unit 22 may be a single processing device, a separate processing device, or multiple processing devices. The processing device can be a microprocessor, a microcontroller, a digital signal processor, a microcomputer, a central processing unit, a field programmable gate array, a programmable logic device, a state machine, a logic circuit, an analog circuit, a digital circuit, and/or A device that processes signals (analog and/or digits) arbitrarily according to hard code and/or operational instructions of the circuit. The processing module 24 and/or the baseband processing unit 22 may have associated memory and/or memory elements, which may be a single memory device, multiple memory devices, and/or processing modules. Group 24 embedded circuit. The memory device can be a read only memory, a random access memory, a volatile memory, a nonvolatile memory, a static memory, a dynamic memory, a flash memory, a cache memory, and/or Any device that stores digital information. Note that if the processing module 24 and/or the baseband processing unit 22 includes a plurality of processing devices, the processing devices may be centrally arranged (eg, directly connected by wired and/or wireless busbars) or distributed (eg, , through the indirect connection via LAN and / or WAN for cloud computing). It is also noted that when the processing module 24 and/or the baseband processing unit 22 perform one or more of its functions through a state machine, analog circuit, digital circuit, and/or logic circuit, the memory and/or memory of the corresponding operational command is stored. Memory components can be embedded or externally attached to the package In a circuit containing the state machine, analog circuit, digital circuit, and/or logic circuit. It should also be noted that the memory elements are stored, and the processing module 24 and/or the baseband processing unit 22 perform hard code and/or operational instructions associated with at least some of the steps and/or functions illustrated in at least one of the figures.

The front end module (FEM) 14 includes a plurality of power amplifiers (PAs) 34-36, a plurality of receiver-transmitter (RX-TX) split modules 38-40, a plurality of antenna tuning units (ATUs) 42-44, and Band (FB) switch 46. Note that the FEM 14 may include more than two paths Pas 34-36 (where the RX-TX split modules 38-40 and ATU 42-44 are connected to the FB switch 46) or may include a single path. For example, FEM 14 may include one path for 2G (second generation) cellular services, one path for 3G (third generation) cellular services, and a third path for wireless local area network (WLAN) services. Of course, there are many other exemplary path combinations in FEM 14 to support one or more wireless communication standards (eg, IEEE 802.11, Bluetooth, Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Radio Frequency Identification (RFID). ) Enhanced Packet Radio Service (EDGE), General Packet Radio Service (GPRS), WCDMA, High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Long Term Evolution (LTE), WiMAX (Microwave Storage) Take global interoperability) and / or its variants).

In one working example, processing module 24 performs one or more functions of a portable computing device that requires wireless transmission of data. At this point, the processing module 24 provides outbound data (eg, voice, text, audio, video, graphics, etc.) to the baseband processing unit or module 22, which is based on one or more wireless communication standards ( For example, GSM, CDMA, WCDMA, HSUPA, HSDPA, WiMAX, EDGE, GPRS, IEEE 802.11, Bluetooth, ZigBee, Universal Mobile Telecommunications System (UMTS), Long Term Evolution (LTE), IEEE 802.16, Data Optimization Improvement (EV- DO), etc.) Convert outbound data into one or more outbound symbol streams. Such conversion includes at least one of: scrambling, puncturing, coding, interleaving, constellation mapping, modulation, spread spectrum, frequency hopping, beamforming, space time block coding, space frequency block coding, frequency domain-time Domain conversion and/or digital baseband-intermediate frequency conversion. Note that the baseband processing unit 22 converts the outbound data. A single outbound symbol stream for single-input single-output (SISO) communication and/or multi-input single-output (MISO) communication, and converting outbound data into multiple outbound symbol streams for single-input multiple-output ( SIMO) and Multiple Input Multiple Output (MIMO) communication.

A baseband processing unit 22 provides the one or more outbound symbol streams to the surface acoustic wave transmitter portion 20, and the surface acoustic wave transmitter portion 20 converts the outbound symbol stream into one or more outbound RF signals (eg, signals in one or more of the bands 800 MHz, 1800 MHz, 1900 MHz, 2000 MHz, 2.4 GHz, 5 GHz, 60 GHz, etc.). The surface acoustic wave transmitter portion 20 includes at least one upconversion module, at least one variable frequency bandpass filter (FTBPF), and an output module; it can be configured to directly convert the topology (eg, direct conversion of baseband or near baseband symbolic flow to RF signals) Or a super heterodyne topology (eg converting a baseband or near baseband signed stream to an IF signal and then converting the IF signal to an RF signal).

For direct conversion, the surface acoustic wave transmitter portion 20 can have a Cartesian based topology, a polarization based topology, or a hybrid polarization-Cartesian based topology. In a Cartesian-based topology, the surface acoustic wave transmitter portion 20 will in-phase and quadrature components of the one or more outbound symbol streams (eg, A _I (t)cos(ω _BB (t) + Φ, respectively) _I (t)) and A _Q (t) cos(ω _BB (t) + Φ _Q (t))) are in-phase and quadrature components of one or more transmitter local oscillations (TXLO) (eg, cos, respectively) ω _RF (t)) and sin (ω _RF (t)) are mixed to produce a mixed signal. The FTBPF filters the mixed signals, and the output modules adjust (eg, common mode filtering and/or differential to single-ended) to generate one or more output upconverted signals (eg, A(t)cos (ω _BB (t) + Φ(t) + ω _RF (t))). A power amplifier driver (PAD) module amplifies the outbound upconverted signal to produce a pre-power amplified (pre-PA) outbound RF signal.

In a phase polarization based topology, the surfaceless acoustic wave transmitter portion 20 includes oscillations for generating an outbound symbol stream (eg, based on phase information (+/- ΔΦ [phase shift] and/or Φ(t) [phase modulation] The oscillator of the adjusted cos(ω _RF (t)). The resulting adjusted oscillation (eg cos(ω _RF (t)+/-△Φ) or cos(ω _RF (t)+Φ(t) )) can be further adjusted by amplitude information of the outbound symbol stream (eg A(t) [amplitude modulation]) to produce one or more upconverted signals (eg A(t)cos(ω _RF (t)+ /-△Φ) or A(t)cos(ω _RF (t)+Φ(t)). The FTBPF filters one or more upconverted signals and the output module adjusts (eg common mode filtering and / or differential single-ended conversion) They. The Power Amplifier Driver (PAD) module amplifies the outbound upconverted signal to produce an outbound RF signal that is preamplified by power.

In a frequency polarization based topology, the surfaceless acoustic wave transmitter portion 20 includes an oscillation for generating an outbound symbol stream (eg, based on frequency information (eg, +/- Δf [frequency shift] and/or f(t) [frequency Modulation] an oscillator that adjusts the cos(ω _RF (t)). The resulting adjusted oscillation (eg cos(ω _RF (t)+/-Δf) or cos(ω _RF (t)+f(t ))) can be further adjusted by the amplitude information of the outbound symbol stream (eg A(t) [amplitude modulation]) to produce one or more upconverted signals (eg A(t)cos(ω _RF (t) +/- Δf) or A(t)cos(ω _RF (t) + f(t)). The FTBPF filters one or more upconverted signals and the output module adjusts (eg common mode filtering) And/or differential single-ended conversion) them. A power amplifier driver (PAD) module amplifies the outbound upconverted signal to produce an outbound RF signal that is preamplified by power.

In a hybrid polarization-Cartesian based topology, the surface acoustic wave transmitter portion 20 will phase information of the outbound symbol stream (eg, cos(ω _BB (t) +/- ΔΦ) or cos(ω _BB (t)+ Φ(t))) and amplitude information (eg A(t)) are separated. The surface acoustic wave transmitter portion 20 combines the in-phase and quadrature components of the one or more outbound symbol streams (eg, cos(ω _BB (t) + Φ _I (t)) and cos(ω _BB (t), respectively). +ΦQ(t))) mixed with the in-phase and quadrature components of one or more transmitter local oscillations (TX LO) (eg, cos(ω _RF (t)) and sin(ω _RF (t)), respectively) Produces a mixed signal. The FTBPF filters the mixed signals, and the output modules condition (eg, common mode filtering and/or differential single-ended conversion) to generate one or more outbound upconverted signals (eg, A(t)cos(ω _BB) (t) + Φ(t) + ω _RF (t))). A power amplifier driver (PAD) module amplifies a standardized outbound upconverted signal and injects amplitude information (eg, A(t)) into a standardized outbound upconverted signal to produce a pre-powered (pre-PA) outbound RF signal. (eg A(t)cos(ω _RF (t)+Φ(t))). Other examples of the surfaceless acoustic wave transmitter portion 20 will be described with reference to Figs.

For the super-heterodyne topology, the surface acoustic wave transmitter portion 20 includes a baseband (BB)-intermediate frequency (IF) portion and an IF-radio frequency (RF) portion. The BB-IF portion can be a polarization based topology, a Cartesian based topology, a hybrid polarization-Cartesian based topology or a mixed stage of upconverting outbound symbol streams. In the first three examples, the BB-IF section generates an IF signal (eg, A(t)cos(ω _IF (t) + Φ(t))), and the IF-RF section includes a mixing stage, a filter stage, and a power amplifier driver ( PAD) to generate an outbound RF signal that is preamplified by power.

When the BB-IF section includes a mixing stage, the IF-RF section may have a polarization based topology, a Cartesian based topology, or a hybrid polarization-Cartesian based topology. In this case, the BB-IF section converts the outbound symbol stream (eg A(t)cos((ω _BB (t)+Φ(t)))) into an IF symbol stream (eg A(t)cos( ω _IF (t) + Φ(t))) The IF-RF section converts the IF symbol stream into an out-of-power amplified outbound RF signal.

The surface acoustic wave transmitter unit 20 outputs a pre-power amplified outbound RF signal to the power amplifier modules (PA) 34-36 of the front end module (FEM) 14. The PA 34-36 includes one or more power amplifiers connected in series and/or in parallel to the amplified pre-power amplified RF signals to produce an outbound RF signal. Note that PA 34-36 parameters (such as gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rate of rise, settling time, overshoot, stability factor, etc.) can be processed from baseband The control signals received by unit 22 and/or processing module 24 are adjusted. For example, the processing source of the SOC 12 (eg, BB processing unit 22 and/or processing module 24) monitors the transmission conditions due to changes in transmission conditions (eg, corresponding channel changes, distance changes between TX units and RX units, antenna property changes, etc.) Change and adjust the properties of PA 34-36 to optimize performance. This determination is not made independently; for example, it can be made based on other parameters of the front-end module that can be adjusted (eg ATU 42-44, RX-TX separation module 38-40) to optimize the transmission and reception of RF signals. .

The RX-TX separation module 38-40 (which may be a duplexer, a circulator or a transformer balun or other separate means for providing a TX signal and an RX signal using a shared antenna) attenuates the outbound RF signal. The RX-TX separation module 38-40 can adjust its outbound station based on control signals received from the baseband processing unit and/or processing module 24 of the SOC 12 Attenuation of the RF signal. For example, when the transmit power is relatively low, the RX-TX split module 38-40 can be adjusted to reduce its attenuation of the TX signal.

The antenna tuning unit (ATU) 42-44 is tuned to provide the desired impedance that is substantially matched to the antenna 16. After tuning, the ATU 42-44 provides the attenuated TX signal from the RX-TX split module 38-40 to the antenna 16 for transmission. Note that the ATU 42-44 can be adjusted continuously or periodically to track the impedance variation of the antenna 16. For example, baseband processing unit 22 and/or processing module 24 can detect changes in impedance of antenna 16 and provide control signals to ATUs 42-44 based on the detected changes to change their impedance accordingly.

In this example, the surface acoustic wave transmitter portion 20 has two outputs: one for the first frequency band and the other for the second frequency band. The above discussion is concerned with the conversion process of outbound data to outbound RF signals in a single frequency band (eg, 850 MHz, 900 MHz, etc.). This process is similar to the conversion of outbound data to RF signals in other frequency bands (eg, 1800 MHz, 1900 MHz, 2100 MHz, 2.4 GHz, 5 GHz, etc.). Note that when a single antenna 16 is used, the surface acoustic wave transmitter 20 generates outbound RF signals in other frequency bands in the other frequency bands. A band (FB) switch 46 of the FEM 14 connects the antenna 16 to a suitable output of the surfaceless acoustic wave transmitter output path. The FB switch 46 receives control information from the baseband processing unit 22 and/or the processing module 24 for selecting a path to connect to the antenna 16.

Antenna 16 also receives one or more inbound RF signals and provides them to one of ATUs 42-44 via a frequency band (FB) switch 46. The ATU 22-24 provides the inbound RF signal to the RX-TX split module 38-40, which routes the signal to the receiver (RX) RF-IF portion of the SOC 12. The RX RF-IF section 28 converts the inbound RF signal (eg, A(t)cos(ω _RF (t) + Φ(t))) into an inbound IF signal (eg, A _I (t)cos(ω _IF (t) ) +Φ _I (t)) and A _Q (t)cos(ω _IF (t) + Φ _Q (t))). Various embodiments of the RX RF-IF portion 28 will be illustrated in Figures 15-23 or other figures.

The RX IF-BB section 30 converts the inbound IF signal into one or more inbound symbol streams (e.g., A(t)cos(ω _BB (t) + Φ(t))). At this time, the RX IF-BB section 30 includes a mixing section and a combining & filtering section. The mixing section mixes the inbound IF signal with a second local oscillation (e.g., LO2 = IF-BB, where BB can range from zero to a few MHz) to produce I and Q mixing signals. The combining & filtering unit combines (for example, adding a mixing signal together to include a sum component and a differential component), and then filtering the combined signal to a large attenuation and a number component, and using the substantially un-attenuated differential component as an inbound symbol flow.

Baseband processing unit 22 is based on one or more wireless communication standards (eg, GSM, CDMA, WCDMA, HSUPA, HSDPA, WiMAX, EDGE, GPRS, IEEE 802.11, Bluetooth, ZigBee, Universal Mobile Telecommunications System (UMTS), Long Term Evolution ( LTE), IEEE 802.16, Data Optimization Improvement (EV-DO), etc.) convert inbound symbol streams into inbound data (eg, voice, text, audio, video, graphics, etc.). The conversion may include at least one of the following: digital intermediate frequency-baseband conversion, time domain-frequency domain conversion, space-time block decoding, space-frequency packet decoding, demodulation, spread spectrum decoding, frequency hopping decoding, beamforming decoding. , constellation de-mapping, de-interlacing, decoding, de-puncturing, and/or descrambling. Note that processing module 24 converts a single inbound symbol stream into inbound data for single-input single-output (SISO) communication and/or multiple-input single-output (MISO) communication, and converts multiple inbound symbol streams into Inbound data for single-input multiple-output (SIMO) and multiple-input multiple-output (MIMO) communications.

The power management unit 26 is integrated in the SOC 12 to perform various functions. These functions include monitoring power connections and battery charging, charging the battery when necessary, controlling power to other components of the SOC 12, generating supply voltages, turning off unnecessary SOC modules, controlling the sleep mode of the SOC module, and/or providing an instant clock. . To facilitate the generation of the power supply voltage, the power management unit 26 may include one or more switched mode power supplies and/or one or more linear regulators.

With such a portable computing communication device 10, expensive and discrete off-chip components (such as SAW filters, duplexers, inductors, and/or capacitors) can be eliminated and their functionality can be implemented on a single die. Front End Module (FEM) 14. In addition, the absence of the SAW receiver section and the SAW-free transmitter section facilitate the elimination of discrete off-chip components.

3 is a schematic block diagram of a portable computing communication device 10 that includes a system on a chip (SOC) 52 and a front end module (FEM) 50 of another embodiment, in accordance with another embodiment of the present invention. The SOC 52 includes a power management unit 26, a SAW-free receiver unit 18, a SAW-free transmitter unit 20, and a baseband processing unit 22, and may further include a processing module. The FEM 50 includes a plurality of power amplifier modules (PA) 34-36, a plurality of RX-TX split modules 38-40, and at least one antenna tuning unit (ATU) 54.

In the present embodiment, SOC 52 is used to simultaneously support at least two types of wireless communication (e.g., cellular telephone calls and WLAN communications and/or Bluetooth communications). Thus, the no-SAW transmitter 20 generates two (or more) different frequency bands of outbound RF signals in the manner described with reference to FIG. 2 and/or with reference to one or more of the following figures. The first of these different frequency outbound RF signals can be provided to one of the PAs 34-36 of the FEM 50 and the other outbound RF signals to the other PA 34-36. The function of each of the TX-RX separation modules 38-40 is as described with reference to Figure 2 and will be described with reference to at least one of the following figures. The ATU 54 tuned according to the control signal from the SOC 52 provides the antenna 16 with two outbound RF signals for transmission.

Antenna 16 also receives inbound RF signals of two or more different frequency bands and provides them to ATU 54. The ATU 54 may include a splitter for separating the two inbound RF signals and separating the impedance matching circuits (eg, one or more LC circuits) of each of the separated signals; for separating the signals and separating the impedance matching circuits A balun transformer; or an impedance matching circuit for both signals, wherein the two signals are provided to the RX-TX separation module 38-40.

The RX-TX split modules 38-40 rely on respective frequency bands, respectively, which only pass inbound and outbound RF signals within respective frequency bands (e.g., 850-900 MHz and 1800-1900 MHz). Therefore, the first TX-RX separation module 38-40 provides a first band inbound RF signal to the first input of the no SAW RX portion 18, and the second TX-RX separation module 38-40 provides a second band inbound. The RF signal is applied to the second input of the no SAWRX section 18. The no-SAW RX section 18 processes the inbound RF signal to produce a first inbound in accordance with a method that has been described with reference to FIG. 2 and/or which will be described with reference to at least one of the following figures. Information and second inbound information.

4 is a schematic block diagram of a portable computing communication device 10 including a system on a chip (SOC) 12 or 52 coupled to a front end module (FEM) network 60 via an RF connection 70, in accordance with another embodiment of the present invention. The SOC 12 or 52 includes a power management unit 26, a SAW-free receiver unit 18, a SAW-free transmitter unit 20, and a baseband processing unit 22, and may further include a processing module. The RF connection 70 can be at least one of a coaxial cable, an elastic fiber cable, an elastic waveguide, and/or other high frequency cable. The FEM network 60 includes a plurality of FEMs 62-68 (eg, two or more), wherein each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX separation modules, and at least An antenna tuning unit (ATU) and a band switcher (SW). Note that the structure of at least one of the FEMs 62-68 is as described with reference to FIG.

Each of the FEMs 62-68 may support the same frequency band, different frequency bands, or a combination thereof, respectively. For example, two FEMs can support the same frequency band (eg, 850-900 MHz and 1800-1900 MHz), while the other two can support different frequency bands (eg, 2.4 GHz, 5 GHz, 60 GHz, etc.). In this example, the SOC 12 or 52 may be based on multiple RF communication parameters (eg, transmit power level, received signal strength, out-of-band block, signal to noise ratio, signal to interference ratio, operating frequency, interference with other wireless communications, etc.) At least one of the selections of one of the FEMs 62-68 having the same frequency band. For example, SOC 12 or 52 selects a FEM that is capable of providing cellular communication at the current best performance level and another FEM capable of providing the current best performance level of WLAN, personal area network or other wireless network communication.

Since each of the FEMs 62-68 is programmable, the SOC 12 or 52 can program the selected modules to reduce mutual interference. For example, FEMs that support cellular communications can be tuned to have additional attenuation within the wireless local area network communication band (eg, 2.4 GHz, 5 GHz, 60 GHz, etc.). Additionally, as conditions (e.g., interference, transmit-receive distance, antenna parameters, environmental factors, etc.) change, the SOC 12 or 52 can adjust the parameters of the selected FEM to substantially compensate for the change. Alternatively, the SOC 12 or 52 may select another FEM to perform at least one of the two communications.

The SOC 12 or 52 may select multiple FEMs 62-68 to support MIMO communication, SIMO communication, and/or MISO communication. For example, in 2*2 MIMO communication, one FEM can be selected for one of the TX/RX MIMO communications, and the other FEM can be selected for another TX/RX MIMO communication.

The SOC 12 or 52 may also select one FEM to support transmissions within one frequency band and another FEM to support reception within the same frequency band. For example, the SOC 12 or 52 may select the first FEM to support the 1800 MHz cellular telephone transmission and the second FEM to support the 1800 MHz cellular telephone reception. For another example, SOC 12 or 52 may select the first FEM to support 1800 MHz cellular telephone transmission, the second FEM to support 900 MHz cellular telephone transmission, the third FEM to support 1800 MHz cellular telephone reception, and the fourth FEM to support 900 MHz cellular telephone reception. As another example, SOC 12 or 52 may select a first FEM to support 1800 MHz cellular telephone transmission, a second FEM to support 900 MHz cellular telephone transmission, and a second FEM to support 1800 MHz cellular telephone reception, the first FEM supporting 900 MHz cellular telephone reception.

FEM network 60 can be implemented on a single die on a single package substrate; on multiple dies on a single substrate (eg, each FEM on one die); each FEM acts as a separate integrated circuit (IC) implementation. In the latter case, at least one of the FEMs 62-68 can be remote from the SOC 12 or 52. For example, the portable computing communication device can be a wireless femtocell transceiver supporting cellular telephone communication, wherein at least one FEM is physically at a distance (eg, greater than 1 meter) from the SOC 12 or 52. In addition, one of the FEMs can be used to communicate with the base station while one or more other FEMs can be used to communicate with other wireless communication devices, such as cellular.

For example, device 10 communicates with a base station (BS) using conventional cellular services while the link between the device and other wireless communication devices uses another frequency band. The SOC processing module coordinates the internet and/or cellular access of other devices and the signal conversion of various links.

As another example, device 10 acts as a wireless nanometer of 1-4 cells or other handheld devices Microcell base station use. The wireless local area link between devices can comply with one or more protocols. One protocol complies with traditional cellular standards (eg, a wireless femtocell base station distributes a local area wireless link like a BS). Another protocol enables wireless femtocell base station devices to be extended as user interfaces over Internet Protocol (IP) channels. A link to the handset is connected to the access point (AP), or the handset is linked to other devices to form a grid, thereby being logically connected to the AP by other means.

As another example, device 10 is used as a wireless femtocell (e.g., an AP) that uses a data call to the calling system to wirelessly provide an IP channel to the AP that logically connects the AP to the Internet. Application server anywhere. For example, the carrier does not have to provide a telephone system interface for voice calls. The IP channel traverses the AP to connect, for example, an Internet telephony client within the domain to the Internet telephony network. The load and capacity of the data channel from the carrier of the AP determines the number of active handsets supported by an AP.

In this example, the link from the AP to the supported wireless device is not within the cellular band, but instead uses the traditional cellular standard (ie, the AP is similar to the BS, and the AP performs when the mobile client is running on the supported wireless device) Converter function). Alternatively, the link between device 10 and the supported wireless device uses a proprietary series of calling steps that are not part of the cellular standard. At this point, the AP runs the device client and the device is only a remote UI extension on the IP channel.

As another example, device 10 determines if it should be a femtocell base station for other wireless devices. At this point, device 10 determines whether it meets a quality threshold (eg, can give a good and sustained signal to the carrier, has better battery life, is not used for mobile calls, etc.). If so, it will register with the carrier as a femtocell in a given geographic location. Once registered, it will search for nearby wireless devices (eg, cellular) in a point-to-point wireless manner (60 GHz, TVWS, 2.4 GHz, etc.). For the devices it identifies, device 10 determines the signal strength of the carrier of each wireless device (e.g., they pass information). For a wireless device with weak or no signal strength per carrier (e.g., BS of a carrier), device 10 actively becomes the femtocell base station of the wireless device. If not The line device expects the device 10 to be its own femtocell base station, which uses the carrier to register itself as a femtocell base station for the wireless device. Note that this can be a dynamic process between several devices, one of which can act as a femtocell base station AP for other devices. If the condition changes, one of the other devices described above can become the femtocell base station AP of these devices, and the device as the femtocell base station AP becomes the UE of the new femtocell base station AP. As another example, multiple devices can be combined to form a femto-network. At this time, one device serves as a relay station of one or more other devices for accessing a device as a wireless femtocell base station AP. Alternatively, the cooperation may include having multiple wireless femtocell base station devices as hosts for the local devices, and they are linked to other APs to provide connectivity. This sharing may be one of the wireless femtocell base station devices providing a cellular voice connection, the other providing a cellular data connection, and the third providing a WLAN connection.

As another example, multiple devices are in a confined geographic area (eg, in a car, in a room, etc.) and use agreements to determine which device will act as a wireless femtocell base station AP for other devices and which services are provided. For example, a group of devices (at least one of which can act as a femtocell base station AP) establish a point-to-point link (60 GHz, TVWS, 2.4 GHz, etc.) with each other, and then compare the nodes on the mobile site that span the time in groups. To determine if these links can continue over time and whether they move substantially together (eg in the same car or train, etc.). If they determine that they are in the same mobile vehicle, they will report each other's specific average carrier quality values. Based on these magnitudes, they can determine which handset has the best overall signal for the carrier. Each device can be on a different carrier, or they can all be on the same carrier. In each mode, the signals of one device and the other are very different, and this difference can be a function of many variables, such as the position in the motor vehicle and the distance from the body. If the best signal is significantly better than a given device can be implemented over its direct carrier link, it will request that the device with the best signal be the host. Once registration is complete, the call will be delivered to the other device via the AP host.

If the carrier signal is below the threshold, the process repeats and another device can be selected as the new host. In this particular case, all devices know which other devices are being tested, at least until they are out of range. As another example, for devices participating in a web conference, each device provides a user interface to one person (ie, a device user) at a time. Thus, each device essentially supports the same one-to-one wireless connection using the carrier. In order to reduce redundant traffic and reduce the cost of increasing network capacity, the first device of the network conference actively becomes a wireless femtocell base station AP of other devices in the same geographical area. If accepted, the first device registers with the carrier and then acts as a wireless femtocell base station AP for other devices of the network conference. An extension of this scheme can be applied to any type of audio and/or video conference, whether or not multiple users within a given geographic area will participate in the conference through the portable computing communication device. Another extension may include sharing a server-based application with other devices (eg, one device is a wireless femtocell base station AP that accesses an Internet-hosted application (eg, a database, video game, etc.), and other devices pass the Wireless femtocell base station AP accesses Internet-hosted applications).

As another example, a device used as a wireless femtocell base station AP is configured according to its environment (eg, for use in an office, at home, in a car, in a public place, in a private place, in a public use, in a private use, etc.). The configuration options include frequency usage mode, transmit power, number of units for support, centralized femtocell control, decentralized femtocell control, allocated capacity, coding level, symbol and/or channel connection In. For example, if in a public place, the device will be used as a public wireless femtocell or private wireless femtocell. When the device is used as a private femtocell base station, it selects a configuration that ensures the privacy of the communications it supports.

5 is a schematic block diagram of a portable computing communication device 10 including a system on a chip (SOC) 12 or 52 coupled to a front end module (FEM) network 80 via an RF connection 90, in accordance with another embodiment of the present invention. The SOC 12 or 52 includes a power management unit 26, a SAW-free receiver unit 18, a SAW-free transmitter unit 20, and a baseband processing unit 22, A processing module can also be included. The RF connection 90 can be at least one of a coaxial cable, an elastic fiber cable, an elastic waveguide, and/or other high frequency cable. The FEM network 80 includes a plurality of FEMs 62-68 (e.g., two or more) and a frequency conversion module 82. The frequency conversion module 82 includes one or more bypass RF-RF conversion modules. Each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX split modules, at least one antenna tuning unit (ATU), and a band switcher (SW). Note that the structure of at least one of the FEMs 62-68 is as described with reference to FIG.

The functions of SOC 12 or 52 and FEM 62-68 are similar to SOC 12 or 52 and FEM 62-68 in FIG. In this embodiment, the inbound RF signal from the FEM and/or the outbound RF signal from the SOC 12 or 52 may be frequency converted prior to routing between the SOC 12 or 52 and the corresponding FEM. For example, SOC 12 or 52 may form an input and outbound RF signal for processing a carrier frequency of 2.4 GHz, but with baseband functionality to generate a symbol stream in accordance with a plurality of standardized wireless protocols and/or proprietary protocols. At this point, SOC 12 or 52 generates an outbound symbol stream according to a given radio protocol and upconverts the symbol stream to an RF signal having a 2.4 GHz carrier frequency.

An RF-RF frequency conversion module 86 including a local oscillator, mixing module, and filtering mixes the outbound RF signal with local oscillations to produce a mixed signal. The filter section filters the mixed signal to produce an outbound RF signal of a desired carrier frequency (eg, 900 MHz, 1800 MHz, 1900 MHz, 5 GHz, 60 GHz, etc.). Note that the frequency conversion module 82 can include multiple RF-RF conversion modules (one or more for increasing the carrier frequency and/or one or more for reducing the carrier frequency). In this regard, the implementation of the general purpose SOC 12 or 52 can be coupled with various implementations of the FEM network 80 (eg, the number of FEM modules 62-68, the number of RF-RF conversion modules, etc.) to form various portable calculations. Communication device.

6 is a schematic block diagram of a portable computing communication device 10 including a plurality of system-on-a-chip (SOC) 12 connected to a front end module (FEM) network 60 via an RF connection 78 or in accordance with another embodiment of the present invention. 52. Each SOC 12 or 52 includes a power management unit 26, a no-SAW receiver unit 18, a no-SAW transmitter unit 20, a baseband processing unit 22, and a processing module. The RF connection 78 can be a coaxial cable, At least one of an elastic fiber optic cable, an elastic waveguide, and/or other high frequency cable. The FEM network 60 includes a plurality of FEMs 62-68 (eg, two or more), wherein each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX separation modules, and at least one Antenna Tuning Unit (ATU) and Band Switcher (SW). Note that the structure of at least one of the FEMs 62-68 is as described with reference to FIG.

In this embodiment, one SOC 12 or 52 uses at least one of the FEMs 62-68 to support one or more wireless communications (eg, cellular, WLAN, WPAN, etc.) and the other SOC 12-52 uses one or more other FEMs 62- 68 to support one or more other wireless communications. In order to reduce interference between wireless communications and/or to optimize each wireless communication, at least one SOC 12 or 52 provides control signals to FEMs 62-68 to adjust its performance. In addition to the use of different FEMs 62-68 for each SOC 12 or 52, in another example, two or more SOCs 12 or 52 may share FEM 62-68 by a switching module (not shown) in a time division manner. . In yet another example, one SOC 12 or 52 may use one path of the FEM 62-68, and the other SOC 12 or 52 may use at least one of the other paths of the FEM 62-68.

7 is a schematic block diagram of a portable computing communication device 10 including a plurality of system-on-a-chip (SOC) 12 connected to a front end module (FEM) network 80 via an RF connection 90, or in accordance with another embodiment of the present invention. 52. The SOC 12 or 52 includes a power management unit 26, a SAW-free receiver unit 18, a SAW-free transmitter unit 20, and a baseband processing unit 22, and may further include a processing module. The RF connection 90 can be at least one of a coaxial cable, an elastic fiber cable, an elastic waveguide, and/or other high frequency cable. The FEM network 80 includes a plurality of FEMs 62-68 (e.g., two or more) and a frequency conversion module 82. The frequency conversion module 82 includes one or more bypass RF-RF conversion modules. Each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX split modules, at least one antenna tuning unit (ATU), and a band switcher (SW). Note that the structure of at least one of the FEMs 62-68 is as described with reference to FIG.

In this embodiment, one SOC 12 or 52 uses at least one of the FEMs 62-68 to support one or more wireless communications (eg, cellular, WLAN, WPAN, etc.), One SOC 12-52 uses one or more other FEMs 62-68 to support one or more other wireless communications. In order to reduce interference between wireless communications and/or to optimize each wireless communication, at least one SOC 12 or 52 provides control signals to FEMs 62-68 to adjust its performance. Additionally, at least one wireless communication can be passed through the frequency conversion module 82 to increase or decrease the carrier frequency of the wireless communication.

FIG. 8 is a schematic block diagram of a portable computing communication device 10 including a system on a chip (SOC) 100 coupled to a front end module (FEM) network 60 via an RF connection 70, in accordance with another embodiment of the present invention. The SOC 100 includes a power management unit 26, a plurality of SAWless receiver sections 18-1-18-2, a plurality of SAWless transmitter sections 20-1-20-2, one or more baseband processing units 22, and may also include Processing module. The RF connection 70 can be at least one of a coaxial cable, an elastic fiber cable, an elastic waveguide, and/or other high frequency cable. The FEM network 60 includes a plurality of FEMs 62-68 (eg, two or more), wherein each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX separation modules, and at least one Antenna Tuning Unit (ATU) and Band Switcher (SW). Note that the structure of at least one of the FEMs 62-68 is as described with reference to FIG.

In the present embodiment, SOC 100 is capable of utilizing at least one of FEMs 62-68 for multiple concurrent wireless communications. For example, a pair of SAW-free transmitters & receivers can be used for WLAN communications and another pair of SAW-free transmitters & receivers can be used for 850 or 900 MHz cellular telephone communications. As another example, a pair of SAW-free transmitters & receivers can be used for cellular voice communications, and another pair of SAW-free transmitters & receivers can be used for cellular data communications. Note that these concurrent wireless communications may be in the same frequency band with different carrier frequencies and/or in different frequency bands.

9 is a schematic block diagram of a portable computing communication device 10 including a system on a chip (SOC) 100 coupled to a front end module (FEM) network 80 via an RF connection 70, in accordance with another embodiment of the present invention. The SOC 100 includes a power management unit 26, a plurality of SAWless receiver sections 18-1-18-2, a plurality of SAWless transmitter sections 20-1-20-2, one or more baseband processing units 22, and may also include Processing module. The RF connection 70 can be at least one of a coaxial cable, an elastic fiber cable, an elastic waveguide, and/or other high frequency cable. The FEM network 80 includes a plurality of FEMs 62-68 (e.g., two or more) and a frequency conversion module. The frequency conversion module 82 includes one or more bypass RF-RF conversion modules. Each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX split modules, at least one antenna tuning unit (ATU), and a band switcher (SW). Note that the structure of at least one of the FEMs 62-68 is as described with reference to FIG.

In the present embodiment, the SOC 100 can utilize at least one of the FEMs 62-68 for multiple concurrent wireless communications, and the carrier frequency of at least one of the wireless communications can be converted by the frequency conversion module 82. For example, a pair of SAW-free transmitters & receivers can be used for WLAN communications and another pair of SAW-free transmitters & receivers can be used for 850 or 900 MHz cellular telephone communications. As another example, a pair of SAW-free transmitters & receivers can be used for cellular voice communications, and another pair of SAW-free transmitters & receivers can be used for cellular data communications. In any of the above examples, the carrier frequency of at least one of the wireless communications can be increased or decreased by the frequency conversion module 82.

10 is a schematic block diagram of a portable computing communication device 10 including a system on a chip (SOC) 110 coupled to a front end module (FEM) network 120 via an RF connection 122, in accordance with another embodiment of the present invention. The SOC 110 includes a power management unit 26, an intermediate frequency (IF)-baseband (BB) receiver unit 112, a BB-IF transmitter unit 114, and a baseband processing unit 22, and may further include a processing module. The RF connection 122 can be at least one of a coaxial cable, an elastic fiber optic cable, an elastic waveguide, and/or other high frequency cable.

FEM network 120 includes a plurality of FEMs 62-68 (e.g., two or more) and a plurality of RF-TF TX and RX pair 124-138. Each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX split modules, at least one antenna tuning unit (ATU), and a band switcher (SW). Each of the TX IF-RF sections 132-138 includes a polarization based topology, a Cartesian based topology, a hybrid polarization-Cartesian based topology or a mixing, filtering & mixing module, respectively. Each of the RX RF-IF sections 124-130 includes a low noise amplifier section and a downconversion section, respectively. Note that the structure of at least one of the FEMs 62-68 is as described with reference to FIG.

In this embodiment, the baseband processing module 22 is based on one or more wireless communication protocols. Convert outbound data to one or more outbound symbol streams. The TX BB-IF unit 114 includes a mixing module that mixes the outbound symbol stream with a transmit IF local oscillation (eg, an oscillation having a frequency of several tens of MHz to several tens of GHz) to generate one or more outputs. Station IF signal.

The SOC 110 provides an outbound IF signal to the FEM network 120 over the RF connection 122. In addition, SOC 110 provides a selection signal indicating which of the pair of RX-TX sections 124-130 and the corresponding FEM 62-68 will support wireless communication. The selected TX IF-RF sections 132-138 mix the IF signal with a second local oscillation (e.g., an RF-IF frequency oscillation) to produce one or more mixed signals. The combining & filtering unit combines the one or more mixed signals and filters them to produce an outbound RF signal for the pre-PA, which will be provided to the corresponding FEM 62-68.

For inbound RF signals, the antenna associated with FEM 62-68 receives the signal and provides it to a Band Switcher (SW) (if included) or to the ATU (if no switch is included). The FEM 62-68 processes the inbound RF signals in the manner described above and provides the processed inbound RF signals to the respective RX RF-IF portions 124-130. The RX RF-IF section 124-130 mixes the inbound RF signal with a second RX local oscillation (eg, RF-IF frequency oscillation) to produce one or more inbound IF mixing signals (eg, I and Q mixing) The signal component or a polarization format signal at IF (eg A(t)cos(ω _IF (t) + Φ(t)).

The RX IF-BB portion 112 of the SOC 110 receives one or more inbound IF mixing signals and converts them into one or more inbound symbol streams. The baseband processing module 22 converts one or more inbound symbol streams into inbound data. Note that SOC 110 may include multiple RX IF-BB and TX BB-IF sections to support multiple concurrent wireless communications.

11 is a schematic block diagram of a portable computing communication device 10 including a system on chip (SOC) 140 coupled to a front end module (FEM) network 142 via RF connections 152-154, in accordance with another embodiment of the present invention. The SOC 140 includes a power management unit 26, an intermediate frequency (IF)-baseband (BB) receiver unit 144, a BB-IF transmitter unit 146, and a baseband processing unit 22, and may further include a processing module. The RF connections 152-154 may be at least one of a coaxial cable, an elastic fiber cable, an elastic waveguide, and/or other high frequency cable.

FEM network 142 includes a plurality of FEMs 62-68 (e.g., two or more) and a pair of RF-IF TX and RX sections 148-150. Each of the FEMs 62-68 includes a plurality of power amplifier modules (PAs), a plurality of RX-TX split modules, at least one antenna tuning unit (ATU), and a band switcher (SW). The TX IF-RF section 150 includes a polarization based topology, a Cartesian based topology, a hybrid polarization-Cartesian based topology or a mixing, filtering & mixing module. The RX RF-IF section 148 includes a low noise amplifier section and a downconversion section. Note that the structure of at least one of the FEMs 62-68 is as described with reference to FIG.

In the present embodiment, baseband processing module 22 converts outbound data into one or more outbound symbol streams in accordance with one or more wireless communication protocols. The TX BB-IF unit 146 includes a mixing module that mixes the outbound symbol stream with a transmitted IF local oscillation (eg, an oscillation having a frequency of several tens of MHz to several tens of GHz) to generate one or more outputs. Station IF signal.

The SOC 140 provides an outbound IF signal to the FEM network 142 over the RF connections 152-154. The TX IF-RF section 150 mixes the IF signal with a second local oscillation (e.g., an RF-IF frequency oscillation) to produce one or more mixed signals. The combining & filtering unit combines the one or more mixed signals and filters them to produce an outbound RF signal for the pre-PA, which will be provided to the corresponding FEM 62-68.

For inbound RF signals, the antenna associated with FEM 62-68 receives the signal and provides it to a Band Switcher (SW) (if included) or to the ATU (if no switch is included). The FEM 62-68 processes the inbound RF signal and provides the processed inbound RF signal to the RX RF-IF portion 148 in the manner described above. The RX RF-IF section 148 mixes the inbound RF signal with a second RX local oscillation (e.g., RF-IF frequency oscillation) to produce one or more inbound IF mixing signals (e.g., I and Q mixing signal components). Or a polarization format signal at IF (eg A(t)cos(ω _IF (t) + Φ(t)).

The RX IF-BB portion 144 of the SOC 140 receives one or more inbound IF mixing signals and converts them into one or more inbound symbol streams. The baseband processing module 22 converts one or more inbound symbol streams into inbound data. Note that the SOC 140 may include a plurality of RX IF-BB 144 and TX BB-IF sections 146 to support multiple concurrent wireless communications. letter.

12 is a schematic block diagram of a portable computing communication device 10 including a system on a chip (SOC) 160 coupled to a front end module (FEM) network 162 via an RF connection 176, in accordance with another embodiment of the present invention. The SOC 160 includes a power management unit 26, a no-SAW receiver (RX) downconversion unit 164, a SAW-free (TX) upconversion unit 166, and a baseband processing unit 22, and may further include a processing module. The RF connection 176 can be at least one of a coaxial cable, an elastic fiber optic cable, an elastic waveguide, and/or other high frequency cable.

FEM network 162 includes a plurality of FEMs 168-174 (e.g., two or more) and a pair of RF-IF TX and RX sections. Each of the FEM 168-174 includes a plurality of power amplifier drivers (PADs), a plurality of low noise amplifiers (LNAs), a plurality of power amplifier modules (PAs), a plurality of RX-TX separation modules, and at least one antenna. Tuning unit (ATU) and band switcher (SW). Note that the structure of at least one of the FEMs 168-174 is as described with reference to FIG.

In the present embodiment, baseband processing module 22 converts outbound data into one or more outbound symbol streams in accordance with one or more wireless communication protocols. The no-SAW TX upconverter 166 converts the outbound symbol stream into one or more outbound upconverted signals, and the no SAW TX upconverter 166 can be implemented similar to the no SAW TX upconverter 166 lacking the power amplifier driver.

The SOC 160 provides an outbound upconverted signal to the FEM network 162 via the RF connection 176. The SOC 160 may also provide an FEM selection signal to the FEM network 162. The selected FEM module receives the out-of-station upconverted signal through a power amplifier driver (PAD). The PAD amplifies the outbound upconverted signal to produce an outbound RF signal of the pre-PA, which is then processed by the FEM 168-174 in the manner described above and/or as will be described with reference to at least one of the following figures.

For inbound RF signals, the antenna associated with FEM 168-174 receives the signal and provides it to a Band Switcher (SW) (if included) or to the ATU (if no switch is included). The ATU and RX-TX split modules process the inbound RF signal in the manner described above and provide the processed inbound RF signal to the LNA. The LNA amplifies the inbound RF signal to Generate an amplified inbound RF signal.

The no SAW RX portion 164 (similar to the SAW receiver portion implementation lacking the LNA) receives one or more amplified inbound IF mixing signals and converts them into one or more inbound symbol streams. The baseband processing module 22 converts one or more inbound symbol streams into inbound data. Note that the baseband processing unit 22 and/or the processing module can provide control signals to the LNAs and/or PADs of each FEM 168-174 to adjust its performance (eg, gain, linearity, bandwidth, efficiency, noise, output dynamics). Range, slew rate, rate of rise, settling time, overshoot, stability factor, etc.).

13 is a schematic block diagram of a portable computing communication device including a system on a chip (SOC) 180 coupled to a front end module (FEM) 182, in accordance with another embodiment of the present invention. The SOC 180 includes a plurality of SAW-free receiver sections (only the LNA and variable frequency bandpass filters (FTBPF) of the receiver section are shown), and a plurality of SAW-free transmitter sections (only the power amplifier driver (PAD) is shown) , a processing module, a baseband processing module (not shown or included in the processing module), and a power management unit (not shown).

The FEM 182 includes a low band (LB) path, a high band (HB) path, and a band switcher (FB SW). The LB path includes a power amplifier module (PA), a low-band impedance stage (LB Z), a low-band low-pass filter (LB LPF), a switch (SW), and a transmit-receive separation module (TX-RX ISO) ( For example, a duplexer), a second switch (SW), and an antenna tuning unit (ATU). The HB path includes a power amplifier module (PA), a high-band impedance stage (HBZ), a high-band low-pass filter (HB LPF), a switch (SW), and a transmit-receive separation module (TX-RX ISO) (for example) A duplexer), a second switch (SW), and an antenna tuning unit (ATU). Note that low-band paths can be used to support low-band GSM, EDGE, and/or WCDMA wireless communications, and high-band paths can be used to support high-bandwidth GSM, EDGE, and/or WCDMA wireless communications.

As described above and/or as will be described with reference to at least one of the following figures, SOC 180 is used to output an outbound RF signal of a pre-PA and for inputting an inbound RF signal. The FEM 182 receives the outbound RF signals of the pre-PA through the LB path or the HB path and amplifies them through the corresponding PA modules. Impedance level (LB Z or HB Z) in PA mode The desired load is provided on the output of the group and is connected to a low pass filter (LB LPF or HB LPF). The LPF filters the outbound RF signal, and the outbound RF signal is provided to the TX-RX ISO module or ATU according to the configuration of the switch (SW). If the switch connects the LPF to the TX-RX ISO module, the TX-RX module attenuates the outbound RF signals before providing them to the ATU. The functions of the ATU are as described above and/or will be described with reference to at least one of the following figures.

Note that there are no discrete components between SOC 180 and FEM 182. In particular, portable computing communication devices do not require the discrete SAW filters necessary in existing cellular telephone embodiments. At least one of the following contributes to the elimination of SAW filters and/or other conventional external components: the structure without the SAW receiver, the structure without the SAW transmitter, and/or the programmability of the various components of the FEM 182.

14 is a schematic block diagram of a portable computing communication device including a system on a chip (SOC) 190 coupled to a front end module (FEM) 192, in accordance with another embodiment of the present invention. The SOC 190 includes a plurality of SAW-free receiver sections (only the LNA and variable frequency bandpass filters (FTBPF) of the receiver section are shown), and a plurality of SAW-free transmitter sections (only the power amplifier driver (PAD) is shown) , a processing module, a baseband processing module (not shown or included in the processing module), and a power management unit (not shown).

The FEM 192 includes a low band (LB) path, a high band (HB) path, and a band switcher (FB SW). The LB path includes a power amplifier module (PA), a low-band impedance stage (LB Z), a switch (SW), a low-band low-pass filter (LB LPF), and a transmit-receive separation module (TX-RX ISO) ( For example, a duplexer), a second switch (SW), and an antenna tuning unit (ATU). The HB path includes a power amplifier module (PA), a high-band impedance stage (HBZ), a switch (SW), a high-band low-pass filter (HB LPF), and a transmit-receive separation module (TX-RX ISO) (for example) A duplexer), a second switch (SW), and an antenna tuning unit (ATU). Note that low-band paths can be used to support low-band GSM, EDGE, and/or WCDMA wireless communications, and high-band paths can be used to support high-bandwidth GSM, EDGE, and/or WCDMA wireless communications.

In various embodiments of SOC 190, frequency conversion in the receiver portion of SOC 190 The bandpass filter provides an image signal that adequately filters out-out blockers and filters that have a non-negligible effect on the desired signal. This will reduce the dynamic range requirement of the analog-to-digital converter (ADC) of the receiver section (the input of the baseband processing module or the input of the RX BB-IF section). The superheterodyne structure of the receiver section facilitates reduction of power consumption and deadband compared to a comparable direction conversion receiver section.

15 is a schematic block diagram of an RF-IF receiver portion 204 of a SOC 200 including a FEM module (including a transformer T1, a tunable capacitor network C1, and/or a low noise amplifier module, in accordance with an embodiment of the present invention). (LNA) 206), mixing module 208, mixing register 210-212, variable frequency bandpass filter (FTBPF) circuit module (including FTBPF 222 and/or other registers 214-220), and receiver IF-BB section 224. The SOC 200 also includes a SAW-free transmitter portion 202 and may also include a baseband processing unit, a processing module, and a power management unit.

In an operational example, an inbound RF signal is received through an antenna. The inbound RF signal includes the desired signal component of the RF and the undesired component of the frequency above or below the RF (the component above is shown). Regarding the local oscillation of the RF-IF section 204 (e.g., f _LO ), if the signal is at r _RF -2f _IF , an image signal appears. Note that the RF used here and throughout the text includes frequencies in the radio band up to 3 GHz and frequencies in the 3 GHz-300 GHz millimeter wave (or microwave) band.

The antenna provides an inbound RF signal to the FEM that processes the RF signal in the manner described above and/or as will be described with reference to at least one of the following figures. Transformer T1 receives the FEM processed inbound RF signal and converts it into a differential signal, and a tunable capacitor network C1 (eg, a plurality of series connected switches and capacitors, wherein the plurality of parallel connections) filters the differential signal. The tunable capacitor network C1 receives control signals from the baseband processing unit and/or processing module (eg, SOC processing resources) to enable the required capacitance.

A low noise amplifier module (LNA) 206 comprising one or more low noise amplifiers connected in series and/or in parallel amplifies the inbound RF signal to produce an amplified inbound RF signal number. The LNA 206 can receive a control signal from the SOC processing resource, wherein the control signal indicates a setting of at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, swing rate, rise rate, settling time, overshoot Quantity and stability factor.

The mixing module 208 receives the amplified inbound RF signal and converts it into an in-phase (I) signal component and a quadrature (Q) signal using a conversion module (eg, a π/2 phase shifter or other type of phase control circuit). Component. A mixer of the mixing module 208 mixes the I signal component with an I signal component of a local oscillation (eg, fLO) to produce an I-mixed signal, and another mixer combines the Q signal component with the local oscillation. The Q signal components are mixed to produce a Q-mixed signal. Note that the mixer of the mixing module 208 can be a balanced mixer, a double balanced mixer, a passive switching mixer, a Gilbert cell mixer or other types of two sines, respectively. A circuit that multiplies signals and produces "frequency and" signal components and "frequency difference" signal components. Also note that the I and Q mixed signals can be differential or single-ended signals; differential signals are shown.

The mixing registers 210-212 filter and/or buffer the I and Q mixed signals, which are then provided to the FTBPF structures (e.g., registers 214-220 and variable frequency bandpass filters (FTBPF) 222). Note that the I and Q mixed signals respectively include desired signal components in the form of IF, and may also include image signal components in the form of IF. It is also noted that the mixing module 208 and/or the mixing registers 210-212 may include filtering to attenuate unwanted signal components such that they have little effect on the IF signal components.

FTBPF 222 (various embodiments will be described with reference to the following figures) filters the IF signal by attenuating the mirrored IF signal component and by substantially unattenuating the desired IF signal component. For example, suppose the FTBPF transforms the narrowband baseband bandpass filter response frequency into an IF (eg, RF-LO) filter response. For this example, it is also assumed that RF is 2 GHz, LO2 is 1900 GHz, and RF _image is 1800 GHz. Based on these assumptions, the mixing module 208 will generate an I-mixed signal and a Q-mixed signal, the resulting signal being a combination of the desired signal and the image signal. In a simplified manner, the I-mixed signal (for example, cos(RF)*cos(LO2)) includes 1/2cos(2000-1900)+1/2cos(2000+1900) of the desired signal component and 1/ of the image signal component. 2cos(1800-1900)+1/2cos(1800+1900), Q-mixed signal (eg sin(RF)*sin(LO)) including 1/2cos(2000-1900)-1/2cos of the desired signal component (2000+1900) and 1/2cos(1800-1900)-1/2cos(1800+1900) of the image signal component. Note that the frequency component of 2000+1900 is filtered by the register after the mixer.

The narrow band of the FTBPF filters out the image frequency (1800-1900) and the undesired signal component, leaving the component of the desired signal component at a frequency of (2000-1900). Specifically, 1/2 cos (2000-1900) of the I-mixed signal and 1/2 cos (2000-1900) from the Q-mixed signal are left. The FTBPF 222 uses these two inputs to achieve addition of the terms of the desired signal component (eg, 1/2cos(2000-1900) + 1/2cos(2000-1900)=cos(2000-1900)), and implements the image signal component. Addition of terms (eg 1/2cos(1800-1900)-1/2cos(1800-1900)=0 (ideally)). Therefore, the image signal component is attenuated while the signal component is expected to pass substantially without attenuation.

To enhance the filtering of the FTBPF 222, it can receive one or more control signals from the SOC processing resources. The control signal can cause the FTBPF 222 to adjust the center frequency of the baseband filter response (changing the center frequency of the high Q IF filter) to change the quality factor of the filter to change the gain to change the bandwidth and the like.

The receiver IF-BB section 224 includes a mixing section and a combining & filtering section. The mixing section mixes the inbound IF signal with the second local oscillation to produce a combined I and Q signal. The combining & filtering section combines the I and Q mixed signals to produce a combined signal, which is then filtered to produce one or more inbound symbol streams.

Although the currently shown RF-IF section 204 is connected to a single antenna for SISO (Single Input Single Output) communication, the scheme can also be applied to MISO (Multiple Input Single Output) communication and MIMO (Multiple Input Multiple Output) communication. . In these cases, multiple antennas (eg, 2 or more) are connected to a corresponding number of FEMs (or a smaller number of FEMs according to the receive path in the FEM). The FEM is connected to a plurality of receiver RF-IF sections (for example, the same number of antennas), and these receiver RF-IF sections are associated with a corresponding number of receivers IF-BB sections. 224 connections. The baseband processing unit processes the plurality of symbol streams described above to generate inbound data.

The RX RF-IF section 204 has at least one of the following advantages and/or includes at least one of the following features: the superheterodyne receiver structure is superior to the corresponding direct conversion receiver in terms of deadband and power consumption; using complex baseband impedance in the FTBPF 222 Bandpass filter center frequency frequency shift, thereby enabling the center frequency of the on-chip high Q image band rejection filter to be tuned to the desired frequency; and only the signal local oscillator is required, which can be used for downconverting mixers and FTBPF 222 .

16 is a schematic block diagram of an RF-IF receiver portion 232 of a SOC 230 including an FEM interface module (including a transformer T1 and/or a tunable capacitor network C1), a variable frequency bandpass, in accordance with another embodiment of the present invention. Filter (FTBPF) 234, low noise amplifier module (LNA) 206, mixing section (including mixing module 208 and/or mixing buffer 210-212). The SOC 230 also includes a receiver IF-BB section 224, a SAW-free transmitter section 202, and may also include a baseband processing unit, a processing module, and/or a power management unit.

In an operational example, an inbound RF signal is received through an antenna. The inbound RF signal includes the desired signal component of the RF and the undesired component of the frequency above or below the RF (the component above is shown). Regarding the local oscillation of the RF-IF section 232 (for example, f _LO ), if the signal is at r _RF -2f _IF , an image signal appears. The antenna provides an inbound RF signal to the FEM that processes the RF signal in the manner described above and/or as will be described with reference to at least one of the following figures. The transformer T1 receives the FEM-processed inbound RF signal and converts it into a differential signal, and the tunable capacitor network C1 filters the differential signal based on a control signal from the SOC processing resource.

The FTBPF 234 (various embodiments will be described with reference to the following figures) filters the inbound RF signal by attenuating the image signal component and the undesired signal component and by the substantially un-attenuated desired RF signal component. For example, assume that the FTBPF converts the narrowband baseband bandpass filter response to RF (eg, the carrier frequency of the desired signal component) to produce a high Q RF filter response. The narrowband high Q RF filter filters out the image signal component and the undesired signal component and passes through the substantially un-attenuated desired signal component.

A low noise amplifier module (LNA) 206 amplifies the desired inbound RF signal component to produce an amplified desired inbound RF signal. The LNA 206 can receive a control signal from the SOC 230 processing resource, wherein the control signal indicates a setting of at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, swing rate, rise rate, settling time, super Adjustment and stability factor.

Mixing module 208 receives the amplified inbound RF signal and converts it into an in-phase (I) signal component and a quadrature (Q) signal component using a π/2 phase shifter or other type of phase control circuit. A mixer of the mixing module 208 mixes the I signal component with an I signal component of a local oscillation (eg, fLO) to produce an I-mixed signal, and another mixer combines the Q signal component with the local oscillation. The Q signal components are mixed to produce a Q-mixed signal. Note that the I and Q mixed signals can be differential or single-ended signals; differential signals are shown.

The mixing buffer buffers the I and Q mixed signals, which are then provided to a filter (eg, a bandpass filter). Filters 236 and 238 filter the I and Q mixed signals, respectively, which are then provided to RX IF-BB section 224.

The receiver IF-BB section 224 includes a mixing section and a combining & filtering section. The mixing section mixes the inbound IF signal with the second local oscillation to produce a combined I and Q signal. The combining & filtering section combines the I and Q mixed signals to produce a combined signal, which is then filtered to produce one or more inbound symbol streams.

Although the currently shown RF-IF section 232 is connected to a single antenna for SISO (Single Input Single Output) communication, the scheme can also be applied to MISO (Multiple Input Single Output) communication and MIMO (Multiple Input Multiple Output) communication. . In these cases, multiple antennas (eg, 2 or more) are connected to a corresponding number of FEMs (or a smaller number of FEMs according to the receive path in the FEM). The FEM is connected to a plurality of receiver RF-IF sections (e.g., the same number of antennas), which in turn are coupled to a corresponding number of receiver IF-BB sections 224. The baseband processing unit processes the plurality of symbol streams described above to generate inbound data.

17 is a schematic block diagram of an RF-IF receiver portion 242 of a SOC 240 including a front end module interface (including a transformer T1 and/or may be included in accordance with another embodiment of the present invention). Capacitor Network C1), a pair of inverter-based low noise amplifier modules (LNA) 244-246, mixing module 248, and a pair of transimpedance amplifier modules (including transimpedance amplifiers, respectively) TIA) 250-252, impedance (Z) 254-256 and/or register 258-260). The SOC 240 also includes a receiver IF-BB section 224, a SAW-free transmitter section 202, and may also include a baseband processing unit, a processing module, and a power management unit.

In an operational example, an inbound RF signal is received through an antenna. The inbound RF signal includes the desired signal component of the RF and the undesired component of the frequency above or below the RF (the component above is shown). Regarding the local oscillation of the RF-IF section 204 (e.g., f _LO ), if the signal is at r _RF -2f _IF , an image signal appears. The antenna provides an inbound RF signal to the FEM that processes the RF signal in the manner described above and/or as will be described with reference to at least one of the following figures. Transformer T1 receives the FEM processed inbound RF signal and converts it into a differential signal, and tunable capacitor network C1 filters the differential signal based on control signals from SOC 240 processing resources.

The first LNA 244 amplifies the positive leg of the inbound RF signal to produce a positive leg current RF signal, and the second LNA 246 amplifies the negative term of the inbound RF signal to produce a negative term RF signal. The LNAs 244-246 can receive control signals from the SOC 240 processing resources, respectively, wherein the control signals indicate settings for at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, swing rate, rate of rise, establishment Time, overshoot and stability factor.

The mixing module 248 receives the positive current RF signal and the negative current RF signal and converts them into an in-phase (I) current signal and a quadrature (Q) current using a π/2 phase shifter or other type of phase control circuit. signal. The mixer of the mixing module 248 mixes the I current signal with a local current (eg, fLO) I current signal to generate an I-mixed current signal (eg, i _BB-1 ), and the Q current is The locally oscillating Q current signal is mixed to produce a Q mixed current signal (eg, i _BB-Q ). Note that the current signals mixed by I and Q can be differential signals or single-ended signals; differential signals are shown. It is also noted that the current signals of the I and Q mixing include an image component and a desired component, respectively.

TIA 250-252 (one or more of its embodiments will be described with reference to at least one of the following figures) receives I and Q mixed current signals and converts them to voltages by impedance (z) such that the resulting I and The Q voltage mixed signal has an attenuated image component and a substantially un-attenuated desired component. The combination of TIA 250-252 and impedance (z) provides a low impedance path between their input and reference potential (eg, Vdd or ground) for frequencies below IF and provides a higher frequency than IF. A low impedance path between their respective inputs. For frequencies close to IF, TIA 250-252 amplifies them and converts them into voltage signals. The register provides the I and Q voltage signal components to the RX IF-BB section 224, which converts them into an inbound symbol stream.

The RX RF-IF portion 224 provides at least one of the following advantages and/or includes at least one of the following features: a superheterodyne receiver structure that is superior to a corresponding direct conversion receiver in terms of deadband and power consumption; and substantially eliminates superheterodyne The offset and flicker noise problems that exist in the receiver.

18 is a schematic block diagram of an RF-IF receiver portion 271 of a SOC 270 including an FEM interface module (including a transformer T1 and/or a tunable capacitor network C1), an RF frequency conversion band, in accordance with another embodiment of the present invention. Pass filter (FTBPF) 272, a pair of inverter-based low noise amplifier module (LNA) 274-276, mixing module 278, and a pair of transimpedance amplifier modules (including transimpedance amplifiers, respectively) (TIA) 280-282, impedance (Z) 284-286 and/or scratchpad 280-286) and IF FTBPF 288. The SOC 270 also includes a receiver IF-BB section 224, a SAW-free transmitter section 202, and may also include a baseband processing unit, a processing module, and a power management unit.

In the present embodiment, the function of the RF FTBPF 272 is as described with reference to FIG. 16, and the functions of the TIA 280-282 are as described with reference to FIG. The IF FTBPF 288 is synchronized to the RF clock and its center frequency is RF. The bandwidth of the IF FTBPF 288 is such that the image signal is substantially attenuated and the desired signal component is passed substantially un-attenuated. Therefore, the image signal is filtered three times: by RF FTBPF 272, by TIA 280-282 and then by IF FTBPF 288.

The RX RF-IF section 271 provides at least one of the following advantages and/or includes at least one of the following Features: Two clocks (such as RF and LO2) are used; the superheterodyne receiver structure outperforms the corresponding direct conversion receiver in terms of deadband and power consumption; flicker noise is not important, so the baseband circuit can It is small; non-inductive LNA 274-276 can be used (for example, LNA can be implemented as an inverter); no DC offset occurs, thus eliminating the large offset cancellation circuit; the receiver structure is comparable Conversion receiver frequency planning flexibility; includes advanced bandpass filtering stages across the RX chain; and can be easily integrated into the SOC 270.

19 is a schematic block diagram of an RF-IF receiver portion 292 of a SOC 290 including an FEM interface module (including a transformer T1 and/or a tunable capacitor network C1), an RF variable frequency band, in accordance with another embodiment of the present invention. Pass filter (FTBPF) 272, a pair of inverter-based low noise amplifier module (LNA) 274-276, mixing module 278, and a pair of transimpedance amplifier modules (including transimpedance amplifiers, respectively) (TIA) 280-282, impedance (Z) 284-286 and/or scratchpad 280-286) and IF FTBPF 294. The SOC 290 also includes a receiver IF-BB section 224, a SAW-free transmitter section 202, and may also include a baseband processing unit, a processing module, and a power management unit.

In the present embodiment, the function of the IF FTBPF 294 is as described with reference to FIG. 15, and the function of the TIA is as described with reference to FIG. The RF FTBPF 272 is synchronized to the LO clock and its center frequency is at IF. The bandwidth of the RF FTBPF 272 is such that the image signal is substantially attenuated and the desired signal component is passed substantially un-attenuated. Therefore, the image signal is filtered three times: by RF FTBPF 272, by TIA 280-282 and then by IF FTBPF 294.

The RX RF-IF portion 292 provides at least one of the following advantages and/or includes at least one of the following features: using one clock (e.g., LO2); the superheterodyne receiver structure is superior to the corresponding direct conversion receiver in terms of deadband and power consumption; Flicker noise is not important, so the baseband circuitry can be small; non-inductive LNA 274-276 can be used (for example, LNA can be implemented as an inverter); no DC offset occurs, thus eliminating large footprint offsets Elimination of circuitry; receiver architecture with frequency planning flexibility comparable to direct conversion receivers; includes advanced bandpass filtering stages across RX chains; and can be easily integrated Into SOC 290.

20 is a schematic block diagram of a dual band RF-IF receiver section 302 of a SOC 300 including a FEM interface module (including transformer T1 and/or tunable capacitor network C1), frequency conversion, in accordance with another embodiment of the present invention. Bandpass filter (FTBPF) 304, a pair of low noise amplifier modules (LNA) 306-308, and a mixing section (including a pair of mixing modules 310-312, mixing registers 314-320, and/or Filters 322-328). The SOC 300 also includes a receiver IF-BB section 224, a SAW-free transmitter section 202, and may also include a baseband processing unit, a processing module, and/or a power management unit.

In an operational example, an inbound RF signal is received through an antenna. The inbound RF signal includes one or more desired signal components (eg, one at f _RF1 and the other at f _RF2 ) and an undesired component at a frequency above or below RF (showing a higher component). Regarding the local oscillation of the RF-IF section (one for the first desired RF signal and the other for the second desired RF signal -f _LO1 and f _LO2 ), if the signal is at r _RF1 -2f _IF1 and / or at r _RF2 - 2f _IF2 , one or more image signal components will appear. The antenna provides an inbound RF signal to the FEM that processes the RF signal in the manner described above and/or as will be described with reference to at least one of the following figures. The transformer T1 receives the FEM-processed inbound RF signal and converts it into a differential signal, and the tunable capacitor network C1 filters the differential signal based on a control signal from the SOC processing resource.

FTBPF 304 (various embodiments will be described with reference to the following figures) filters the inbound RF signal by attenuating the image signal component and the undesired signal component and by the substantially un-attenuated desired RF signal component. For example, assume that the FTBPF converts the narrowband baseband bandpass filter to RF1 and RF2 (eg, the carrier frequency of the desired signal component) to produce two high Q RF filters. The narrowband high Q RF filter filters out the image signal component and the undesired signal component, respectively, and passes through the substantially un-attenuated desired signal component.

The first low noise amplifier module (LNA) amplifies the desired inbound RF1 signal component (when included in the inbound RF signal) to produce an amplified desired inbound RF1 signal, the second low noise amplifier module (LNA) Amplify the desired inbound RF2 signal component (when inbound RF The signal is included in the signal to produce an amplified desired inbound RF2 signal. Each LNA can receive a control signal from the SOC processing resource, wherein the control signal indicates setting of at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, swing rate, rising rate, setup time, Overshoot and stability factor.

The first mixing module of the mixing section receives the amplified desired inbound RF1 signal and converts it into an in-phase (I) signal component and a quadrature (Q) signal using a π/2 phase shifter or other type of phase control circuit. Component. The mixer of the first mixing module mixes the I signal component with the I signal component of the local oscillation (eg, f _LO1 ) to generate a first I-mixed signal, and the Q signal component and the local oscillator The Q signal components are mixed to produce a first Q mixed signal. Note that the first I and Q mixed signals can be differential signals or single-ended signals; differential signals are shown.

The second mixing module of the mixing section receives the amplified desired inbound RF2 signal and converts it into an in-phase (I) signal component and a quadrature (Q) signal using a π/2 phase shifter or other type of phase control circuit. Component. The mixer of the second mixing module mixes the I signal component with the I signal component of the local oscillation (eg, f _LO2 ) to generate a second I-mixed signal, and the Q signal component and the local oscillator The Q signal components are mixed to produce a second Q mixed signal. Note that the second I and Q mixed signals can be differential signals or single-ended signals; differential signals are shown. Each mixer buffers their respective I and Q mixed signals, which are then provided to a filter (eg, a bandpass filter). The filter filters the I and Q mixed signals, which are then provided to the RX IF-BB section 224.

Although the currently shown RF-IF section 302 is connected to a single antenna for SISO (Single Input Single Output) communication, the scheme can also be applied to MISO (Multiple Input Single Output) communication and MIMO (Multiple Input Multiple Output) communication. . In these cases, multiple antennas (eg, 2 or more) are connected to a corresponding number of FEMs (or a smaller number of FEMs according to the receive path in the FEM). The FEM is connected to a plurality of receiver RF-IF sections (e.g., the same number of antennas), which in turn are coupled to a corresponding number of receiver IF-BB sections. The baseband processing unit processes the plurality of symbol streams described above to generate inbound data.

The RX RF-IF section 302 provides at least one of the following advantages and/or includes at least one of the following features: using one clock (e.g., LO2); being able to receive two inbound RF signals with a single RF input; no need for two external SAWs A filter, an FTBPF 304 effectively filters two channels (eg, RF1 and RF2 signals); the center frequencies of the two high QRF filters are controlled by the local oscillator clock; and can be easily integrated into the SOC 300.

21 is a schematic block diagram of an RF-IF receiver portion 332 of a SOC 330 including an FEM interface module (including a transformer T1 and/or a tunable capacitor network C1) with frequency conversion, in accordance with another embodiment of the present invention. Low noise amplifier module (LNA) 336 of bandpass filter (FTBPF) 338, RF variable frequency bandpass filter (FTBPF) 334 with negative resistance, and mixing section (including mixing module 340, mixing temporary storage) 342-344 and/or filters 346-348). The SOC 330 also includes a receiver IF-BB section 224, a SAW-free transmitter section 202, and may also include a baseband processing unit, a processing module, and/or a power management unit.

In the present embodiment, the parasitic resistance (Rp) shown is associated with the FEM interface module to represent switching losses (eg, FTBPF) and/or inductance losses. The inductance loss is mainly due to the ohmic resistance of the transformer coil (such as the metal wire on the substrate) and/or the substrate loss under the transformer. Due to the tuning of the capacitor C1, the inductance loss is the main component of the RF segment impedance. A lower parasitic resistance will reduce the quality factor of the filter and reduce the out-of-band attenuation of frequencies other than RF. The negative resistance in FTBPF 334 effectively increases the parasitic resistance, which increases the quality factor and out-of-band attenuation.

In an operational example, an inbound RF signal is received through an antenna. The inbound RF signal includes the desired signal component of the RF and the undesired component of the frequency above or below the RF (the component above is shown). Regarding the local oscillation of the RF-IF section 332 (e.g., f _LO ), if the signal is at r _RF -2f _IF , an image signal component appears. The antenna provides an inbound RF signal to the FEM that processes the RF signal in the manner described above and/or as will be described with reference to at least one of the following figures. Transformer T1 receives the FEM processed inbound RF signal and converts it into a differential signal, and tunable capacitor network C1 filters the differential signal based on control signals from SOC 330 processing resources.

FTBPF 334 (various embodiments will be described with reference to the following figures) filters the inbound RF signal by attenuating the image signal component and the undesired signal component and by the substantially un-attenuated desired RF signal component. For example, assume that FTBPF 334 converts a narrowband baseband bandpass filter to RF (eg, the carrier frequency of a desired signal component) to produce a high QRF filter. The narrowband high QRF filter filters out the image signal component and the undesired signal component, respectively, and passes through the substantially un-attenuated desired signal component. In addition, FTBPF 334 includes a negative resistance that is similar to parasitic resistance (Rp) and compensates for losses represented by parasitic resistance (eg, effectively increasing the quality factor of the filter and increasing the out-of-band attenuation). The negative resistance can be dynamically adjusted based on the change in parasitic resistance by a control signal from the SOC 330 processing resource.

A low noise amplifier module (LNA) 336 amplifies the desired inbound RF signal component to produce an amplified desired inbound RF signal. The LNA 336 can receive a control signal from the SOC 330 processing resource, wherein the control signal indicates a setting of at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, swing rate, rise rate, settling time, overshoot Quantity and stability factor. Additionally, the LNA 336 can include an RF FTBPF 338 that functions similarly to the RF FTBPF 334 described above to further attenuate the image signal component. Mixing module 340 receives the amplified desired inbound RF signal and converts it into an in-phase (I) signal component and a quadrature (Q) signal component using a π/2 phase shifter or other type of phase control circuit.

The mixer of the mixing module 340 mixes the I signal component with the I signal component of the local oscillation (eg, f _LO ) to generate an I-mixed signal, and combines the Q signal component with the Q-signal component of the local oscillation. Mixing to produce a Q-mixed signal. Note that the I and Q mixed signals can be differential or single-ended signals; differential signals are shown.

The mixing buffer buffers the I and Q mixed signals, which are then provided to a filter (eg, a bandpass filter). The filter filters the I and Q mixed signals, which are then provided to the RX IF-BB section 224.

Although the currently shown RF-IF section 332 is used for SISO (single input single output) The single antenna connection of the letter, but the scheme can also be applied to MISO (Multiple Input Single Output) communication and MIMO (Multiple Input Multiple Output) communication. In these cases, multiple antennas (eg, 2 or more) are connected to a corresponding number of FEMs (or a smaller number of FEMs according to the receive path in the FEM). The FEM is connected to a plurality of receiver RF-IF sections (e.g., the same number of antennas), which in turn are coupled to a corresponding number of receiver IF-BB sections. The baseband processing unit processes the plurality of symbol streams described above to generate inbound data.

The RX RF-IF portion 332 provides at least one of the following advantages and/or includes at least one of the following features: an off-chip SAW filter and matching elements are no longer needed; a negative resistance increases the quality factor of the FTBPF 334; the inductance loss can be compensated, so the inductance has Lower tolerances; reduced need for a thick metal layer, thereby reducing die manufacturing costs; the center frequencies of the two high Q RF filters are controlled by the local oscillator clock; and can be easily integrated into the SOC 330.

22 is a schematic block diagram of an RF-IF receiver portion 352 of a SOC 350 including an FEM interface module (including a transformer T1 and/or a tunable capacitor network C1) having a complex baseband in accordance with another embodiment of the present invention. (BB) Impedance variable frequency bandpass filter (FTBPF) 354, low noise amplifier module (LNA) 356, and mixing section (including mixing module 340 and/or mixing buffer 342-344). The SOC 350 also includes a receiver IF-BB section 224, a SAW-free transmitter section 202, and may also include a baseband processing unit, a processing module, and/or a power management unit.

In an operational example, an inbound RF signal is received through an antenna. The inbound RF signal includes the desired signal component of the RF and the undesired component of the frequency above or below the RF (the component above is shown). Regarding the local oscillation of the RF-IF section 332 (e.g., f _LO ), if the signal is at R _RF -2f _IF , an image signal component appears. The antenna provides an inbound RF signal to the FEM that processes the RF signal in the manner described above and/or as will be described with reference to at least one of the following figures. Transformer T1 receives the FEM processed inbound RF signal and converts it into a differential signal, and tunable capacitor network C1 filters the differential signal based on control signals from SOC 350 processing resources.

FTBPF 354 (various embodiments will be described with reference to the following figures) The image signal component and the undesired signal component are attenuated and the inbound RF signal is filtered by the substantially un-attenuated desired RF signal component. For example, assume that FTBPF 354 converts a narrowband baseband bandpass filter to RF (eg, the carrier frequency of a desired signal component) to produce a high QRF filter. The narrowband high QRF filter filters out the image signal component and the undesired signal component, respectively, and passes through the substantially un-attenuated desired signal component. The center frequency of the narrowband baseband BPF can be adjusted by the use of the complex baseband impedance 354. For example, depending on the adjustment of the complex BB impedance 354, the band pass region can be made higher or lower in frequency.

A low noise amplifier module (LNA) 356 amplifies the desired inbound RF signal component to produce an amplified desired inbound RF signal. The LNA 356 can receive a control signal from the SOC 350 processing resource, wherein the control signal indicates a setting of at least one of: gain, linearity, bandwidth, efficiency, noise, output dynamic range, swing rate, rise rate, settling time, super Adjustment and stability factor.

The mixing module 340 of the mixing section receives the amplified desired inbound RF signal and converts it into an in-phase (I) signal component and a quadrature (Q) signal component using a π/2 phase shifter or other type of phase control circuit. . The mixer of the mixing module 340 mixes the I signal component with the I signal component of the local oscillation (eg, f _LO ) to generate an I-mixed signal, and combines the Q signal component with the Q-signal component of the local oscillation. Mixing to produce a Q-mixed signal. Note that the I and Q mixed signals can be differential or single-ended signals; differential signals are shown.

Mixing registers 342-344 buffer the I and Q mixed signals, which are then provided to a filter (e.g., a bandpass filter). Filters 346-348 filter the I and Q mixed signals, which are then provided to RX IF-BB section 224.

Although the currently shown RF-IF section 352 is connected to a single antenna for SISO (Single Input Single Output) communication, the scheme can also be applied to MISO (Multiple Input Single Output) communication and MIMO (Multiple Input Multiple Output) communication. . In these cases, multiple antennas (eg, 2 or more) are connected to a corresponding number of FEMs (or a smaller number of FEMs according to the receive path in the FEM). FEM is connected to multiple receiver RF-IF sections (for example, with an antenna The same number of receivers, these receiver RF-IF sections are in turn connected to a corresponding number of receiver IF-BB sections. The baseband processing unit processes the plurality of symbol streams described above to generate inbound data.

The RX RF-IF portion 352 provides at least one of the following advantages and/or includes at least one of the following features: a superheterodyne receiver has advantages over a similar direct conversion receiver in minimum area and power; the use of complex baseband impedance in the FTBPF 354 enables the band The center frequency of the pass filter changes; the complex baseband impedance 354 can be implemented with switches and capacitors, and its center is controlled by the LO clock; the on-chip high Q mirror band rejection filter is used with the same LO clock used by the downconverting mixer ( For example, FTBPF) is tuned to the desired frequency; RF-IF section 352 uses a signal phase locked loop (PLL); and can be easily integrated into SOC 350.

23 is a schematic block diagram of a transmitter portion of SOC 360 including an upconversion mixing module 362, a transmitter local oscillator module (LO) 364, and a variable frequency bandpass filter (FTBPF), in accordance with an embodiment of the present invention. 366, an output module (including capacitor arrays 368-370 and/or transformer T1) and a power amplifier driver (PAD) 372. The PAD 372 includes transistors Q1-Q2, a resistor R1, and a capacitor C1 as shown. Note that capacitor C1 and/or resistor R1 can be implemented using one or more transistors Q1-Q2. The SOC 360 also includes a SAWless receiver portion 364 and may also include a baseband processing unit, a processing module, and/or a power management unit.

In one operational example, upconversion mixing module 362 receives baseband (BB) I and Q signals (e.g., analog and orthogonal representations of outbound symbol streams). The upconversion mixing module 362 can convert the BBI and Q signals to an upconverted signal using a direct conversion topology or a superheterodyne topology, the carrier frequency of which is at the desired RF.

FTBPF 366 (various embodiments will be described with reference to the following figures) filters the upconverted signal by attenuating out-of-band signal components and by substantially un-attenuating up-converted signals. For example, assume that FTBPF 366 converts a narrowband baseband bandpass filter to RF (eg, the carrier frequency of the upconverted signal) to produce a high Q RF filter. The narrowband high Q RF filter filters out the out-of-band signal and passes the substantially un-attenuated up-converted signal.

Capacitor arrays 368-370 provide an adjustable low pass filter that filters common mode noise and/or linear noise. Transformer T1 converts the differential upconverted signal into a single-ended signal The latter is then amplified by PAD 372. The PAD 372 provides an amplified upconverted signal to the FEM, which is further amplified by the FEM to separate it from the inbound RF signal and provide it to the antenna for transmission.

The TX portion provides at least one of the following advantages and/or includes at least one of the following features: a superheterodyne receiver has advantages over a similar direct conversion receiver in minimum area and power; uses a TXLO 364 with a transmitter upconverting mixer LC load The synchronous FTBPF 366 reduces transmitter noise and other out-of-band noise at the RX frequency, but has little effect on the desired TX signal; the baseband impedance of the high Q FTBPF 366 can be achieved with a capacitor, and its center frequency is TX LO 364 control; eliminated TX SAW filter; and easy integration into SOC 360.

24 is a schematic block diagram of a transmitter portion 382 of a SOC 380 that includes an upconversion mixing module 362, a transmitter local oscillator module (LO), and a variable frequency bandpass filter (FTBPF) in accordance with another embodiment of the present invention. ), an output module (including capacitor arrays 368-370 and/or transformer T1) and a power amplifier driver (PAD) 372. The PAD 372 includes transistors, resistors, and capacitors as shown in the figure. Note that the capacitance and/or resistance can be achieved with one or more transistors. The SOC 380 also includes a SAWless receiver portion 364 and may also include a baseband processing unit, a processing module, and/or a power management unit.

In this embodiment, the upconversion mixing module includes a passive mixing structure as shown, and the passive mixing structure can employ a 50% duty cycle LO clock. In a running example, the LOI and Q signal components are mixed by the circuit on the left side of the figure, and the BBI and Q signal components are mixed by the circuit on the right side of the figure. The mixed LO signal component is then mixed with the mixed BB signal component to produce an upconverted signal. For example, LO_I+ injects energy into its corresponding capacitance and LO_I- extracts energy from the capacitance (and vice versa), thereby producing a varying voltage across the capacitor at a rate corresponding to LO. LO_Q+ and LO_Q- do similar processing on their capacitance, only phase shifting by 90 degrees. The varying voltage across the capacitor is superimposed by the summing node to produce a mixed LO signal component. A similar process occurs on the baseband side of the mixer.

TX portion 382 provides at least one of the following advantages and/or includes at least one of the following The Vb1 and Vb2 driven transistors are high voltage transistors (eg, Vds voltage > 2.5V); and the TX structure provides a low power, high efficiency region design and uses a passive mix driven by a 50% duty cycle LO clock. The frequency converter reduces power consumption compared to a mixer driven by a 25% duty cycle clock.

25 is a schematic block diagram of a portion of an RF-IF receiver portion including a single-ended FTBPF (Frequency Bandpass Filter) 394, in accordance with one embodiment of the present invention. This portion of the RX RF-IF section includes a transformer T1, a variable capacitor network C1, and an LNA 392. The FTBPF 394 includes a plurality of transistors (e.g., a switching network) and a plurality of baseband impedances (Z _BB(s) ) 396-402.

In an operational example, a front end module (FEM) 390 receives an inbound RF signal through an antenna, and processes the RF signal as described above and/or as described with reference to at least one of the following figures, and processes the FEM 390 The inbound RF signal is provided to transformer T1. Transformer T1 raises or lowers the voltage level of the inbound RF signal, which is then filtered by variable capacitance network C1. Note that transformer T1 may be omitted if there is no need to adjust the voltage level of the inbound RF signal and/or the separation provided by transformer T1 is not required.

The FTBPF 394 provides a high Q (quality factor) RF filter that filters the inbound RF signal such that the desired signal component of the inbound RF signal is substantially un-attenuated to the LNA 392 and undesired signal components (eg, block, mirror) Etc.) attenuation. To implement the filter, the baseband impedance (Z _BBz(s) ) 396-402 provides a low Q baseband filter with corresponding filter response, where each baseband impedance can be a capacitor, a switched capacitor filter, or a switched capacitor resistor. And / or complex impedance. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal provided by clock generator 404 to produce a high Q RF filter. FIG. 27 shows a frequency conversion of a low Q baseband filter in response to a high Q RF filter, and FIG. 26 shows an embodiment of a clock generator 404.

As shown in Figure 26, a clock generator (various embodiments of which will be described with reference to at least one of the following figures) produces four clock signals, each having a 25% duty cycle and sequentially phase shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and can be adjusted to better track the carrier frequency. The clock generator 404 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal.

Returning to the discussion of Figure 25, the FTBPF 394 receives clock signals that are coupled to the transistors to sequentially connect their respective baseband impedances to the inbound RF signals. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the baseband impedance response (the low Q bandpass filter is commonly) is transferred to the RF, thereby implementing a high QRF bandpass filter.

28 is a schematic block diagram of a single-ended FTBPF 410 comprising four transistors and four capacitors, wherein the transistors and capacitors provide baseband impedance, in accordance with one embodiment of the present invention. Four capacitors provide concentrated baseband impedance, which provides a low Q baseband bandpass filter as shown in FIG. Specifically, the impedance of one capacitor (or four in parallel) is 1/sC, where s is 2 π f. Therefore, as the frequency (f) approaches zero, the impedance of the capacitor approaches infinity, and as the frequency (f) increases, the impedance of the capacitor decreases. In addition, the phase of the capacitor changes from 90° to -90° at zero frequency.

Returning to the discussion of Figure 28, since a clock signal is applied to the transistor, the capacitor is connected to a common node of the FTBPF 410 (e.g., the input of the FTBPF). In this way, the performance of the capacitor can be frequency shifted to the rate of the clock signal as shown in Figure 30 (e.g., _fLO ). Specifically, the impedance of the capacitor (and the four capacitors in parallel) is moved to the frequency of the clock. Since the LO is close to infinite impedance, the FTBPF 410 has a high impedance at the LO and therefore has less effect on the signal component of the carrier frequency and the LO. As the frequency deviates from LO, the impedance of the FTBPF 410 decreases, so the FTBPF 410 effectively "short" the signal component of the carrier frequency that is not equivalent to the LO.

31 is a schematic block diagram of a portion of an RF-IF receiver portion including a differential FTBPF 412 (frequency band pass filter) in accordance with another embodiment of the present invention. This part of the RX RF-IF section includes transformer T1, variable capacitor network C1 and LNA 393. The FTBPF 412 includes a plurality of transistors and a plurality of baseband impedances (Z _BB(s) ) 414-420.

In an operational example, a front end module (FEM) 390 receives an inbound RF signal through an antenna, and processes the RF signal as described above and/or as described with reference to at least one of the following figures, and processes the FEM 390 The inbound RF signal is provided to transformer T1. Transformer T1 converts the single-ended inbound RF signal into a differential inbound RF signal.

The FTBPF 412 provides a differential high Q (quality factor) RF filter that filters the differential inbound RF signal such that the desired signal component of the inbound RF signal is substantially un-attenuated to the LNA 393 and undesired signal components (eg, block , mirroring, etc.) attenuation. To implement the filter, the baseband impedance (Z _BBz(s) ) 414-420 together provide a low Q baseband filter with a corresponding filter response, where each baseband impedance can be a capacitor, a switched capacitor filter, or a switched capacitor resistor, respectively. And / or complex impedance. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal provided by clock generator 422 to produce a high Q RF filter. FIG. 33 shows a frequency conversion of a low Q baseband filter in response to a high Q RF filter, and FIG. 32 shows an embodiment of a clock generator 422.

As shown in Figure 32, clock generator 422 (which various embodiments will be described with reference to at least one of the following figures) produces four clock signals, each having a 25% duty cycle and sequentially phase shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and can be adjusted to better track the carrier frequency. The clock generator 422 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal.

Returning to the discussion of Figure 31, the FTBPF 412 receives clock signals that are coupled to the transistors to sequentially connect their respective baseband impedances to the inbound RF signals. number. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the baseband impedance response (the low Q bandpass filter is commonly) is transferred to the RF, thereby implementing a high QRF bandpass filter.

Figure 34 is a schematic block diagram of a portion of an RF-IF receiver portion including a single-ended FTBPF 430 (frequency conversion bandpass filter) in accordance with another embodiment of the present invention. This portion of the RX RF-IF section includes a transformer T1, a variable capacitor network C1, and an LNA 392. The FTBPF 430 includes a plurality of transistors and a complex baseband filter 432.

In an operational example, a front end module (FEM) 390 receives an inbound RF signal through an antenna, and processes the RF signal as described above and/or as described with reference to at least one of the following figures, and processes the FEM 390 The inbound RF signal is provided to transformer T1. Transformer T1 raises or lowers the voltage level of the inbound RF signal, which is then filtered by variable capacitance network C1. Note that transformer T1 may be omitted if there is no need to adjust the voltage level of the inbound RF signal and/or the separation provided by transformer T1 is not required.

The FTBPF 430 provides a high Q (quality factor) RF filter that filters the inbound RF signal such that the desired signal component of the inbound RF signal is substantially un-attenuated to the LNA 392 and undesired signal components (eg, block, mirror) Etc.) attenuation. To implement the filter, complex baseband filter 432 provides a low Q baseband filter whose bandpass region can be offset by zero frequency. Note that the performance of the complex baseband filter 432 (eg, bandwidth, attenuation rate, quality factor, frequency offset, etc.) can be adjusted by control signals from the SOC processing resources.

The frequency offset low Q baseband filter is frequency converted to a desired RF frequency by a clock signal provided by clock generator 434 to produce a frequency offset high Q RF filter. 36 illustrates frequency conversion of a frequency shifted low Q baseband filter to a frequency shifted high Q RF filter, and FIG. 35 illustrates one embodiment of a clock generator 434.

As shown in Figure 35, clock generator 434 (which various embodiments will be described with reference to at least one of the following figures) produces four clock signals, each having a 25% duty cycle and sequentially phase shifted by 90°. The frequency of the clock signal corresponds to the load of the inbound RF signal The wave frequency can be adjusted to better track the carrier frequency. The clock generator 434 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal. Alternatively, at least one clock signal of the FTBPF 430 can be used as the LO clock signal.

Returning to the discussion of Figure 34, the FTBPF 430 receives clock signals that are coupled to the transistors to sequentially connect their respective complex baseband filters to the inbound RF signals. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the response of complex baseband filter 432 is transferred to RF (and/or LO), thereby implementing a high Q RF bandpass filter.

37 is a schematic block diagram of a portion of an RF-IF receiver portion including a differential FTBPF 440 (frequency band pass filter) in accordance with another embodiment of the present invention. This portion of the RX RF-IF section includes a transformer T1, a variable capacitor network C1, and an LNA 393. The differential FTBPF 440 includes a plurality of transistors and a complex baseband filter 442.

In an operational example, a front end module (FEM) 390 receives an inbound RF signal through an antenna, and processes the RF signal as described above and/or as described with reference to at least one of the following figures, and processes the FEM 390 The inbound RF signal is provided to transformer T1. Transformer T1 converts the single-ended inbound RF signal into a differential inbound RF signal.

The differential FTBPF 440 provides a high Q (quality factor) RF filter that filters the differential inbound RF signal such that the desired signal component of the inbound RF signal is substantially un-attenuated to the LNA 393 and undesired signal components (eg, block , mirroring, etc.) attenuation. To implement the filter, complex baseband filter 442 provides a low Q baseband filter whose bandpass region can be offset by zero frequency. Note that the performance of the complex baseband filter 442 (eg, bandwidth, attenuation rate, quality factor, frequency offset, etc.) can be adjusted by control signals from the SOC processing resources.

The frequency offset low Q baseband filter is frequency converted to a desired RF frequency by a clock signal provided by clock generator 444 to produce a frequency offset high QRF filter. FIG. 39 illustrates frequency conversion of a frequency shifted low Q baseband filter to a frequency offset high QRF filter, and FIG. 38 illustrates one embodiment of a clock generator 444.

As shown in Figure 38, clock generator 444 (which various embodiments will be described with reference to at least one of the following figures) produces four clock signals, each having a 25% duty cycle and sequentially phase shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and can be adjusted to better track the carrier frequency. The clock generator 444 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal. Alternatively, at least one clock signal of the FTBPF 440 can be used as the LO clock signal.

Returning to the discussion of Figure 37, the FTBPF 440 receives clock signals that are coupled to the transistors to sequentially connect their respective complex baseband filters to the inbound RF signals. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the response of the complex baseband filter 442 is shifted to RF (and/or LO), thereby implementing a high QRF bandpass filter.

40 is a schematic block diagram of a portion of an RF-IF receiver portion including an FTBPF 440 (frequency band pass filter) in accordance with another embodiment of the present invention. This portion of the RX RF-IF section includes a transformer T1, a variable capacitor network C1, and an LNA 393. The differential FTBPF 440 includes a plurality of transistors and a complex baseband filter 442. The complex baseband filter 442 includes a plurality of baseband impedances (e.g., Z _BB(s) ) 450-456, a positive gain stage (Gm) 458, and a negative gain stage (-GM) 460.

In an operational example, a front end module (FEM) 390 receives an inbound RF signal through an antenna, and processes the RF signal as described above and/or as described with reference to at least one of the following figures, and processes the FEM 390 The inbound RF signal is provided to transformer T1. Transformer T1 converts the single-ended inbound RF signal into a differential inbound RF signal.

The differential FTBPF 440 provides a high Q (quality factor) RF filter that filters the differential inbound RF signal such that the desired signal component of the inbound RF signal is substantially un-attenuated to the LNA 393 and undesired signal components (eg, block , mirroring, etc.) attenuation. To implement the filter, complex baseband filter 442 provides a low Q baseband filter whose bandpass region can be offset by a zero frequency based on the ratio between the gain level and the baseband impedance. Note that each baseband impedance can be a capacitor, a switched capacitor filter, or Switched capacitor resistance and / or complex impedance. Also note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance and/or the gain of at least one gain stage can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (eg, bandwidth, attenuation rate, quality factor, etc.) ).

The frequency offset low Q baseband filter is frequency converted to a desired RF frequency by a clock signal provided by clock generator 444 to produce a frequency offset high Q RF filter. Figure 42 shows a high frequency RF filter with frequency offset and Figure 41 shows an embodiment of a clock generator 444.

As shown in FIG. 41, clock generator 444 (which various embodiments will be described with reference to at least one of the following figures) produces four clock signals, each having a 25% duty cycle and sequentially phase shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and can be adjusted to better track the carrier frequency. The clock generator 444 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal. Alternatively, at least one clock signal of the FTBPF 440 can be used as the LO clock signal.

Returning to the discussion of FIG. 40, FTBPF 440 receives clock signals that are coupled to the transistors to sequentially connect their respective complex baseband filters 442 and inbound RF signals. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the response of complex baseband filter 442 is shifted to RF (and/or LO), thereby implementing a high Q RF bandpass filter.

Figure 43 is a schematic block diagram of a portion of an RF-IF receiver portion including an FTBPF 440 (frequency band pass filter) in accordance with another embodiment of the present invention. This portion of the RX RF-IF section includes a transformer T1, a variable capacitor network C1, and an LNA 393. The differential FTBPF 440 includes a plurality of transistors and a complex baseband filter 442. The complex baseband filter 442 includes a plurality of capacitors, a positive gain stage (Gm) 458, and a negative gain stage (-GM) 460.

In an operational example, a front end module (FEM) 390 receives an inbound RF signal through an antenna, as described above and/or with reference to at least one of the following figures. The RF signal is processed and the inbound RF signal processed by the FEM 390 is supplied to the transformer T1. Transformer T1 converts the single-ended inbound RF signal into a differential inbound RF signal.

The differential FTBPF 440 provides a high Q (quality factor) RF filter that filters the differential inbound RF signal such that the desired signal component of the inbound RF signal is substantially un-attenuated to the LNA 393 and undesired signal components (eg, block , mirroring, etc.) attenuation. To implement the filter, complex baseband filter 442 provides a low Q baseband filter whose bandpass region can be offset by a zero frequency based on the ratio between the gain stage and the capacitance. Note that the capacitance of each capacitor can be the same, different, or a combination thereof. It is also noted that the capacitance of each capacitor and/or the gain of at least one gain stage can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (eg, bandwidth, attenuation rate, quality factor, etc.) ).

The frequency offset low Q baseband filter is frequency converted to a desired RF frequency by a clock signal provided by clock generator 444 to produce a frequency offset high Q RF filter. A clock generator 444, as shown in FIG. 44 (which various embodiments will be described with reference to at least one of the following figures), generates four clock signals, each having a 25% duty cycle and sequentially phase shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and can be adjusted to better track the carrier frequency. The clock generator 444 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal. Alternatively, at least one clock signal of the FTBPF 440 can be used as the LO clock signal.

Returning to the discussion of Figure 43, FTBPF 440 receives clock signals that are coupled to the transistors to sequentially connect their respective complex baseband filters 442 and inbound RF signals. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the response of the complex baseband filter 442 is shifted to RF (and/or LO), thereby implementing a high QRF bandpass filter.

Figure 45 is a schematic block diagram of a portion of an RF-IF receiver portion including an FTBPF 440 (frequency band pass filter) in accordance with another embodiment of the present invention. This portion of the RX RF-IF section includes a transformer T1, a variable capacitor network C1, a control module 470, and an LNA 393. The differential FTBPF 440 includes a plurality of transistors and a complex baseband filter 442. The complex baseband filter 442 includes a plurality of baseband impedances (e.g., Z _BB ( _s )) 450-456, a positive gain stage (Gm) 458, and a negative gain stage (-GM) 460.

In an operational example, a front end module (FEM) 390 receives an inbound RF signal through an antenna, and processes the RF signal as described above and/or as described with reference to at least one of the following figures, and processes the FEM 390 The inbound RF signal is provided to transformer T1. Transformer T1 converts the single-ended inbound RF signal into a differential inbound RF signal.

The differential FTBPF 440 provides a high Q (quality factor) RF filter that filters the differential inbound RF signal such that the desired signal component of the inbound RF signal is substantially un-attenuated to the LNA 393 and undesired signal components (eg, block , mirroring, etc.) attenuation. To implement the filter, complex baseband filter 442 provides a low Q baseband filter whose bandpass region can be offset by a zero frequency based on the ratio between gain stage and baseband impedance, which ratio is provided by control module 470 The control signal is set.

Control module 470 is part of the SOC processing resource that determines the desired low Q bandpass filter response (eg, gain, bandwidth, quality factor, frequency offset, etc.) based on at least one of the following: signal to noise of the inbound RF signal Ratio (SNR), signal to interference ratio (SIR) of the inbound RF signal, strength of the received signal, bit error rate, and the like. Based on the desired response, control module 470 determines the settings of the baseband impedance and/or gain module. Note that the control module 470 can continuously update, periodically update, and/or meet performance criteria criteria (eg, transmit power level changes, SNR below threshold, low SIR) based on changes in various factors it monitors. Updated at a threshold, the strength of the received signal is below a threshold, etc.).

Once the frequency response of the low Q baseband filter is determined (or updated), the low Q baseband filter is converted to the desired RF frequency by the clock signal provided by clock generator 476 to produce a frequency offset high QRF filter. A clock generator 476, as shown in FIG. 46 (which various embodiments will be described with reference to at least one of the following figures), generates four clock signals, each having a 25% duty cycle and sequentially phase shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and can be adjusted to Good tracking of the carrier frequency. The clock generator 476 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal. Alternatively, at least one clock signal of the FTBPF 440 can be used as the LO clock signal.

Returning to the discussion of Figure 45, the FTBPF 440 receives clock signals that are coupled to the transistors to sequentially connect their respective complex baseband filters 442 and inbound RF signals. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the response of complex baseband filter 442 is shifted to RF (and/or LO), thereby implementing a high Q RF bandpass filter.

47 is a schematic block diagram of a complex baseband (BB) filter 442 that includes a plurality of adjustable baseband impedances 480-486, an adjustable positive gain stage 488, and an adjustable negative gain stage 490, in accordance with one embodiment of the present invention. Each of the adjustable baseband impedances can include at least one of: an optional capacitor network 492 (eg, a tunable capacitor), a programmable switched capacitor network 494, and a programmable switched capacitor filter 496 (1st to nth order) And any combination of components (eg, inductors, capacitors, resistors) that provide the desired baseband frequency response.

The adjustable gain stages (+Gm and -Gm) 488-490 may each include an amplifier connected to a gain network. The gain network may include at least one of the following: a resistor, a capacitor, a variable resistor, a variable capacitor, and the like. In this regard, the gain of each gain stage can be adjusted to vary the performance of the complex baseband filter 442. Specifically, the frequency offset of the low Q band pass filter can be changed by changing the gain by the impedance value of the adjustable impedance. Additionally or alternatively, the bandwidth, gain, swing rate, quality factor, and/or other performance of complex baseband filter 442 may be varied by control signals provided by control module 470.

48 is a diagram showing the frequency response of converting the frequency response of the complex BB filter 442 to a high Q RF filter for the RX RF-IF section, including the tunable complex baseband filtering shown in FIG. 47, in accordance with an embodiment of the present invention. The FTBPF 440 of the 442. In this diagram, the bandwidth, slew rate, gain, frequency offset, and/or other performance of the low Q baseband filter provided by the complex baseband filter 442 can be adjusted. The adjustable and adjusted features of the low Q bandpass filter can be converted to RF (or LO). In this regard, by adjusting the performance of the low-Q baseband filter, the corresponding high Q can be similarly adjusted. Baseband filter performance.

Figure 49 is a schematic block diagram of a portion of an RF-IF receiver portion including an FTBPF 412 (frequency band pass filter) in accordance with another embodiment of the present invention. This portion of the RX RF-IF section includes an I 504 and Q RF-IF mixer 500 and a mixing buffer 502. The FTBPF module includes the FTBPF and other registers. The FTBPF includes a plurality of transistors and a plurality of baseband impedances (e.g., Z _BB(s) ) 414, 416, 418, and 420.

In one example of operation, I mixer 504 mixes the I component of the inbound RF signal with the I component of the local oscillation (e.g., f _LO2 = f _RF - f _IF 500) to produce an I-mixed signal. The I mix register buffers the I-mixed signal and provides the buffered I-mixed signal to the FTBPF module 412. Similarly, the Q mixer mixes the Q component of the inbound RF signal with the Q component of the local oscillation (eg, f _LO2 =f _RF -f _IF ) to produce a Q-mixed signal. The Q mixing register buffers the Q-mixed signal and provides the buffered Q-mixed signal to the FTBPF module 412. The FTBPF 412 provides a high Q (quality factor) IF filter that filters the inbound IF signal (eg, the I and Q mixed signals) such that the desired signal component of the inbound IF signal is transmitted substantially un-attenuated and the undesired signal Components (such as block, mirror, etc.) are attenuated. To implement the filter, the baseband impedances (Z _BBz(s) ) 414, 416, 418, and 420 together provide a low Q baseband filter with a baseband filter response, where each baseband impedance can be a capacitive, switched capacitor filter, respectively. , switched capacitor resistance and / or complex impedance. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The frequency offset low Q baseband filter is frequency converted to a desired IF frequency by a clock signal provided by clock generator 510 to produce a frequency shifted high QIF filter. Figure 51 illustrates frequency conversion of a frequency shifted low Q baseband filter to a frequency shifted high QIF filter. Figure 50 illustrates one embodiment of a clock generator 510.

As shown in FIG. 50, clock generator 510 (which various embodiments will be described with reference to at least one of the following figures) produces four clock signals, each having 25% of the clock signal. The duty cycle is sequentially shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the inbound IF signal and can be adjusted to better track the carrier frequency. The clock generator 510 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal (e.g., LO2). Alternatively, at least one clock signal of the FTBPF 412 can be used as the LO clock signal.

Returning to the discussion of Figure 49, the FTBPF 412 receives clock signals that are coupled to the transistors to sequentially connect their respective baseband impedances to the inbound IF signals. Since the clock rate is at the IF (eg, the carrier frequency of the desired component of the inbound IF signal), the baseband impedance response (low Q bandpass filter) is transferred to IF (and/or LO2) to achieve a high QIF bandpass filter .

Figure 52 is a schematic block diagram of a portion of an RF-IF receiver portion including an IF FTBPF (Frequency Variable Bandpass Filter) module 530, in accordance with another embodiment of the present invention. This part of the RX RF-IF section includes the I and QRF-IF mixers as well as the mixing registers. The IF FTBPF 530 module includes a differential IF FTBPF 530 and other registers. The differential IF FTBPF 530 includes a plurality of transistors and a plurality of baseband impedances (e.g., Z _BB(s) ).

In one operational example, I mixer 522 mixes the I component of the inbound RF signal with the I component of the local oscillation (eg, f _LO2 =f _RF -f _IF 520) to produce an I-mixed signal. The I mix register 522 buffers the I-mixed signal and provides the buffered I-mixed signal to the FTBPF 530 module. Similarly, Q mixer 523 mixes the Q component of the inbound RF signal with the Q component of the local oscillation (e.g., f _LO2 = f _RF - f _IF 521) to produce a Q-mixed signal. The Q mix register 523 buffers the Q-mixed signal and provides the buffered Q-mixed signal to the FTBPF 530 module.

The FTBPF 530 provides a high Q (quality factor) IF filter that filters the inbound IF signal (eg, the I and Q mixed signals) such that the desired signal component of the inbound IF signal is transmitted substantially undecreased and the desired signal Components (such as block, mirror, etc.) are attenuated. To implement the filter, the baseband impedances (Z _BBz(s) ) 532, 534, 536, 538, 540, 542, 544, and 546 together provide a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor, respectively. Filter, switched capacitor resistance and / or complex impedance. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The frequency offset low Q baseband filter is frequency converted to a desired IF frequency by a clock signal provided by the clock generator to produce a frequency shifted high Q IF filter. A clock generator 550, as shown in FIG. 53, which will be described with reference to at least one of the following figures, produces eight clock signals, each having a duty cycle of 12.5% and sequentially phase shifted by 45[deg.]. The frequency of the clock signal corresponds to the carrier frequency of the inbound IF signal and can be adjusted to better track the carrier frequency. The clock generator 550 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal (e.g., LO2). Alternatively, at least one clock signal of the FTBPF can be used as the LO clock signal.

Returning to the discussion of Figure 52, the FTBPF 530 receives clock signals that are coupled to the transistors to sequentially connect their respective baseband impedances to the inbound IF signals. Since the clock rate is at the IF (eg, the carrier frequency of the desired component of the inbound IF signal), the baseband impedance response (low Q bandpass filter is commonly) is transferred to IF (and / or LO2) to achieve high Q IF bandpass filtering Device.

Figure 54 is a schematic block diagram of a portion of an RF-IF receiver portion including a single-ended FTBPF 560 (frequency bandpass filter) and a single-ended FTBPF 560 including a negative resistance, in accordance with one embodiment of the present invention. This part of the RXRF-IF section includes transformers, variable capacitor networks, and LNAs. The FTBPF 560 includes a plurality of transistors and a plurality of baseband impedances (Z _BB(s) ) 562, 564, 566, and 568.

In an operational example, a front end module (FEM) 390 receives an inbound RF signal through an antenna, and processes the RF signal as described above and/or as described with reference to at least one of the following figures, and processes the FEM 390 The inbound RF signal is provided to the transformer. The transformer raises or lowers the voltage level of the inbound RF signal, which is then filtered by a variable capacitance network. Note that if the voltage level of the inbound RF signal is not required The transformer can be omitted by making adjustments and/or without the separation provided by the transformer.

The FTBPF 560 provides a high Q (quality factor) RF filter that filters the inbound RF signal such that the desired signal component of the inbound RF signal is substantially un-attenuated to the LNA 392 and undesired signal components (eg, block, mirror) Etc.) attenuation. To implement the filter, the baseband impedances (Z _BB (s)) 562, 564, 566, and 568 together provide a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or Or complex impedance. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

In addition, FTBPF 560 includes a negative resistance (eg, -2R) to compensate for inductance losses, compensate for switching losses, and/or improve the selectivity and/or quality factor of the low Q bandpass filter. The negative resistance can be implemented as shown in Figure 56, i.e., includes a plurality of transistors. The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal provided by the clock generator to produce a high Q RF filter. The clock generator shown in Figure 55 (which various embodiments will be described with reference to at least one of the following figures) produces four clock signals, each having a 25% duty cycle and sequentially phase shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and can be adjusted to better track the carrier frequency. The clock generator 572 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal.

Returning to the discussion of Figure 54, the FTBPF 560 receives clock signals that are coupled to the transistors to sequentially connect their respective baseband impedances to the inbound RF signals. Since the clock rate is at the RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the baseband impedance response (the low Q bandpass filter is commonly) is transferred to the RF, thereby implementing a high Q RF bandpass filter.

Figure 57 is a schematic block diagram of a portion of an RF-IF receiver portion that includes a differential FTBPF 580 (frequency bandpass filter) and a differential FTBPF 580 that includes a negative resistance, in accordance with one embodiment of the present invention. This part of the RXRF-IF section includes the transformer, variable capacitance network, and LNA 393. The differential FTBPF 580 includes a plurality of transistors and a plurality of baseband impedances (Z _BB (s)).

In an operational example, a front end module (FEM) 390 receives an inbound RF signal through an antenna, and processes the RF signal as described above and/or as described with reference to at least one of the following figures, and processes the FEM 390 The inbound RF signal is provided to the transformer. The transformer raises or lowers the voltage level of the inbound RF signal, which is then filtered by a variable capacitance network. Note that the transformer can be omitted if the voltage level of the inbound RF signal does not need to be adjusted and/or the separation provided by the transformer is not required.

The FTBPF 580 provides a high Q (quality factor) RF filter that filters the inbound RF signal such that the desired signal component of the inbound RF signal is substantially un-attenuated to the LNA 393 and undesired signal components (eg, block, mirror) Etc.) attenuation. To implement the filter, the baseband impedance (Z _BB (s)) together provides a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

In addition, FTBPF 580 includes a negative resistance (eg, -2R) to compensate for inductance losses, compensate for switching losses, and/or improve the selectivity and/or quality factor of the low Q bandpass filter. The negative resistance can be implemented as shown in FIG.

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal provided by clock generator 582 to produce a high QRF filter. A clock generator 582, as shown in Figure 58 (which various embodiments will be described with reference to at least one of the following figures), generates four clock signals, each having a 25% duty cycle and sequentially phase shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the inbound RF signal and can be adjusted to better track the carrier frequency. The clock generator 582 can also generate a local oscillator clock signal (not shown) for downconverting the inbound RF signal to an inbound IF signal.

Returning to the discussion of Figure 57, the FTBPF 580 receives clock signals that are clocked. The numbers are connected to the transistors to sequentially connect their respective baseband impedances to the inbound RF signal. Since the clock rate is at RF (e.g., the carrier frequency of the desired component of the inbound RF signal), the baseband impedance response (the low Q bandpass filter is commonly) is transferred to the RF, thereby implementing a high QRF bandpass filter.

Figure 59 is a schematic block diagram of a portion of an RF-IF receiver portion including a dual band FTBPF (Frequency Bandpass Filter) 590, in accordance with another embodiment of the present invention. This part of the RX RF-IF section includes transformers, variable capacitor networks, and LNAs 392-1 and 392-2. The FTBPF 590 includes a plurality of transistors and a plurality of baseband impedances (Z _BB (s)) 592, 594, 596, and 598.

In one operational example, front end module (FEM) 390 receives dual band inbound RF signals (e.g., _fRF1 and _fRF2 ) through an antenna, as described above and/or as described with reference to at least one of the following figures. The RF signal is supplied to the transformer by the FEM processed inbound RF signal. The transformer raises or lowers the voltage level of the inbound RF signal, which is then filtered by the variable capacitance network C1. Note that the transformer can be omitted if the voltage level of the inbound RF signal does not need to be adjusted and/or the separation provided by the transformer is not required.

The FTBPF 590 provides two high-Q (quality factor) RF filters (one centered at f _RF1 and the other centered on f _RF2 ). These filters filter the inbound RF signal to make the expectations of the dual-band inbound RF signal. The signal components are transmitted to the LNAs 392-1 and 392-2 substantially un-attenuated and the unwanted signal components (e.g., block, mirror, etc.) are attenuated. The two high QRF filters are formed by a plurality of baseband impedances (Z _BB (s) 592, 594, 596, and 598) and a plurality of transistors, wherein each baseband impedance includes a further plurality of baseband impedances (eg, Z _BB '( s) 592, 594, 596 and 598) and a further plurality of transistors. A plurality of other baseband impedances (Z _BB '(s) 592, 594, 596, and 598) provide a low Q baseband filter, wherein each of the other plurality of baseband impedances may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and / or complex impedance. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

Clock signal provided by clock generator 600 (the frequency f _D) of the low Q baseband filter frequency of the desired RF frequency (e.g., _{f D = (f LO1 -f LO2} ) / 2) to produce a high QRF filter. The clock generator shown in FIG. 60 600 (its various embodiments the at least one reference to the following figures) generates four clock signals (e.g., LO _'1 to LO' _4), each clock signal having a 25% The duty cycle is sequentially shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the first frequency band of the inbound RF signal (eg, f _RF1 or f _LO1 ) minus the difference of the carrier frequency of the second frequency band of the inbound RF signal (eg, f _RF2 or f _LO2 ) 1/2, and can be adjusted to better track at least one carrier frequency.

Since the first plurality of transistors are synchronized with LO ₁ -LO ₄ (generated by clock generator 600 as shown in FIG. 60) at a rate f _C , the high QRF filter formed by the first plurality of baseband impedances is converted to Higher expected Rf frequency, where fC = (f _LO1 + f _LO2 )/2. For example, with reference to FIG. 61, the low-Q baseband filter formed by a plurality of additional impedance is frequency-converted to baseband +/- f _D. Therefore, the response of the first high Q bandpass filter is centered at +/-f _D and also shows the third harmonic. Referring to Figure 62, the first high Q band pass filter is frequency converted to f _C -f _D and f _C +f _D to produce two high Q band pass filters. Since f _C =(f _LO1 +f _LO2 )/2, f _D =(f _LO1 -f _LO2 )/2, f _C -f _D =LO2,f _C +f _D =LO1. Therefore, one of the high Q bandpass filters is centered on LO2 (or _fRF2 ) and the other high Q bandpass filter is centered on LO1 (or _fRF1 ). Thus, the first high Q bandpass filter passes the desired signal component of the inbound RF signal at LO2 (or _fRF2 ), and the second high Q bandpass filter passes the inbound RF signal at a frequency of LO1 (or _fRF1) The expected signal component.

Figure 63 is a schematic block diagram of a portion of an RF-IF receiver portion including a dual band differential FTBPF (Frequency Bandpass Filter) 610, in accordance with another embodiment of the present invention. This part of the RX RF-IF section includes transformers, variable capacitor networks, and LNAs 393-1 and 393-2. The FTBPF 610 includes a plurality of transistors and a plurality of baseband impedances (Z _BB (s)) 612, 614, 616, and 618.

In one operational example, front end module (FEM) 390 receives dual band inbound RF signals (e.g., _fRF1 and _fRF2 ) through an antenna, as described above and/or as described with reference to at least one of the following figures. The RF signal is supplied to the transformer T1 after the FEM processed inbound RF signal. The transformer converts the inbound RF signal into a differential inbound RF signal.

The FTBPF 610 provides two high-Q (quality factor) RF filters (one centered on f _RF1 and the other centered on f _RF2 ). These filters filter the inbound RF signal to make the expectations of the dual-band inbound RF signal. The signal components are transmitted to the LNAs 393-1 and 393-2 substantially un-attenuated and the unwanted signal components (e.g., block, mirror, etc.) are attenuated. The two high QRF filters are formed by a plurality of baseband impedances (Z _BB (s) 612, 614, 616, and 618) and a plurality of transistors, wherein each baseband impedance includes a further plurality of baseband impedances (eg, Z _BB '( s) 612, 614, 616 and 618) and a further plurality of transistors. A plurality of other baseband impedances (Z _BB '(s) 612, 614, 616, and 618) provide a low Q baseband filter, wherein each of the other plurality of baseband impedances may be a capacitor, a switched capacitor filter, a switched capacitor resistor, and / or complex impedance. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

Clock signal provided by clock generator 600 (the frequency f _D) of the low Q baseband filter frequency of the desired RF frequency (e.g., _{f D = (f LO1 -f LO2} ) / 2) to produce a high QRF filter. The clock generator shown in FIG. 60 600 (its various embodiments the at least one reference to the following figures) generates four clock signals (e.g., LO _'1 to LO' _4), each clock signal having a 25% The duty cycle is sequentially shifted by 90°. The frequency of the clock signal corresponds to the carrier frequency of the first frequency band of the inbound RF signal (eg, f _RF1 or f _LO1 ) minus the difference of the carrier frequency of the second frequency band of the inbound RF signal (eg, f _RF2 or f _LO2 ) 1/2, and can be adjusted to better track at least one carrier frequency.

Since the first plurality of transistors are synchronized with LO ₁ -LO ₄ (generated by the clock generator as shown in FIG. 60) at a rate f _C , the high QRF filter formed by the first plurality of baseband impedances is converted to be more High expected Rf frequency, where f _C = (fLO ₁ + fLO ₂ )/2. Therefore, one of the high Q bandpass filters is centered on LO2 (or _fRF2 ) and the other high Q bandpass filter is centered on LO1 (or _fRF1 ). Thus, the first high Q bandpass filter passes the desired signal component of the inbound RF signal at LO2 (or _fRF2 ), and the second high Q bandpass filter passes the inbound RF signal at a frequency of LO1 (or _fRF1) The expected signal component. 64 is a schematic block diagram of a portion of an RF-IF receiver portion including a transformer, a variable capacitance network, a pair of inverter-based LNAs 395, a mixer, and an output temporary, in accordance with another embodiment of the present invention. Memory (or unity gain driver). The mixer includes a plurality of transistors, a pair of transimpedance amplifiers (TIAs) 622 and 624, and associated impedances (Z) 626 and 628.

In one running example, the LNA 395 provides differential currents (i _RF and -i _RF ) to the mixer. In the current domain, the mixer mixes the differential current with the differential I 630 component of the local oscillation (LO _IP and LO _IN ) to produce an I-mixed current signal. The mixer also Q632 differential current differential component (LO _QP and LO _QN) mixing a local oscillation signal to generate a current Q mixed.

The first TIAs 622 and 624 amplify the I-mixed current signals through the associated impedances (Z) 626 and 628 and produce a voltage domain I mixed signal. Similarly, the second TIA amplifies the Q-mixed current signal through the associated impedances (Z) 626 and 628 and produces a voltage domain Q-mixed signal.

Figure 65 is a schematic block diagram of a clock generator 634 for an RF-IF receiver section in accordance with another embodiment of the present invention. The clock generator (its various embodiments will be described with reference to at least one of the following figures) produces four clock signals (e.g., LO _IP , LO _IN , LO _{QP ,} and LO _QN ), each having a 25% duty cycle Ratio and phase shift by 90°.

Figure 66 is a schematic block diagram of a transimpedance amplifier (TIA) and corresponding impedances (Z) 640 and 642, in accordance with one embodiment of the present invention. The TIA includes a current source, a frequency dependent amplifier (-A(s), an IF transistor (T _IF ), and a low frequency transistor (T _LF ). The corresponding impedance in each output pin of the TIA includes resistors, capacitors, and transistors.

In a running example, the differential input current is received at in- and in+. Current node analysis of the negative input node (eg KCL-Kirchoff current law) shows that the current source current (ib) is equal to the input current (iI _N ) + the current through the capacitor (iC) + through the T _IF Current (i _OUT ) + current through T _LF . The positive input (out+) KVL (Kirchhoff voltage law) shows that the output voltage (Vout+) is equal to Vdd-Z*I _OUT (ie, the current through T _IF ).

At high frequencies (e.g., r _RF above the inbound RF signal), the impedance of the capacitor becomes dominant and the input is substantially reduced; therefore, the output current (i _OUT ) contains substantially no high frequency components. At low frequencies (e.g., below the R & lt inbound RF signal _RF), for T _IF amplifier configuration and a low-frequency transistor, T _IF for the low frequency current is substantially open. This can be achieved by changing the size of the transistor and biasing the amplifier so that the impedance of the T _LF at low frequencies is much smaller than Z+T _IF .

For the desired frequency (e.g., f _RF) within a frequency range, compared to the impedance of the impedance and the corresponding T _IF Z640,642, the capacitor having a higher impedance and T _LF. Therefore, iO _UT = i _b -i _IN and v _OUT = Z*i _OUT . Accordingly, the TIA and corresponding impedances Z640, 642 can be tuned to provide a high Q RF bandpass filter. Note that at least one component of the TIA can be adjusted by a control signal provided by the SOC processing resource to adjust the performance of the high Q bandpass filter.

Figure 67 is a schematic block diagram of a low noise amplifier (LNA) 670 that includes FTBPFs 650, 672, 674, and 678, in accordance with one embodiment of the present invention. The LNA 670 includes a current source, a pair of input transistors (T3 and T4), a pair of bias transistors (T1 and T2), and an output impedance (showing the resistance, but can also be an inductor, a transistor, a capacitor, and/or Combinations. Note that the current source can be replaced by passive devices (such as resistors, inductors, capacitors, and/or combinations thereof) or can be omitted. FTBPFs 650, 672, 674, and 678 can be located in LNA 670 as shown in the figure. position.

68 is a schematic block diagram of a differential 4-phase FTBPF (frequency conversion bandpass filter) 680 that includes a plurality of transistors and four baseband impedances (eg, Z _BB (s)) 682, 684, in accordance with an embodiment of the present invention. 686 and 688. The baseband impedances (Z _BB (s)) 682, 684, 686, and 688 together provide a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal (eg, LO ₁ -LO ₄ ) provided by the clock generator to produce a high QRF or IF filter. The differential high QRF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

Figure 69 is a schematic illustration of the frequency response of a 4-phase FTBPF 680 showing signal feedthrough harmonics and superimposed signal harmonics, in accordance with one embodiment of the present invention. The signal feedthrough harmonics 692 are at +/-3, +/-5, +/-7, and +/-9, and the superimposed signal harmonics 690 are at -3, -5, -7, and -9.

70 is a schematic block diagram of a 3-phase FTBPF (frequency conversion band pass filter) 700 including a plurality of transistors and three baseband impedances (eg, Z _BB (s)) 702, 704, and in accordance with another embodiment of the present invention. 706. The baseband impedances (Z _BB (s)) 702, 704, and 706 together provide a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

A clock signal (e.g., LO ₁ -LO _^) when provided by the clock generator shown in FIG. 71 by the low-Q baseband filter frequency of the desired RF frequency to produce a high Q RF or IF filter. The differential high Q RF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

Figure 72 is a schematic illustration of the frequency response of a 3-phase FTBPF 700 showing signal feedthrough harmonics and superimposed signal harmonics, in accordance with one embodiment of the present invention. The signal feedthrough harmonics 708 are at +/- 5 and +/- 7, and the superimposed signal harmonics 710 are at 5 and 7.

Figure 73 is a schematic block diagram of a 4-phase FTBPF (frequency conversion bandpass filter) 712 comprising a plurality of transistors and 4 capacitors in accordance with another embodiment of the present invention. These capacitors together provide a low Q baseband filter. Note that the capacitance of each capacitor can be the same, different, or a combination thereof. It is also noted that the capacitance of each capacitor can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (eg, bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal (eg, LO ₁ -LO ₄ ) provided by the clock generator to produce a high Q RF or IF filter. The differential high Q RF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

74 is a schematic block diagram of a 4-phase FTBPF (frequency conversion bandpass filter) 714 including a plurality of transistors and two baseband impedances connected to the transistors as shown (eg, Z, in accordance with another embodiment of the present invention). _BB (s)). The baseband impedance (Z _BB (s)) together provides a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal (eg, LO ₁ -LO ₄ ) provided by the clock generator to produce a high Q RF or IF filter. The differential high Q RF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

Figure 75 is a schematic block diagram of a 4-phase FTBPF (frequency conversion bandpass filter) 716 comprising a plurality of transistors and 4 baseband impedances (e.g., Z _BB (s)), in accordance with another embodiment of the present invention. The baseband impedance (Z _BB (s)) together provides a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal (eg, LO ₁ -LO ₄ ) provided by the clock generator to produce a high QRF or IF filter. The differential high QRF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

76 is a schematic block diagram of a 4-phase FTBPF (frequency conversion band pass filter) 720 including a plurality of transistors and a complex baseband impedance (eg, Z _{BB, C} (ω)) 722 _, in accordance with another embodiment of the present invention. . The complex baseband impedance provides a low Q baseband filter that is offset from 0 by wOC. Note that the complex baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (eg, bandwidth, attenuation rate, quality factor, frequency offset, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal (eg, LO ₁ -LO ₄ ) provided by the clock generator to produce a high QRF or IF filter. The differential high QRF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

Figure 77 is a schematic block diagram of complex baseband impedance for an FTBPF (Frequency Bandpass Filter), in accordance with one embodiment of the present invention. The complex baseband impedance 726 includes a first baseband impedance (eg, Z _BB (ω)), a negative gain stage (eg, -jGm(ω)V _IM (ω)), a second baseband impedance (eg, Z _BB (ω)), and a positive gain stage. (eg jGm(ω)V _RE (ω)). Therefore, the complex baseband impedance includes a real component (RE) and an imaginary component (IM). The complex baseband impedance provides a low Q bandpass filter with a frequency response as shown, where the real component is represented by a curve with w > 0 and the imaginary component is represented by a curve with w <

Figure 78 is a schematic block diagram of a 4-phase FTBPF (frequency conversion bandpass filter) including a complex baseband impedance that is implemented by a capacitor, in accordance with one embodiment of the present invention. The complex baseband impedance provides a low Q baseband filter 730 that is offset from 0 by wOC, which is dependent on the ratio between the gain (Gm) and the capacitive impedance (C _BB ). Note that the complex baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (eg, bandwidth, attenuation rate, quality factor, frequency offset, etc.). For example, the capacitance and/or gain modules can be adjusted.

The clock signal supplied by the clock generator (e.g., LO ₁ -LO ₄₎ low-Q baseband filter frequency offset converted to a desired RF frequency to produce a high Q RF or IF filter. The differential high Q RF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

Figure 79 is a schematic block diagram of an m-phase FTBPF (frequency conversion bandpass filter) 732 comprising a plurality of transistors and m capacitors, where m = > 2, in accordance with one embodiment of the present invention. These capacitors together provide a low Q baseband filter. Note that the capacitance of each capacitor can be the same, different, or a combination thereof. It is also noted that the capacitance of each capacitor can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (eg, bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal (eg, LO ₁ -LO ₄ ) provided by the clock generator to produce a high QRF or IF filter. The differential high QRF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

Figure 80 is a schematic block diagram of an m-phase FTBPF (frequency conversion bandpass filter) 734 comprising a plurality of transistors and m baseband impedances (e.g., Z _BB (s)), where m is 4, in accordance with one embodiment of the present invention. Integer multiple and greater than 4. The baseband impedance (Z _BB (s)) together provides a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal (eg, LO ₁ -LO _M ) provided by the clock generator to produce a high QRF or IF filter. The differential high QRF filter filters the differential I signal component and the differential Q signal component of the IF signal such that the desired signal component of the IF signal is transmitted substantially un-attenuated and the undesired signal component (eg, block, mirror, etc.) is attenuated.

Figure 81 is a schematic block diagram of an m-phase FTBPF (frequency conversion bandpass filter) 736 including a plurality of transistors and m/2 baseband impedances (e.g., Z _BB (s)), where m is included, in accordance with one embodiment of the present invention. Greater than or equal to 4. The baseband impedance (Z _BB (s)) together provides a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal (eg, LO ₁ -LO ₄ ) provided by the clock generator to produce a high QRF or IF filter. The differential high QRF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

82 is a schematic block diagram of an m-phase FTBPF (frequency conversion bandpass filter) 738 including a plurality of transistors and m baseband impedances (eg, Z _BB (s)), where m is greater than or equal to, in accordance with an embodiment of the present invention. 2. The baseband impedance (Z _BB (s)) together provides a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal (eg, LO ₁ -LO ₄ ) provided by the clock generator to produce a high QRF or IF filter. The differential high QRF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

Figure 83 is a schematic block diagram of a single-ended m-phase FTBPF (frequency conversion bandpass filter) 740 comprising a plurality of transistors and m baseband impedances (e.g., Z _BB (s)), where m is included, in accordance with one embodiment of the present invention. Greater than or equal to 2. The baseband impedance (Z _BB (s)) together provides a low Q baseband filter, where each baseband impedance can be a capacitor, a switched capacitor filter, a switched capacitor resistor, and/or a complex impedance, respectively. Note that the impedance of each baseband impedance can be the same, different, or a combination thereof. It is also noted that the impedance of each baseband impedance can be adjusted by control signals from the SOC processing resources to adjust the performance of the low Q baseband filter (e.g., bandwidth, attenuation rate, quality factor, etc.).

The low Q baseband filter is frequency converted to the desired RF frequency by a clock signal (eg, LO ₁ -LO ₄ ) provided by the clock generator to produce a high QRF or IF filter. The differential high QRF filter filters the differential RF or IF signal such that the desired signal component of the RF or IF signal is transmitted substantially un-attenuated and the unwanted signal components (eg, block, mirror, etc.) are attenuated.

FIG 84 is a schematic diagram of the phase frequency response 740 m FTBPF according to an embodiment of the present invention, showing low Q bandpass filter is converted to a higher frequency (e.g., f _LO). f _LO corresponds to RF frequency, IF frequency, local oscillation, or a combination thereof.

Figure 85 is a schematic block diagram of a clock generator 750 for an m-phase FTBPF, in accordance with one embodiment of the present invention. The clock generator includes a plurality of flip flops (DFF) 752, 754, and 756 and a plurality of pulse narrowers 758, 760, and 762. Flip-flops 752, 754, and 756 are synchronized with a clock signal (clk) and a clock gate signal (clkb) at a rate of m*f _RF . The clock pulses obtained from each of the flip flops 752, 754 and 756 are pulse narrowed by the respective pulse constrictors.

Pulse narrowers 758, 760 and 762 comprise two pairs of transistors connected as shown. left The transistor below the side is smaller than the other transistors, making the rising edge time slower than the falling edge time, thereby narrowing the pulse.

Figure 86 is a schematic block diagram of a clock generator 770 for an m-phase FTBPF, in accordance with another embodiment of the present invention. The clock generator includes a plurality of flip flops (DFF) 772, 774, and 776 and a plurality of AND gates. Flip-flops 772, 774, and 776 are synchronized with a clock signal (clk) and a clock gate signal (clkb) at a rate of (1/2)*m*f _RF . The AND gate receives the non-inverted output from the first flip-flop 772 and the inverted output from the next flip-flop 774 to ensure that successive clock pulses do not overlap.

Figure 87 is a schematic block diagram of a clock generator 790 for an m-phase FTBPF, in accordance with another embodiment of the present invention. The clock generator includes a ring oscillator 792 and a plurality of logic circuits. Each logic circuit includes a gate and an inverter or a register. The gate value of the ring oscillator 792 is the clock rate m*f _RF (m is an odd number which is equal to or greater than 3). Each logic circuit receives successive pulses from ring oscillator 792 such that successive clock pulses do not overlap.

Figure 88 is a schematic block diagram of a clock generator 800 for a 3-phase FTBPF that includes a ring oscillator 792 and a plurality of logic circuits, in accordance with one embodiment of the present invention. Each logic circuit includes a combination of a gate and a register and/or an inverter. For example, each logic circuit includes a gate, an inverter, and a register. The gate of the ring oscillator 792 is gated at a clock rate of 3*f _RF . Through the logic circuit, the AND gate is biased to produce a 1/3 duty cycle non-overlapping clock (eg, clk 1 802, clk 2 806, and clk 3 804).

Figure 89 is a schematic block diagram of a clock generator 810 for a 3-phase FTBPF that includes two ring oscillators 792 and a plurality of logic gates in accordance with another embodiment of the present invention. Each logic circuit includes a combination of a gate and a register and/or an inverter. For example, each logic circuit includes a gate, an inverter, and a register. A first ring oscillator clock rate of the gate 792 is 3 * f _RF, the second ring oscillator gate 792 is inverted 3 * f _RF (Inversion) (e.g. -3 * f _RF). In this configuration, clock signals 1-3812, 814, and 816 are as shown in FIG. 88, and clock signals 4-6818, 820, and 822 are the inverse of clock signals 1-3, respectively.

Figure 90 is a schematic block diagram of a portion of a front end module (FEM) 810 and a portion of a SOC 812, in accordance with one embodiment of the present invention. This portion of the FEM 810 includes a power amplifier module (PA) 814, a duplexer, a balanced network 818, and a common mode sensing circuit. The duplexer includes a transformer (or other structure, such as a frequency selectable duplexer and/or an electronically balanced duplexer), and the balanced network 818 includes at least one variable resistor and at least one variable capacitor. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. This portion of SOC 812 includes peak detector 820, tuning engine 822, and low noise amplifier module (LNA). Alternatively, peak detector 820 and/or tuning engine 822 may be located in FEM 810.

In one operating example, the PA 814 provides an outbound RF signal to the center tap of the primary double coil of the transformer. Depending on the impedance difference between the antenna and the balanced network 818, the current of the outbound RF signal is split between the two coils. If the impedance of the balanced network 818 substantially matches the antenna impedance, the current is substantially evenly split to the two coils.

With the coil configuration as shown, if the currents of the primary coils are substantially equal, then their magnetic fields in the secondary coils substantially cancel each other out. Therefore, the secondary outbound RF signal is substantially attenuated. For an inbound RF signal, the primary two coils generate a magnetic field based on the current of the inbound RF signal. At this point, the magnetic field is increased, thus producing twice the current in the secondary relative to the primary (assuming each coil has the same number of turns). Therefore, the transformer amplifies the inbound RF signal.

If the antenna impedance does not match the impedance of the balanced network 818, an outbound RF signal current component (e.g., TX leakage) will appear in the secondary. For example, assuming that the current flowing from the coil to the inductor is i _P1 and the current flowing from the coil to the balanced network 818 is i _P2 , the amount of TX leakage can be expressed as i _P1 -i _P2 . The resistance of the common mode induced current senses the amount of TX leakage. For example, the voltage at the center node of the resistor is equal to VS-(R ₁ *2i _R +R ₁ *i _P2 -R ₂ *i _P1 ), where VS is the secondary voltage and 2i _R is the received inbound RF signal Current. Assuming R ₁ =R ₂ and i _P1 =i _P2 , the voltage at the center node is equal to 1/2 of VS. However, if i _{P1 is} not equal to i _P2 , the voltage at the center node of the resistor will deviate from 1/2 VS, and the amount of deviation is proportional to the difference.

Detector 820 detects that the voltage at the center node of the resistor deviates from the difference of 1/2 VS and provides an arithmetic expression of the difference to tuning engine 822. Tuning engine 822 parses the difference and generates a control signal to adjust the impedance of the balanced network. For example, if i _P1 >i _P2 , the voltage of the common mode sensing circuit (eg, the center node of the resistor) will be greater than 1/2 VS, which indicates that the impedance of the balanced network 818 is too large. Thus, tuning engine 822 generates control signals to reduce the impedance of balanced network 818. For another example, if i _P1 <i _P2 , the voltage of the common mode sensing circuit will be less than 1/2 VS, which means that the impedance of the balanced network is too small. Thus, tuning engine 822 generates control signals to increase the impedance of balanced network 818.

Tuning engine 822 can resolve the common mode voltage deviation, determine the desired impedance of balanced network 818, and generate control signals accordingly. Alternatively, tuning engine 822 can iteratively generate control signals to gradually adjust the impedance of balanced network 818 until the desired impedance is obtained. Using any method, the function of the tuning engine 822 is to maintain the impedance of the balanced network 818 substantially matched to the impedance of the antenna (changes over time, usage, and/or environmental conditions) to minimize the amount of TX leakage.

91 is a schematic block diagram of a partial front end module (FEM) 830 and a portion of SOC 832, in accordance with another embodiment of the present invention. This portion of the FEM 830 includes a power amplifier module (PA) 836, a duplexer 838, a balanced network 842, an antenna tuning unit (ATU) 840, and a common mode sensing circuit. Duplexer 838 includes a transformer (or other structure, such as frequency selectable duplexer 838 and/or electronically balanced duplexer 838) that includes at least one variable resistor and at least one variable capacitor. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. This portion of SOC 832 includes peak detector 848, tuning engine 850, lookup table (LUT) 844, processing module 846, and low noise amplifier module (LNA) 852. Alternatively, peak detector 848 and/or tuning engine 850 can be located in FEM 830.

In addition to the functionality provided by the common mode sensing circuit (i.e., resistor), detector 848, tuning engine 850, and balance network 842 for balancing the impedance of the balanced network 842 with the antenna impedance (as described with reference to Figure 90), The FEM 830 also includes the ATU 840. ATU 840 includes one or more fixed passive components and/or one or more variable passive elements Pieces. For example, the ATU 840 can include a variable capacitance-inductor circuit, a variable capacitance, a variable inductance, and the like.

In one operational example, the PA 836 provides an amplified outbound RF signal to a duplexer 838 that includes a transformer as described with reference to FIG. The duplexer 838 outputs the amplified outbound RF signal to the ATU 840, tuning the ATU 840 through settings stored in the LUT 844 to provide the desired antenna matching circuitry (e.g., impedance matching, quality factor, bandwidth, etc.). The ATU 840 outputs the outbound RF signal to the antenna for transmission.

For an inbound RF signal, the antenna receives the signal and provides it to the ATU 840, which in turn provides it to the duplexer 838. The duplexer 838 outputs the inbound RF signal to the LNA 852 and the common mode sensing circuit. The functions of the common mode sensing circuit, detector 848, tuning engine 850, and balancing network 842 are as described above with reference to FIG.

Processing module 846 is used to monitor various parameters of FEM 830. For example, the processing module 846 can monitor antenna impedance, transmit power, performance of the PA 836 (eg, gain, linearity, bandwidth, efficiency, noise, output dynamic range, swing rate, rise rate, settling time, overshoot, stability) Factor, etc.), received signal strength, SNR, SIR, adjustments made by the tuning engine 850, and the like. Processing module 846 parses these parameters to determine if the performance of FEM 830 can be further optimized. For example, the processing module 846 can determine that adjusting the ATU 840 can improve the performance of the PA 836. At this point, processing module 846 addresses LUT 844 to provide the desired settings for ATU 840. If such a change in ATU 840 affects the impedance balance between ATU 840 and balanced network 842, tuning engine 850 will make the appropriate adjustments.

In another embodiment, the processing module 846 provides the functionality of the tuning engine 850 and adjusts the balance of the ATU 840 and the balancing network 842 to achieve the desired performance of the FEM 830. In yet another embodiment, the balancing network 842 is fixed and the ATU 840 provides the desired adjustments in the FEM 830 to achieve impedance balancing and achieve the desired performance of the FEM 830.

Figure 92 is a diagram for 2G and 3G cellular operation in accordance with another embodiment of the present invention. A schematic block diagram of a portion of the front end module (FEM) 860 and a portion of the SOC 862. This part of the FEM 860 includes a power amplifier module (PA) 866, a duplexer, a balanced network, and a common mode sensing circuit. The duplexer includes a transformer (or other structure, such as a frequency selectable duplexer and/or an electronically balanced duplexer), and the balanced network includes a switch, at least one variable resistor, and at least one variable capacitor. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. This portion of SOC 862 includes peak detector 872, tuning engine 874, switches, and low noise amplifier module (LNA) 876. Alternatively, peak detector 872 and/or tuning engine 874 may be located in FEM 860.

In this embodiment, the duplexer is best suited for Frequency Division Duplex (FDD), which is used in 3G cellular telephone applications and where the balanced network switch and LNA 876 switch are open. In Time Division Duplex (TDD) for 2G cellular applications, the balanced network is shorted by a switch. This substantially eliminates the 3-dB theoretical insertion loss limit and leaves only implementation loss. Note that for 2G transmissions, the LNA 876 switch is off, and for 2G reception, the LNA 876 switch is turned on. Note also that for the 3G mode, the functions of the FEM and SOC 862 are as described with reference to Figures 90 and/or 91.

Figure 93 is a schematic block diagram of a portion of a front end module (FEM) 860 and a portion of a SOC 862 shown in Figure 92 in a 2G TX mode, in accordance with one embodiment of the present invention. In this mode, the LNA 876 switch shorts the LNA 876 and the balanced network switch shorts the balanced network. Due to the short circuit across the secondary coil, the primary coil is also substantially shorted. Therefore, the PA 866 is efficiently connected directly to the antenna.

Figure 94 is a schematic block diagram of a portion of a front end module (FEM) 860 and a portion of a SOC 862 shown in Figure 92 in a 2G RX mode, in accordance with one embodiment of the present invention. In this mode, the LNA switch is turned on and the balanced network switch is turned off, thus shorting the balanced network. In this configuration, the transformer functions as a balun transformer for the receiver section.

Figure 95 is a schematic block diagram of a small signal balancing network 880 that includes a plurality of transistors, a plurality of resistors, and a plurality of capacitors, in accordance with one embodiment of the present invention. The selection of the resistors included in the balanced network can be controlled by a multi-bit signal (eg 10 bits), and the selection of the capacitance contained in the balanced network can be made by another multi-bit signal (eg 5 bits) Take control.

For example, if the resistive side of the balanced network includes four resistor-transistor circuits, the common node of one of the resistor-transistor circuits is coupled to the gate of the next resistor-transistor circuit. In this example, each gate is also connected to receive a 4-bit bit control signal. For example, the gate of the leftmost resistor-transistor circuit receives the most significant bit, the next leftmost resistor-transistor circuit receives the second most significant bit, and so on. In addition, the resistance of the leftmost resistor-transistor circuit is R4, the resistance of the next leftmost resistor-transistor circuit is R3, and so on. Thus, for example, when the 4-bit control signal is 0001, only the rightmost resistor-transistor circuit is turned on, and its resistor R1 provides the final resistance. When the 4-bit control signal is 0011, the two rightmost resistance-transistor circuits are turned on, and the final resistance is R1//R2. When the 4-bit control signal is 0111, the three rightmost resistance-transistor circuits are turned on, and the final resistance is R1//R2//R3. When the 4-bit control signal is 1111, all four resistor-transistor circuits are turned on and the final resistance is R1//R2//R3//R4. The capacitive side function of the balanced network is similar.

In another embodiment, each of the resistive-transistor circuitry and each of the capacitor-transistor circuitry can be independently controlled by the bits of the respective control signal. For the four-resistor-transistor circuit configuration described in the above figures and modified herein, control signal 1000 produces resistor R4; control signal 0100 produces resistor R3; control signal 1010 produces resistor R4//R2; and so on.

Figure 96 is a schematic block diagram of a large signal balancing network 882 that includes an RLC (resistor-inductor-capacitor) network and a plurality of transistors, in accordance with one embodiment of the present invention. The transistor is gated on and off to provide a different combination of resistance, inductance and/or capacitance of the RLC network to achieve the desired balanced network impedance. At this point, the transistor has a relatively small voltage swing, so a lower voltage transistor can be used.

Figure 97 is a schematic block diagram of a portion of a front end module (FEM) 890 and a portion of a SOC 892, in accordance with another embodiment of the present invention. This portion of the FEM 890 includes a power amplifier module (PA) 896, a duplexer 898, a balanced network 900, and a common mode sensing circuit. Duplex The 898 includes a transformer (or other structure, such as a frequency selectable duplexer 898 and/or an electronically balanced duplexer 898) that includes at least one variable resistor and at least one variable capacitor. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. This portion of the SOC includes a peak detector 902, a tuning engine 904, a leak detection 906 module, and a low noise amplifier module (LNA) 908. Alternatively, peak detector 902, leakage amount detection 906 module, and/or tuning engine 904 may be located in FEM 890.

The function of this embodiment is similar to the embodiment shown in Fig. 90 except for the leak amount detecting 906 module. The leakage module is used to detect changes in the transistor on-resistance of the circuit in the balanced network 900 based on the PA 896 output. For example, if the PA 896 output is increased, it will cause the transistor on-resistance in the balanced network 900 to change. This change affects the overall impedance of the balancing network 900. Accordingly, the leak detection 906 module detects an on-resistance change and provides a representative signal to the tuning engine 904 and/or processing module (as shown in FIG. 91).

Tuning engine 904 adjusts the impedance of balancing network 900 based on the amount of leakage detection 906 module input. Alternatively or in addition, the processing module uses the input from the leak detection 906 module to adjust the ATU settings. Regardless of which particular method is employed, the variation in the on-resistance of the transistors in the transistor and/or the power amplifier in the balanced network 900 is compensated.

Figure 98 is a schematic block diagram of a portion of a front end module (FEM) 910 and a portion of a SOC 912, in accordance with another embodiment of the present invention. This portion of the FEM 910 includes a power amplifier module (PA) 916, a duplexer 918, a balanced network 920, and a common mode sensing circuit. The duplexer 918 includes a transformer (or other structure, such as a frequency selectable duplexer 918 and/or an electronically balanced duplexer 918) that includes at least one variable resistor and at least one variable capacitor. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. This portion of SOC 912 includes peak detector 922, processing module 926 (which includes the functionality of the tuning engine), and low noise amplifier module (LNA) 924. Alternatively, peak detector 922 and/or tuning engine may be located in FEM 910.

For the ability to adjust the TX attenuation and/or RX gain of duplexer 918, the functionality of this embodiment is similar to the embodiment shown in FIG. For example, when the transmit power is relatively low (eg, the blockage of the inbound RF signal is small and/or the signal strength of the inbound RF signal is relatively high), the processing module 926 provides a signal to the duplexer 918 to enable duplexing. The 918 reduces TX attenuation, thereby reducing insertion loss.

For example, if the duplexer 918 includes a transformer and/or other type of frequency selective duplexer 918 as shown in FIG. 90, a partial filter can be shorted to increase losses at the expense of reduced separation. As another example, if the duplexer 918 includes an electronically balanced duplexer, the separation can be balanced with the separation of the balanced network.

Figure 99 is a schematic block diagram of a portion of a front end module (FEM) 930 and a portion of a SOC 932, in accordance with another embodiment of the present invention. This portion of the FEM 930 includes a power amplifier module (PA) 936, a duplexer 938, and a balancing network 940. The duplexer 938 includes a transformer (or other structure, such as frequency selectable duplexer 938 and/or electronically balanced duplexer 938), parasitic capacitance and compensation capacitance, and the balanced network includes at least one variable resistor and at least one variable capacitance. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. This portion of the SOC 932 includes a peak detector, a processing module (including the functionality of the tuning engine), and a low noise amplifier module (LNA) 940. Only the LNA 940 is shown.

In this embodiment, the compensation capacitance is increased to compensate for the mismatch of parasitic capacitances (e.g., Cp1 and Cp2) due to the mismatch between the primary coils (e.g., L1 and L2). Therefore, the compensation capacitors (Cc1 and Cc2) are selected such that Cp1+Cc1=Cp2+Cc2. After the compensation capacitor is increased, the separation bandwidth of the duplexer 938 is greater than the separation bandwidth when there is no compensation capacitor.

100 is a schematic block diagram of a portion of a front end module (FEM) 950 and a portion of an LNA 952, in accordance with another embodiment of the present invention. This portion of the FEM 950 includes a power amplifier module (PA) 954, a duplexer 956, and a balanced network 958. The duplexer 956 includes a transformer (or other structure, such as a frequency selectable duplexer and/or an electronically balanced duplexer 956) having parasitic capacitances (Cp3 and Cp4). LNA 952 includes an input transistor, Bias transistor, inductor (L3) and load impedance (Z), where the input transistor has a parasitic capacitance (Cp). Since L3 is included in the LNA 952, the common mode spacing of the duplexer 956 and the LNA 952 is improved compared to the conventional LNA 952 input configuration.

Figure 101 is a schematic block diagram of an equivalent circuit of a portion of the front end module (FEM) and a portion of the LNA shown in Figure 100, in accordance with one embodiment of the present invention. This schematic shows how the common mode spacing is improved. The unbalanced current connected to the secondary winding (L) through the parasitic capacitances (Cp3 and Cp4) of the transformer is connected to different resonant circuits formed by the inductance (L3) and the parasitic capacitance of the input transistor. The resonant circuit provides high differential impedance and low common mode impedance.

Figure 102 is a schematic block diagram of a portion of a front end module (FEM) 960 and a portion of a SOC 962, in accordance with another embodiment of the present invention. This part of the FEM 960 includes a power amplifier module (PA), a duplexer, a balanced network 970, and a common mode sensing circuit. The duplexer includes a transformer (or other structure, such as a frequency selectable duplexer and/or an electronically balanced duplexer), and the balanced network includes at least one variable resistor and at least one variable capacitor. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. This portion of SOC 962 includes peak detector 974, processing module 976 (which includes the functionality of the tuning engine), and single-ended low noise amplifier module (LNA) 972. Alternatively, peak detector 974 and/or tuning engine may be located in FEM 960.

In this embodiment, the common mode spacing is substantially eliminated by using a single-ended LNA 972. The functions of the FEM 960 and other parts of the SOC 962 shown in the figure are as described above.

Figure 103 is a schematic block diagram of a transformer of a duplexer in accordance with one embodiment of the present invention. The transformer includes a primary coil (L1 & L2) and a secondary coil (L2). The primary coils each have the same number of turns; the secondary coils can have the same number of turns or different turns as the primary coil. The winding of the coil is as shown.

Figure 104 is a schematic illustration of an implementation of a transformer implemented on four thick metal layers of an IC package substrate and/or integrated circuit on a printed circuit board, in accordance with one embodiment of the present invention. The primary coil is on the upper two layers and the secondary coil is on the lower two layers. The first coil of the secondary on one layer can be connected in series or in parallel with other coils on the other layers.

Figure 105 is a schematic illustration of an implementation of a transformer on three thick metal layers of an IC package substrate and/or an IC on a printed circuit board, in accordance with one embodiment of the present invention. The primary coil is on the top layer and the next layer is used for interconnection. At least one primary coil can be rotated by 90°. The secondary coil is located on the third layer below.

Figure 106 is a schematic block diagram of a portion of a front end module (FEM) 990 and a portion of a SOC 992, in accordance with another embodiment of the present invention. This portion of the FEM 990 includes a power amplifier module (PA) 994, a duplexer 996, a balanced network 1000, a tone injection module 998, and a common mode sensing circuit. The duplexer 996 includes a transformer (or other structure, such as a frequency selectable duplexer 996 and/or an electronically balanced duplexer 996) that includes at least one variable resistor and at least one variable capacitor. The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. This portion of SOC 962 includes peak detector 1002, processing module 1004 (which includes the functionality of the tuning engine), a baseband processing unit, and a low noise amplifier module (LNA) 1006. Alternatively, peak detector 1002 and/or tuning engine may be located in FEM 990.

In one example of operation, the functions of the common mode sensing circuit, tuning engine, detector 1002, and balancing network 1000 are as described above. In many cases, these components reduce transmitter (TX) and/or receiver (RX) noise when the receiver band is below or equal to the LNA 1006 noise platform. When the TX and / or RX noise is at or below the noise platform, it is difficult to track, making it difficult to track the impedance of the antenna.

To enhance tracking of the antenna impedance, the tone module 998 injects a tone (eg, Acos(ω _{RX_RF} (t))) into the receiver band. The duplexer 996 attenuates the RX tone differently than the TX signal because it is located in the RX band and the duplexer 996 and the balanced network 1000 can be tuned for the TX band. Therefore, an easily detectable leakage signal is generated on the RX side of the duplexer 996 (e.g., on the secondary of the transformer).

The leakage signal based on the RX tone propagates through the receiver section until it is converted to a baseband signal. At baseband, the pitch amplitude is a measure of the RX band spacing. Based on the measured values of the RX band spacing, the impedance of the antenna can be determined. As the impedance of the antenna changes, the antenna tuning unit and/or the balance network 1000 can be adjusted to track the resistance of the antenna. anti. Note that the tone can be easily removed at the baseband.

Figure 107 is a schematic block diagram of a portion of a front end module (FEM) 1010 and a portion of a SOC 1012, in accordance with another embodiment of the present invention. This portion of the FEM 1010 includes a power amplifier module (PA) 1014, a duplexer 1016, a balanced network 1018, and a common mode sensing circuit (not shown). The duplexer 1016 includes a transformer (or other structure, such as a frequency selectable duplexer 1016 and/or an electronically balanced duplexer 1016). The common mode sensing circuit includes a pair of resistors connected between the secondary of the transformer. This portion of SOC 1012 includes peak detector 1002 (not shown), processing module 1020 (which performs the functions of the tuning engine), and low noise amplifier module (LNA) 1022. Alternatively, peak detector 1002 and/or tuning engine may be located in FEM 1010.

The balanced network 1018 includes an RLC network having a plurality of variable resistors, a plurality of variable capacitors, and at least one inductor. In this embodiment, the balanced network 1018 can be tuned to provide a substantially variable impedance to better match the antenna impedance.

Figure 108 is a schematic block diagram of the impedance of a resistive-transistor (R-T) circuit of a balanced network, in accordance with one embodiment of the present invention. The capacitance is equivalent to the parasitic capacitance of the transistor. Since the R-T circuit includes a true passive resistor, it can contribute to the 3dB theoretical limit on insertion loss.

Figure 109 is a schematic block diagram of the impedance of a resistive-transistor (R-T) circuit of a balanced network in accordance with another embodiment of the present invention. In this embodiment, the R-T circuit includes an inductively weakened common source transistor. Therefore, it is an active resistor that does not contribute to the 3dB theoretical limit on insertion loss. Therefore, the only loss in the balanced network is the implementation loss.

Figure 110 is a schematic block diagram of a balanced network 1030 that includes an impedance upconverter 1032 and one or more baseband impedances (Zbb 1034), in accordance with one embodiment of the present invention. The impedance upconverter is synchronized to the desired frequency (eg f _LO or f _RF ). The combination of impedance upconverter 1032 and baseband impedance can be implemented in a manner similar to the m-phase variable frequency bandpass filter described above.

Figure 111 is a schematic block diagram of a balanced network including two impedance upconverters 1042, 1044 and corresponding baseband impedances (Zbb 1046, 1048) in accordance with another embodiment of the present invention. Each impedance upconverter is synchronized to a desired frequency (eg, f _{RF_TX} or f _{RF_RX} ). Each combination of impedance upconverters 1042, 1044 and one or more baseband impedances can be implemented in a manner similar to the m-phase variable frequency bandpass filter described above.

Figure 112 is a schematic block diagram of a negative impedance 1050 for balancing a network, in accordance with one embodiment of the present invention. The circuit includes a baseband negative impedance 1050 circuit, such as shown in Figure 56, and the upconverter 1052 can be implemented in a manner similar to the m-phase variable frequency bandpass filter described above.

113 is a schematic block diagram of a polarization receiver 1060 that includes a phase locked loop (PLL) 1068, an analog to digital converter (ADC 1064, 1066), a phase processing module 1062, and a peak detector 1070, in accordance with an embodiment of the present invention. And amplitude processing module 1062. The PLL 1068 includes a phase and frequency detector (PFD), a charge pump, a loop filter, a voltage controlled oscillator (VCO), a frequency divider (which can be a 1:1 divider), a summing module, and a modulator ( Sigma-delta) module.

In an operational example, the antenna receives an inbound RF signal (eg, A(t)cos(w _RF (t) + θ(t))) and provides it to the PLL of the receiver via FEM (not shown). 1068 and peak detector 1070. Peak detector 1070 (possibly an envelope detector) separates the amplitude term (eg, A(t)). The amplitude term is then converted to a digital signal by ADCs 1064, 1066. The PLL 1068 processes cos(ω _RF (t) + θ(t)) of the inbound RF signal to extract a phase signal (eg, θ(t)). The processing module 1062 parses the amplitude signal and the phase signal to recover the transmitted data.

Figure 114 is a schematic block diagram of a scratchpad circuit that can be used to connect a local oscillator PLL 1082 to a mixer of a downconversion mixing module and/or an upconversion mixing mode, in accordance with one embodiment of the present invention. group. The scratchpad circuit includes a differential register and a braided connection 1086. The braided connection 1086 produces an increased inductance (relative to the parallel line), thereby attenuating undesirable high frequency components to the mixer. In addition, the size and nature of the braided connection 1086 can be selected to achieve the desired inter-line capacitance, thereby producing a tone Harmonic and distributed L-C circuit.

Figure 115 is a schematic block diagram of an interleaved connection 1100 that includes a first line on one layer of a substrate (e.g., a die, a package substrate, etc.) and another line on another layer of the substrate, in accordance with one embodiment of the present invention. These lines are interleaved on two layers to increase magnetic coupling with each other. Additionally, at least one of the lines may include an inductive loop to increase its inductance.

Figure 116 is a schematic block diagram of a receiver including an input, a downconversion mixing section, and a transimpedance amplifier (TIA 1126, 1128), in accordance with one embodiment of the present invention. The input unit includes a MN 1112, a gain module, an inductor, and a capacitor. The downconversion mixing section includes a mixer and a local oscillator. The TIAs 1126 and 1128 respectively include a transistor and a resistor connected as shown. Note that the positive input can also be connected to the common node between the resistor and the transistor on the positive output, and the negative input can also be connected to the common node between the resistor and the transistor on the negative output.

As used herein, the term "substantially" or "approximately" provides an industry-accepted tolerance for the relationship between the respective terms and/or components. Such industry accepted tolerances range from less than 1% to 50% and correspond to, but are not limited to, component values, integrated circuit processing fluctuations, temperature fluctuations, rise and fall times, and/or thermal noise. The relationship between components varies from a small percentage difference to a large difference. Also, as used herein, the terms "operably connected," "connected," and/or "coupled" are meant to include an intermediate element (eg, including, but not limited to, elements, elements, circuits, and/or modules) A direct connection and/or an indirect connection, wherein for an indirect connection, the intermediate insertion element does not change the information of the signal, but its current level, voltage level and/or power level can be adjusted. It is also possible herein to infer that a connection (i.e., one element is connected to another element by inference) includes direct and indirect connection between two elements by the same method as "operably connected." As may also be used herein, the term "operably connected" indicates that the element includes one or more of the following: a power connection, an input, an output, etc., for performing one or more corresponding functions at startup and may further include one or Inferred connections for multiple other components. This article may also be used, the term "related", as this It is possible to use a single element and/or a direct and/or indirect connection of an element embedded in another element. As may also be used herein, the term "comparative results are advantageous", as may be used herein, to mean that a comparison between two or more elements, signals, etc. provides a desired relationship. For example, when the desired relationship is that signal 1 has a magnitude greater than signal 2, an advantageous comparison can be obtained when the magnitude of signal 1 is greater than the amplitude of signal 2 or the amplitude of signal 2 is less than the amplitude of signal 1.

Although the transistor shown in the above figures is a field effect transistor (FET), it will be understood by those skilled in the art that the above transistor may use any type of transistor structure including, but not limited to, bipolar, metal oxide. Semiconductor field effect transistor (MOSFET), N-well transistor, P-well transistor, enhanced, depletion mode, and zero voltage threshold (VT) transistor.

The invention has been described above by means of method steps illustrating the specified functions and relationships. For the convenience of description, the boundaries and order of these functional component modules and method steps are specifically defined herein. However, as long as a given function and relationship can be properly implemented, changes in boundaries and order are allowed. The boundaries or order of any such variations are considered to be within the scope of the appended claims.

The invention has been described at least in part by means of one or more embodiments. The embodiments of the invention used herein are illustrative of the aspects, features, concepts and/or examples of the invention. Physical embodiments constituting the apparatus, manufacturing method, machine, and/or step of the present invention may include at least one of the aspects, features, concepts, examples, and the like described with reference to at least one embodiment described herein.

The invention has also been described above with the aid of functional modules that illustrate certain important functions. For the convenience of description, the boundaries of these functional component modules are specifically defined herein. When these important functions are properly implemented, it is permissible to change their boundaries. Similarly, flowchart modules are also specifically defined herein to illustrate certain important functions. For a wide range of applications, the boundaries and order of the flowchart modules can be additionally defined as long as these important functions are still implemented. Variations in the boundaries and sequence of the above-described functional modules and flow-through functional modules are still considered to be within the scope of the claims. Technical in the field Personnel are also aware of the functional modules described herein, as well as other illustrative modules, modules, and components, which may be, for example, or by discrete components, integrated circuits of special functions, processors with appropriate software, and the like. The device is combined.

10‧‧‧Portable computing communication device

12‧‧‧System on a Chip (SOC)

14‧‧‧ Front End Module (FEM)

16‧‧‧Antenna

18‧‧‧No surface acoustic wave receiver

20‧‧‧No surface acoustic wave transmitter

22‧‧‧Baseband processing unit

24‧‧‧Processing module

26‧‧‧Power Management Unit

28‧‧‧ Receiver (RX) Radio Frequency (RF) - Intermediate Frequency (IF) Department

30‧‧‧Receiver (RX) IF-Baseband (BB)

32‧‧‧Variable Bandpass Filter (FTBPF)

34-36‧‧‧Power Amplifier (PA)

38-40‧‧‧Receiver-transmitter (RX-TX) separation module

42-44‧‧‧Antenna Tuning Unit (ATU)

46‧‧‧Band (FB) switcher

Claims (10)

A portable computing device comprising: a front end module coupled to the antenna portion and configured to separate one or more outbound radio frequency signals from one or more inbound radio frequency signals; a surface acoustic wave receiver for: passing The following steps convert the one or more inbound RF signals into one or more inbound IF signals: frequency conversion of the baseband filter response to an IF filter response or an RF filter response, wherein the frequency of the baseband filter response Transforming is used to adequately filter out-of-band blocking and filtering image signals that have a non-negligible effect on the desired signal of the one or more inbound IF signals; when the baseband filter is responsive to the RF filter Filtering the one or more inbound radio frequency signals in response to the RF filter response; and filtering the filter according to the intermediate frequency filter response when the baseband filter response is converted to the intermediate frequency filter response Decoding one or more inbound IF signals; and converting the one or more inbound radio frequency signals into one or more inbound symbol streams; no surface acoustic wave transmitter, Converting one or more outbound symbol streams into the one or more outbound radio frequency signals; and a baseband processing unit for: converting outbound data to the one or more outbound symbol streams; The one or more inbound symbol streams are converted to inbound data. The portable computing device of claim 1, further comprising: the front end module is further configured to use one or more second inbound radio frequency signals Separating one or more second outbound radio frequency signals, wherein the one or more inbound and outbound radio frequency signals are in a first frequency band, and the one or more second inbound radio frequency signals are in a second frequency band The surfaceless acoustic wave receiver is further configured to: convert the one or more second inbound radio frequency signals into one or more second inbound intermediate frequency signals by: step of: responding to the second baseband filter Converting to at least one of a second intermediate frequency filter response and a second RF filter response; filtering the second RF filter response when the second baseband filter responds to the second RF filter response The one or more second inbound radio frequency signals; and filtering the one or more according to the second intermediate frequency filter response when the second baseband filter is responsive to the second intermediate frequency filter response a plurality of second inbound intermediate frequency signals; and converting the one or more second inbound intermediate frequency signals into one or more second inbound symbol streams; the surfaceless acoustic wave transmitter is further configured to Or multiple second out Converting the symbol stream to the one or more second outbound radio frequency signals; and the baseband processing unit is further configured to: convert the second outbound data to the one or more second outbound symbol streams; The one or more second inbound symbol streams are converted to a second inbound material. The portable computing device of claim 1, wherein the front end module comprises: an antenna tuning unit coupled to the antenna portion and tuned for providing impedance matching with the antenna portion Impedance; one or more power amplifiers for amplifying the one or more outbounds Radio frequency signals to generate one or more amplified outbound radio frequency signals; a separation module coupled to the surfaceless wave receiver, the antenna tuning unit, and the one or more power amplifiers, the separation module Outputting the one or more amplified outbound radio frequency signals to the antenna tuning unit; and attenuating the one or more amplified outputs in a connection of the separation module to the surfaceless wave receiver The station RF signal thereby separating the one or more inbound radio frequency signals from the one or more outbound radio frequency signals. The portable computing device of claim 3, wherein the baseband processing unit is further configured to generate at least one of: an antenna tuning unit control signal, configured to adjust an impedance change according to the antenna portion An impedance of the antenna tuning unit; a separation control signal for adjusting attenuation of the one or more output RF signals; and a power amplifier control signal for adjusting one or more parameters of the one or more power amplifiers. The portable computing device of claim 1, wherein the surface-free wave transmitter comprises: an up-conversion mixing module, configured to convert the one or more outbound symbol streams into one Or a plurality of upconverted signals; a variable frequency bandpass filter for: converting the second baseband filter response to a second RF bandpass filter response; and filtering according to the second RF bandpass filter response One or more upconverted signals to produce one or more filtered upconverted signals; and an output module for adjusting the one or more filtered upconverted signals To generate one or more adjusted upconverted signals; and a power amplifier driver for amplifying the one or more adjusted upconverted signals to generate the one or more outbound radio frequency signals. The portable computing device of claim 5, wherein the baseband processing unit is further configured to: generate a transmitter control signal, the transmitter control signal to adjust at least one of the following: A two baseband filter response, the second RF bandpass filter response, and parameters of the power amplifier driver. The portable computing device of claim 1, wherein the surface-free wave receiver comprises: a radio frequency-intermediate frequency receiver unit, comprising: a low noise amplifier for amplifying the one or more Inbound radio frequency signals to generate one or more amplified inbound radio frequency signals; an intermediate frequency down conversion module for converting the one or more amplified inbound radio frequency signals into the one or more inbound stations An intermediate frequency signal; and a variable frequency band pass filter having the RF band pass filter response for filtering the one or more inbound radio frequency signals or filtering the one or more inbound intermediate frequency signals; a frequency-baseband receiver section for converting the one or more inbound IF signals into one or more inbound symbol streams. The portable computing device of claim 1, further comprising: a first integrated circuit for supporting the first baseband processing unit, the surfaceless wave receiver, and the surfaceless a wave transmitter; and a second integrated circuit for supporting the front end module. The portable computing device of claim 1, further comprising at least one of the following: a processing module, configured to: Performing one or more portable computing device functions to generate the outbound data; and executing the one or more portable computing device functions to process the input; and a power management unit for performing the portable One or more power management functions of the computing device. A portable computing device includes: a front end module, the front end module comprising: a plurality of power amplifiers, wherein a power amplifier of the plurality of power amplifiers amplifies a first outbound radio frequency of the plurality of outbound radio frequency signals a signal; a plurality of separation modules, wherein the separation module of the plurality of separation modules separates the first inbound radio frequency signal of the plurality of inbound radio frequency signals from the first outbound radio frequency signal; and at least one An antenna tuning unit for providing an impedance matching the impedance of the antenna portion according to the control signal, wherein the antenna tuning unit receives the first inbound radio frequency signal from the antenna portion, and outputs the to the antenna portion a first outbound radio frequency signal; a surface acoustic wave receiver for converting a plurality of inbound radio frequency signals into a plurality of inbound symbol streams, wherein the surfaceless acoustic wave receiver converts the baseband filter response to an intermediate frequency filter Response or RF filter response, wherein the frequency transform of the baseband filter response is used to adequately filter the out-of-band block and filter the desired signal for the one or more inbound RF signals Generating a non-negligible image signal; a surface acoustic wave transmitter for converting a plurality of outbound symbol streams into the plurality of outbound radio frequency signals; and a baseband processing unit for: varying impedance of the antenna portion Generating the control signal; Converting a plurality of outbound data to the plurality of outbound symbol streams; and converting the plurality of inbound symbol streams into a plurality of inbound materials.