TWI485706B - Resistive memory and memory cell thereof - Google Patents

Description

Resistive memory and its memory cell

The present invention relates to a resistive memory cell, and more particularly to a resistive memory cell of a back to back configuration.

Based on the many advantages of resistive memory structures, the application of resistive memory structures to non-volatile memory has become a trend today. In the prior art, the resistive memory structure includes a transition metal oxide layer formed of, for example, nickel oxide (NiO), titanium oxide (TiO2), copper oxide (CuO) or hafnium oxide (HfO). Oxide layer). This transition metal oxide is sandwiched between two metal layers to form a so-called Metal-Insulator-Metal (MIM) structure. Although the so-called MIM structure can be completed by a post-metallization process, in the case of a resistive memory as an embedded memory, this metallized post-process requires an extra mask and process. The steps are completed, causing great troubles in production.

In addition, since the resistive memory provides a certain resistance value, a certain degree of leakage occurs when the resistance value provided is low. In addition to wasting power, this leakage phenomenon will also produce certain effects on the system to which the resistive memory belongs. Interference effects reduce system performance.

The invention provides a resistive memory and a resistive memory cell thereof, which effectively reduces leakage current which may be generated on a memory cell.

The resistive memory cell of the present invention comprises a substrate, a first doped region, a second doped region, and a gate. The first doping region and the second doping region are also disposed in the substrate, the gate is disposed on the substrate, and covers a portion of the first doping region and a portion of the second doping region, wherein the gate is a floating gate . In addition, the first doping region and the second doping region respectively receive the first reference voltage and the second reference voltage, and the overlapping regions of the first doping region and the second doping region and the gate are respectively according to the first reference voltage and The voltage difference of the second reference voltage provides a different first impedance value and a second impedance value, respectively.

The invention further provides a resistive memory comprising a plurality of resistive memory cells, a plurality of bit lines, and word lines. The resistive memory cells are arranged in an array manner to form a plurality of memory lines and a plurality of memory columns. The bit lines are respectively coupled to the resistive memory cells of the memory row, and the word lines are respectively coupled to the resistive memory cells of the memory column. . Each of the resistive memory cells includes a substrate, a first doped region, a second doped region, and a gate. The first doping region and the second doping region are also disposed in the substrate, the gate is disposed on the substrate, and covers a portion of the first doping region and a portion of the second doping region, wherein the gate is a floating gate . In addition, the first doping region and the second doping region respectively receive the first reference voltage and the second reference voltage, and the overlapping regions of the first doping region and the second doping region and the gate are respectively according to the first reference voltage and The voltage difference of the second reference voltage is separately provided Different first and second impedance values.

Based on the above, the present invention provides a memory space of a bit by providing a transistor structure having a floating gate to constitute a resistive memory cell, effectively transmitting a single transistor. Moreover, under the condition that the first impurity region and the second impedance provided by the first doping region and the overlap region of the second doping region and the gate are complementary, the channel of the single resistive memory cell necessarily has a high The path of the impedance, in other words, the leakage current generated in the channel of the resistive memory cell can be effectively reduced, saving unnecessary power consumption.

The above described features and advantages of the invention will be apparent from the following description.

100,411~4MN‧‧‧Resistive memory cells

110‧‧‧Base

121‧‧‧First Miscellaneous District

122‧‧‧Second mixed area

130‧‧‧ gate

D1, part of d2‧‧‧

VREF1, V1, V2‧‧‧ first reference voltage

VREF2‧‧‧second reference voltage

GND‧‧‧ Grounding voltage

310, 320, 330, 340, 351, 352, 360‧‧‧ segments

VRESET‧‧‧Reset voltage value

VSET‧‧‧Set voltage value

VTH1~VTH4‧‧‧ threshold voltage

400‧‧‧Resistive memory

BL1~BLN‧‧‧ bit line

WL1~WLM‧‧‧ character line

1 is a schematic diagram of a resistive memory cell in accordance with an embodiment of the present invention.

FIG. 2 is a schematic diagram showing the operation mode of the resistive memory cell according to the embodiment of the present invention.

FIG. 3A is a diagram showing the relationship between the voltage and the impedance value of the first doping region according to the embodiment of the present invention.

FIG. 3B is a diagram showing the relationship between the voltage and the impedance value of the second doping region according to the embodiment of the present invention.

FIG. 3C is a diagram showing the relationship between the voltage and the impedance value of the resistive memory cell 100 according to the embodiment of the present invention.

4 is a schematic diagram of a resistive memory according to an embodiment of the invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a resistive memory cell 100 according to an embodiment of the invention. The resistive memory cell 100 includes a substrate 110, a first doping region 121, a second doping region 122, and a gate 130. The first doping region 121 and the second doping region 122 are disposed in the substrate 110, and the first doping region 121 and the second doping region 122 are not in contact. In addition, the gate 130 is disposed on the substrate 110 and covers a partial region d1 of the first doping region 121 and a partial region d2 of the second doping region 122. In this embodiment, the first doping region 121 and the second doping region 122 respectively receive the first reference voltage VREF1 and the second reference voltage VREF2. It is worth noting that the gate 130 is a floating gate, that is, the gate 130 exhibits a high impendence state.

In addition, the voltage values of the first reference voltage VREF1 and the second reference voltage VREF2 are different, and the resistive memory cell 100 is partially overlapped with the first doping region 121 and the second doping region 122 by the gate 130. The first impedance value and the second impedance value are respectively provided. The first impedance value and the second impedance value are determined according to the voltage difference between the first reference voltage VREF1 and the second reference voltage VREF2.

The resistive memory cell 100 of the present embodiment is a bipolar structure. In brief, the first impedance value and the second impedance value respectively provided by the first doping region 121 and the second doping region 122 may be complementary. . That is, when the first impedance value provided by the overlapping region of the first doping region 121 and the gate 130 is a relatively high high impedance value, the overlapping region of the second doping region 122 and the gate 130 is provided. Second impedance value It can be a relatively low low impedance value. In contrast, when the first impedance value provided by the overlapping region of the first doping region 121 and the gate 130 is a relatively low low impedance value, the overlapping region of the second doping region 122 and the gate 130 provides the first The second impedance value can be a relatively high high impedance value.

In other words, at least one of the first doped region 121 and the second doped region 122 of the resistive memory cell 100 and the overlap region of the gate 130 provides a relatively high high impedance value. That is to say, an unnecessary leakage phenomenon due to a low impedance value of the channel of the resistive memory cell 100 can be effectively reduced.

Incidentally, when the first doping region 121 is a source, the second doping region 122 may be a drain, and when the first doping region 121 is a drain, the second doping region 122 is Can be the source.

In addition, the region between the gate 130 and the second doping region 122 of the first doping region 121 of the substrate 110 is a dielectric layer material, such as cerium oxide (SiO2), hafnium oxide (HfOx), zirconia. (ZrOx), titanium oxide (TiOx), tantalum oxide (TaOx), (nickel oxide (NiOx), copper oxide (CuOx) or aluminum oxide (AlOx), etc., and partial regions d11 and d2 have the above dielectric layer A local area of the material.

Please refer to FIG. 2 below. FIG. 2 is a schematic diagram showing the operation mode of the resistive memory cell 100 according to the embodiment of the present invention. In FIG. 2, the first reference voltage V1 received by the first doping region 121 may be a positive voltage greater than 0 volts or a negative voltage less than 0 volts. In contrast, the second reference voltage V2 received by the second doping region 122 may be a ground voltage GND equal to 0 volts. Of course, the second reference voltage is not necessarily a ground voltage GND equal to 0 volts.

Referring to FIG. 2 and FIG. 3A simultaneously, FIG. 3A is a diagram showing the relationship between the voltage and the impedance value of the first doping region 121 according to the embodiment of the present invention. In the graph of FIG. 3A, the horizontal axis represents the voltage value of the first reference voltage V1, the gate 130 is equal to the ground voltage GND of 0 volts, and the bias state of the second doping region 122 can be ignored (eg, Can be set to floating state). The vertical axis represents the current value generated on the first doping region 121. In other words, the reciprocal of the slope of the line segments 310 and 320 can represent different impedance values provided by the overlapping regions of the first doping region 121 and the gate 130 under different conditions.

It can be seen from the line segment 310 located in the first quadrant that when the first reference voltage V1 is smaller than the reset voltage value VRESET, the first impedance value provided by the overlapping region of the first doping region 121 and the gate 130 is equal to the relatively low low impedance. value. Further, by the line segment 320 located in the first quadrant, the overlap of the first doping region 121 and the gate 130 as the first reference voltage V1 is incremented and when the first reference voltage V1 is greater than or equal to the reset voltage value VRESET. The first impedance value provided by the region is changed from a relatively low low impedance value to a relatively high high impedance value (the slope of line segment 310 is greater than the slope of line segment 320).

In addition, in the line segment 320 located in the third quadrant, when the first reference voltage V1 is greater than the set voltage value -VSET, the first impedance value provided by the overlapping region of the first doping region 121 and the gate 130 is equal to a relatively high value. High impedance value. Further, by the line segment 320 located in the third quadrant, the first doping region 121 and the first reference voltage V1 are decremented, and when the voltage value of the first reference voltage V1 is less than or equal to the negative set voltage value -VSET. The first impedance value provided by the overlap region of the gate 130 is changed from a relatively high high impedance value to a relatively low low impedance value.

For the portion of the second doping region 122, please refer to FIG. 2 and FIG. 3B simultaneously. FIG. 3B is a diagram showing the relationship between the voltage and the impedance value of the second doping region 122 according to the embodiment of the present invention. In the graph of FIG. 3B, the horizontal axis represents the voltage value of the gate 130, the second reference voltage V2 is equal to the ground voltage of 0 volts, and the vertical axis represents the current value generated on the second impurity region 122. At this time, the bias state of the first doping region 121 can be ignored (for example, it can be set to a floating state). In other words, the slopes of the line segments 330 and 340 can then represent different impedance values provided by the overlapping regions of the second doping region 122 and the gate 130 under different conditions.

It can be seen from the line segment 340 located in the first quadrant that when the voltage of the second reference voltage V2 is less than the set voltage value VSET, the second impedance value provided by the overlapping region of the second doping region 122 and the gate 130 is equal to a relatively high height. Impedance value. Further, by the line segment 330 located in the third quadrant, the overlapping area of the second doping region 122 and the gate 130 is increased as the second reference voltage V2 is incremented and when the second reference voltage V2 is greater than or equal to the set voltage value VSET. The provided second impedance value is changed from a relatively high high impedance value to a relatively low low impedance value (the slope of line segment 330 is greater than the slope of line segment 340).

Referring to FIG. 2 and FIG. 3B simultaneously, it can be seen from the line segment 330 located in the third quadrant that the overlap region of the second doping region 122 and the gate 130 when the second reference voltage V2 is greater than the negative reset voltage value -VRESET. The second impedance value provided is equal to a relatively low low impedance value. Further, by the line segment 340 located in the third quadrant, as the second reference voltage V2 decreases, when the second reference voltage V2 is less than or equal to the negative set voltage value -VRESET, the second doping region 122 and the gate 130 are The second impedance value provided by the overlap region is changed from a relatively low low impedance value to a relatively high high impedance value.

2 and FIG. 3C, in FIG. 3C, FIG. 3C is a diagram showing the relationship between the voltage and the impedance value of the resistive memory cell 100 according to the embodiment of the present invention. The horizontal axis is applied to the voltage difference between the first doping region 121 and the second doping region 122, and the vertical axis represents the current value generated between the first and second doping regions 121 and 122. In a state where the voltage difference is lower than the threshold voltage VTH1 and greater than zero, the equivalent impedance provided by the resistive memory cell 100 is equal to the reciprocal of the slope of the line segment 360. At this time, the first doping region 121 of the resistive memory cell 100 and the overlapping region of the second doping region 122 and the gate 130 respectively provide a first impedance value equal to a low impedance value and a second impedance value equal to a high impedance value. The equivalent impedance provided by the resistive memory cell 100 is equal to the sum of the low impedance value and the high impedance value and is approximately equal to the relatively high high impedance value. When the voltage difference is increased between the threshold voltages VTH1 and VTH2, the equivalent impedance provided by the resistive memory cell 100 is equal to the reciprocal of the slope of the line segment 352, that is, a relatively low low impedance value, and the resistive memory at this time. The first doping region 121 of the cell 100 and the overlap region of the second doping region 122 and the gate 130 both provide a relatively low low impedance value. When the voltage difference is increased to be greater than the threshold voltage VTH2, the first doping region 121 of the resistive memory cell 100 and the overlapping region of the second doping region 122 and the gate 130 respectively provide a first impedance value equal to the high impedance value and A second impedance value equal to the low impedance value, the equivalent impedance provided by the resistive memory cell 100 is equal to the sum of the low impedance value and the high impedance value and is approximately equal to the relatively high high impedance value.

In a state where the voltage difference is higher than the threshold voltage VTH3 and less than zero, the equivalent impedance provided by the resistive memory cell 100 is equal to the reciprocal of the slope of the line segment 360. At this time, the first doping region 121 and the second doping region 122 of the resistive memory cell 100 are The overlap region with the gate 130 respectively provides a first impedance value equal to the low impedance value and a second impedance value equal to the high impedance value, and the equivalent impedance provided by the resistive memory cell 100 is equal to the sum of the low impedance value and the high impedance value. And approximately equal to a relatively high high impedance value. When the voltage difference decreases between the threshold voltages VTH3 and VTH4, the equivalent impedance provided by the resistive memory cell 100 is equal to the reciprocal of the slope of the line segment 351, that is, a relatively low low impedance value, and the resistive memory at this time. The first doping region 121 of the cell 100 and the overlap region of the second doping region 122 and the gate 130 both provide a relatively low low impedance value. When the voltage difference decreases to less than the threshold voltage VTH4, the first doping region 121 of the resistive memory cell 100 and the overlapping region of the second doping region 122 and the gate 130 respectively provide a first impedance value equal to the high impedance value and A second impedance value equal to the low impedance value, the equivalent impedance provided by the resistive memory cell 100 is equal to the sum of the low impedance value and the high impedance value and is approximately equal to the relatively high high impedance value.

It is not difficult to know from the above description that when the resistive memory cell 100 stores data, the first doping region 121 and the overlapping region of the second doping region 122 and the gate 130 can be respectively provided with a value equal to a low impedance value. An impedance value and a second impedance value equal to the high impedance value to represent a logic level 0, and the first doping region 121 and the overlapping region of the second doping region 122 and the gate 130 are respectively provided to be equal to a high impedance value. The first impedance value and the second impedance value equal to the low impedance value represent a logic level of one. Further, the above logic state can be read by making the voltage difference between the threshold voltages VTH1 and VTH2 or by causing the voltage difference to be between VTH3 and VTH4. Of course, the definition of the impedance state provided by the above logic level and the first doping area 121 and the second doping area 122 is only an example, and the designer can according to his needs. The above description is not intended to limit the invention.

In the present embodiment, the slopes of the line segments 351 and 352 may be equal.

Please refer to FIG. 4. FIG. 4 is a schematic diagram of a resistive memory 400 according to an embodiment of the invention. The resistive memory 400 includes a plurality of resistive memory cells 411 to 4MN and a plurality of bit lines BL1 to BLN and word lines WL1 to WLM. The resistive memory cells 411~4MN are arranged according to an array to form a plurality of memory lines and a plurality of memory columns. The resistive memory cells 411~4MN may be the resistive memory cells 100 as illustrated in the embodiment of FIG. The bit lines BL1 BLBLN are respectively coupled to the resistive memory cells 411~4MN of the memory lines, and the word lines WL1 WWLM are respectively coupled to the resistive memory cells 411~4MN of the memory columns. For example, the bit line BL1 is coupled to the resistive memory cells 411, 421, . . . , 4M1 of the first memory row, and the word line WL1 is coupled to the resistive memory cells 411, 412 of the first memory column. ..., 41N.

In summary, the present invention proposes a resistive memory cell constructed by using a floating gate, and the first and second impurity regions and gates of the resistive memory cell under the back-to-back structure formed by the floating gate The first and second impedances respectively provided by the overlapping regions may assume complementary states. In this way, one of the first and second impedances exhibits a high impedance value, effectively reducing the leakage current that may occur in the resistive memory cell. Therefore, the performance of the resistive memory cell is effectively improved.

100‧‧‧Resistive memory cells

110‧‧‧Base

121‧‧‧First Miscellaneous District

122‧‧‧Second mixed area

130‧‧‧ gate

D1, part of d2‧‧‧

VREF1‧‧‧ first reference voltage

VREF2‧‧‧second reference voltage

Claims (10)

A resistive memory cell includes: a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate; a gate disposed on the substrate and covering the portion The first doping region and a portion of the second doping region, the gate is a floating gate, wherein the first doping region and the second doping region respectively receive a first reference voltage and a second reference a voltage, and the first doping region and the overlapping region of the second doping region and the gate respectively provide different first impedance values according to a voltage difference between the first reference voltage and the second reference voltage, and A second impedance value. The resistive memory cell of claim 1, wherein the first impedance value provided by the overlapping region of the first doping region and the gate when the absolute value of the voltage difference is less than a reset voltage value Equal to a high impedance value, when the absolute value of the voltage difference is not less than the reset voltage value, the first impedance value provided by the overlap region of the first doping region and the gate is changed to a low impedance value. Where the high impedance value is greater than the low impedance value. The resistive memory cell of claim 2, wherein when the absolute value of the voltage difference is less than a set voltage value, the second impedance value provided by the overlap region of the second doping region and the gate is equal to And the low impedance value, when the absolute value of the voltage difference is not less than the set voltage value, the second impedance value provided by the overlap region of the second doping region and the gate is changed to the high impedance value. The resistive memory cell of claim 3, wherein the reset voltage value is equal to the set voltage value. The resistive memory cell of claim 1, wherein the first doping region is one of a drain and a source, and the second dorm region is another one of a drain and a source. A resistive memory comprising: a plurality of resistive memory cells arranged in an array to form a plurality of memory lines and a plurality of memory columns, wherein each of the resistive memory cells comprises: a substrate; a first impurity a second doped region disposed in the substrate; a gate disposed on the substrate and covering a portion of the first doped region and a portion of the second doped region, The gate is a floating gate, wherein the first doping region and the second doping region respectively receive a first reference voltage and a second reference voltage, and the first doping region and the second doping region The overlap region with the gate respectively provides a first impedance value and a second impedance value according to a voltage difference between the first reference voltage and the second reference voltage; and a plurality of bit lines and word lines The bit lines are respectively coupled to the resistive memory cells of the memory lines, and the word lines are respectively coupled to the resistive memory cells of the memory columns. The resistive memory of claim 6, wherein the first impedance value provided by the overlapping region of the first doping region and the gate when the absolute value of the voltage difference is less than a reset voltage value Equal to a high impedance value, when the absolute value of the voltage difference is not less than the reset voltage value, the first impedance value provided by the overlap region of the first doping region and the gate is changed to a low impedance value. Where the high impedance value is greater than the low impedance value. The resistive memory of claim 7, wherein when the absolute value of the voltage difference is less than a set voltage value, the second impedance value provided by the overlap region of the second doping region and the gate is equal to And the low impedance value, when the absolute value of the voltage difference is not less than the set voltage value, the second impedance value provided by the overlap region of the second doping region and the gate is changed to the high impedance value. The resistive memory of claim 8, wherein the reset voltage value is equal to the set voltage value. The resistive memory of claim 6, wherein the first doped region is one of a drain and a source, wherein the second doped region is the other of the drain and the source.