TWI571873B - Resistive memory apparatus - Google Patents

Description

Resistive memory device

The present invention relates to a resistive memory device, and more particularly to an arrangement structure of a memory cell of a resistive memory device.

Please refer to FIG. 1. FIG. 1 is a circuit diagram of a conventional resistive memory device. The resistive memory device 100 is composed of a plurality of memory cell pairs 111 to 114. Wherein, the memory cell pair 111 is taken as an example, the memory cell pair 111 has two memory cells 1111 and 1112, and the memory cell 1111 is composed of a transistor T1 and a resistor R1, and the memory cell 1112 is composed of a transistor T2 and a resistor R2. .

The conventional memory cell pairs 111 to 114 in Fig. 1 share the source line and the bit line in the memory cells in each memory cell pair. Taking the memory cell pair 111 as an example, the memory cells 1111 and 1112 in the memory cell pair 111 share the same bit line BL1 and the same source line SL1. In the configuration of FIG. 1, the memory cell pairs 111, 113 of the same row share the same source line SL1, the memory cell pairs 112, 114 of the same row share the same source line SL2, and the memory cell pairs 111 of the same column. The 112 shares the same bit line BL1, and the memory cell pairs 113 and 114 of the same column share the same bit line BL2.

When the resistive memory device 100 is formed, If the memory cell 1111 is the selected memory cell, the word line WL1 corresponding to the memory cell 1111 is set to 3V, and the remaining word lines WL2 to WL4 are set to 0V; the bit line BL1 corresponding to the memory cell 1111 is set to 4V. The bit line BL2 is set to 1.5 V; the source line SL1 corresponding to the memory cell 1111 is set to 0 V, and the source line SL2 is set to 3 V. At this time, the end points between the memory cells 1111 and 1112 coupled to the source line SL1 and the bit line BL1 will also withstand a voltage difference of 4V, that is, the unselected memory cell 1112 will be formed by this time. Interference, resulting in an unanticipated state. In addition, similar interference actions occur in the setting or resetting operation of the resistive memory device 100, and the operational efficiency of the resistive memory device 100 is reduced.

The invention provides a resistive memory device, which can reduce the interference phenomenon between memory cells which may occur during the operation thereof.

The resistive memory device of the present invention includes a plurality of memory cell pairs arranged on the substrate in an array manner and arranged on the substrate in an array manner. Each memory cell pair includes: an active region, a source line, a first resistor and a second resistor, a first bit line, and a second bit line. The active region is formed on the substrate, and the first word line and the second word line are formed on the substrate and are interlaced with the active region. The source line is formed on the substrate and coupled to the active region. The first resistor and the second resistor are disposed on the substrate and coupled to the active region respectively. The first bit line and the second bit line are formed on the first resistor and the second resistor, and are coupled to the first resistor and the second resistor. The first bit line and the second bit line extend substantially in a first direction parallel to the first word line and the second word line.

Based on the above, the resistive memory device of the present invention, wherein the memory cells in the memory cell pair structure are respectively coupled with different bit lines, thereby receiving multiple memories of the same source line in the resistive memory device. The cells respectively receive different bit lines, and the plurality of memory cells receiving the same bit line are respectively coupled to different source lines. In this way, when the resistive memory device performs operations (for example, forming, set, or reset), the interference state generated between the memory cells can be effectively alleviated, and the resistive memory device is lifted. The performance produced during operation.

The above described features and advantages of the invention will be apparent from the following description.

100, 200, 500‧‧‧ resistive memory devices

111~114, 201~204‧‧‧ memory cell pairs

4111, 1112, 501~504‧‧‧ memory cells

210‧‧‧Base

211~213‧‧‧Source/Bungee Area

221, 222‧‧ ‧ gate structure

420‧‧‧ protruding parts

AA, AA’‧‧‧ active area

BL1~BL4‧‧‧ bit line

CON11, CON21, CON31, CON41, CON12, CON22, CON32, CON42, CON13, CON23, CON22", CON21', CON22', CON23'‧‧‧ connection structure

CCON11, CCON21, CCON12, CCON22, CM11, CM12, CCON22", CM12", CCON13, CM13', CCON23'‧‧‧ Center

D1~D7‧‧ Direction

M11, M12, M13, MP1, MP2, M12", M11', M12', M13'‧‧‧ metal layers

R1~R4, R2', R1", R2"‧‧‧ resistance

SL1, SL2, SL1', SL1"‧‧‧ source line

T1~T4‧‧‧O crystal

WL1~WL4‧‧‧ word line

FIG. 1 is a circuit diagram of a conventional resistive memory device.

FIG. 2A is a schematic diagram showing the layout of a resistive memory device 200 according to an embodiment of the invention.

Figure 2B is a cross-sectional view of the resistive memory device 200 in accordance with line II' of Figure 2A.

FIG. 3 is a schematic diagram showing the layout of another embodiment of the memory cell shown in FIG. 2A.

4A is a schematic diagram showing the layout of another embodiment of the memory cell shown in FIG. 2A.

FIG. 4B is a schematic diagram showing the layout of the memory cell shown in FIG. 4A for another embodiment. FIG.

FIG. 5 is an equivalent circuit diagram of a resistive memory device according to an embodiment of the present invention.

FIG. 2A is a schematic diagram showing the layout of a resistive memory device 200 according to an embodiment of the invention. Figure 2B is a cross-sectional view of the resistive memory device 200 in accordance with line II' of Figure 2A. Referring to FIG. 2A and FIG. 2B simultaneously, the resistive memory device 200 includes a plurality of memory cell pairs 201-204 arranged in an array manner. Taking the memory cell pair 201 as an example, the memory cell pair 201 includes an active area AA, resistors R1 and R2, a source line SL1, word lines WL1 and WL2, and bit lines BL1 and BL2. Word lines WL1 and WL2 are formed on the substrate 210 and extend in the direction D1. The regions in which the word lines WL1 and WL2 cover the active region AA can respectively form the first gate structure 221 and the second gate structure 222 that couple the resistors R1 and R2. The regions of the active region AA that are not covered by the word lines WL1 and WL2 may be doped to form source/drain regions 211-213, respectively. The source line SL1 is formed above the active area AA and extends along the direction D2. The source line SL1 is coupled to the source/drain region 213 between the word lines WL1 and WL2 through the connection structure CON23, the metal layer M13 and the connection structure CON13. . The resistor R1 is formed on the substrate 210 and can be coupled to the source/drain region 211 on the other side of the word line WL1 through the connection structure CON31, the metal layer MP1, the connection structure CON21, the metal layer M11, and the connection structure CON11. The bit line BL1 is formed over the resistor R1 and extends substantially in a direction D1 parallel to the word line WL1. The bit line BL1 can be coupled to the resistor R1 directly or through the connection structure CON41. The resistor R2 is formed on the substrate and can be coupled to the source/drain region 212 on the other side of the word line WL2 through the connection structure CON32, the metal layer MP2, the connection structure CON22, the metal layer M12, and the connection structure CON12. The bit line BL2 is formed over the resistor R2 and extends substantially in a direction D1 parallel to the word line WL1. The bit line BL2 can be coupled to the resistor R2 directly or through the connection structure CON42. Note that, in this embodiment, the source line SL1 is coupled to the source/drain region 213 through the connection structures CON13, CON23 and the metal layer M13, and the resistor R1 is transmitted through the connection structures CON11, CON21, CON31 and the metal layer M11, The MP1 is coupled to the source/drain region 211, and the resistor R2 is coupled to the source/drain region 212 through the connection structures CON12, CON22, and CON32, and the metal layers M12 and MP2. However, the present invention is not limited thereto, and the source line is not limited thereto. The SL and the resistors R1, R2 can also be coupled to the source/drain regions with more or less layers of connection structures and metal layers depending on process requirements.

Specifically, as shown in FIG. 2A, the connection structure CON21 has a center CCON21, the metal layer M11 has a center CM11, and the connection structure CON11 has a center CCON11. The center CCON21 of the connection structure CON21 is disposed with the center CM11 of the metal layer M11 shifted toward the direction D3, and the center CCON11 of the connection structure CON11 is disposed with the center CM11 of the metal layer M11 shifted toward the direction D4. On the other hand, the connection structure CON22 has a center CCON22, the metal layer M12 has a center CM12, and the connection structure CON12 has a center CCON12. The center CCON22 of the connection structure CON22 is offset in the direction D3 by the center CM12 of the metal layer M12, and the center CCON12 of the connection structure CON12 is shifted in the direction D4 by the center CM12 of the metal layer M12. Note that in the present embodiment, the direction D1 and the direction D3 are the same direction, but the present invention is not limited thereto, and in other embodiments, the direction D1 and the direction D3 may be different directions. In addition, in the present embodiment, the direction D3 and the direction D4 are parallel and opposite directions, but the present invention is not limited thereto, and in other embodiments, the direction D3 may be only a direction different from D4. as the picture shows, The present invention can be configured such that the bit lines of the resistive memory device can be arranged substantially parallel to the word lines by offsetting the locations of the connection structures CON11, CON21, CON12, CON22 and the metal layers M11, M12.

Please refer to FIG. 3. FIG. 3 is a schematic diagram showing the layout of the memory cell shown in FIG. 2A. 2A, the active area AA of the embodiment shown in FIG. 2A extends substantially in the same direction D2 as the source line SL1, and the active area AA' of the embodiment is in a direction different from the source line SL1. D5 extends. In addition, the source line SL1 of the embodiment shown in FIG. 2A covers the active area AA, and the direction D2 and the direction D1 are perpendicular to each other. The source line SL1 of the embodiment covers only a part of the active area AA', and the direction D5 is staggered and not perpendicular to the direction D1, and is coupled to the source line SL1 and the active area AA, and the connection structures CON13, CON23 and metal The layer M13 is disposed at the intersection of the source line SL1 and the active area AA'. Please note that the metal layer M12" and the connection structure CON22" in this embodiment respectively have a metal center CM12" and a center CCON22". Wherein, the center CCON22" of the connection structure CON22" is disposed with the center CM12" of the metal layer M12" shifted toward the direction D4, and the center CCON12 of the connection structure CON12 is offset from the center CM12" of the metal layer M12" toward the direction D3 And set. As shown, the present invention can be configured such that the active area AA' and the source line SL1 extend in different directions such that the bit lines of the resistive memory device can be arranged substantially parallel to the word line.

Please refer to FIG. 4A. FIG. 4A is a schematic diagram showing the layout of another embodiment of the memory cell shown in FIG. 2A. 2A, the source line SL1 of the embodiment shown in FIG. 2A is disposed above the active area AA, and through the offset connection structures CON11, CON21, The positions of CON12, CON22 and metal layers M11 and M12 are such that the resistor R1 and the resistor R2 are coupled to the active area AA. In this embodiment, the resistor R1" and the resistor R2" are disposed above the active region AA, and the source line SL1' is coupled to the active source through the positions of the offset connection structures CON13, CON23' and the metal layer M13'. District AA. Specifically, referring to Fig. 4A, the connection structure CON23' has a center CCON23', the metal layer M13' has a center CM13', and the connection structure CON13 has a center CCON13. Wherein, the center CCON23' of the connection structure CON23' is disposed with the center CM13' of the metal layer M13' shifted toward the direction D6, and the center CCON13 of the connection structure CON13 is offset from the center CM13' of the metal layer M13' toward the direction D7. And set. As shown, the present invention can be configured such that the bit lines BL1, BL2 of the resistive memory device can be substantially parallel to the word lines WL1, WL2 by shifting the positions of the connection structures CON13, CON23' and the metal layer M13'. .

Please refer to FIG. 4B. FIG. 4B is a schematic diagram showing the layout of the memory cell shown in FIG. 4A for another embodiment. The difference from FIG. 4A is that the source line SL1" of the embodiment has a protruding portion 420. The protruding portion is formed over the connecting structure CON23 to cover a portion of the active area AA. Therefore, the embodiment does not need to offset the connection structure CON13. The positions of CON23 and metal layer M13 can be such that the bit lines BL1, BL2 of the resistive memory device can be arranged substantially parallel to the word lines WL1, WL2.

Incidentally, in the above embodiments, the bit line, the word line, and the source line of the memory cell pair fabricated in the form of a wafer may be formed by using a material as a wire in the wafer, such as a metal layer, and connected. The structure can be formed using a connection layer (VIA or contact) in the wafer.

Referring to FIG. 5, FIG. 5 is an equivalent circuit diagram of a resistive memory device according to an embodiment of the present invention. The resistive memory device 500 includes a plurality of memory cells 501-504. Among them, the memory cells 501 to 504 include transistors T1 to T4, respectively, and include resistors R1 to R4, respectively. Taking the memory cell 501 as an example, the source terminal of the transistor T1 is coupled to the source line SL1 and the drain terminal of the transistor T1 is coupled to the resistor R1, and the other end of the resistor R1 is coupled to the bit line BL1.

In the embodiment of FIG. 5, on the circuit, the memory cells 501 and 502 share the source line SL1 and are coupled to the bit lines BL1 and BL2, respectively; the memory cells 503 and 504 share the source line SL2 and are coupled respectively. The bit lines BL1 and BL2; the memory cells 501 and 503 share the bit line BL1 and are respectively coupled to the source lines SL1 and SL2; and the memory cells 502 and 504 share the bit line BL2 and are respectively coupled to the source lines. SL1 and SL2. Further, the word line and the bit line extend substantially in the direction D1, and the source line extends in the direction D2 different from the direction D1.

When the resistive memory device 500 performs a forming operation, if the memory cell 503 is a selected memory cell (the memory cells 501, 502, and 504 are unselected memory cells), the voltage of the bit line BL1 can be set. For 4V, the voltages of the source lines SL1 and SL2 can be set to 3V and 0V, the voltage of the bit line BL2 can be set to 1.5V, and the voltages of the word lines WL1 and WL2 are set to 3V and 0V, respectively. As a result, the transistor T3 can be turned on in accordance with the voltage on the word line WL1, and the forming operation is performed in accordance with the voltage difference (4.0 V) on the bit line BL1 and the source line SL2. At the same time, the voltage difference experienced by the memory cell 504 is equal to the voltage on the bit line BL2 minus the voltage on the source line SL2 is approximately equal to 1.5V, that is, the memory cell 504 is subjected to The interference is effectively reduced and the leakage that may occur is reduced.

In addition, when the set operation is performed on the resistive memory device 500, if the memory cell 503 is a selected memory cell (the memory cells 501, 502, and 504 are unselected memory cells), the voltage of the bit line BL1 is, for example, It can be set to 2V, the voltages of the source lines SL1 and SL2 can be set to 1V and 0V, the voltage of the bit line BL2 can be set to 0V, and the voltages of the word lines WL1 and WL2 are set to 3V and 0V, respectively. In this way, the transistor T3 can be turned on according to the voltage on the word line WL1, and the setting operation is performed according to the voltage difference (2.0 V) on the bit line BL1 and the source line SL2. At the same time, the voltage difference between the memory cells 501, 502 is approximately equal to 1V, and the voltage difference experienced by the memory cell 504 is approximately equal to 0V, that is, the interference experienced by the memory cells 501, 502, 504 is effectively reduced. Small and reduce the leakage that may occur.

In addition, when performing a reset operation on the resistive memory device 500, if the memory cell 503 is a selected memory cell (the memory cells 501, 502, and 504 are unselected memory cells), the voltage of the bit line BL1. For example, it can be set to 0V, the voltages of the source lines SL1 and SL2 can be set to 0V and 2V, the voltage of the bit line BL2 can be set to 1V, and the voltages of the word lines WL1 and WL2 are set to 5V and 0V, respectively. In this way, the transistor T3 can be turned on according to the voltage on the word line WL1, and the reset operation is performed according to the voltage difference (-2.0 V) on the bit line BL1 and the source line SL2. At the same time, the voltage difference between the memory cells 501, 502, and 504 is approximately equal to 0V, 1V, and -1V, respectively, that is, the interference received by the memory cells 501, 502, and 504 is effectively avoided, and the possibility is reduced. The resulting leakage phenomenon.

In summary, the memory cell pair provided by the present invention can make resistive memory The bit line of the device is arranged substantially parallel to the word line, and further enables the memory cell in the resistive memory device to perform at least one of the bit line and the source line of each memory cell when performing various operations. The voltage is individually set, and the effect of the interference and leakage is further reduced by the influence of the adjacent memory cells during the process, thereby further improving the efficiency of the resistive memory device.

200‧‧‧Resistive memory device

201~204‧‧‧ memory cell pairs

AA‧‧‧Active Area

R1, R2‧‧‧ resistance

SL1, SL2‧‧‧ source line

WL1~WL4‧‧‧ word line

BL1~BL4‧‧‧ bit line

Direction D1~D4‧‧‧

CON11, CON21, CON12, CON22, CON13, CON23‧‧‧ connection structure

CCON11, CCON21, CM11, CCON12, CCON22, CM12‧‧ Center

M11, M12, M13‧‧‧ metal layer

Claims (13)

A resistive memory device comprising: a plurality of memory cell pairs arranged on a substrate in an array manner, each of the memory cell pairs comprising: an active region formed on the substrate; a first word line and a second word a line formed on the substrate and interlaced with the active region; a source line formed on the substrate and coupled to the active region; a first resistor and a second resistor disposed on the substrate And respectively coupled to the active region; and a first bit line and a second bit line formed on the first resistor and the second resistor, and coupled to the first resistor and the second And a resistor, wherein the first bit line and the second bit line extend substantially in a first direction parallel to the first word line and the second word line. The resistive memory device of claim 1, wherein the active region is disposed on the substrate along a second direction, the first direction being substantially interlaced with the second direction. The resistive memory device of claim 2, wherein the source line is disposed along a third direction and covers at least a portion of the active area. The resistive memory device of claim 3, further comprising a first connection structure, wherein the first connection structure is disposed in a region where the source line overlaps the active region, and the source line is transparent The first connection structure is coupled to the active Area. The resistive memory device of claim 4, wherein the source line is formed above the active area, and the third direction is substantially the same as the second direction, and further includes: a second connection structure, configuration Above the active area, and coupled to the first resistor. The resistive memory device of claim 5, wherein the second connecting structure has a second center, further comprising: a first metal layer disposed above the second connecting structure and having a first a third metal structure is disposed above the first metal layer and coupled to the first resistor, and has a third center, wherein the second center is from the center of the first metal layer The four directions are offset, and the third center is offset from the center of the first metal layer toward a fifth direction. The resistive memory device of claim 6, further comprising: a fourth connecting structure disposed above the active area and having a fourth center; a second metal layer disposed on the fourth connection Above the structure, and having a second metal layer center; a fifth connection structure, disposed above the second metal layer and coupled to the second resistor, and having a fifth center, wherein the fourth center The center of the second metal layer is offset in the fourth direction, and the fifth center is offset from the center of the second metal layer toward the fifth direction. The resistive memory device of claim 7, wherein the first resistor and the second resistor are offset from the source line in the fifth direction. The resistive memory device of claim 7, wherein the first resistor is offset from the source line toward the fifth direction, and the second resistor is offset from the source line to the fourth direction . The resistive memory device of claim 2, wherein the source line extends substantially parallel to the active area along the second direction, and the first connection structure has a first center, further comprising: a first metal layer is disposed above the first connection structure and has a first metal layer center; a second connection structure is disposed above the first metal layer and coupled to the source line, and has a first a second center; wherein the first center is offset from a center of the first metal layer toward a third direction, and the second center is offset from a center of the first metal layer toward a fourth direction. The resistive memory device of claim 10, wherein the third direction is opposite to the fourth direction. The resistive memory device of claim 4, wherein the third direction is substantially the same as the second direction, and the source line has a protrusion covering the portion of the active area. The resistive memory device of claim 1, wherein the memory cell pairs arranged in the same row share the same first bit line, second bit line, first word line, and second word line, the same column The memory cell pairs share the same source line.