TWI479664B - Thin film transistor and method for manufacturing the same and liquid crystal display panel using the same - Google Patents
Thin film transistor and method for manufacturing the same and liquid crystal display panel using the same Download PDFInfo
- Publication number
- TWI479664B TWI479664B TW101150833A TW101150833A TWI479664B TW I479664 B TWI479664 B TW I479664B TW 101150833 A TW101150833 A TW 101150833A TW 101150833 A TW101150833 A TW 101150833A TW I479664 B TWI479664 B TW I479664B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate
- thin film
- film transistor
- insulating layer
- nitrogen
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims description 44
- 238000000034 method Methods 0.000 title claims description 13
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 38
- 229910052757 nitrogen Inorganic materials 0.000 claims description 23
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 17
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 11
- MGWGWNFMUOTEHG-UHFFFAOYSA-N 4-(3,5-dimethylphenyl)-1,3-thiazol-2-amine Chemical compound CC1=CC(C)=CC(C=2N=C(N)SC=2)=C1 MGWGWNFMUOTEHG-UHFFFAOYSA-N 0.000 claims description 10
- 239000007769 metal material Substances 0.000 claims description 10
- JCXJVPUVTGWSNB-UHFFFAOYSA-N nitrogen dioxide Inorganic materials O=[N]=O JCXJVPUVTGWSNB-UHFFFAOYSA-N 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 8
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 229910052707 ruthenium Inorganic materials 0.000 claims description 5
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 3
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 2
- 229910052727 yttrium Inorganic materials 0.000 claims description 2
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052684 Cerium Inorganic materials 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Ceramic Engineering (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Liquid Crystal (AREA)
Description
本發明係關於一種薄膜電晶體及其製作方法。 The present invention relates to a thin film transistor and a method of fabricating the same.
採用薄膜電晶體作為驅動元件的液晶顯示面板已廣泛應用於顯示設備中，例如電視，筆記本電腦或者顯示器中。然，薄膜電晶體之閘極絕緣層均係沉積於閘極上，由此，在製作閘極絕緣層時較易對閘極產生影響，例如閘極之金屬材料被氧化，閘極在被氧化後之電阻值較被氧化前高，從而導致薄膜電晶體之訊號傳輸時間增加，使得訊號出現延遲，進而無法滿足目前液晶顯示面板分辨率增加之需求。 Liquid crystal display panels using thin film transistors as driving elements have been widely used in display devices such as televisions, notebook computers or displays. However, the gate insulating layer of the thin film transistor is deposited on the gate, thereby making it easier to affect the gate when the gate insulating layer is formed. For example, the metal material of the gate is oxidized, and the gate is oxidized. The resistance value is higher than that before being oxidized, which leads to an increase in the signal transmission time of the thin film transistor, which causes the signal to be delayed, thereby failing to meet the increasing resolution of the current liquid crystal display panel.
有鑑於此，必要提供一種能夠防止閘極層被氧化之薄膜電晶體。 In view of the above, it is necessary to provide a thin film transistor capable of preventing the gate layer from being oxidized.
進一步，提供一種薄膜電晶體的製作方法。 Further, a method of fabricating a thin film transistor is provided.
再次，提供一種包括前述薄膜電晶體之液晶面板。 Again, a liquid crystal panel including the aforementioned thin film transistor is provided.
一種薄膜電晶體，包括：至少一金屬材料的閘極；及一閘極絕緣層，覆蓋該閘極，該閘極絕緣層為包含有氧化矽，以 及含有氮與矽之鍵結之化學物質與含有氮與氧及矽之鍵結之化學物質二者其中至少之一的混合物，且該閘極絕緣層中氧原子的濃度與氮原子的濃度比值小於3，其中，所述氧原子的濃度係指單位體積內氧原子之數量，氮原子的濃度係指單位體積內氮原子之數量。 A thin film transistor comprising: a gate of at least one metal material; and a gate insulating layer covering the gate, the gate insulating layer containing yttrium oxide And a mixture of a chemical substance containing a bond between nitrogen and ruthenium and a chemical substance containing a bond of nitrogen and oxygen and ruthenium, and a ratio of a concentration of oxygen atoms to a concentration of nitrogen atoms in the gate insulating layer Less than 3, wherein the concentration of the oxygen atom means the number of oxygen atoms per unit volume, and the concentration of the nitrogen atom means the number of nitrogen atoms per unit volume.
一種薄膜電晶體之製作方法，包括：形成至少一金屬材質的閘極；在反應腔室內充入矽甲烷、二氧化氮氣體以及氮氣採用化學氣相沉積的方法形成閘極絕緣層於該閘極上，該閘極絕緣層為包含有氧化矽，以及含有氮與矽之鍵結之化學物質與含有氮與氧及矽之鍵結之化學物質二者其中至少之一的混合物，且該閘極絕緣層中氧原子的濃度與氮原子的濃度比值小於3。 A method for fabricating a thin film transistor, comprising: forming a gate electrode of at least one metal material; filling a methane, a nitrogen dioxide gas, and a nitrogen gas in the reaction chamber to form a gate insulating layer on the gate by chemical vapor deposition The gate insulating layer is a mixture containing at least one of a cerium oxide, a chemical substance containing a bond of nitrogen and cerium, and a chemical substance containing a bond of nitrogen and oxygen and cerium, and the gate is insulated The ratio of the concentration of oxygen atoms in the layer to the concentration of nitrogen atoms is less than 3.
一種液晶顯示面板，包括複數薄膜電晶體、多列平行間隔設置的掃描線、多行平行間隔設置且與該多列掃描線垂直絕緣交叉的資料線、複數設置在該多列掃描線及該多行資料線所界定區域的畫素電極、一相對該畫素電極設置的公共電極，該薄膜電晶體設置在該多列掃描線與該多行資料線交叉區域。 A liquid crystal display panel comprising a plurality of thin film transistors, a plurality of columns of parallel spaced scan lines, a plurality of rows of parallel spaced apart data lines vertically intersecting the plurality of columns of scan lines, a plurality of scan lines disposed on the plurality of columns, and the plurality of scan lines A pixel electrode in a region defined by the row data line, a common electrode disposed opposite to the pixel electrode, the thin film transistor being disposed at an intersection of the plurality of columns of scan lines and the plurality of rows of data lines.
相較於先前技術，由於該閘極絕緣層之形成過程中採用氮氣進行稀釋，由此，在形成閘極絕緣層過程中，不會使得含有金屬材料的閘極發生氧化，進而保證了閘極較低的電阻率，防止訊號傳輸時間之延遲。 Compared with the prior art, since the gate insulating layer is diluted with nitrogen during the formation process, the gate electrode containing the metal material is not oxidized during the formation of the gate insulating layer, thereby ensuring the gate. Lower resistivity prevents delays in signal transmission time.
10‧‧‧薄膜電晶體 10‧‧‧film transistor
11‧‧‧基板 11‧‧‧Substrate
12‧‧‧閘極 12‧‧‧ gate
13‧‧‧閘極絕緣層 13‧‧‧ gate insulation
14‧‧‧半導體層 14‧‧‧Semiconductor layer
15‧‧‧源極 15‧‧‧ source
16‧‧‧汲極 16‧‧‧汲polar
S201~S205‧‧‧步驟 S201~S205‧‧‧Steps
100‧‧‧液晶顯示面板 100‧‧‧LCD panel
101‧‧‧掃描線 101‧‧‧ scan line
102‧‧‧資料線 102‧‧‧Information line
104‧‧‧畫素電極 104‧‧‧pixel electrodes
105‧‧‧公共電極 105‧‧‧Common electrode
圖1是閱圖1，是本發明液晶顯示面板的結構示意圖。 1 is a schematic view showing the structure of a liquid crystal display panel of the present invention.
圖2是圖1所示薄膜電晶體沿Ⅳ-Ⅳ線的剖面結構示意圖。 2 is a schematic cross-sectional view of the thin film transistor of FIG. 1 taken along line IV-IV.
圖3為圖2所示製作薄膜電晶體之一實施方式的方法流程圖。 3 is a flow chart of a method of fabricating one embodiment of the thin film transistor of FIG. 2.
請參閱圖1，是本發明液晶顯示面板一畫素結構的結構示意圖。該液晶顯示面板100包括多列相互平行之掃描線101、多欄相互平行並分別與該掃描線101絕緣相交之資料線102、複數鄰近該掃描線101與該資料線102交叉處設置的薄膜電晶體10(thin film transistor，TFT)、複數畫素電極104及一與該複數畫素電極104相對設置之公共電極105。該畫素電極104矩陣排布在該多列相互平行之掃描線101及多欄相互平行的掃描線101所界定的區域內。該薄膜電晶體10的閘極對應連接至一掃描線101，其源極對應連接至一資料線102，其汲極對應連接至一畫素電極104。 Please refer to FIG. 1 , which is a structural diagram of a pixel structure of a liquid crystal display panel of the present invention. The liquid crystal display panel 100 includes a plurality of columns of scanning lines 101 parallel to each other, a plurality of columns parallel to each other and insulated from the scanning lines 101, and a plurality of thin film electrodes disposed adjacent to the intersection of the scanning lines 101 and the data lines 102. A thin film transistor (TFT), a plurality of pixel electrodes 104, and a common electrode 105 disposed opposite the complex pixel electrode 104. The matrix of the pixel electrodes 104 is arranged in a region defined by the plurality of columns of scanning lines 101 which are parallel to each other and the scanning lines 101 which are parallel to each other. The gate of the thin film transistor 10 is correspondingly connected to a scan line 101, the source of which is correspondingly connected to a data line 102, and the drain of which is correspondingly connected to a pixel electrode 104.
當該多列掃描線101接收外界提供的掃描電壓時，該多欄資料線102接收外界提供的資料電壓，並載入至相應的薄膜電晶體10的源極。如果此時該薄膜電晶體10處於打開狀態，則該資料電壓傳送至該薄膜電晶體10的汲極並載入在該畫素電極104。該公共電極105同時接收外界提供的公共電壓，由此在該畫素電極104與該公共電極105間會產生一電場以控制液晶分子的轉動，從而實現圖像顯示。 When the multi-column scan line 101 receives the scan voltage supplied from the outside, the multi-column data line 102 receives the data voltage supplied from the outside and loads it into the source of the corresponding thin film transistor 10. If the thin film transistor 10 is in an open state at this time, the data voltage is transferred to the drain of the thin film transistor 10 and loaded on the pixel electrode 104. The common electrode 105 simultaneously receives a common voltage supplied from the outside, whereby an electric field is generated between the pixel electrode 104 and the common electrode 105 to control the rotation of the liquid crystal molecules, thereby realizing image display.
如圖2所示，是圖1所示薄膜電晶體10沿Ⅳ-Ⅳ線的剖面結構示意圖，薄膜電晶體10包括基板11、閘極12、閘極絕緣層13、半導體層14、源極15以及汲極16。其中，閘極12以銅作為電極材料形成於基板11上。閘極絕緣層13之主要成分為氧化矽(SiOn，n為自然數)，另外還包括含有氮與矽之鍵結(Si-N)之化學物質或/及含 有氮與氧以及矽之鍵結(Si-N-O)之化學物質，其中氧原子的濃度與氮原子濃度比值小於3。該原子濃度可藉由二次離子質譜(SIMS，secondary ion mass spectroscopy)儀器測試獲得，該氮原子與氧原子的濃度分別係指單位體積(1立方釐米，1cm3)內該氮原子與氧原子之數量。 2 is a schematic cross-sectional view of the thin film transistor 10 of FIG. 1 along the line IV-IV. The thin film transistor 10 includes a substrate 11, a gate 12, a gate insulating layer 13, a semiconductor layer 14, and a source 15. And bungee jumping 16. The gate 12 is formed on the substrate 11 using copper as an electrode material. The main component of the gate insulating layer 13 is yttrium oxide (SiOn, n is a natural number), and further includes a chemical substance containing nitrogen and lanthanum bond (Si-N) or/and There is a chemical substance of nitrogen and oxygen and a bond of yttrium (Si-N-O), wherein the ratio of the concentration of the oxygen atom to the concentration of the nitrogen atom is less than 3. The atomic concentration can be obtained by a secondary ion mass spectroscopy (SIMS) instrument. The concentration of the nitrogen atom and the oxygen atom respectively refers to the nitrogen atom and the oxygen atom per unit volume (1 cubic centimeter, 1 cm 3 ). Quantity.
該閘極絕緣層13中鄰近閘極12且對應氧原子濃度與氮原子濃度比值小於3之厚度為閘極絕緣層13整體厚度之7.5%到12.5%。 The thickness of the gate insulating layer 13 adjacent to the gate 12 and corresponding to the oxygen atom concentration to the nitrogen atom concentration ratio of less than 3 is 7.5% to 12.5% of the overall thickness of the gate insulating layer 13.
該閘極絕緣層13覆蓋於該閘極12與基板11上。半導體層14形成於該閘極絕緣層13上，源極15與汲極16分別形成於閘極12對應的該半導體層14上的兩端，其中，源極15與汲極16之間設置有一通道(未標示)。可理解，本實施方式係以底閘極結構進行說明。 The gate insulating layer 13 covers the gate 12 and the substrate 11. The semiconductor layer 14 is formed on the gate insulating layer 13. The source 15 and the drain 16 are respectively formed on both ends of the semiconductor layer 14 corresponding to the gate 12. The source 15 and the drain 16 are disposed between the drain. Channel (not labeled). It can be understood that the present embodiment is described by the bottom gate structure.
請一併參閱圖2和圖3，其中，圖3為本發明一實施方式中製作該薄膜電晶體的方法流程圖，該製作方法包括如下步驟： Please refer to FIG. 2 and FIG. 3 , wherein FIG. 3 is a flowchart of a method for fabricating the thin film transistor according to an embodiment of the present invention. The manufacturing method includes the following steps:
步驟S201，提供基板11，該基板的材質可為玻璃。 In step S201, a substrate 11 is provided, and the material of the substrate may be glass.
步驟S202，形成以金屬材料作為電極材料的閘極12於基板11上，該閘極12可以是在一反應腔室內採用物理氣相法在基板11上沉積一定厚度的金屬銅層，再經由圖案化後形成。在本實施例中，該金屬材料優選為電阻率較低之銅(Cu)。 Step S202, forming a gate 12 having a metal material as an electrode material on the substrate 11. The gate 12 may be a metal copper layer deposited on the substrate 11 by a physical vapor phase in a reaction chamber, and then passing through the pattern. Formed after the formation. In the present embodiment, the metal material is preferably copper (Cu) having a low electrical resistivity.
步驟S203，采用化學氣相沉積的方法在該閘極12上形成閘極絕緣層，其中，在化學氣相沉積的過程中，在密閉之反應腔室內充入矽甲烷(SiH4)、二氧化氮(NO2)氣體以及氮氣(N2)的混合物作為化學氣相沉積所需的反應氣體。具體地，在反應腔室中通入SiH4、NO2以及N2在370攝氏度以上的反應溫度中使該些氣體進行化學 反應，從而在閘極12與基板11上沉積形成主要成分為氧化矽(SiOx)，另外還包括含有氮與矽之鍵結化矽(Si-N)之化學物質或/及含有氮與氧以及化矽之鍵結(Si-N-O)之化學物質，由於在形成閘極絕緣層13的過程中通入矽甲烷(SiH4)、二氧化氮(NO2)氣體之同時，還通入氮氣(N2)對前述兩種氣體進行稀釋並作為反應氣體，使得閘極12中之銅不易被氧化。 Step S203, forming a gate insulating layer on the gate 12 by chemical vapor deposition, wherein in the process of chemical vapor deposition, the closed reaction chamber is filled with methane (SiH4) and nitrogen dioxide. A mixture of (NO2) gas and nitrogen (N2) is used as a reaction gas required for chemical vapor deposition. Specifically, the gases are chemically introduced into the reaction chamber by passing SiH4, NO2, and N2 at a reaction temperature of 370 degrees Celsius or higher. The reaction is deposited on the gate 12 and the substrate 11 to form a main component of cerium oxide (SiOx), and further includes a chemical substance containing nitrogen and lanthanum bonded cerium (Si-N) or/and containing nitrogen and oxygen, and The chemical substance of the bismuth bond (Si-NO) is introduced into the gate insulating layer 13 while introducing methane (SiH4) and nitrogen dioxide (NO2) gas, and also introducing nitrogen gas (N2). The above two gases are diluted and used as a reaction gas so that the copper in the gate 12 is not easily oxidized.
優選地，在通入前述反應氣體形成閘極絕緣層13之初期，如：閘極絕緣層13整體沉積時間之前5%到10%時間段內，氮氣的充入量以單位時間內氮氣與二氧化氮之體積比值大於1.5為宜，以對該二氧化氮氣體進行稀釋，對應地，在此時間段內，鄰近閘極12形成之氧原子濃度與氮原子濃度比值小於3之閘極絕緣層13之厚度為閘極絕緣層13整體厚度之7.5%到12.5%。而在形成閘極絕緣層13之其他時間段內可以適量充入氮氣或者停止充入氮氣，且對應之閘極絕緣層13中氮原子與氧原子的濃度比並不受以上比例之限制。 Preferably, in the initial stage of forming the gate insulating layer 13 by the reaction gas, for example, the filling amount of nitrogen in the period of 5% to 10% before the deposition time of the gate insulating layer 13 is nitrogen and two in a unit time. Preferably, the volume ratio of the nitrogen oxide is greater than 1.5 to dilute the nitrogen dioxide gas, and correspondingly, the gate insulating layer formed by the adjacent gate 12 having an oxygen atom concentration to a nitrogen atom concentration ratio of less than 3 during this period of time. The thickness of 13 is 7.5% to 12.5% of the overall thickness of the gate insulating layer 13. In other periods during which the gate insulating layer 13 is formed, an appropriate amount of nitrogen gas may be charged or nitrogen gas may be stopped, and the concentration ratio of nitrogen atoms to oxygen atoms in the corresponding gate insulating layer 13 is not limited by the above ratio.
步驟S204，形成半導體層14於該閘極絕緣層13上，該半導體層14可以是一氧化銦鎵鋅(IGZO)薄膜。 In step S204, a semiconductor layer 14 is formed on the gate insulating layer 13. The semiconductor layer 14 may be an indium gallium zinc oxide (IGZO) film.
步驟S205，形成源極15與汲極16分別位於該半導體層14的兩端，其中，源極15與汲極16之間設置有一通道。 In step S205, the source 15 and the drain 16 are respectively formed at two ends of the semiconductor layer 14, and a channel is disposed between the source 15 and the drain 16.
相較於先前技術，由於閘極絕緣層13於氮氣環境下形成，由此，在形成閘極絕緣層13過程中，不會使得含有銅材料的閘極12發生氧化，進而保證了閘極12較低的電阻率，防止訊號的時間延遲，提高液晶顯示面板的解析度。 Compared with the prior art, since the gate insulating layer 13 is formed under a nitrogen atmosphere, the gate electrode 12 containing the copper material is not oxidized during the formation of the gate insulating layer 13, thereby ensuring the gate 12 The lower resistivity prevents the time delay of the signal and improves the resolution of the liquid crystal display panel.
可變更地，該薄膜電晶體10還可以為頂閘極結構，相應地，該頂閘極薄膜電晶體中覆蓋該閘極的閘極絕緣層的材料與前述閘極絕緣層13的材料相同，製程方法也類似，在此不再累述。另外，雖本實施例中該薄膜電晶體10僅包括一個閘極，然在本發明其他實施例中亦可為雙閘極(dual-gate TFT)結構或者多閘極(multi-gate TFT)結構。 Optionally, the thin film transistor 10 can also be a top gate structure. Correspondingly, the material of the gate insulating layer covering the gate in the top gate thin film transistor is the same as the material of the gate insulating layer 13 . The process method is similar, and will not be described here. In addition, although the thin film transistor 10 includes only one gate in this embodiment, in other embodiments of the present invention, it may be a dual-gate TFT structure or a multi-gate TFT structure. .
當然，本發明並不局限於上述公開的實施例，本發明還可以是對上述實施例進行各種變更。本技術領域人員可以理解，只要在本發明的實質精神範圍之內，對以上實施例所作的適當改變和變化都落在本發明要求保護的範圍之內。 Of course, the present invention is not limited to the above-disclosed embodiments, and the present invention may be variously modified in the above embodiments. Those skilled in the art will appreciate that appropriate changes and modifications of the above embodiments are within the scope of the invention as claimed.
10‧‧‧薄膜電晶體 10‧‧‧film transistor
11‧‧‧基板 11‧‧‧Substrate
12‧‧‧閘極 12‧‧‧ gate
13‧‧‧閘極絕緣層 13‧‧‧ gate insulation
14‧‧‧半導體層 14‧‧‧Semiconductor layer
15‧‧‧源極 15‧‧‧ source
16‧‧‧汲極 16‧‧‧汲polar
Claims (13)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101150833A TWI479664B (en) | 2012-12-28 | 2012-12-28 | Thin film transistor and method for manufacturing the same and liquid crystal display panel using the same |
| CN201310157160.2A CN103915346B (en) | 2012-12-28 | 2013-04-30 | Thin film transistor, manufacturing method thereof and liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101150833A TWI479664B (en) | 2012-12-28 | 2012-12-28 | Thin film transistor and method for manufacturing the same and liquid crystal display panel using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201427029A TW201427029A (en) | 2014-07-01 |
| TWI479664B true TWI479664B (en) | 2015-04-01 |
Family
ID=51040943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101150833A TWI479664B (en) | 2012-12-28 | 2012-12-28 | Thin film transistor and method for manufacturing the same and liquid crystal display panel using the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103915346B (en) |
| TW (1) | TWI479664B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113661574B (en) * | 2020-03-12 | 2024-04-09 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display panel |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201130054A (en) * | 2009-07-10 | 2011-09-01 | Semiconductor Energy Lab | Method for manufacturing semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6245652B1 (en) * | 1998-09-04 | 2001-06-12 | Advanced Micro Devices, Inc. | Method of forming ultra thin gate dielectric for high performance semiconductor devices |
| EP1475828A4 (en) * | 2002-01-15 | 2012-02-22 | Tokyo Electron Ltd | Cvd method and device for forming silicon-containing insulation film |
| CN101393936A (en) * | 2008-11-10 | 2009-03-25 | 友达光电股份有限公司 | Low gate type thin-film transistor and method for producing the same |
| KR20170119742A (en) * | 2009-07-03 | 2017-10-27 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method for manufacturing semiconductor device |
-
2012
- 2012-12-28 TW TW101150833A patent/TWI479664B/en active
-
2013
- 2013-04-30 CN CN201310157160.2A patent/CN103915346B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201130054A (en) * | 2009-07-10 | 2011-09-01 | Semiconductor Energy Lab | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103915346B (en) | 2017-02-15 |
| TW201427029A (en) | 2014-07-01 |
| CN103915346A (en) | 2014-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7494274B2 (en) | Semiconductor Device | |
| JP7390520B1 (en) | Transistors, light emitting display devices, semiconductor devices | |
| JP7072601B2 (en) | Liquid crystal display device | |
| JP7170097B2 (en) | light emitting device | |
| JP7421003B2 (en) | Transistors, light emitting display devices, semiconductor devices | |
| JP6868675B2 (en) | Semiconductor device | |
| JP2024050729A (en) | Semiconductor Device | |
| JP2020053695A (en) | Semiconductor device | |
| Yamazaki et al. | Physics and technology of crystalline oxide semiconductor CAAC-IGZO: application to displays | |
| US20140152932A1 (en) | Liquid crystal display device | |
| TW201250988A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| US20140117347A1 (en) | Thin Film Transistor and Active Matrix Flat Display Device | |
| TWI479664B (en) | Thin film transistor and method for manufacturing the same and liquid crystal display panel using the same | |
| CN104319261B (en) | A kind of preparation method of array base palte, array base palte and display device | |
| JP7209692B2 (en) | semiconductor equipment | |
| CN113661574B (en) | Display substrate, preparation method thereof and display panel |