TWI479342B - Multi-level hierarchical routing matrices for pattern-recognition processors - Google Patents

Description

Multi-level routing matrix for pattern recognition processor

Embodiments of the present invention generally relate to pattern recognition processors, and more particularly, in some embodiments, to connection architectures for such processors.

In the field of computing, pattern recognition tasks are becoming more and more challenging. The amount of data being transmitted between computers is increasing, and the number of types that users want to identify is increasing. For example, spam or malware is typically detected by searching for a pattern in a stream (eg, a particular phrase or fragment code). The number of patterns increases with spam and malware, as new types of samples can be implemented to search for new variants. Searching for a data stream for each of these patterns can create a computational bottleneck. Usually, when receiving a stream of data, it is searched for each type, one at a time. The delay before the system is ready to search for a portion of the data stream increases with the number of patterns. Therefore, pattern recognition can slow down the reception of data.

Such pattern recognition processors may include a large number of finite state machines (FSMs) that move from state to state as the input is processed. The internal connections of conventional processors rely on physical wires connected to a flip-flop or other memory component. However, such connections may not be able to match the performance of a type of search processor. Moreover, such connections are generally not configurable or incapable of meeting a desired functionality. It may be challenging to implement the distance, speed and configurability of such connections in a type of identification processor.

FIG. 1 illustrates an example of a system 10 for searching a data stream 12. System 10 can include a pattern recognition processor 14 that searches for data stream 12 based on search criteria 16.

Each search criterion may specify one or more target expressions (ie, patterns). The phrase "target expression" means that the pattern recognition processor 14 is searching for a sequence of data. Examples of target expressions include spelling a sequence of characters in a word, specifying a sequence of genetic base pairs of a gene, forming a picture of one of a portion of an image, or a sequence of bits in a video file, forming part of a program. A sequence of bits in an executable file or a sequence of bits in an audio file that forms part of a song or a spoken phrase.

A search criterion can specify more than one target expression. For example, a search criterion may specify all five-letter words beginning with the letter sequence "cl", any word beginning with the letter sequence "cl", containing the word "cloud" more than three paragraphs, and the like. The number of possible groups of target expressions is arbitrarily large, for example, there may be as many target expressions as the data arrays that the data stream can present. Search criteria can be expressed in a variety of formats, including regular expressions, concisely specifying target expression groups without having to enumerate one of the target expressions.

Each search criterion may consist of one or more search terms. Thus, each target expression of a search criterion may include one or more search terms and certain target expressions may use a common search term. As used herein, the phrase "search term" refers to a sequence of data that is searched during a single search cycle. The data sequence can include multiple data bits in binary format or in other formats (eg, decimal, ASCII, etc.). The sequence can encode the data with a single digit or multiple digits (eg, a number of binary digits). For example, the pattern recognition processor 14 can search a text data stream 12 one character at a time, and the search item can specify a group of individual characters, for example, the letter "a", the letter "a" or "e". Or, specify a wildcard search term for all of a single character.

The search term may be less than or greater than a specified character (or other glyph - that is, the base unit of information expressed by the data stream, for example, a note, a genetic base pair, a 10-digit bit, or a sub-pixel) The number of yuan. For example, a search term can be 8 bits and a single character can be 16 bits, in which case two consecutive search terms can specify a single character.

The search criteria 16 can be formatted by a compiler 18 for use in the pattern recognition processor 14. Formatting can include deconstructing the search term from such search criteria. For example, if the glyph represented by the data stream 12 is larger than the search terms, the compiler can decompose the search criteria into a plurality of search terms to search for a single glyph. Similarly, if the glyphs represented by the data stream 12 are smaller than the search terms, the compiler 18 can provide each individual glyph with a single search term with one of the unused bits. The compiler 18 can also format the search criteria 16 to support various rule representation operators that are not natively supported by the pattern recognition processor 14.

The pattern recognition processor 14 can search the data stream 12 by evaluating each new item from the data stream 12. Here, the word "item" refers to the amount of data that can match a search term. During a search cycle, pattern recognition processor 14 may determine whether the currently presented item matches the current search term in the search criteria. If the item matches the search item, the "advance" assessment, that is, the next item is compared with the next search item in the search criteria. If the item does not match, the next item is compared to the first item in the search criteria to reset the search.

Each search criterion can be compiled into one of the different finite state machines (FSMs) in the pattern recognition processor 14. The finite state machines can be run in parallel to search the data stream 12 based on the search criteria 16. When the data stream 12 matches the previous search term, the finite state machines may step through each successive search term in a search criterion, or if the search term is not matched, the finite state machine may start searching The first search term for the search criteria.

Pattern recognition processor 14 may evaluate each new item based on a number of search criteria and their respective search terms, for example, at approximately the same time during a single device cycle. The parallel finite state machines can each receive an item from the data stream 12 at about the same time, and each of the parallel finite state machines can determine whether the item advances the parallel finite state machine into its search criteria The next search item. The parallel finite state machines may evaluate terms based on a relatively large number of search criteria (eg, more than 100, more than 1000, or more than 10,000). Because of their parallel operation, they can apply the search criteria to a data stream 12 having a relatively high frequency width (eg, greater than or substantially equal to 64 MB per second or 128 MB per second). Without slowing down the data stream. In some embodiments, the search loop duration is not scaled by the number of search criteria, so the number of search criteria can have little effect on the performance of the pattern recognition processor 14.

When a search criterion is met (i.e., after advancing to and matching with the last search term), the pattern recognition processor 14 can report the satisfaction of the criteria to a processing unit, such as a central processing unit (CPU). ) 20. The central processing unit 20 can control the pattern recognition processor 14 and other portions of the system 10.

System 10 can be any of a variety of systems or devices that search for a stream of data. For example, system 10 can search for data stream 12 on a desktop, laptop, handheld, or other type of computer. System 10 can also be a network node, such as a router, a server, or a client (e.g., one of the computers of the type previously described). System 10 can be in some other category of electronic devices, such as a copier, a scanner, a printer, a game console, a television, an on-board video distribution or recording system, a cable box, a number of people A media player, a factory automation system, a car computer system, or a medical device. (The terms used to describe these various examples of the system (as many other terms are used herein) may share certain references, and thus should not be narrowly understood by virtue of the other items listed).

The data stream 12 can be one or more of a variety of types of data streams that a user or other entity may wish to search. For example, data stream 12 may receive a stream of data via a network, such as a packet received via the Internet or a voice or material received via a cellular network. Data stream 12 may be data received from a sensor (e.g., an imaging sensor, a temperature sensor, an accelerometer, or the like, or a combination thereof) in communication with system 10. The data stream 12 can be received by the system 10 as a series of data streams, where the data is received in an order of meaning (such as in a significant time, lexical or semantic order). Alternatively, data stream 12 may be received in parallel or out of order and then converted to a series of data streams, for example, by reordering packets received over the Internet. In some embodiments, the data stream 12 can present items in a serial fashion, but the bits expressing each of the items can be received in parallel. The data stream 12 can be received from a source external to the system 10 or can be formed by interrogating a memory device and forming a data stream 12 from the stored data.

Looking at the type of data in the data stream 12, a designer can select different types of search criteria. For example, the search criteria 16 can be a virus definition file. The virus or other malware can be characterized and the pattern of malware can be used to form a search criterion indicating whether the data stream 12 is likely to be delivering malware. The resulting search criteria can be stored on a server, and an operator of one of the client systems can subscribe to download the search criteria to one of the services of system 10. When different types of malware appear, the search criteria 16 can be periodically updated from the server. The search criteria can also be used to specify undesired content that can be received via a network, for example, unwanted email (often referred to as spam) or other content that a user dislikes.

The data stream 12 can be searched by a third party interested in the material being received by the system 10. For example, the data stream 12 can be searched for text, an audio sequence, or a video sequence that appears in a copyrighted work. The data stream 12 can be searched for statements relating to a criminal investigation or civil action or an employer's interest. In other embodiments, monitoring a data stream for the data of interest may search for one instance.

The search criteria 16 may also include a pattern in the data stream 12, for example, one of the patterns may be translated in a memory addressable by the CPU 20 or the pattern recognition processor 14. For example, the search criteria 16 can each define an English word for which a corresponding Spanish word is stored in the memory. In another example, the search criteria 16 may specify an encoded version of the data stream 12 (eg, MP3, MPEG 4, FLAC, Ogg Vorbis, etc.) for which one of the data streams 12 may be decoded. Version, or vice versa.

The pattern recognition processor 14 may be integrated with the CPU 20 into a single component, such as a single device, or may be formed as a separate component. For example, the pattern recognition processor 14 can be a separate integrated circuit. The pattern recognition processor 14 may be referred to as a "synergy processor" or a "pattern recognition coprocessor".

FIG. 2 illustrates an example of a pattern recognition processor 14. The pattern recognition processor 14 can include an identification module 22 and a summary module 24. The identification module 22 can be configured to compare the received item to the search term, and the recognition module 22 and the summary module 24 can cooperate to determine whether matching an item with a search term satisfies a search criterion.

The identification module 22 can include a column of decoders 28 and a plurality of characteristic cells 30. Each feature cell 30 can define a search term, and the set of feature cells 30 can form a parallel finite state machine that forms a search criterion. The components of the feature cell 30 can form a search term array 32, a detection array 34, and a boot routing matrix 36. The search term array 32 can include a plurality of input conductors 37, each of which can cause each of the feature cells 30 to communicate with the column decoder 28.

Column decoder 28 may select a particular conductor among a plurality of input conductors 37 based on the contents of data stream 12. For example, column decoder 28 may initiate one byte to one of 256 columns to one of 256 columns based on a value that can represent a byte received by one of the items. A one-tuple entry 0000 0000 may correspond to a top column of the plurality of input conductors 37, and a one-tuple entry 1111 1111 may correspond to a bottom column of the plurality of input conductors 37. Thus, depending on which items are received from the data stream 12, different input conductors 37 can be selected. Upon receiving a different item, column decoder 28 may undo the column corresponding to the previous item and initiate a column corresponding to the new item.

The detection array 34 can be coupled to a detection busbar 38 that outputs a signal indicating that the search criteria are fully or partially satisfied to the summary module 24. The launch routing matrix 36 can selectively enable and deactivate the boot feature cell 30 based on, for example, the number of search terms that have been matched in a search criterion.

The summary module 24 can include a latch matrix 40, a summary routing matrix 42, a threshold logic matrix 44, a logic product matrix 46, a logic sum matrix 48, and an initialization routing matrix 50.

Latch matrix 40 can implement portions of certain search criteria. Some search criteria (eg, certain rule expressions) count only one match or the first occurrence of a match group. Latch matrix 40 may include a latch that records whether a match has occurred. When it is determined that the search criteria are satisfied or not further satisfied - that is, an earlier search term may need to be matched again before the search criteria can be met, the latches may be cleared during initialization and cycled during operation Reinitialize reinitially.

The summary routing matrix 42 can function similar to the initiation routing matrix 36. The summary routing matrix 42 may receive signals indicative of the match on the detection bus 38 and may route the signals to different group logic lines 53 connected to the threshold logic matrix 44. The summary routing matrix 42 may also route the output of the initialization routing matrix 50 to the detection array 34 to reset portions of the detection array 34 when it is determined that a search criterion is satisfied or not further satisfied.

The threshold logic matrix 44 can include a plurality of counters, for example, a 32-bit counter configured to increment or decrement the count. The threshold logic matrix 44 can be loaded with an initial count and can count up or down from the count based on the match sent by the recognition module. For example, the threshold logic matrix 44 can count the number of occurrences of a word in a certain length of text.

The output of the threshold logic matrix 44 can be an input to the logical product matrix 46. The logical product matrix 46 can selectively produce "product" results (e.g., "AND" functions in Boolean logic). The logical product matrix 46 can be implemented as a square matrix in which the number of output products is equal to the number of input lines from the threshold logic matrix 44, or the logical product matrix 46 can have an input different from the number of outputs. The resulting product value can be output to the logical sum matrix 48.

Logic and matrix 48 can selectively generate sums (e.g., "OR" functions in Boolean logic). The logical sum matrix 48 can also be a square matrix, or the logical sum matrix 48 can have an input that is different from the number of outputs. Since the inputs are logical products, the output of the logic and matrix 48 can be a logical sum of (e.g., the sum of products of the Boolean logic (SOP) form). The output of the logical sum matrix 48 can be received by the initialization routing matrix 50.

The initialization routing matrix 50 can reset portions of the detection array 34 and the summary module 24 via the summary routing matrix 42. The initialization routing matrix 50 can also be implemented as a square matrix, or the initialization routing matrix 50 can have an input that is different from the number of outputs. The initialization routing matrix 50 may, in response to a signal from the logic and matrix 48, reinitialize the pattern identifying other portions of the processor 14 when a search criterion is satisfied or the search criteria are not further satisfied.

The summary module 24 can include an output buffer 51 that receives the output of the threshold logic matrix 44, the summary routing matrix 42, and the logic and matrix 48. The output of summary module 24 can be transmitted from output buffer 51 to CPU 20 (FIG. 1) on output bus 26. In some embodiments, an output multiplexer can multiplex signals from such components 42, 44, and 48 and output signals indicative of criteria or matching search terms to CPU 20 (FIG. 1). In other embodiments, the results from the pattern recognition processor 14 may be reported without transmitting the signals through the output multiplexer, which is not meant to imply or omit any of the other features described herein. For example, signals from the threshold logic matrix 44, the logic product matrix 46, the logic and matrix 48, or the initialization routing matrix 50 can be transmitted to the CPU in parallel on the output bus 26.

3 illustrates a portion of a single feature cell 30 (referred to herein as a component of a search term cell 54) in a search term array 32 (FIG. 2). The search term cell 54 can include an output conductor 56 and a plurality of memory cells 58. Each of the memory cells 58 can be coupled to both one of the output conductor 56 and one of the plurality of input conductors 37. In response to selecting its input conductor 37, each of the memory cells 58 can output a value indicative of its stored value to output data through the output conductor 56. In some embodiments, the plurality of input conductors 37 can be referred to as "word lines," and the output conductors 56 can be referred to as a "data line."

Memory cell 58 can comprise any of a variety of types of memory cells. For example, memory cell 58 can be a volatile memory such as a dynamic random access memory (DRAM) cell having a transistor and a capacitor. The source and drain of the transistor can be respectively connected to one of the capacitor plates and the output conductor 56, and the gate of the transistor can be connected to one of the input conductors 37. In another example of volatile memory, each of the memory cells 58 can comprise a static random access memory (SRAM) cell. The SRAM cell can have an output that is selectively coupled to the output conductor 56 by an access transistor controlled by one of the input conductors 37. Memory cell 58 may also contain non-volatile memory, such as phase change memory (eg, an ovonic device), flash memory, germanium-oxide-nitride-oxide-germanium (SONOS). Memory, magnetoresistive memory or other types of non-volatile memory. The memory cell 58 can also include a flip-flop (e.g., a memory cell made of a logic gate).

4 and 5 illustrate an example of a search term cell 54 in operation. Figure 4 illustrates that search term cell 54 receives one of the search terms that do not match the cell, and Figure 5 illustrates a match.

As illustrated in FIG. 4, the search term cell 54 can be configured to search for one or more items by storing the data in the memory cell 58. The memory cells 58 can each represent one of the data streams 12 that can be presented. For example, in FIG. 3, each memory cell 58 represents a single letter or number, beginning with the letter "a" and ending with the number "9". . The memory cell 58 representing the item satisfying the search term can be programmed to store a first value, and the memory cell 58 not representing the item satisfying the search term can be programmed to store a different value. In the illustrated example, search term 54 is configured to search for the letter "b." The memory cell 58 representing "b" can store 1 or logic high, and the memory cell 58 not representing "b" can be programmed to store 0 or logic low.

To compare one of the data streams 12 from the search term, the column decoder 28 can optionally couple to the input conductor 37 representing the memory cell 58 of the received item. In Figure 4, data stream 12 presents a lowercase "e". This item may be presented by data stream 12 in the form of an octet ASCII code, and column decoder 28 may interpret the byte as a list of addresses to output a signal thereon by energizing conductor 60. .

In response, memory cell 58 controlled by conductor 60 can output a signal indicative of one of the data stored by memory cell 58 and can be delivered by output conductor 56. In this case, since the letter "e" is not one of the items specified by the search term cell 54, it does not match the search term, and the search term cell 54 outputs a value of 0, indicating that no match is found.

In Figure 5, data stream 12 presents a character "b". Additionally, column decoder 28 can interpret this as a single address, and column decoder 28 can select conductor 62. In response, the memory cell 58 representing the letter "b" outputs its stored value, in which case the value is one, indicating a match.

The search term cell 54 can be configured to search for more than one item at a time. A plurality of memory cells 58 can be programmed to store one, thereby specifying one of the search terms that matches more than one item. For example, the memory cell 58 representing the lowercase letter "a" and the capital letter "A" can be programmed to store 1 and the search term cell 54 can search for any one. In another example, the search term cell 54 can be configured to output a match if any of the characters are received. All memory cells 58 can be programmed to store 1 such that the search term 54 can act as one of the search criteria.

6-8 illustrate the recognition module 22 searching for a word based on a plurality of search criteria (for example). Specifically, FIG. 6 illustrates that the recognition module 22 detects the first letter of a word, FIG. 7 illustrates the detection of the second letter, and FIG. 8 illustrates the detection of the last letter.

As illustrated in Figure 6, the identification module 22 can be configured to search for the word "big." Three adjacent characteristic cells 63, 64 and 66 are illustrated. The feature cell 63 is configured to detect the letter "b". The feature cell 64 is configured to detect the letter "i". The signature cell 66 is configured to detect both the letter "g" and the search criteria.

FIG. 6 also depicts additional details of the detection array 34. The detection array 34 can include one of the characteristic cells 63, 64, and 66 to detect the cell 68. Each of the detection cells 68 can include a memory cell 70 (such as one of the types of memory cells described above (eg, a flip-flop)) that indicates the characteristic cell 63, Whether 64 or 66 is active or inactive. The detection cell 68 can be configured to output a signal indicative of whether the detected cell is active and indicating whether a signal indicative of a match has been received from its associated search term 54 to the enable routing matrix 36. The inactive eigencells 63, 64, and 66 can ignore the match. Each of the detection cells 68 can include an AND gate having inputs from the memory cell 70 and the output conductor 56. The output of the AND gate can be routed to either or both of the detection bus 38 and the routing matrix 36.

The enable routing matrix 36 can in turn selectively activate the characterization cells 63, 64, and 66 by writing to the memory cells 70 in the detection array 34. The initiation routing matrix 36 can initiate the signature cells 63, 64 or 66 based on the search criteria and which search term is being searched for in the data stream 12 next.

In Figure 6, data stream 12 presents the letter "b". In response, each of the characteristic cells 63, 64, and 66 can output a signal indicative of one of the values stored in the memory cell 58 (which represents the letter "b") connected to the conductor 62 on its output conductor 56. . The detection cells 68 can then each determine whether they have received a signal indicating that a match and whether or not they are active. Since the characteristic cell 63 is configured to detect the letter "b" and is active (as indicated by its memory cell 70), the detection cell 68 in the characteristic cell 63 can indicate the first search indicating that the search criteria have been matched. One of the items is output to the start routing matrix 36.

As illustrated in FIG. 7, after matching the first search term, the initiation routing matrix 36 can initiate the next feature cell 64 by writing 1 to the memory cell 70 in its detection cell 68. In the case where the next item satisfies the first search term (for example, if the received item sequence "bbig"), the start routing matrix 36 can also maintain the active state of the feature cell 63. During a portion of the time or substantially all of the time during which the data stream 12 is searched, the first search term of the search criteria may remain in an active state.

In FIG. 7, data stream 12 presents the letter "i" to recognition module 22. In response, each of the characteristic cells 63, 64, and 66 can output a signal indicative of one of the values stored in the memory cell 58 (which represents the letter "i") connected to the conductor 72 on its output conductor 56. The detection cells 68 can then each determine whether they have received a signal indicating that a match and whether or not they are active. Since the characteristic cell 64 is configured to detect the letter "i" and is active (as indicated by its memory cell 70), the detection cell 68 in the characteristic cell 64 can A signal indicating that one of the search terms below its search criteria has been matched is output to the boot routing matrix 36.

Next, launching routing matrix 36 can initiate feature cell 66, as illustrated in FIG. The activation feature cell 64 can be revoked prior to evaluating the next item. The activation feature cell 64 can be revoked by resetting the memory cell 70 between the detection cycles by the detection cell 68 of the feature cell 64, or by initiating the routing matrix 36 to revoke the activation feature cell 64, for example.

In Figure 8, data stream 12 presents item "g" to column decoder 28, which selects conductor 74 representing item "g". In response, each of the characteristic cells 63, 64, and 66 can output a signal indicative of one of the values stored in the memory cell 58 (which represents the letter "g") connected to the conductor 74 on its output conductor 56. . The detection cells 68 can then each determine whether they have received a signal indicating that a match and whether or not they are active. Since the characteristic cell 66 is configured to detect the letter "g" and is active (as indicated by its memory cell 70), the detection cell 68 in the characteristic cell 66 can indicate that the last match has been matched to its search criteria. One of the search terms is output to the start routing matrix 36.

An end of a search criterion or a portion of a search criterion may be identified by the initiation routing matrix 36 or the detection cell 68. Such components 36 or 68 may include memory indicating whether their characteristic cells 63, 64 or 66 are the last search term specifying a search criterion or a component of a search criterion. For example, a search criterion may specify all sentences in which the word "cattle" appears twice, and the recognition module may output a signal indicating each occurrence of "cattle" in a sentence to the summary module, the summary The module can count the occurrences to determine if the search criteria are met.

The characteristic cells 63, 64 or 66 can be activated under a number of conditions. A characteristic cell 63, 64 or 66 may be "always active", which means that it remains active during all or substantially all of a search. An example of an always-acting characteristic cell 63, 64 or 66 is the first characteristic cell of the search criteria (e.g., characteristic cell 63).

A feature cell 63, 64 or 66 may be "active at the time of request", which means that the feature cell 63, 64 or 66 matches a previous condition (eg, matches a previous search term in a search criterion) When) is in effect. An example is a feature cell 64 that is active in the request of the feature cell 63 in Figures 6-8 and a feature cell 66 in the action of the feature cell 64.

A feature cell 63, 64 or 66 may be "self-starting", which means that once it is activated, it activates itself as long as it matches its search term. For example, a self-starting feature cell having one of the search terms matched by any numerical digit can remain active in the sequence "123456xy" until the letter "x" is reached. Whenever the search term of the self-starting feature cell is matched, it can initiate the next feature cell in the search criteria. Therefore, an always-acting feature cell can be formed by a self-starting feature cell and a feature cell that acts upon request: the self-starting feature cell can be programmed and all of its memory cells 58 are stored, and After each item, the characteristic cells in the action at the time of the request are repeatedly started. In some embodiments, each of the characteristic cells 63, 64, and 66 may include in its detection cell 68 or in the initiation routing matrix 36 a memory cell that specifies whether the characteristic cell is always active, thereby A single characteristic cell forms an always acting trait cell.

FIG. 9 illustrates an example of one of the identification modules 22 configured to search in parallel based on a first search criterion 75 and a second search criterion 76. In this example, the first search criterion 75 specifies the word "big" and the second search criterion 76 specifies the word "cab." A signal indicating that one of the current items from the data stream 12 can be communicated to the feature cells in each of the search criteria 75 and 76 at substantially the same time. Each of the input conductors 37 spans both search criteria 75 and 76. Thus, in some embodiments, both search criteria 75 and 76 can generally evaluate the current term at the same time. It is believed that this accelerates the evaluation of search criteria. Other embodiments may include more feature cells configured to evaluate more search criteria in parallel. For example, some embodiments may include more than 100, 500, 1000, 5000, or 10,000 signature cells operating in parallel. These characterization cells can generally evaluate hundreds or thousands of search criteria simultaneously.

Search criteria with a different number of search terms can be formed by assigning more or fewer signature cells to the search criteria. Simple search criteria can consume fewer resources in the form of eigencells than complex search criteria. It is believed that this reduced model recognizes the cost of processor 14 (FIG. 2) relative to processors having a large number of substantially identical cores (all configured to evaluate complex search criteria).

10 through 12 illustrate both an example of a more complex search criterion and the features of the launch routing matrix 36. The boot routing matrix 36 can include a plurality of boot routing cells 78, the group of which can be associated with each of the character cells 63, 64, 66, 80, 82, 84, and 86. For example, each of the eigencells can include 5, 10, 20, 50 or more priming routing cells 78. The boot routing cell 78 can be configured to transmit an enable signal to a search term below a search criterion when matching a previous search term. The boot routing cell 78 can be configured to route the enable signal to neighboring feature cells or other boot routing cells 78 within the same feature cell. The initiation routing cell 78 can include memory indicating which feature cells correspond to the next search term in a search criterion.

As illustrated in Figures 10-12, the identification module 22 can be configured to search based on complex search criteria rather than criteria for specifying a single word. For example, the suffix module 22 can be configured to search for words beginning with a first code 88 and ending with one of the two tail codes 90 or 92. The illustrated search criteria stipulate the words beginning with the letters "c" and "l" in the sequence and ending with the letter sequence "ap" or the letter sequence "oud". This is an example of one of the search criteria for one of a plurality of target expressions (eg, the word "clap" or the word "cloud").

In FIG. 10, the data stream 12 presents the letter "c" to the recognition module 22, and the feature cell 63 is both active and detecting a match. In response, launching routing matrix 36 may initiate the next feature cell 64. The initiation of the routing matrix 36 also maintains the active state of the eigencell 63, since the eigencell 63 is the first search term in the search criteria.

In Figure 11, data stream 12 presents a letter "l" and feature cell 64 recognizes a match and is active. In response, the initiation routing matrix 36 can transmit an enable signal to both the first signature cell 66 of the first trailer code 90 and the first signature cell 82 of the second trailer code 92. In other instances, more tail codes may be initiated, or multiple first codes may initiate one or more tail codes.

Next, as illustrated in FIG. 12, the data stream 12 presents the letter "o" to the recognition module 22, and the feature cell 82 of the second tail code 92 detects a match and is active. In response, the initiation routing matrix 36 can initiate a feature cell 84 below the second tail code 92. The search for the first tail code 90 can be stopped while allowing the feature cell 66 to become inactive. The steps illustrated in Figures 10 through 12 may continue through the letters "u" and "d", or the search may be stopped until the next match of the first code 88.

Embodiments of the pattern recognition processor 14 can include any configuration of the signature cells 30. 13 through 16 illustrate a hierarchical configuration of a characteristic cell 30 in accordance with an embodiment of the present invention. In one embodiment, as depicted in FIG. 13, one of the first levels of the hierarchy may include a characteristic cell 30 configured as a group 94 of two characteristic cells 30 (characteristic 1 and characteristic 0). Each feature cell 30 can receive an input (eg, an enable state signal) and can output a next state signal to another group of feature cells. Each of the characterization cells 30 in the group 94 can be coupled to provide an output one output drive selection 96 from the group 94 based on the output of each characterization cell 30. For example, in one embodiment, the output drive selection 96 can be configured to output one of the next state output "0" signals received from the characterization cell 30, the next state output "1" signal, or two next. The logical OR of the status output signal.

As shown in FIG. 14, a second level hierarchy can include each group 94 of signature cells configured as one of the columns 94 of the group 94. Each column 98 can include any number of groups 94 of characteristic cells 30. For example, in the embodiment shown in FIG. 14, column 98 can include eight groups 94 of two characterization cells 30, such as group 0 through group 7.

As shown in FIG. 15, one of the levels of the third level may include a plurality of columns 98 that are aggregated into blocks 100, with each block 100 containing one or more columns 98. In one embodiment of processor 14, each block 100 can include 16 columns 98, such as columns 0 through 15. Pattern recognition processor 14 may then include any number of blocks 100 for implementing the programmed state machine and pattern search described above. As shown in FIG. 16, in one embodiment, pattern recognition processor 14 may include 512 blocks, for example, block 0 through block 512.

Group 94, column 98, and block 100 illustrated above illustrate one hierarchical configuration of feature cells. A programmed state machine can include any number of characteristic cells 30. Thus, each group, column or block can contain multiple programmed state machines. During operation of pattern recognition processor 14, such as during the seek cycle described above, the next state signal is selected by output from each of the characterization cells 30 and driven by the output of each group 94. Each state of a programmed state machine (eg, one or more feature cells) is routed to a state below the programmed state machine (referred to as "next state route").

17 through 21 illustrate a multi-hierarchy routing matrix that provides next state routing, programmability, and high throughput in accordance with an embodiment of the present invention. As used herein, the term "routing matrix" refers to a plurality of connections used for routing communications between components of the pattern recognition processor 14. The "routing matrix" described below may be functionally different from the matrix described above in Figures 1 through 12. As further explained below, the routing matrix can provide a programmable and/or non-programmable connection at each level of each level of the pattern recognition processor 14 described above, in each level, and between each level. . The connections may identify the routing lines between the feature cells, groups, columns, and blocks of the pattern identification processor 14. Such connections may include, but are not limited to, the following types of connections: programmable and non-programmable; one-way and two-way; logical combinations ("or", "and", "mutually exclusive", etc.); selectors ( For example, one of many); and an isolator (blocking to a line of connections). A programmable connection can be configured to perform any of the functions listed above. For example, a programmable connection can be programmed into one-way, two-way, any logical combination, selector, splitter, and the like. An unprogrammable connection can perform any of the functionalities described above, but cannot be programmed to have a different functionality.

The connection symbols summarized in Table 1 below show the connections in Figures 17 to 21:

Figure 17 depicts a hierarchical hierarchy comprising a group 94 of feature cells 30 as described above in Figure 13 and in accordance with an embodiment of the present invention. As mentioned above, each feature cell 30 can receive an enable feature cell as one of the next states input. As also mentioned above, based on the pattern matching performed by the search criteria programmed in the feature cell 30, the feature cell 30 can generate an output that enables the next active state (next state signal).

The routing of the input and output signals of the characteristic cells 30 is determined by such connections. The characteristic cells 30 of the group 94 can be interconnected by the local routing line 102 (the local routing 0 and the local routing 1). The output of the characterization cell 30 of group 94 is coupled by output connection 104 to local routing line 102 and output driver selection 96. For example, the eigencell 0 is coupled to the local routing line 0 by a first output connection 104A and the eigencell 1 is coupled to the local routing line 1 by a second output connection 104B. As depicted in Figure 17, in one embodiment, the output connection is a "first level" connection that is not programmable. In this embodiment, the connection 104 is non-removable and non-configurable. In other embodiments, the output connection 104 can be stylized.

Output drive selection 96 can be programmed to drive any number or type of signals from the received output of characteristic cell 30. As mentioned above, in one embodiment, the output drive selection 96 can be configured to output one of three possible logical outputs: "Next State Output 0"; "Next State Output 1"; Or the logical OR of the two next state output signals. In other embodiments, the output drive selection 96 can be configured to output other logical combinations, such as "and", "not", and/or "mutually exclusive".

The local routing line 102 can be coupled by input connection 106 to an input 105 of the characterization cell 30 (which can represent one or more input signals). For example, eigencell 0 can be coupled to local routing lines 0 and 1 by input connections 106A and 106B, respectively. Similarly, the characteristic cells 1 can be coupled to the local routing line 0 and the local routing line 1 by input connections 106C and 106D, respectively. As shown in Figure 17, the input connection 106 can be a "1st level" connection that can be programmed. In this embodiment, the input connection 106 can be configured to provide a logical "OR" to any of the connection inputs 105.

Figure 18 depicts a hierarchy of columns 98 having groups 94 as described above in Figure 14 and in accordance with one embodiment of the present invention. As mentioned above, each column 98 can include any number of groups 94 of characteristic cells 30, such as group 0 through group 7 shown in FIG. Groups of columns 98 may be interconnected by column routing lines 108. In one embodiment, column routing lines 108 may be provided for each column of block 100. Thus, in one embodiment where each block 100 has 16 columns 98, 16 column routing lines can be provided, for example, column routing line 0 to column routing line 15.

The output from the output drive selection 96 of each group 94 can be coupled to each column routing line 108 by an output connection 110. In one embodiment, the output connections can be programmed to "level 2" connections. As shown in FIG. 18, for example, group 0 can be coupled to column routing lines 0 and 15 by output connections 110A and 110B, respectively. Group 7 can be coupled to column routing lines 0 and 15 by output connections 110C and 110D, respectively. All other column routing lines (not shown) may be coupled by output connection 110 to the output drive selections of Groups 0 through 7. The output connections 110 can be configured such that the output drive selection 96 of a group 94 can drive or not drive a particular column routing line 108.

Additionally, column routing line 108 can be coupled to input 105 of each characteristic cell 30 by input connection 112. In one embodiment, the input connection 112 can be a "program 2" connection that can be programmed. For example, column routing line 108 can be coupled to input of eigencell 0 of group 0 by input connections 112A and 112B, and column routing line 108 can be coupled to input of eigencell 1 of group 0 by input connections 112C and 112D. Similarly, as also shown in FIG. 18, column routing line 108 can be coupled to input of eigencell 0 of group 7 by input connections 112E and 112F, and column routing line 108 can be coupled to group 7 by input connections 112G and 112H. Characteristic cell 1. Other column routing lines (not shown) may be coupled to the input of each of the characterization cells 30 of each of the groups 94 of columns 98. In this embodiment, the input connection 112 can be programmed to be one of the logical inputs "OR" of any of the connected inputs of the feature cell 30. In other embodiments, the connections may be unprogrammable and/or bidirectional.

Next, FIG. 19 illustrates a hierarchical level of a block 100 having a plurality of columns 98 as described above in FIG. 15 and in accordance with an embodiment of the present invention. As described above, block 100 can include any number of columns 98, such as columns 0 through 15. Columns 98 of block 100 may be connected by block internal routing lines 114. The block internal routing line 114 can be coupled to the column routing line 112 by a bidirectional connection 116. In one embodiment, the two-way connections may be programmable "level 3" connections. For example, the block internal line by line 0 can be coupled by bidirectional connection 116A to column 0 of routing line 0 and by bidirectional connection 116B to column 0 of routing line 15. The block internal line is coupled by line 0 from bidirectional connection 116C to column 15 routing line 0 and by bidirectional connection 116D to column 15 routing line 15. Similarly, block internal routing line 23 can be coupled by bidirectional connection 116E to column 0 routing line 0 and by bidirectional connection 116F to column 0 column routing line 15. In addition, as also shown in FIG. 19, the block internal routing line 23 can be coupled by a bidirectional connection 116G to the column 15 routing line 0 and by the bidirectional connection 116H to the column 15 routing line 15. Other block internal lines (not shown) may be coupled to each of the column routing lines 112 of each column 98 by a bidirectional connection 116.

As described above, the two-way connection 116 can be programmable. Thus, the bidirectional connection 116 can be programmed to enable one or more of the intra-block routing lines 114 to drive a respective column routing line 112 or to enable one or more column routing lines 112 to drive a respective block interior. Routing line 114. Each bidirectional connection 116 can be individually programmed to achieve a configuration of the connection between the column routing line 112 and the block internal routing line 114 on a line by line basis. In other embodiments, the connections may be unprogrammable and/or unidirectional.

20 illustrates a top level hierarchy 117 of a routing matrix having a block 100 in accordance with an embodiment of the present invention. In one embodiment, as shown in FIG. 20, the top level 117 may include 512 blocks 100, such as block 0 through block 511. Block 100 may be interconnected by a top level routing line 118. The top level routing line 118 can be connected to the block internal routing line 114 by a bidirectional connection 120. Thus, as shown in FIG. 20, the top level routing line 0 can be coupled to the block internal routing line 0 and the block internal routing line 23 of block 0 by bidirectional connections 120A and 120B, respectively. Similarly, top level routing line 0 can be coupled to block internal 0 and block internal 23 of block 511 by bidirectional connections 120C and 120D, respectively. As shown in FIG. 20, the top level routing line 23 can be coupled to the block internal routing line 0 and the block internal routing line 23 of block 0 by bidirectional connections 120E and 120F, respectively. In addition, the top level routing line 23 can be coupled to the block internal line 0 and the block internal line 23 of the block 511 by bidirectional connections 120G and 120H, respectively. All other top level routing lines (not shown) may be coupled to the block inner line 114 of block 100 by a bidirectional connection 120.

As shown in FIG. 20, the bidirectional connection 120 can be a "fourth level connection" that can be programmed. The bidirectional connection can be programmed to enable one or more of the block internal routing lines 114 to drive a respective top level routing line 118 or to enable one or more top level routing lines 118 to drive a respective block internal routing line 114. . Thus, connection 120 can be programmed and configured on a line by line basis. In other embodiments, the connections may be unprogrammable and/or unidirectional.

Advantageously, the multi-hierarchy routing matrix described above provides the regularity of programmability of the device, redundant implementations for improved production and manufacturing yields, variability of different applications, and more logical changes. Easy visualization and implementation.

As mentioned above, such connections may be capable of "blocking" a line such that no signal is routed on a line to enable the isolator of one of the redundant sections of the pattern recognition processor 14 to be deactivated. 21 illustrates the isolation of one or more characteristic cells 30 of the pattern recognition processor 14 in accordance with an embodiment of the present invention. For example, the pattern recognition processor 14 can include a block 130 of feature cells 30 that provides more capacity than that used by the pattern recognition processor 14. That is, during manufacturing, to increase yield, the type identification processor 14 can produce a memory capacity (excessive characteristic cells 30) that is greater than the capacity specified for the function of the processor 14. During manufacture and testing of processor 14, excess signature cells 30 may be "deactivated" by removing feature cells available to the programmed state machine used by processor 14. Some embodiments may not use all of the blocks of the characteristic cells 30. In such embodiments, blocks that are not in use may be deactivated. The deactivated block may not be "launched" and/or "powered" and may not be updated during the update cycle.

Block 130 may be coupled to other portions of pattern recognition processor 14 by a connection 132 between the top level routing line and the block internal routing line. In this embodiment, connection 132 can be a programmable "level 4 connection" that can be programmed to any desired functionality. Thus, if block 130 provides excess capacity, connection 132 can be programmed to isolate block 130 from the remainder of the routing lines. Thus, the programmable connection 132 can "block" the connection between the top level routing line 118 and the block internal routing line 114. Block 130 may be referred to as "deactivated." In addition, the unused block 130 can be "powered off", such as by setting an appropriate stylized bit in block 130.

In contrast, other blocks for providing memory capacity for the programmed state machine of the pattern recognition processor 14 can be accessed through the top level routing line 118 and the block internal routing line 114. For example, as shown in FIG. 21, block 134 is also connected by connection 136 to the same top level routing line 118 as deactivated block 132. As shown in Figure 21, connection 136 can be a programmable level 4 connection. However, connection 136 can be programmed to enable access to the memory capacity provided by block 134, such as by allowing the top level routing line to drive the block internal routing lines (or vice versa). In other embodiments, the feature cell 30 may be deactivated at the column level, such as by staging the connection 138 between the block internal routing line 114 and the column routing line 112, and/or, for example, by a program The connection 140 between the routing line 112 and the local routing line 102 is deactivated at the group level.

Moreover, in other embodiments, the multi-hierarchy routing matrix described above may differ in tiers, connections, etc. based on the pattern matching functionality implemented in the pattern recognition processor 14. For example, other embodiments may include a different number of levels in a hierarchy, and/or include a different number of connections between levels, groups, columns, and/or blocks. In addition, other embodiments may include different stylized functions that can be used to programmatically connect, different types of connections and different points in the hierarchy, the ability to programmatically block the connection lines into multiple lines, and in the hierarchy. The ability to add and/or remove different functionalities at different levels.

FIG. 22 illustrates a process 142 of configuring the multi-hierarchy routing matrix described above in accordance with an embodiment of the present invention. During configuration of the pattern recognition processor 14, the connections between each level and each level of the hierarchy can be programmed in either order. Moreover, such connections can be programmed manually or automatically based on the particular pattern matching implementation desired in the pattern recognition processor 14. It should also be appreciated that the stylization of connections between levels or levels of a matrix may depend on the functionality programmed into other levels of the matrix. First, the connection at the first level hierarchy can be programmed (block 144). For example, this may include the connection between the output of the stylized feature cell 30 and the local routing line 102 and the input of the stylized feature cell 30 and the local routing line 102, such as stylized as described above in FIG. Connection 106. In some embodiments, the input and/or output connections from the characterization cell 30 may be unprogrammable and may not be stylized. For example, as also described above in FIG. 17, in one embodiment, the output connection 104 can be a non-programmable connection.

Next, the connection at one of the second levels of the hierarchy can be programmed (block 146). In one embodiment, this stylization may include an input connection between the stylized column routing line 108 and a group 94, as described above in FIG. For example, the connection 112 between the input of the signature cell 30 and the column routing line 108 can be programmed as a logical "or" (or other function) to the input 105 of the signature cell 30. Similarly, output connection 110 can be programmed to provide the desired functionality between the column routing lines and output driver selection 96 of group 94.

In addition, the connection at one of the third levels of the hierarchical routing matrix can be programmed (block 148). As discussed above in FIG. 19, in one embodiment, the connection 116 between the column routing line 112 and the block internal routing line 114 can be programmed. For example, connection 116 can be programmed to provide the desired functionality between block internal routing line 114 and column routing line 112 to isolate (deactivate) certain feature cells or provide any other programmable functionality. .

Next, the connection at a fourth level hierarchy can be programmed (block 150). In the embodiment illustrated in FIG. 20 above, this stylization may include a connection between the stylized block internal routing line 114 and the top level routing line 118. For example, the connection 120 shown above in FIG. 20 can be programmed to provide the desired functionality between the top level routing line 118 and the block internal routing line 114. As also discussed above in FIG. 21, in some embodiments, this stylization can include the redundancy capacity (eg, characteristic cells) of the deactivation pattern recognition processor 14. As shown in Figure 22, this stylization of the connection can continue until the nth level of the routing matrix (block 152). By stabilizing the connections of the routing matrix, the pattern recognition processor 14 can be configured to provide the desired logic and next state routing between the characterization cells (and state machines). As mentioned above, the stylization of the connections provides an understanding of the configuration of the pattern recognition processor 14 and also provides routing flexibility and variability for different implementations.

10. . . system

12. . . Data stream

14. . . Model recognition processor

16. . . Search criteria

18. . . translater

20. . . Central processing unit

twenty two. . . Identification module

twenty four. . . Summary module

26. . . Output bus

28. . . Column decoder

30. . . Characteristic cell

32. . . Search item array

34. . . Detection array

36. . . Start routing matrix

37. . . Input conductor

38. . . Detection bus

40. . . Latch matrix

42. . . Summary routing matrix

44. . . Threshold logic matrix

46. . . Logical product matrix

48. . . Logic and matrix

50. . . Initialize the routing matrix

51. . . Output buffer

53. . . Group logic line

54. . . Search for cell

56. . . Output conductor

58. . . Memory cell

60. . . conductor

62. . . conductor

63. . . Characteristic cell

64. . . Characteristic cell

66. . . Characteristic cell

68. . . Detecting cell

70. . . Memory cell

72. . . conductor

74. . . conductor

75. . . First search criteria

76. . . Second search criteria

78. . . Start routing cell

80. . . Characteristic cell

82. . . Characteristic cell

84. . . Characteristic cell

86. . . Characteristic cell

88. . . First code

90. . . Tail code

92. . . Tail code

94. . . Group

96. . . Output driver selection

98. . . Column

100. . . Block

102. . . Local routing line

104A. . . First output connection

104B. . . Second output connection

105. . . Input

106A. . . Input connection

106B. . . Input connection

106C. . . Input connection

106D. . . Input connection

108. . . Column routing line

110A. . . Output connection

110B. . . Output connection

110C. . . Output connection

110D. . . Output connection

112. . . Input connection

112A. . . Input connection

112B. . . Input connection

112C. . . Input connection

112D. . . Input connection

112E. . . Input connection

112F. . . Input connection

112G. . . Input connection

112H. . . Input connection

114. . . Block internal routing line

116A. . . Two-way connection

116B. . . Two-way connection

116C. . . Two-way connection

116D. . . Two-way connection

116E. . . Two-way connection

116F. . . Two-way connection

116G. . . Two-way connection

116H. . . Two-way connection

117. . . Top level hierarchy

118. . . Hierarchical routing line

120A. . . Two-way connection

120B. . . Two-way connection

120C. . . Two-way connection

120D. . . Two-way connection

120E. . . Two-way connection

120F. . . Two-way connection

120G. . . Two-way connection

120H. . . Two-way connection

130. . . Block

132. . . Connection (deactivate block)

134. . . Block

136. . . connection

138. . . connection

140. . . connection

1 illustrates an example of a system for searching for a data stream;

2 is a diagram showing an example of a type identification processor in the system of FIG. 1;

3 is a diagram showing an example of a search term cell in the type identification processor of FIG. 2;

4 and FIG. 5 illustrate the search term cell of FIG. 3 for searching a data stream for a single character;

6 to 8 illustrate an identification module including a plurality of search term cells for searching a data stream for a word;

Figure 9 illustrates an identification module configured to perform parallel searches for data streams for two words;

10 to FIG. 12 illustrate that the identification module searches for one of a plurality of words having the same first code according to the search criteria;

13 to FIG. 16 are diagrams showing a hierarchical configuration of a characteristic cell of a pattern recognition processor according to an embodiment of the present invention;

17 to 20 illustrate a multi-level routing matrix of a type identification processor according to an embodiment of the present invention;

21 illustrates a portion of a feature cell that disables a pattern recognition processor in accordance with an embodiment of the present invention;

22 is a flow diagram of one of the processes for programming a connection of a multi-hierarchical routing matrix in accordance with an embodiment of the present invention.

30. . . Characteristic cell

94. . . Group

96. . . Output driver selection

98. . . Column

100. . . Block

Claims (31)

An apparatus for pattern recognition, comprising: a pattern recognition processor, comprising: a plurality of logical groups, wherein each logical group comprises a plurality of first routing lines and one or more characteristic cells, wherein Each of the one or more characteristic cells includes an enable input for enabling the feature cell and an enable output for enabling one of the feature cells, wherein the one or more of each of the logic groups The feature cells are selectively coupled to the first routing lines by a plurality of first connections, and wherein the first connections comprise enabling input connections and enabling output connections, the enabling input connections connecting the one or more characteristic cells The enable input of each of the feature cells is coupled to the first routing line by being programmed to be programmed to perform one of a plurality of functions, the enabled output connections The enable output of each of the one or more signature cells is coupled to the first routing line by being unprogrammable to perform more than one of the specific ones of the plurality of functions; a logical column, wherein each logical column includes one or more of the plurality of logical groups, wherein the one or more logical groups of each logical column are coupled to the plurality of second routing lines by the plurality of second connections And wherein the second routing lines are selectively coupled to the enable input by the second connections; and a plurality of logical blocks, wherein each logical block includes one or more of the plurality of logical columns, The one or more logical columns of each of the logical blocks are coupled to the third routing line by a third connection; Wherein the plurality of logical blocks are coupled by a fourth connection to a fourth routing line. The apparatus of claim 1, wherein each of the plurality of logical groups further comprises one of the one or more characteristic cells coupled to the respective logical group to output a drive selector. The apparatus of claim 2, wherein the output drive selector is configured to provide an output based on an output of the one or more characteristic cells of the respective group. The apparatus of claim 2, wherein the output drive selector is configured to output one of the one or more characteristic cells of the respective logical group or the one or more of the logical group A logical combination of one of these outputs of the feature cell. The device of claim 2, wherein each of the one or more signature cells of each logical group is coupled to a respective output drive selector by a non-programmable connection. The device of claim 1, wherein each of the plurality of logical groups includes two characteristic cells. The device of claim 1, wherein each of the plurality of signature cells is configured to receive one or more inputs and output a subsequent status signal. The device of claim 7, wherein the first connections comprise a first programmable connection. The device of claim 8, wherein the first programmable connection is configured to provide a logical combination of one of the one or more inputs of each of the characteristic cells. The device of claim 2, wherein the output drive selector of each logical group is coupled to the second routing lines by respective ones of the second connections, wherein each of the second connections Others include a stylized connection. The apparatus of claim 1, wherein the one or more characteristic cells of each logical group are each coupled to the second routing line by a programmable connection. The apparatus of claim 1, wherein the one or more logical columns of each logical block are each coupled to the third routing line by a programmable connection. The device of claim 1, wherein the fourth connection is a programmatic connection. An apparatus for pattern recognition, comprising: a pattern recognition processor, comprising: a hierarchical routing matrix, the matrix comprising: a first level comprising one or more characteristic cells, wherein the one or Each of the plurality of characteristic cells includes an enable input for enabling the feature cell and an enable enable output for another feature cell, wherein each feature cell is coupled to the one or more first programmable links And an unprogrammable connection, the one or more programmable connections configured to be programmed to perform a plurality of functions, the non-programmable connection not being programmable to perform more than a specific one of the plurality of functions And wherein the one or more first programmable connections are coupled to the enable input of each of the one or more feature cells, wherein the unprogrammable connection is coupled to the one or more feature cells a enable output of a characteristic cell; a second level comprising one or more groups of characteristic cells, The groups are coupled to the one or more column routing lines via one or more second programmable connections, wherein the one or more column routing lines are coupled to the enable input by the one or more second connections; a third level comprising one or more columns of the group, wherein the columns are coupled to one or more third programmable links; and a fourth level comprising one or more of the columns, Where the blocks are coupled to one or more fourth programmable connections. The apparatus of claim 14, wherein the hierarchical routing matrix is configured to provide a next state route between the one or more signature cells. The device of claim 14, wherein the one or more characteristic cells of each group are coupled to one or more individually unprogrammable connections. The device of claim 16, wherein each of the one or more groups comprises one or more of the one or more feature cells coupled to the one or more feature cells. The apparatus of claim 16, wherein one of the one or more second programmable connections is configured such that one of the individual ones of the groups is capable of driving or not driving a list of routes line. The apparatus of claim 16, wherein one of the one or more third programmable connections is configured to enable a column of routing lines to drive a block internal routing line or to enable a block internal routing line Drive a list of routing lines. The apparatus of claim 16, wherein each of the fourth programmable connections is configured to enable a block internal routing line to drive a top level routing line or to enable a top level routing line to drive Within the block Department routing line. A pattern recognition processor comprising: a plurality of routing lines, wherein the plurality of routing lines are configured to be routed between a plurality of characteristic cells of the processor, wherein each of the characteristic cells of the characteristic cells comprises Enabling one of the signature cells to enable input and for enabling one of the signature cells to enable output; a plurality of programmable links coupled to one of the plurality of routing lines, the first one or more, wherein Each of the plurality of programmable connections is configured to be programmed to perform any of a plurality of functions; and a plurality of non-programmable connections coupled to one of the plurality of routing lines Or more, each of the unprogrammable connections cannot be programmed to perform more than a particular one of the plurality of functions. The processor of claim 21, wherein one or more of the plurality of programmable connections comprise one-way or two-way connections. A processor is identified as in claim 21, wherein one or more of the plurality of programmable connections are configured to provide a one-way or two-way connection. The processor of claim 21, wherein one or more of the plurality of programmable connections are configured to provide a logical "or", a logical "and" or a logical "mutual exclusion" or . The processor of claim 21 is characterized in that one or more of the plurality of programmable connections are configured to provide a selector. The processor of claim 21, wherein one or more of the plurality of programmable connections are configured to provide an isolator. A method for pattern recognition, comprising: stylizing one or more first programmable connections of a plurality of routing connections of a type identification processor, wherein the first programmable connections are configured Any one of being programmed to perform a plurality of functions and coupled to a first level comprising one or more characteristic cells interconnected via one or more local routing lines, wherein the one or more characteristic cells Each feature cell includes means for enabling one of the feature cells to enable input and for enabling another feature cell by being unprogrammable by one of a particular one of the plurality of functions that cannot be programmed to perform more than the plurality of functions An enable output; and a programmatically identifying one or more second programmable connections of the plurality of routing connections of the processor, wherein the second programmable links are coupled to include the one or more features One of the one or more groups of cells, the second level. The method of claim 27, comprising: stabilizing one or more third programmable connections of the plurality of routing connections of the model identification processor, wherein the third programmable links are coupled to include the one Or one of the one or more columns of multiple groups, the third level. The method of claim 27, comprising: stabilizing one or more fourth programmable connections of the plurality of routing connections of the pattern recognition processor, wherein the fourth programmable links are coupled to include the one Or a fourth level of one or more of the plurality of columns. The method of claim 29, comprising programming the first programmable connection, the second programmable connection, the third programmable connection or the fourth programmable connection, or any combination thereof to disable the type One of the identification processors Or multiple characteristic cells. A system for pattern recognition, comprising: a routing matrix for a type identification processor, the matrix comprising: a plurality of programmable links, which are equal to two of the type identification processors or Between two or more components, wherein each of the plurality of programmable connections is configured to be programmed to perform any of a plurality of functions; and a plurality of non-programmable connections, etc. Between two or more components of the identification processor, wherein each unprogrammable connection cannot be programmed to perform more than a particular one of the plurality of functions; wherein the components include configured to search for each a feature cell of at least a portion of the data stream, a logical configuration of the eigen cells, and/or any combination thereof, wherein each of the eigen cells of the eigen cell includes an enable input for enabling the eigen cell and Used to enable one of the other feature cells to enable output.