TWI478221B - Semiconductor device manufacturing method and bonding device - Google Patents

Semiconductor device manufacturing method and bonding device Download PDF

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TWI478221B
TWI478221B TW101129615A TW101129615A TWI478221B TW I478221 B TWI478221 B TW I478221B TW 101129615 A TW101129615 A TW 101129615A TW 101129615 A TW101129615 A TW 101129615A TW I478221 B TWI478221 B TW I478221B
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substrate
capillary
electrode pad
side electrode
wire
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TW201330069A (en
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Takashi Imoto
Katsuhiro Ishida
Hideo Komoda
Shogo Watanabe
Yuichi Sano
Akira Tanimoto
Yoriyasu Ando
Naoto Takebe
Masaji Iwamoto
Yasuo Takemoto
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Toshiba Kk
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85148Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518Translational movements
    • H01L2224/85181Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
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    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Description

半導體裝置之製造方法及接合裝置Semiconductor device manufacturing method and bonding device

本發明係關於一種半導體裝置之製造方法及接合裝置。The present invention relates to a method of fabricating a semiconductor device and a bonding device.

先前已知有於形成有佈線層之基板上載置有控制器晶片及記憶體晶片等晶片的半導體裝置。如此之半導體裝置中,以金屬導線來將設於基板上之電極墊與設於晶片上之電極墊連接(以下亦稱作接合),藉此,使基板與晶片互相電性連接。A semiconductor device in which a wafer such as a controller wafer or a memory wafer is placed on a substrate on which a wiring layer is formed is known. In such a semiconductor device, an electrode pad provided on a substrate is connected to an electrode pad provided on a wafer by metal wires (hereinafter also referred to as bonding), whereby the substrate and the wafer are electrically connected to each other.

如此之半導體裝置中,隨著通信速度之高速化,期望抑制成本且降低雜訊。又,有在形成於基板上之電極墊之表面形成鍍金之情形。因此,期望抑制金之使用量,以謀求成本之抑制。又,期望於抑制金之使用量從而使得銲墊部分之鍍金變薄之情形中,亦能確保金屬導線與銲墊之連接強度,且順利地連續進行接合。In such a semiconductor device, as the communication speed is increased, it is desirable to suppress the cost and reduce the noise. Further, there is a case where gold plating is formed on the surface of the electrode pad formed on the substrate. Therefore, it is desirable to suppress the amount of gold used in order to suppress the cost. Further, in the case where the amount of gold used is suppressed so that the gold plating of the pad portion is thinned, the connection strength between the metal wire and the pad can be ensured, and the bonding can be smoothly performed continuously.

本發明之目的係提供一種抑制成本且降低雜訊之同時,確保金屬導線與銲墊之連接強度,且可順利地連續進行接合之半導體裝置之製造方法。SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device which can suppress the cost and reduce noise while ensuring the connection strength between the metal wires and the pads, and can be smoothly and continuously bonded.

根據本申請發明之一態樣,提供一種半導體裝置之製造方法,其係藉由從前端被供給金製導線之毛細管、及可切換夾持導線之閉合狀態與鬆開導線之開放狀態之箝位器, 以導線連接形成於基板之第一面上之基板側電極墊、與形成於搭載於基板之第一面上之晶片上之晶片側電極墊。半導體裝置之製造方法包含以下步驟:於基板側電極墊上藉由無電解鍍敷而形成鍍鎳;於鍍鎳上藉由無電解鍍敷而形成鍍鈀;於成為鍍鈀上之最表層藉由無電解鍍敷而形成鍍金;使毛細管靠近晶片,將導線之一端連接於晶片側電極墊;於箝位器之開放狀態下,使毛細管向晶片上方移動;使毛細管向朝向基板側電極墊之第1方向移動。毛細管之朝向第1方向之移動係進行至超過一次接合位置正上方的位置。使毛細管向與第1方向之相反第2方向移動,且靠近基板側電極墊,而將導線一次接合於基板側電極墊。在比一次接合位置更向第1方向移動之位置上將導線二次接合。使毛細管向基板上方移動,將箝位器切換成閉合狀態,使毛細管向基板之更上方移動。According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, which is characterized in that a capillary of a gold wire is supplied from a tip end, and a closed state of the switchable wire and a clamped state of the wire are released. , The substrate-side electrode pad formed on the first surface of the substrate and the wafer-side electrode pad formed on the wafer mounted on the first surface of the substrate are connected by wires. The manufacturing method of the semiconductor device includes the steps of: forming nickel plating by electroless plating on the substrate-side electrode pad; forming palladium plating by electroless plating on nickel plating; and forming the outermost layer on the palladium plating layer by Electroless plating forms gold plating; the capillary is brought close to the wafer, one end of the wire is connected to the wafer side electrode pad; in the open state of the clamper, the capillary is moved above the wafer; and the capillary is directed toward the substrate side electrode pad Move in 1 direction. The movement of the capillary in the first direction is performed to a position directly above the one engagement position. The capillary is moved in the second direction opposite to the first direction, and is close to the substrate-side electrode pad, and the wire is once bonded to the substrate-side electrode pad. The wires are secondarily joined at a position that is moved further in the first direction than the primary bonding position. Moving the capillary over the substrate switches the clamp to a closed state, moving the capillary further above the substrate.

以下參照隨附附圖,詳細說明本發明之實施形態之半導體裝置及其製造方法。另,本發明並不限於該實施形態。Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. Further, the present invention is not limited to the embodiment.

(第1實施形態)(First embodiment)

圖1係顯示第1實施形態之接合裝置之概要構成之圖。接合裝置50具備控制部1、記憶部2、毛細管3、箝位器4而構成。圖2係顯示使用圖1所示之接合裝置製造之半導體裝置之一例之圖。Fig. 1 is a view showing a schematic configuration of a bonding apparatus according to a first embodiment. The bonding device 50 includes a control unit 1 , a memory unit 2 , a capillary tube 3 , and a clamper 4 . Fig. 2 is a view showing an example of a semiconductor device manufactured using the bonding apparatus shown in Fig. 1.

首先,針對使用接合裝置50製造之半導體裝置60之概要構成進行說明。半導體裝置60具備基板5、控制器(晶片 7)、記憶體晶片(晶片)9。基板5例如係於絕緣性樹脂基板內部或表面上設有佈線層者,且兼作元件搭載基板與端子形成基板。作為如此之基板5,可使用利用玻璃-環氧樹脂或玻璃-BT樹脂(雙馬來醯亞胺.三嗪樹脂)等之印製佈線板。於基板5之第一面5a上形成有複數個電極墊(基板側電極墊6)。First, a schematic configuration of the semiconductor device 60 manufactured using the bonding device 50 will be described. The semiconductor device 60 includes a substrate 5 and a controller (wafer) 7) Memory chip (wafer) 9. The substrate 5 is, for example, a wiring layer provided inside or on the surface of the insulating resin substrate, and also serves as a component mounting substrate and a terminal forming substrate. As such a substrate 5, a printed wiring board using a glass-epoxy resin or a glass-BT resin (bismaleimide. triazine resin) or the like can be used. A plurality of electrode pads (substrate side electrode pads 6) are formed on the first surface 5a of the substrate 5.

圖3係將基板之基板側電極墊部分放大之部分放大平面圖。圖4係沿著圖3所示之A-A線之箭視剖面圖。如圖3及圖4所示,於基板5內部形成有作為佈線層之佈線圖案13。佈線圖案13例如使用銅形成、藉由電解鍍敷形成、使用輥軋銅箔形成。又,佈線圖案13亦有以使用電解鍍敷、無電解鍍敷、輥軋銅箔之多層結構形成之情形。Fig. 3 is an enlarged plan view showing an enlarged portion of a substrate-side electrode pad portion of a substrate. Figure 4 is an arrow cross-sectional view taken along line A-A of Figure 3. As shown in FIGS. 3 and 4, a wiring pattern 13 as a wiring layer is formed inside the substrate 5. The wiring pattern 13 is formed, for example, of copper, formed by electrolytic plating, and formed using a rolled copper foil. Further, the wiring pattern 13 may be formed by a multilayer structure using electrolytic plating, electroless plating, or rolled copper foil.

佈線圖案13之表面係由阻焊劑等保護膜14覆蓋。保護膜14之一部分藉由蝕刻而開口,使佈線圖案13之一部分露出。該露出之佈線圖案13部分係作為基板側電極墊6發揮功能。The surface of the wiring pattern 13 is covered with a protective film 14 such as a solder resist. A part of the protective film 14 is opened by etching to expose a part of the wiring pattern 13. The exposed wiring pattern 13 portion functions as the substrate-side electrode pad 6.

於佈線圖案13之露出部分之表面,首先藉由無電解鍍敷實施鍍鎳(Ni),從而形成第1層31。接著,於鍍鎳之表面,藉由無電解鍍敷實施鍍鈀(Pd),從而形成第2層32。然後,於鍍鈀之表面,藉由無電解鍍敷實施鍍金(Au),從而形成第3層33。因此,於基板側電極墊6之最表層(第3層)藉由無電解鍍敷而實施鍍金。On the surface of the exposed portion of the wiring pattern 13, first, nickel plating (Ni) is performed by electroless plating to form the first layer 31. Next, palladium plating (Pd) is performed on the surface of the nickel plating by electroless plating to form the second layer 32. Then, gold plating (Au) is performed on the surface of the palladium plating by electroless plating to form the third layer 33. Therefore, gold plating is performed on the outermost layer (third layer) of the substrate-side electrode pad 6 by electroless plating.

控制器7係從複數個記憶體晶片9中選擇進行資料之寫入或讀出之記憶體晶片9。控制器7控制對所選擇之記憶體晶 片9之資料的寫入、或對記憶於選擇之記憶體晶片9之資料的讀出等。控制器7搭載於基板5之第一面5a上。於控制器7之上表面形成有複數個電極墊(晶片側電極墊8)。The controller 7 selects a memory chip 9 for writing or reading data from a plurality of memory chips 9. The controller 7 controls the selected memory crystal The writing of the data of the slice 9 or the reading of the data stored in the selected memory chip 9 is performed. The controller 7 is mounted on the first surface 5a of the substrate 5. A plurality of electrode pads (wafer-side electrode pads 8) are formed on the upper surface of the controller 7.

記憶體晶片9係NAND型快閃記憶體等記憶元件。記憶體晶片9設有複數塊,積層並搭載於基板5之第一面5a上。記憶體晶片9彼此於平面上稍錯開地積層。記憶體晶片9之上表面中,於因記憶體晶片9錯開地積層而露出之部分,形成有電極墊(晶片側電極墊10)。The memory chip 9 is a memory element such as a NAND flash memory. The memory chip 9 is provided with a plurality of blocks, and is laminated and mounted on the first surface 5a of the substrate 5. The memory chips 9 are stacked one on another in a plane on the plane. On the upper surface of the memory chip 9, an electrode pad (wafer-side electrode pad 10) is formed in a portion where the memory wafer 9 is stacked in a staggered manner.

基板側電極墊6與晶片側電極墊8、10以導線11連接,從而,形成於基板5上之佈線圖案13與控制器7與記憶體晶片9互相電性連接。導線11係以藉由接合裝置50而接合從而將電極墊6、8、10間連接之方式設置,但關於其詳情將於下文敍述。樹脂模型部12係以合成樹脂構成,且覆蓋基板5之第一面5a側,將搭載於第一面5a上之控制器7、記憶體晶片9、導線11密封。The substrate-side electrode pad 6 and the wafer-side electrode pads 8 and 10 are connected by a wire 11, whereby the wiring pattern 13 formed on the substrate 5 and the controller 7 and the memory chip 9 are electrically connected to each other. The wires 11 are provided in such a manner as to be joined by the bonding device 50 to connect the electrode pads 6, 8, 10, but the details thereof will be described later. The resin mold portion 12 is made of synthetic resin, and covers the first surface 5a side of the substrate 5, and seals the controller 7, the memory chip 9, and the wires 11 mounted on the first surface 5a.

接著,針對接合裝置50之概要構成進行說明。接合裝置50具備控制部1、記憶部2、毛細管3、箝位器4。控制部1基於記憶於記憶部2之程式而使毛細管3及箝位器4動作,且利用導線11連接設於半導體裝置60中之電極墊6、8、10間。Next, a schematic configuration of the joining device 50 will be described. The bonding device 50 includes a control unit 1, a memory unit 2, a capillary tube 3, and a clamper 4. The control unit 1 operates the capillary 3 and the clamp 4 based on the program stored in the memory unit 2, and is connected between the electrode pads 6, 8, and 10 in the semiconductor device 60 by the wires 11.

毛細管3於其中心部具有貫通孔3a,於貫通孔3a內插入金製導線11。導線11係通過貫通孔3a而從毛細管3之前端供給。毛細管3之前端成為能將導線11按壓且連接於電極墊6、8、10之形狀。The capillary 3 has a through hole 3a at its center portion, and a gold wire 11 is inserted into the through hole 3a. The wire 11 is supplied from the front end of the capillary 3 through the through hole 3a. The front end of the capillary 3 has a shape in which the wire 11 can be pressed and connected to the electrode pads 6, 8, 10.

箝位器4設於毛細管3之根側,可切換夾持插通於毛細管3之貫通孔3a內的導線11之閉合狀態、與鬆開導線11之開放狀態。毛細管3與箝位器4可藉由未圖示之驅動裝置3維地移動,且藉由控制部1之控制進行特定動作。The clamper 4 is provided on the root side of the capillary 3, and can switch between the closed state of the wire 11 inserted into the through hole 3a of the capillary 3 and the open state of the loosened wire 11. The capillary 3 and the clamper 4 are three-dimensionally movable by a driving device (not shown), and a specific operation is performed by the control of the control unit 1.

接著,說明藉由接合裝置50將導線11接合於電極墊6、8、10之順序。圖5係用以說明接合順序之流程圖。圖6~圖17係導線11被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。另,圖6~圖17中,將與基板5之第一面5a垂直之軸作為Y軸,將離開基板5之第一面5a之方向作為正方向進行說明。又,將與Y軸正交且與從晶片側電極墊8朝向基板側電極墊6之方向平行之軸作為X軸,將從晶片側電極墊8朝向基板側電極墊6之方向作為正方向進行說明。以下順序係按照記憶於記憶部2之控制程式,由控制部1使毛細管3或箝位器4動作而進行。Next, the order in which the wires 11 are bonded to the electrode pads 6, 8, 10 by the bonding device 50 will be described. Figure 5 is a flow chart for explaining the joining sequence. 6 to 17 are cross-sectional views showing a portion where the wire 11 is joined, and showing a step of joining. In FIGS. 6 to 17, the axis perpendicular to the first surface 5a of the substrate 5 is referred to as a Y-axis, and the direction away from the first surface 5a of the substrate 5 is described as a positive direction. Moreover, the axis orthogonal to the Y-axis and parallel to the direction from the wafer-side electrode pad 8 toward the substrate-side electrode pad 6 is taken as the X-axis, and the direction from the wafer-side electrode pad 8 toward the substrate-side electrode pad 6 is made to be the positive direction. Description. The following procedure is performed by the control unit 1 by operating the capillary 3 or the clamper 4 in accordance with the control program stored in the memory unit 2.

首先,將導線11之前端接合於控制器7之晶片側電極墊8(步驟S1)。另,作為接合對象之電極墊亦可為記憶體晶片9之晶片側電極10。如圖6所示,於從毛細管3之前端部突出之導線11之前端形成有球體20。球體20係藉由對噴燈(未圖示)與導線11間施加電壓產生之火花,使從毛細管3前端突出之導線11熔融而形成。步驟S1中,如圖7所示,使向晶片側電極墊8之上方移動之毛細管3沿著Y軸向負方向即晶片側電極墊8下降,以壓扁球體20之方式按壓於晶片側電極墊8而進行接合。導線11之接合中,藉由毛細管3對導線11施加荷重與超音波。First, the leading end of the wire 11 is joined to the wafer side electrode pad 8 of the controller 7 (step S1). Further, the electrode pad to be bonded may be the wafer side electrode 10 of the memory chip 9. As shown in Fig. 6, a spherical body 20 is formed at the front end of the wire 11 projecting from the front end of the capillary 3. The ball 20 is formed by melting a wire 11 protruding from the tip end of the capillary 3 by a spark generated by applying a voltage between a torch (not shown) and the wire 11. In step S1, as shown in FIG. 7, the capillary 3 that has moved toward the upper side of the wafer-side electrode pad 8 is lowered in the negative direction of the Y-axis, that is, the wafer-side electrode pad 8, and is pressed against the wafer-side electrode by squeezing the ball 20. The pad 8 is joined. In the bonding of the wires 11, a load and an ultrasonic wave are applied to the wires 11 by the capillary 3.

接著,如圖8所示,使箝位器4成為開放狀態,使毛細管3向沿著Y軸之正方向即上方移動(步驟S2)。一般而言,使毛細管3向上方移動時,亦進行向另一方向之移動以使導線11具有環形狀,但此處省略其說明。Next, as shown in FIG. 8, the clamper 4 is opened, and the capillary 3 is moved upward in the positive direction along the Y-axis (step S2). In general, when the capillary 3 is moved upward, the movement in the other direction is also performed so that the wire 11 has a ring shape, but the description thereof is omitted here.

接著,使毛細管3向沿著X軸之正方向(第1方向)即基板側電極墊6之方向移動(步驟S3)。再者,對於基板側電極墊6進行2次以毛細管3之前端按壓導線11而接合的步驟,於下文將進行詳述。以下說明中,將第1次接合稱作一次接合,將第2次接合稱作二次接合。又,將進行一次接合之位置作為一次接合點21進行圖示,將進行二次接合之位置作為二次接合點22進行圖示。步驟S3中,使毛細管3移動至超過一次接合點21之正上方之位置。即,與進行一次接合時之毛細管3之X軸方向之位置相比進而向沿著X軸之正方向側移動。Next, the capillary 3 is moved in the direction along the positive direction (first direction) of the X-axis, that is, in the direction of the substrate-side electrode pad 6 (step S3). In addition, the step of bonding the lead wires 11 to the front end of the capillary 3 by the substrate side electrode pad 6 is performed twice, and will be described in detail below. In the following description, the first bonding is referred to as primary bonding, and the second bonding is referred to as secondary bonding. Further, the position at which the bonding is performed once is illustrated as the primary bonding point 21, and the position at which the secondary bonding is performed is illustrated as the secondary bonding point 22. In step S3, the capillary 3 is moved to a position directly above the joint point 21. In other words, it moves further along the positive side of the X-axis than the position of the capillary 3 in the X-axis direction when the bonding is performed once.

接著,如圖10所示,使毛細管3向沿著X軸之負方向(與第1方向相反之第2方向)移動,且向一次接合點21下降,而將導線11一次接合於一次接合點21(步驟S4)。此處,步驟S4之毛細管3之移動會描繪出箭頭P1所示之軌跡。另,在導線11之一次接合中,藉由毛細管3對導線11施加荷重與超音波。Next, as shown in FIG. 10, the capillary 3 is moved in the negative direction along the X-axis (the second direction opposite to the first direction), and is lowered toward the primary bonding point 21, and the wire 11 is once bonded to the primary bonding point. 21 (step S4). Here, the movement of the capillary 3 of step S4 will depict the trajectory indicated by the arrow P1. Further, in one engagement of the wires 11, a load and an ultrasonic wave are applied to the wires 11 by the capillary 3.

接著,如圖11所示,使毛細管3向沿著Y軸之正方向即上方移動(步驟S5)。然後如圖12所示,使毛細管3移動至二次接合點22之正上方(步驟S6)。如圖13所示,使毛細管3向二次接合點22下降,而將導線11二次接合於二次接合點 22(步驟S7)。另,在導線11之二次接合中,藉由毛細管3對導線11施加荷重與超音波。Next, as shown in FIG. 11, the capillary 3 is moved upward in the positive direction along the Y-axis (step S5). Then, as shown in Fig. 12, the capillary 3 is moved right above the secondary joint 22 (step S6). As shown in FIG. 13, the capillary 3 is lowered toward the secondary joint 22, and the wire 11 is secondarily joined to the secondary joint. 22 (step S7). Further, in the secondary bonding of the wires 11, the load and the ultrasonic waves are applied to the wires 11 by the capillary 3.

接著如圖14所示,使毛細管3向沿著Y軸之正方向即上方移動(步驟S8)。此處,步驟S3~S8中,箝位器4維持在開放狀態,但如圖15所示,將箝位器4切換成閉合狀態,由箝位器4夾持導線11(步驟S9)。然後,於藉由箝位器4夾持導線11之狀態下,使毛細管3向沿著Y軸之正方向即更上方移動(步驟S10),從而拉斷導線11之尾部。根據以上順序,使電極墊6、8間藉由導線11而電性接合。Next, as shown in FIG. 14, the capillary 3 is moved upward in the positive direction along the Y-axis (step S8). Here, in steps S3 to S8, the clamper 4 is maintained in the open state. However, as shown in FIG. 15, the clamper 4 is switched to the closed state, and the wire 11 is held by the clamper 4 (step S9). Then, in a state where the wire 11 is held by the clamper 4, the capillary 3 is moved upward in the positive direction along the Y-axis (step S10), thereby breaking the tail portion of the wire 11. According to the above sequence, the electrode pads 6, 8 are electrically joined by the wires 11.

另,拉斷導線11之尾部後,使用噴燈(未圖示)使從毛細管3之前端突出之導線11產生火花,於導線11之前端再次形成球體20(亦參照圖17)。從該狀態返回至步驟S1之步驟,從而可連續進行對複數個電極墊之接合。Further, after the tail portion of the wire 11 is pulled, a lamp 11 (not shown) is used to cause a spark 11 to protrude from the front end of the capillary 3, and a ball 20 is formed again at the front end of the wire 11 (see also Fig. 17). Returning from this state to the step of step S1, the joining of the plurality of electrode pads can be continuously performed.

圖18係顯示導線11與基板側電極墊6之接合強度之圖。圖18中,縱軸顯示接合強度,橫軸顯示步驟S3中毛細管3移動超過一次接合點21正上方之量即超過移動量。又,超過移動量係將移動超過與導線11之直徑(導線徑)相同的距離之情形作為100%予以顯示。又,使沿著X軸之正方向(第1方向)為+,使沿著X軸之負方向(第2方向)為-。即,圖18中,顯示毛細管3之超過移動量與導線11之接合強度之關係。Fig. 18 is a view showing the bonding strength between the wire 11 and the substrate-side electrode pad 6. In Fig. 18, the vertical axis shows the joint strength, and the horizontal axis shows the amount by which the capillary 3 moves more than once the joint point 21 in step S3, that is, exceeds the amount of movement. Further, the case where the amount of movement exceeds the same distance as the diameter (wire diameter) of the wire 11 is displayed as 100%. Further, the positive direction (first direction) along the X-axis is +, and the negative direction (second direction) along the X-axis is -. That is, in Fig. 18, the relationship between the excess movement amount of the capillary 3 and the bonding strength of the wire 11 is shown.

如圖18所示,設有在進行一次接合前使毛細管3暫時通過一次接合點21之超過移動量,從而可提高導線11之接合強度。又,如圖18所示,將超過移動量設為約75%時,接 合強度達到峰值。As shown in Fig. 18, the amount of excess movement of the capillary 3 temporarily passing through the primary joint 21 before the primary bonding is performed is provided, whereby the bonding strength of the wire 11 can be improved. Moreover, as shown in FIG. 18, when the excess movement amount is set to about 75%, it is connected. The combined strength reaches a peak.

圖19係顯示導線11與基板側電極墊6之接合強度之圖。圖19中以縱顯示接合強度,以橫軸顯示一次接合點21與二次接合點22之距離。另,一次接合點21與二次接合點22之距離係將與導線徑相同之距離作為100%予以顯示。又,使沿著X軸之正方向(第1方向)為+,使沿著X軸之負方向(第2方向)為-。即,圖19中顯示一次接合點21與二次接合點22之距離與導線11之接合強度的關係。Fig. 19 is a view showing the bonding strength between the wire 11 and the substrate-side electrode pad 6. In Fig. 19, the joint strength is shown vertically, and the distance between the primary joint 21 and the secondary joint 22 is shown on the horizontal axis. Further, the distance between the primary bonding point 21 and the secondary bonding point 22 is displayed as 100% of the same distance as the wire diameter. Further, the positive direction (first direction) along the X-axis is +, and the negative direction (second direction) along the X-axis is -. That is, the relationship between the distance between the primary bonding point 21 and the secondary bonding point 22 and the bonding strength of the wire 11 is shown in FIG.

如圖19所示,即使對於比一次接合點21更靠近沿著X軸之負方向側的二次接合點22進行二次接合,接合強度亦不會下降,可維持比設有超過移動量之一次接合進一步有所提高之接合強度。As shown in FIG. 19, even if the secondary bonding 22 which is closer to the negative side of the X-axis than the primary bonding point 21 is subjected to the secondary bonding, the bonding strength does not decrease, and the ratio of the excess movement amount can be maintained. One joint further increases the joint strength.

如上說明,對基板側電極墊6藉由無電鍍敷實施鍍鎳、鍍鈀、鍍金,從而如實施電解鍍敷之情形般,亦可不於基板5上設置電解鍍敷線。電解鍍敷線係用以使電極墊6上析出鍍敷而從電極墊6或佈線圖案13延伸至基板5之端部或其附近的佈線。電解鍍敷線殘留於作為製品之半導體裝置60上,因此成為收發之信號之反射源,從而易成為反射雜訊之原因。另一方面,本實施形態中,藉由無電解鍍敷實施鍍鎳、鍍鈀、鍍金,從而亦可不設置電解鍍敷線,因此可抑制反射雜訊,謀求通信品質之提高。As described above, the substrate-side electrode pad 6 is subjected to nickel plating, palladium plating, or gold plating by electroless plating, and as in the case of performing electrolytic plating, the electrolytic plating line may not be provided on the substrate 5. The electrolytic plating line is a wiring for causing plating on the electrode pad 6 to extend from the electrode pad 6 or the wiring pattern 13 to the end portion of the substrate 5 or its vicinity. Since the electrolytic plating line remains on the semiconductor device 60 as a product, it becomes a reflection source of the signal to be transmitted and received, and is likely to cause reflection of noise. On the other hand, in the present embodiment, nickel plating, palladium plating, or gold plating is performed by electroless plating, and the electrolytic plating line is not provided. Therefore, reflection noise can be suppressed, and communication quality can be improved.

又,使用無電解鍍敷排除電解鍍敷線,從而易確保在佈線圖案13間設置電源區域(與對控制器7或記憶體晶片9供給電源之線或將控制器7或記憶體晶片9接地之線電性連接 的區域)之空間。設置電源區域,從而基板5之電源阻抗變小,可謀求電源開關雜訊之降低。另,以電解鍍敷形成佈線圖案13之情形中設置之電解鍍敷線可利用形成保護膜14前之蝕刻步驟去除,因此佈線圖案13之形成中即使使用電解鍍敷亦不易成為反射雜訊之原因。Further, the electrolytic plating line is removed by electroless plating, so that it is easy to ensure that a power supply region is provided between the wiring patterns 13 (a line for supplying power to the controller 7 or the memory chip 9 or grounding the controller 7 or the memory chip 9) Electrical connection Space). By setting the power supply area, the power supply impedance of the substrate 5 is reduced, and the power switch noise can be reduced. Further, the electrolytic plating line provided in the case where the wiring pattern 13 is formed by electrolytic plating can be removed by the etching step before the protective film 14 is formed. Therefore, even if electrolytic plating is used in the formation of the wiring pattern 13, it is difficult to become a reflection noise. the reason.

又,設於基板側電極墊6最表層之鍍金係藉由無電解鍍敷形成。此處,利用無電解鍍敷形成鍍金時,係通過將第1層31之鎳與金進行置換而進行。該鎳與金之置換有界限,有無法將第3層33鍍金形成為充分厚度之情形。若成為最表層之鍍金之厚度不足,則利用接合實現之與導線11之接合強度易變低。但本實施形態中,藉由設有超過移動量之導線11之一次接合,而謀求導線11之接合強度之提高。因此,即使於成為最表層之鍍金之厚度不足之情形中亦易獲得充分之接合強度。另,只要使鍍金形成得較薄,則可抑制金之使用量,從而可謀求成本之抑制。Further, the gold plating provided on the outermost layer of the substrate-side electrode pad 6 is formed by electroless plating. Here, when gold plating is formed by electroless plating, it is performed by replacing nickel and gold of the first layer 31. This nickel has a limit with the replacement of gold, and it is impossible to form the third layer 33 by gold plating to a sufficient thickness. If the thickness of the gold plating which becomes the outermost layer is insufficient, the bonding strength with the wire 11 by joining is apt to become low. However, in the present embodiment, by providing the primary bonding of the wires 11 exceeding the amount of movement, the bonding strength of the wires 11 is improved. Therefore, it is easy to obtain sufficient joint strength even in the case where the thickness of the gold plating which becomes the outermost layer is insufficient. Further, if the gold plating is formed to be thin, the amount of gold used can be suppressed, and the cost can be suppressed.

又,於一次接合之基礎上進行二次接合後去掉導線11之尾部,從而可穩定地去掉尾部。即,在毛細管3側可使形成球體20時所需之導線11之突出量(質量)穩定。又,在基板側電極墊6側可去掉保留充分接合面積之尾部。因導線11之突出量穩定,從而球體20之形成亦穩定,因此可順利地連續進行接合。另,如圖19所示,亦完全不會影響利用二次接合實現之導線11之接合強度。Further, after the second bonding is performed on the basis of one bonding, the tail portion of the wire 11 is removed, so that the tail portion can be stably removed. That is, the amount of protrusion (mass) of the wire 11 required to form the spherical body 20 can be stabilized on the capillary 3 side. Further, the tail portion which retains the sufficient joint area can be removed on the side of the substrate-side electrode pad 6. Since the amount of protrusion of the wire 11 is stabilized, the formation of the ball 20 is also stabilized, so that the bonding can be smoothly performed continuously. Further, as shown in Fig. 19, the joint strength of the wires 11 by the secondary bonding is also not affected at all.

另,本實施形態中,列舉控制器7與記憶體晶片9兩者設於基板5之第一面5a上之例進行說明,但並不限於此。例 如控制器7亦可設於記憶體晶片9上,記憶體晶片9亦可設於控制器7上。即,半導體裝置60內之控制器7或記憶體晶片9之設置位置並無限制,只要係晶片側電極墊8、10以導線11而與基板側電極墊6連接之構成,則可應用本實施形態。In the present embodiment, an example in which both the controller 7 and the memory chip 9 are provided on the first surface 5a of the substrate 5 will be described, but the invention is not limited thereto. example For example, the controller 7 may be disposed on the memory chip 9, and the memory chip 9 may be disposed on the controller 7. That is, the installation position of the controller 7 or the memory chip 9 in the semiconductor device 60 is not limited, and the present embodiment can be applied as long as the wafer-side electrode pads 8 and 10 are connected to the substrate-side electrode pad 6 by the wires 11. form.

又,以導線11而與基板側電極墊6連接之連接對象並不限於控制器7或記憶體晶片9之電極墊,亦可為設於半導體裝置60內之其他晶片之電極墊。又,記憶體晶片9之塊數並不限於2塊,亦可為1塊或3塊以上。Further, the connection target to be connected to the substrate-side electrode pad 6 by the wire 11 is not limited to the electrode pad of the controller 7 or the memory chip 9, and may be an electrode pad of another wafer provided in the semiconductor device 60. Further, the number of blocks of the memory chip 9 is not limited to two, and may be one or three or more.

其他效果或變形例可由相關領域技術人員容易導出。因此,本發明之更廣泛之態樣並不限於上文表示且記述之特定詳情及代表性實施形態。因此,只要不脫離由隨附之請求項及其等價者所定義之總括性的發明概念之精神或範圍,則可進行各種變更。Other effects or modifications can be easily derived by those skilled in the relevant art. Therefore, the broader aspects of the invention are not limited to the specific details and representative embodiments described above. Accordingly, various modifications may be made without departing from the spirit and scope of the inventions of the inventions.

1‧‧‧控制部1‧‧‧Control Department

2‧‧‧記憶部2‧‧‧Memory Department

3‧‧‧毛細管3‧‧‧ Capillary

3a‧‧‧貫通孔3a‧‧‧through hole

4‧‧‧箝位器4‧‧‧ clamp

5‧‧‧基板5‧‧‧Substrate

5a‧‧‧第一面5a‧‧‧ first side

6‧‧‧基板側電極墊6‧‧‧Substrate side electrode pad

7‧‧‧控制器(晶片)7‧‧‧ Controller (wafer)

8‧‧‧晶片側電極墊8‧‧‧ wafer side electrode pad

9‧‧‧記憶體晶片9‧‧‧ memory chip

10‧‧‧晶片側電極墊10‧‧‧ wafer side electrode pad

11‧‧‧導線11‧‧‧Wire

12‧‧‧樹脂模型部12‧‧‧Resin Model Department

13‧‧‧佈線圖案13‧‧‧Wiring pattern

14‧‧‧保護膜14‧‧‧Protective film

20‧‧‧球體20‧‧‧ sphere

21‧‧‧一次接合點21‧‧‧One joint

22‧‧‧二次接合點22‧‧‧Second joint

31‧‧‧第1層31‧‧‧1st floor

32‧‧‧第2層32‧‧‧2nd floor

33‧‧‧第3層33‧‧‧3rd floor

50‧‧‧接合裝置50‧‧‧Joining device

60‧‧‧半導體裝置60‧‧‧Semiconductor device

圖1係顯示第1實施形態之接合裝置之概要構成之圖。Fig. 1 is a view showing a schematic configuration of a bonding apparatus according to a first embodiment.

圖2係顯示使用圖1所示之接合裝置製造之半導體裝置之一例之圖。Fig. 2 is a view showing an example of a semiconductor device manufactured using the bonding apparatus shown in Fig. 1.

圖3係將基板之基板側電極墊部分放大之部分放大平面圖。Fig. 3 is an enlarged plan view showing an enlarged portion of a substrate-side electrode pad portion of a substrate.

圖4係沿著圖3所示之A-A線之箭視剖面圖。Figure 4 is an arrow cross-sectional view taken along line A-A of Figure 3.

圖5係用以說明接合順序之流程圖。Figure 5 is a flow chart for explaining the joining sequence.

圖6係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Figure 6 is a cross-sectional view of a portion where the wires are joined, and is a view showing a step of bonding.

圖7係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Figure 7 is a cross-sectional view of a portion where the wires are joined, and is a view showing a step of bonding.

圖8係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Fig. 8 is a cross-sectional view showing a portion where the wires are joined, and is a view showing a step of bonding.

圖9係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Figure 9 is a cross-sectional view of a portion where the wires are joined, and is a view showing a step of bonding.

圖10係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Figure 10 is a cross-sectional view of a portion where the wires are joined, and is a view showing a step of bonding.

圖11係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Figure 11 is a cross-sectional view of a portion where the wires are joined, and is a view showing a step of bonding.

圖12係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Figure 12 is a cross-sectional view of a portion where the wires are joined, and is a view showing a step of bonding.

圖13係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Figure 13 is a cross-sectional view of a portion where the wires are joined, and is a view showing a step of bonding.

圖14係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Figure 14 is a cross-sectional view of a portion where the wires are joined, and is a view showing a step of bonding.

圖15係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Fig. 15 is a cross-sectional view showing a portion where the wires are joined, and is a view showing a step of bonding.

圖16係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Figure 16 is a cross-sectional view of a portion where the wires are joined, and is a view showing a step of bonding.

圖17係導線被接合之部分之剖面圖,且係顯示接合之一個步驟之圖。Figure 17 is a cross-sectional view of a portion where the wires are joined, and is a view showing a step of bonding.

圖18係顯示導線與基板側電極墊之接合強度之圖。Fig. 18 is a view showing the bonding strength between the wire and the substrate-side electrode pad.

圖19係顯示導線與基板側電極墊之接合強度之圖。Fig. 19 is a view showing the bonding strength between the wire and the substrate-side electrode pad.

Claims (6)

一種半導體裝置之製造方法,其係藉由從前端被供給金製導線之毛細管、及可切換夾持上述導線之閉合狀態與鬆開上述導線之開放狀態之箝位器,以上述導線連接形成於基板之第一面上的基板側電極墊、與形成於搭載於上述基板之第一面上之晶片上的晶片側電極墊,且於上述基板側電極墊上藉由無電解鍍敷而形成鍍鎳,於上述鍍鎳上藉由無電解鍍敷而形成鍍鈀,於成為上述鍍鈀上之最表層藉由無電解鍍敷而形成鍍金,使上述毛細管靠近上述晶片,將上述導線之一端連接於上述晶片側電極墊,於上述箝位器之開放狀態下,使上述毛細管向上述晶片上方移動,使上述毛細管向朝向上述基板側電極墊之第1方向移動,使上述毛細管靠近上述基板側電極墊,將上述導線一次接合於上述基板側電極墊,使上述毛細管移動,在比上述一次接合位置更向上述第1方向移動之位置將上述導線二次接合於上述基板側電極墊,使上述毛細管向上述基板上方移動,將上述箝位器切換成閉合狀態,使上述毛細管向上述基板之更上方移動; 上述毛細管之向上述第1方向之移動係進行至超過上述一次接合位置之正上方的位置;上述一次接合係一面使上述毛細管向與上述第1方向相反之第2方向移動、一面靠近上述基板側電極墊而進行。A method of manufacturing a semiconductor device, which is formed by a capillary connected to a gold wire from a tip end, and a clamp capable of switching between a closed state of the wire and an open state of the wire; a substrate-side electrode pad on the first surface of the substrate, and a wafer-side electrode pad formed on the wafer mounted on the first surface of the substrate, and nickel plating is formed on the substrate-side electrode pad by electroless plating Palladium plating is formed by electroless plating on the nickel plating, and gold plating is formed on the outermost layer of the palladium plating by electroless plating, and the capillary is brought close to the wafer, and one end of the wire is connected to The wafer-side electrode pad moves the capillary toward the upper side of the wafer in an open state of the clamper, and moves the capillary toward the first direction of the substrate-side electrode pad to bring the capillary closer to the substrate-side electrode pad. And bonding the lead wire to the substrate-side electrode pad once, and moving the capillary tube to the first side at a position more than the primary bonding position The position of the above-described second bonding wire to the substrate-side electrode pad, so that the capillary is moved upward toward the substrate, the clamp is switched to the closed state, the capillary tube so that it more to the upward movement of the substrate; The movement of the capillary in the first direction is performed to a position directly above the primary bonding position, and the primary bonding system moves the capillary toward the second direction opposite to the first direction and approaches the substrate side The electrode pad is used. 一種半導體裝置之製造方法,其係藉由從前端被供給導線之毛細管、及可切換夾持上述導線之閉合狀態與鬆開上述導線之開放狀態之箝位器,以上述導線連接形成於基板之第一面上之基板側電極墊、與形成於搭載於上述基板之第一面上之晶片上的晶片側電極墊,且藉由無電解鍍敷於上述基板側之電極墊之最表層形成鍍金,使上述毛細管靠近上述晶片,將上述導線之一端連接於上述晶片側電極墊,於上述箝位器之開放狀態下,使上述毛細管向上述晶片上方移動,使上述毛細管向朝向上述基板側電極墊之第1方向移動,使上述毛細管靠近上述基板側電極墊,將上述導線一次接合於上述基板側電極墊;上述毛細管之向上述第1方向之移動係進行至超過上述一次接合位置之正上方的位置;上述一次接合係一面使上述毛細管向與上述第1方向相反之第2方向移動、一面靠近上述基板側電極墊而進 行。A method of manufacturing a semiconductor device, which is formed on a substrate by a capillary connected to a lead from a tip end, and a clamp capable of switching between a closed state of the wire and an open state of the wire, and connecting the wire to the substrate a substrate-side electrode pad on the first surface and a wafer-side electrode pad formed on the wafer mounted on the first surface of the substrate, and gold plating is formed on the outermost layer of the electrode pad on the substrate side by electroless plating The capillary is brought close to the wafer, and one end of the wire is connected to the wafer-side electrode pad, and in the open state of the clamp, the capillary is moved upwardly over the wafer, and the capillary is directed toward the substrate-side electrode pad. Moving in the first direction, the capillary is brought close to the substrate-side electrode pad, and the lead wire is once bonded to the substrate-side electrode pad; and the movement of the capillary in the first direction is performed directly above the primary bonding position. a position in which the capillary is moved in a second direction opposite to the first direction, Adjacent to the substrate side electrode pad Row. 如請求項2之半導體裝置之製造方法,其中於上述一次接合後,使上述毛細管向上述基板側電極墊上方移動,使上述毛細管移動,在比上述一次接合之位置更向上述第1方向移動之位置將上述導線二次接合。The method of manufacturing a semiconductor device according to claim 2, wherein after the one-time bonding, the capillary is moved upward over the substrate-side electrode pad, and the capillary is moved to move in the first direction at a position more than the primary bonding. The position double joins the above wires. 如請求項3之半導體裝置之製造方法,其中於上述二次接合後,使上述毛細管向上述基板上方移動,將上述箝位器切換成閉合狀態,使上述毛細管向上述基板之更上方移動。The method of manufacturing a semiconductor device according to claim 3, wherein after the second bonding, the capillary is moved over the substrate, the clamp is switched to a closed state, and the capillary is moved upward of the substrate. 如請求項2至4中任一項之半導體裝置之製造方法,其中於上述基板側電極墊上藉由無電解鍍敷而形成鍍鎳,於上述鍍鎳上藉由無電解鍍敷而形成鍍鈀,上述鍍金係形成於上述鍍鈀上。The method of manufacturing a semiconductor device according to any one of claims 2 to 4, wherein nickel plating is formed on the substrate-side electrode pad by electroless plating, and palladium plating is formed by electroless plating on the nickel plating. The gold plating is formed on the palladium plating. 一種接合裝置,其係以金製導線連接形成於基板之第一面上的基板側電極墊、與形成於搭載於上述基板之第一面上之晶片上之晶片側電極墊,其具備:箝位器,其可切換夾持上述導線之閉合狀態與鬆開上述導線之開放狀態;及控制部,其使從前端被供給導線之毛細管靠近上述晶片,將上述導線之一端連接於上述晶片側電極墊,於上述箝位器之開放狀態下,使上述毛細管向上述晶片上方移動,使上述毛細管向朝向上述基板側電極墊之第1方 向移動,使上述毛細管靠近上述基板側電極墊而將上述導線一次接合於上述基板側電極墊,使上述毛細管向上述基板側電極墊上方移動,使上述毛細管移動,在比上述一次接合之位置更向上述第1方向移動之位置將上述導線二次接合,使上述毛細管向上述基板上方移動,將上述箝位器切換成閉合狀態,使上述毛細管向上述基板之更上方移動;上述毛細管之向上述第1方向之移動係進行至超過上述一次接合位置之正上方的位置;上述一次接合係一面使上述毛細管向與上述第1方向相反之第2方向移動、一面靠近上述基板側電極墊而進行。A bonding apparatus for connecting a substrate-side electrode pad formed on a first surface of a substrate with a gold wire and a wafer-side electrode pad formed on a wafer mounted on a first surface of the substrate, comprising: a tong And a control unit that switches the closed state of the wire and the open state of the wire; and a control unit that brings the capillary that is supplied with the wire from the front end to the wafer, and connects one end of the wire to the wafer side electrode a pad, wherein the capillary moves to the upper side of the wafer in an open state of the clamper, and the capillary faces the first side of the substrate-side electrode pad Moving, the capillary is brought close to the substrate-side electrode pad, and the lead wire is once bonded to the substrate-side electrode pad, and the capillary is moved upward over the substrate-side electrode pad to move the capillary to be more than the one-time bonding position. The lead wire is secondarily joined to the position moving in the first direction, the capillary is moved upward of the substrate, the clamp is switched to a closed state, and the capillary is moved upward of the substrate; The movement in the first direction is performed to a position directly above the primary bonding position, and the primary bonding system is performed while moving the capillary in a second direction opposite to the first direction and approaching the substrate-side electrode pad.
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