TWI478166B - Memory erase methods and devices - Google Patents

Description

Memory erasing method and device

The present invention relates generally to memory devices, and in particular to the memory devices and methods of erasing memory.

Memory devices are typically provided as an internal storage area in a computer. The term memory identifies a data storage device that appears in the form of an integrated circuit chip. Several different types of memory are used in modern electronics, one common type being RAM (random access memory). It is found that RAM is used as the main memory in a computer environment. Most RAMs are volatile, which means they need a steady current to maintain their content. Once the power is turned off, any data in the RAM is lost.

A computer almost always contains a small amount of read-only memory (ROM) that holds instructions for booting the computer. Memory devices that do not lose the data content of their memory cells when power is removed are generally referred to as non-volatile memory. An EEPROM (Electrically Erasable Programmable Read Only Memory) is a special type of non-volatile ROM that can be erased by exposing it to a charge. The EEPROM contains a large number of memory cells with charge storage nodes such as, for example, floating gates or charge traps. The data is stored in a floating gate field effect transistor (FET) memory cell in the form of a charge on the charge storage node. One type of charge storage node (a floating gate) is typically made of a doped polysilicon disposed above the channel region and electrically isolated from other cell elements by a dielectric material (typically an oxide). The charge is transferred to or removed from the floating gate or trap layer by specialized stylization and erase operations to change the threshold voltage of the device.

Yet another type of non-volatile memory system is a flash memory. A typical flash memory includes a memory array that includes a plurality of memory cells based on charge storage nodes. These units are usually grouped into sections called "erased blocks". Each of the cells in the erase block can be programmed by tunneling the charge to its individual charge storage node. However, unlike stylized jobs, erase jobs in flash memory typically erase memory cells with a large number of erase jobs, in which all of the memory cells in a selected erase block are erased with a single job. It should be noted that in recent non-volatile memory devices, the source/汲 of the memory cell FET has been stored by using a plurality of threshold levels or a non-conductive charge trapping layer and storing the trapped data. A plurality of bits are stored in a single unit in one of the charges in the vicinity of each of the poles.

For example, a conventional NOR array, an EEPROM or a flash memory NAND architecture array configures its non-volatile memory cell array in a matrix of columns and rows such that the gate of each non-volatile memory cell in the array Coupled to the word line (WL) by column. However, unlike NOR, each memory cell is not directly coupled to a source line and a column of bit lines. Instead, the memory cells in the array are configured together in a string (typically 8, 16, 32, or more per string), where the memory cells in the string are in a common source line and a column of bits. The lines are coupled together in series from the source to the drain. Note that there are other non-volatile memory array architectures including, but not limited to, AND arrays, OR arrays, and virtual ground arrays.

In modern NAND flash memory, the density of NAND arrays is increasing. As each new generation of processes is developed, the array spacing pattern becomes smaller and smaller. Due to the increased array density, the array-related regions consume a large amount of die space and potentially more than one die package, such as a thin small package (TSOP) memory package.

As a result of the development of process technology, the defect rate in the associated regions of the array is likely to increase due to the extremely close spacing of the data lines (such as their data lines, commonly referred to as bit lines) to the data lines. For example, bit line decoding in an array of increased density typically has a high defect rate.

Newer forms of NAND flash memory compensate for such difficulties by decoding one of the high voltage transistors with a lower voltage transistor to decode a bit line group, such as odd and even pages. Such lower voltage transistors (commonly referred to as low voltage transistors (for example, NMOS or PMOS type)) are relatively large in terms of physical size, higher power transistors are smaller, and are relatively low in higher power transistors. Voltage operation. The bit line is typically charged to approximately 20 volts during a erase operation. In such erase operations, a low voltage transistor (typically a select gate n-type metal oxide semiconductor) is also charged to a higher voltage such that it does not breakdown. The breakdown of this low voltage transistor can trap a high voltage on the bit line.

For the above reasons, and for other reasons familiar to those skilled in the art after reading and understanding this specification, it is necessary to erase the memory block in the case where the low voltage transistor does not break down. .

In the following detailed description of the embodiments, reference is made to the accompanying drawings that form a part thereof. In the drawings, like reference numerals refer to the These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention.

Therefore, the following detailed description is not to be construed as a limitation of the scope of the

FIG. 1 shows a portion of a NAND array 100. In one embodiment, NAND array 100 includes a tub (eg, well) 102 formed in a semiconductor material, such as substrate 101. A source line 104 is connected to the trench region through a source connection as shown. The source side selection gate 105 and the drain side selection gate 107 control access to the NAND strings in the memory. In one embodiment, string select gate transistors 106 and 108 are low voltage NMOS transistors (for example, a low voltage transistor having the same type of configuration as transistors 105 and 107) and are used to control memory. The erase operation in the body 100. Data lines (such as those commonly referred to as bit lines) 110 are used to sense information stored in memory unit 112 of array 100 and to program information into array 112. Unit 112 is configured in logical columns and rows.

This portion of array 100 can be seen in the form of a circuit diagram in FIG. The unit 112 is disposed in the NAND string (such as the odd string 202 and the even string 204), and accesses the odd string 202 and the even string select gate by turning on the odd string select gate transistor 106 by using the signals AWMUX_EVEN and AWMUX_ODD, respectively. The transistor 108 accesses the even string 204. The source side selection gate transistor 105 and the drain side selection gate transistor 107 are controlled by signals SGS and SGD, respectively.

In a NAND memory, a memory cell block is typically grounded by applying all of the word lines in the block and applying a erase voltage to a semiconductor material (eg, a semiconductor) on which the memory cells are formed. One of the regions of the material) and thus the channels of the memory cells are erased by removing charge from the charge storage node. More specifically, charge is typically removed from the charge storage node to the channel by Fowler-Nordheim electron tunneling.

For the typical erase operation of a NAND memory using a low voltage string to select a gate transistor, the gate region of the source and the gate of the string selection gate transistor are erased. The bit line is charged by forward biasing through one of the PN junctions through the trench. When the erase portion of the erase operation is completed, typically the trench and source are discharged to a reference voltage Vss (eg, a substrate voltage, for example ground). The gate of the string select gate transistor is coupled down to Vss by the slot region. The bit line is discharged through the breakdown of the PN junction. For a typical bit line discharge, the PN junction breaks down at about 8 volts, which can apply stress to the low voltage string select gate transistor (which generally cannot withstand this without breaking down) High voltage stress, thus reducing its reliability). A voltage as high as the PN junction breakdown voltage can be trapped on the bit line for a long period of time, which results in further unreliability of the low voltage string selection gate transistor.

In the operation, an erase operation according to an embodiment of the present invention is shown in flow chart form in FIG. In block 302, the slot and source lines of one of the blocks to be erased are charged to a wipe voltage (in one embodiment approximately 20 volts). The gate of the string selection gate transistor is also charged to the erase voltage. In one embodiment the bit line is charged to the erase voltage by being forward biased by one of the PN gates through the pass region voltage. The erase voltage erases the memory cells in the block to be erased. When the erase portion is completed, the erase operation continues in the block 304 where the drain and source lines and the gates of the string select gate transistors. This discharge is tied to one of the intermediate voltages below the erase voltage (in one embodiment approximately 16 volts, at least one string of select gate voltages is selected to be lower than the erase voltage). In block 306, a determination is made as to the level of discharge of the cell voltage and/or source line. For example, if the tank voltage has not reached the intermediate voltage, then discharge continues at block 307 and the tank voltage is monitored at block 306. When the cell voltage reaches an intermediate voltage, the discharge is stopped at block 308, such as by floating the source line and/or the trench region. In block 310, the gate of the string select gate transistor is disconnected from the trench and source lines, and in block 312 its gate is recharged to the erase voltage. This action causes the string selection gate transistor to turn on.

Once the string select gate transistors are turned on, bit line 110 is discharged to the trench/source voltage, and in block 314, such as by connecting the trench and source lines to a reference voltage, such as Vss (eg, ground) restarts the discharge of the slot and source lines. The gate of the string selection gate transistor is floated and discharged by a coupling effect to the trench region and the source line. The bit line 110 is discharged by breakdown of the PN junction between the bit line and the groove. The discharge portion string selection gate transistor remains on during the entire erase operation because it is maintained at a voltage not lower than approximately the difference between the erase voltage and the intermediate voltage (in one embodiment about 4 volts). Therefore, no high voltage remains on the bit line, and the protection string selects the gate transistor from breakdown.

In one embodiment, the slot and/or source voltages are compared to an intermediate voltage in a comparator. The comparator signal changes when the cell and/or source voltage reaches the intermediate voltage and stops discharging. It should be understood that there are numerous methods and circuits for stopping the discharge of the valleys and/or sources at intermediate voltages, and that many of the methods and circuits within the skill of the art are suitable for use herein. Various embodiments of the invention are within the scope of various embodiments of the invention.

A timing diagram of an erase job is shown in FIG. 4, wherein the reference numbers correspond to the diagrams of FIGS. 1 and 2. 4 shows the gate/source 102/104, the gate of the string selection gate transistor 106/108, the bit line 110, and the source 105 and drain 107 select gate signals during the entire erase operation. The voltage of each of them. At time t0, at the beginning of the erase operation, the trench region 102 and the source 104 and the bit line 110 are at a reference voltage (Vss). The gates of the low voltage string select gate transistors 106 and 108 are at a supply voltage (Vcc). At time t1, the gates of transistors 106 and 108 are discharged to Vss. At time t2, transistors 106 and 108 are coupled to the trench/source 102/104 and the trench/source 102/104 is charged to the erase voltage, thereby coupling the transistors 106 and 108 up to the erase voltage. . The trench/source 102/104, the source 105 and the drain 107 select the gate of the gate, and each of the gates of the string selection gate transistors 106 and 108 is charged to the erase voltage. The bit line is coupled upward to the erase voltage by a forward bias of the PN junction between the bit line 110 and the trench region 102.

At time t3, the trench/source 102/104 is disconnected from the erase voltage and connected to Vss. The trench/source 102/104, drain 105 and source 107 select the gate of the gate, and the gates of transistors 106 and 108 begin to discharge towards Vss. At time t4, the gate/source 102/104, the drain 105 and the source 107 select the gate of the gate, and the gates of the transistors 106 and 108 reach an intermediate voltage, and the source/slot region 102/104 is disconnected from Vss. The gates of transistors 106 and 108 are disconnected from trench/source 102/104 and charged to the erase voltage. It is recharged back to the erase voltage before time t5, and when the transistors 106 and 108 are turned on, the bit line 110 is discharged to the intermediate voltage before time t6.

At time t6, as transistors 106 and 108 are turned "on", they are disconnected from the erase voltage and allowed to float. Similarly, the trench/source 102/104 is connected to Vss, and the bit line 110, the source 105 and the drain 107 select the gate of the gate, and the trench/source 102/104 begins to discharge from the intermediate voltage to Vss. . The gates of transistors 106 and 108 begin to discharge at the same rate as trench/source 102/104 by down-coupling. The transistors 106 and 108 remain on during their voltage difference from the slot/source 102/104. At time t7, the trench/source 102/104, the drain 105 and the source 107 select the gate of the gate, and the bit line 110 discharges to Vss, and the gates of the transistors 106 and 108 have passed through The coupling discharges to a difference between the erase voltage and the intermediate voltage (in one embodiment is close to 4 volts).

The difference between the intermediate voltage and the erase voltage is chosen in one embodiment to ensure that the transistors 106 and 108 remain on for the entire discharge portion of the erase operation, such as to avoid breakdown caused by high voltage stress. The bit line 110 is properly discharged to Vss without breaking through the transistors 106 and 108. At time t8, when the downward coupling is completed, the gates of transistors 106 and 108 are charged to Vcc. In this embodiment, the select gates remain open for the discharge to Vss portion of the erase operation, and the select gates are protected from breakdown by being held on. In addition, since there is no breakdown and the string selection gate transistors 106 and 108 remain on, no voltage is trapped on the bit line 110 that can be properly and fully discharged.

FIG. 5 illustrates a functional block diagram of one of the memory systems 520 including one of the non-volatile memory devices 500. The memory device 500 has been simplified to focus on the memory to aid in understanding the features of the stylized embodiment. The memory device 500 is coupled to an external controller 510. Controller 510 is a microprocessor or some other type of control circuit.

Memory device 500 includes a non-volatile memory cell array 530, such as the non-volatile memory cell array illustrated in Figure 1 previously discussed. The memory array 530 is configured with a plurality of banks such as an access line of a word line column and a data line such as a bit line line. In one embodiment, the rows of memory array 530 are comprised of a series of strings of memory cells. As is known in the art, the connection of a cell to a bit line determines that the array is a NAND architecture, an AND architecture, or a NOR architecture.

An address buffer circuit 540 is provided to latch the address signal provided by the I/O circuit 560. The address signals are received and decoded by a column of decoders 544 and a row of decoders 546 to access memory array 530. Those skilled in the art will appreciate that the number of address input connections depends on the density and architecture of the memory array 530, in accordance with the benefit of this description. That is, the number of addresses increases with increasing memory unit counts and increased memory banks and block counts.

The memory device 500 reads the data in the memory array 530 by sensing the voltage or current changes in the rows of the memory array using the sense amplifier/data cache circuit 550. In one embodiment, sense amplifier/data cache circuit 550 is coupled to read and latch a column of data from memory array 530. Data input and output buffer circuit 560 is included for bidirectional data communication and address communication with controller 510 via a plurality of data connections 562. A write circuit 555 is provided to write data into the memory array.

Memory control circuit 570 provides an address circuit and circuitry for decoding signals provided from processor 510 over control connection 572. These signals are used to control operations on the memory array 530, including data reading, data writing (staging), and erasing operations. Memory control circuit 570 can be a state machine, a sequencer, or some other type of controller that generates a memory control signal. In one embodiment, memory control circuit 570 is configured to control bit line charging of the previously discussed stylized embodiments.

In one embodiment, memory control circuit 570 also includes an erase control circuit 571 (which is shown in more detail in FIG. 6) that controls the erase operation of system 520. The erase control circuit is configured to perform the erase operations set forth herein, including providing appropriate voltages to the array and its components, such as to the select decode circuit 548 to control the string select gate transistors for even and odd page operations. 106 and 108 and for controlling the voltage of the erase operation in accordance with one or more of the various methods set forth herein with respect to at least FIGS. 3 and 4.

It should be understood that a number of circuits are suitable for performing this control, and that the selection and configuration of their circuits is within the scope of the present invention.

In an exemplary embodiment (as shown in the block diagram of FIG. 6), one of the erase control circuits, such as circuit 571, includes a charge pump 602 that is pumpable to the erase voltage and that is selectively coupled to the string Control 604, slot control 606, and source control 608 are selected. Slot control 606 and source control 608 are each also selectively coupled to Vss to allow discharge of the same voltage. In addition to being selectively coupled to the trench and/or source, string select control is selectively coupled to Vcc and Vss to allow charging to Vcc and discharging to Vss. A wipe detector 610 determines when the discharge of the trench and/or source reaches the intermediate voltage discussed above. The string selection gate control 612 controls the connection of the gate region and/or the source to the gate of the string selection gate. It should be understood that the design and implementation of this circuit is well within the skill of those skilled in the art, and that the operation is detailed with reference to the various methods set forth herein, and therefore will not be further discussed.

in conclusion

Wiping methods and memory using their erase methods have been shown, including maintaining a low voltage transistor in an on state during discharge after memory erasing, such as to prevent transistor breakdown and bit The voltage on the line is trapped.

Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that the <RTIgt; This application is intended to cover any adaptations or variations of the invention. Therefore, the invention is obviously intended to be limited only by the scope of the claims and the equivalents thereof.

100. . . NAND array

101. . . Substrate

102. . . Slot/well

104. . . Source line

105. . . Source side selection gate

106. . . String selection gate transistor

107. . . Bungary side selection gate

108. . . String selection gate transistor

110. . . Data line

112. . . Array

202. . . Odd string

204. . . Even string

500. . . Non-volatile memory device

510. . . External controller

520. . . Memory system

530. . . Memory array

544. . . Column decoder

546. . . Row decoder

548. . . Select decoding circuit

550. . . Sense amplifier / data cache circuit

555. . . Write circuit

560. . . Write/output circuit

562. . . Data connection

570. . . Memory control circuit

571. . . Erase control circuit

572. . . Control connection

602. . . Charge pump

604. . . String selection control

606. . . Slot control

608. . . Source control

610. . . Erase detector

612. . . String selection gate control

WL1. . . Word line 1

WL32. . . Word line 32

1 is a diagram showing one of partial memory structures in accordance with an embodiment of the present invention;

2 is a partial circuit diagram of a memory according to another embodiment of the present invention;

3 is a flow chart of one of the methods according to another embodiment of the present invention;

4 is a timing diagram of a method in accordance with another embodiment of the present invention;

5 is a functional block diagram of a system in accordance with an embodiment of the present invention; and

Figure 6 is a functional block diagram of one of the erase control circuits in accordance with another embodiment of the present invention.

100. . . NAND array

101. . . Substrate

102. . . Slot area

104. . . Source line

105. . . Source side selection gate

106. . . String selection gate transistor

107. . . Bungary side selection gate

110. . . Data line

112. . . Array

Claims (15)

A method of erasing in a memory, comprising: erasing a block of a memory with a erase voltage, comprising charging a gate of a slot region, a source, and a string selection gate transistor to the wipe And removing the string selection gate transistors of the memory during the discharge of the erase voltage, wherein protecting the string selection gate transistors further comprises: discharging the trench region and the source to a An intermediate voltage; turning on the string selection gate transistors to discharge the data lines of the memory; and discharging the trench regions and the source to a reference voltage. The method of claim 1, wherein the data lines of the memory are discharged by means of a breakdown of a PN junction between each data line and the slot. The method of claim 1, wherein the string selection gate transistors remain turned on by discharging the trench region and the source to the reference voltage. The method of claim 1, wherein discharging the slot and the source to an intermediate voltage further comprises: connecting the slot and the source to the reference voltage; comparing the slot voltage and/or the source voltage And the intermediate voltage; and disconnecting the slot region and the source from the reference voltage when the tank voltage and/or the source voltage is equal to the intermediate voltage. The method of claim 1, wherein the protecting further comprises: turning the string selection gate transistors on after the partial discharge of the erase voltage, wherein the strings are selected during discharge of the erase voltage The gate electro-crystal system operates in an on state. The method of claim 1, wherein the gates of the string selection gate transistors are discharged from the erase voltage via a coupling effect to the one of the trench regions and/or the source. The method of claim 5, wherein the string selection gate transistors are turned on after the partial discharge of the erase voltage further comprises: the trench region, the source, and the gates of the string selection gate transistors Discharging is lower than the erase voltage; and recharging the gates of the string select gate transistors to the erase voltage, wherein the series select gate transistors when the trench is discharged The gate is discharged through a coupling effect with one of the trench regions. The method of claim 1, wherein protecting the string selection gate transistor of the memory during the discharge of the erase voltage further comprises: a voltage between the voltage of the string selection gate transistor and a data line voltage The string selection gate transistors are turned on before the difference reaches a breakdown voltage of the string selection gate transistors, wherein the string selection is performed when one of the memory regions and the source are discharged to a reference voltage The gate transistor is maintained in a conductive mode of operation. A memory device comprising: a memory cell array; and circuitry for controlling and/or accessing the memory cell array, the control circuit configured to perform a method, the method comprising: One of the discharge portions of the operation maintains the gate of the string selection gate transistor at a voltage higher than a tank voltage and a source voltage The method includes: discharging the slot and the source from an erasing voltage to an intermediate voltage; turning on the string selection gate transistors to discharge the data line of the memory; and the slot area and the The source is discharged to a reference voltage. The memory device of claim 9, further comprising: wherein discharging the slot region and the source from an erase voltage to an intermediate voltage comprises discharging the slot region and the source from the erase voltage to be lower than the wipe Except for at least one of the voltages of one of the series select gate transistors, wherein the series of select gate transistors includes recharging the gates of the string select gate transistors to the Erasing the voltage; and discharging the slot and the source to a reference voltage comprises discharging the slot and source from the intermediate voltage to the reference voltage. The memory device of claim 9, wherein the control circuit further comprises an erase control circuit for detecting the cell voltage and/or the source voltage; and when the cell voltage reaches the intermediate voltage The slot and the source are disconnected from the gates of the plurality of string selection gate transistors and the reference voltage; recharging the gates of the plurality of string selection gate transistors; allowing the plurality of strings to be selected The gate voltages of the gate transistors float and reconnect the trench region and the source to the reference voltage when the gates of the plurality of string select gate transistors are recharged. The memory device of claim 9, wherein the slot area and the source are from the The plurality of string selection gate transistors are maintained in a conductive operation state when the intermediate voltage is discharged to the reference voltage. The memory device of claim 9, wherein the gates of the plurality of string selection gate transistors are maintained above the channel region and source when the slot region and the source are discharged from the intermediate voltage to the reference voltage One of the voltage differences of the pole voltage. The memory device of claim 9, wherein the data line of the memory is configured to be discharged by breakdown of a PN junction between each data line and the slot. The memory device of claim 9, wherein the plurality of string selection gate transistors are turned on by recharging the plurality of string selection gate transistors to the erase voltage.