TWI476696B - Work processing device - Google Patents

Description

Work processing device

The present invention relates to the function of an OS (Operating System), and more particularly to the control of a co-processor.

It is not limited to a general-purpose device OS such as a personal computer, and a dedicated device OS such as a mobile phone is also required to have a high level of function. In particular, an OS that can perform a plurality of operations with one CPU (Central Processing Unit) (hereinafter, this type of OS is referred to as a "multiplexed OS") is mounted on most electronic devices.

The multiplexed OS divides the processing time of the CPU into unit time (time slice: Time Slice), and sequentially allocates time segments to a plurality of jobs. Each job can only use the CPU when it is given a time segment by the OS. Perform a job at each time segment. Since the time segment is very short time for the user, multiple work feelings seem to be performed simultaneously. According to this processing method, when the operation A becomes the input standby state and the processing capability of the CPU is not required for the time being, the execution is given to another job B to effectively utilize the processing power of the CPU. Here, the so-called execution system is synonymous with the use of the CPU.

The action of the execution right of the multiplexed OS switching operation is referred to as "work switching". Work switching occurs when a time segment passes, or when a job executes a given instruction. The multiplexed OS stores the context information of the work being performed in the TCB (Working Control Block: Task Control Block) when the execution timing of the work switching arrives. The context information is the data related to the work execution status of the data stored in the CPU's scratchpad during work execution. The TCB is an area secured by the memory in order to maintain the information inherent in the work. The multiplexed OS stores the context information of the work being performed in the TCB, selects the next work assigned to the execution ,, reads the context information from the TCB of the work, and loads it into the CPU scratchpad. In this way, each job gradually performs its own processing in units of time segments.

Although the multiplexed OS has the advantage of being able to perform a plurality of tasks with high efficiency, it also has the disadvantage of newly generating contextual information storage and loading overhead (Overhead). However, in general, multiplexed OS has many advantages even if the work switching is accompanied by a payload.

Patent Document 1: Japanese Laid-Open Patent Publication No. Hei 11-272480

Patent Document 2: Japanese Laid-Open Patent Publication No. 2001-75820

Patent Document 3: Japanese Laid-Open Patent Publication No. Hei 11-234302

Patent Document 4: Japanese Laid-Open Patent Publication No. 2000-10803

Patent Document 5: Japanese Laid-Open Patent Publication No. 2000-276362

Non-Patent Document 1: Mori Katsuhisa, 坂卷佳寿美, 重松宏志 "Hardware implementation of a real-time operating system for embedded control system", Tokyo Metropolitan Industry Research Report of the Institute of Technology, Japan, August 4, 2005, p.55-58

In recent years, an instant OS (hereinafter referred to as "RTOS (Real-Time Operating System)" which is strictly required to be processed in a certain period of time has been gradually popularized with an embedded system (Embedded System). In such a time-critical RTOS, the payload of the work switching may have a large impact on the overall performance of the system.

Also, there are many cases where one part of the work is handed over to an auxiliary processor other than the CPU. The auxiliary processor includes, for example, a DMAC (Direct Memory Access Controller), a Floating Point Processing Unit (FPU), a cryptographic processing unit, and the like. Hereinafter, an operation in which the auxiliary processor executes processing is referred to as "auxiliary processing". The auxiliary processor is a dedicated circuit that is specifically assisted in processing. Therefore, in general, the execution of the auxiliary processor is faster than performing the same auxiliary processing with the CPU. However, a unique payload is generated when utilizing multiple hardware resources of the CPU and the auxiliary processor. In order to further improve the performance of the RTOS, an important issue is to suppress the payload accompanying the auxiliary processing.

The present inventors have completed the present invention in light of the above-described points, and a main object thereof is to provide a technique for performing control work with higher efficiency in multiplex processing, and more particularly to provide a technique for speeding up auxiliary processing.

The form of the invention is a work processing device.

The device has a processing register, a data storage device from the memory to the processing register, an execution control circuit for performing work according to the data of the processing register, a state register for storing the status data of each job, and a control work. The operation switching circuit of the execution state selects the operation selection circuit for the operation according to the predetermined selection condition, and the auxiliary processing circuit that performs the auxiliary processing.

The control circuit is executed to notify the work switching circuit when the system call instruction is executed. The work selection circuit selects an operation to be executed from among the operations indicating the READY state in which the standby state is the executable state.

The work switching circuit selects the output of the work selection circuit when the system call instruction is executed to be the next execution target, retains the data of the processing register in the predetermined memory area, and sets the status data of the work in the change execution. For the selection work, the data retained in the memory area is loaded into the processing register, and the status data is changed from the READY state to the RUN state, thereby switching the operation to be performed.

When the work requires execution of the auxiliary processing, the work switching circuit instructs the auxiliary processing circuit to perform the auxiliary processing.

The data loaded into the processing register can be an instruction (instruction) and an operand (Operand), an instruction without an operand, or a simple data such as a program counter and a stacking indicator. According to this processing method, since the status is managed by the status register, the work switching circuit can perform the operation switching based on the output from the operation selection circuit. When the work requires execution of the auxiliary processing, the work switching circuit receives the execution request in a one-dimensional manner, and instructs the auxiliary processing circuit to perform the auxiliary processing. At this time, the auxiliary processing control can be managed in a one-dimensional manner by the work switching circuit.

Further, any combination of the above constituent elements, or the present invention by a method, a system, a recording medium, or a computer program is also effective as an aspect of the present invention.

According to the present invention, execution control of a more efficient work can be realized in multiplex processing.

First, the work processing device 100 that realizes the work scheduling of the multiplexed OS by the electronic circuit will be described as a "basic example." Then, the hardware configuration of the "double-input type array algorithm (described later)" which is preferable to the work processing apparatus 100 of the second modification is described as "modified example 1". Finally, the work processing apparatus 100 that speeds up the auxiliary processing is described as "Modification 2".

In the following, the description of "this embodiment" is in principle all the "basic examples", "improved example 1" and "modified example 2".

(basic example)

The work processing apparatus 100 shown in this embodiment realizes the work scheduling function of the multiplexed OS by an electronic circuit. Before explaining the work processing apparatus 100 in detail, first, the state transition of the operation will be described with reference to FIG. Here, although the state transition of the operation of the general multiplexed OS is described, the state transition of the operation of the work processing apparatus 100 is also the same. Also, the system call executed by the work processing apparatus 100 is also outlined. The processing method of the work processing apparatus 100 of this embodiment will be described in detail with reference to FIGS. 4 to 10, in addition to the design concept of a general multiplexed OS described with reference to FIGS. 2 and 3. Furthermore, the characteristics of the work processing apparatus 100 will be described by comparing the related processing of the Semaphore, the Mutex, and the event with the general technique as appropriate.

(state transition of work)

Figure 1 is a state transition diagram of the work.

In multiplex processing, each job has a "state". Each operation moves between a plurality of states described later, and is always in any state. The opportunity for state transition is "execution of system call" and "detection of interrupt request signal". System calls are special instructions in the instructions for each job execution. The interrupt request signal is a signal generated when a predetermined data is received from a peripheral device by pressing a keyboard, tapping a mouse, receiving a communication data, and the like. Of course, state transitions are also generated after the time segments assigned to each job pass.

The work is broadly divided into two categories: "general work" and "special work." The general work is the usual work performed by the system call. The special work is the work performed by the detection of the interrupt request signal. This is called the Interrupt Handler. First, after explaining each operating state, various system call commands will be described.

(1) STOP status (stop status)

Indicates that the work is in a stopped state. Both normal work and special work may become STOP. Hereinafter, the work in the STOP state is referred to as "STOP-work".

1-1. General work

When the job execution indicates a system call initiated by another job (hereinafter referred to as "start system call"), the general work in the STOP state transitions to the READY state described later.

1-2. Special work

Special work is usually in STOP. When the interrupt request signal is detected by the operation switching circuit 210 described later, the special operation transitions from the STOP state to the RUN state described later. At this time, the work that was originally in the RUN state migrates to the READY state.

(2) RUN status (execution status)

Indicates that work is in progress. That is, the time segment is assigned to the work to obtain the state of use of the CPU. Both general work and special work may become RUN. Hereinafter, the operation in the RUN state is referred to as "RUN-work". In a plurality of jobs, there is only one operation that can be in the RUN state, and two jobs cannot simultaneously become the RUN state.

2-1. General work

The general operation in the RUN state transitions from the RUN state to the READY state or the WAIT state described later when a predetermined system call is executed. The general work in the RUN state also migrates to the READY state after the time segment has elapsed. In either case, the general work in the READY state transitions to the RUN state to replace the normal work that was originally in the RUN state. When the interrupt request signal is detected, the RUN-work transitions to the READY state. At this time, the special work in the STOP state transitions to the RUN state.

When the RUN-work performs a system call that ends itself (hereinafter referred to as "end system call"), the RUN-work transitions to the STOP state.

2-2. Special work

The special operation of transitioning from the STOP state to the RUN state due to the interrupt request signal returns to the STOP state when the processing itself is terminated. The status that special work may become is only the STOP state and the RUN state.

(3) READY state (executable state)

Indicates that the work is in an executable state. The work in the READY state can be migrated to the RUN state when it is executed by the OS. Only general work may become a READY state. Hereinafter, the work in the READY state is referred to as "READY-work".

When the general operation in the RUN state transitions to a state other than the RUN state by the execution of the system call, or when the special operation of the RUN state ends, the process shifts to the STOP state, and the READY-work transitions to the RUN state. Normal work only moves from the READY state to the RUN state. When there are multiple jobs in the READY state, one of the READY-work moves to the RUN state according to the work priority of one of the context information. When there are multiple READY-work jobs with the same work priority, the work moving to the READY state at the earliest moves to the RUN state.

(4) WAIT status (standby status)

Indicates that the work is waiting for the state in which the established WAIT release condition is established. When the WAIT release condition is established, the work in the WAIT state transitions to the READY state. Only general work may become a WAIT state. Hereinafter, the work in the WAIT state is referred to as "WAIT-work". The WAIT cancellation conditions will be described in detail later.

In summary, each job can only perform its own processing using the CPU when it is in the RUN state. The RTOS manages the status of a plurality of jobs while appropriately switching the RUN-work. According to this, it is possible to realize a processing form in which the CPU executes any work at any time.

(system call)

Next, the system call will be explained. System calls are roughly classified into three types: "Startup System", "WAIT System", and "SET System".

(1) Start system system call

System call related to the migration between the STOP state and the READY state.

1-1. Start system call

RUN-Working Work A makes another system call initiated by General Work B. At this time, the general work B in the STOP state transits to the READY state.

1-2. End system call

Execute the work of this system call, end its own processing, and move from the RUN state to the STOP state. Ending a system call can also be an instruction to end another job for a job.

(2) WAIT system system call

System call related to the migration between the RUN state and the WAIT state.

2-1. Waiting for several flag system calls

Ask for a system call with a banner (described later).

2-2. Waiting for several mutually exclusive system calls

Request for a system call that is mutually exclusive (described later).

2-3. Waiting for several event system calls

A system call that is awaiting an event (described later). In addition to the event ID, the flag type (described later) and the flag condition (described later) are also executed as variables.

In any case, various WAIT cancellation conditions are set by the WAIT system system call. When the WAIT system system call is executed, the RUN-work of the system call is moved to the READY state under the condition that the WAIT release condition is established. On the other hand, when the WAIT release condition is not established, the RUN-work transitions to the WAIT state in which the WAIT release condition is satisfied.

(3) SET system system call

A system call related to the migration between the WAIT state and the READY state. The execution of the SET system system call is an opportunity for the establishment of the WAIT cancellation condition.

3-1. Unlocking the system call

Unlock the system call.

3-2. Disabling Mutual System Calls

Unmutate system calls.

3-3. Setting the event system call

Set the system call for the current flag type (described later) of the event.

3-4. Clearing the flag system call

A system call to clear the current flag type to zero.

In the present embodiment, a description will be given of the total of nine types of system calls, but it is of course possible to construct various system calls.

(General RTOS design ideas)

Figure 2 is a conceptual diagram of a general RTOS.

This RTOS is a multiplexed OS. The general RTOS is implemented as software. The case where the RUN-work is switched from the work A to the work B will be described as an example. Since the work A occupies the CPU, the RTOS issues an interrupt to the CPU and retrieves the use of the CPU from the work A. In addition, the context information of Work A is stored in the TCB. The RTOS selects Work B as the next RUN-work, loading context information from the TCB of Work B to the scratchpad of the CPU. When the loading is finished, the RTOS hands over the CPU to Work B. In this way, the work switching from work A to work B is performed by temporarily taking the CPU usage by the RTOS. The implementation of special work is also the same. At this time, after storing the context information of the RUN-work in the TCB, the usage of the CPU is handed over to the special work to realize the work switching.

Since the RTOS is implemented as software, it is necessary to use the CPU in order to perform its own processing. That is, the RTOS competes with the use of the CPU in its work. Hereinafter, the RTOS implemented by software in this manner is referred to as "software RTOS".

Figure 3 is a circuit diagram of a general CPU executed by the software RTOS.

The CPU 84 includes a processing register 90 that collectively controls the execution of the memory access and execution of the instructions, a processing register 92 that stores various kinds of data such as the context information of the operation, and an arithmetic circuit 94 that performs the calculation. The processing register 92 is a collection of a plurality of types of registers, and is roughly classified into a special register 88 and a general-purpose register 86. The special register 88 is a register that holds a program counter, a stack indicator, a flag, and the like. The general-purpose register 86 is a register for holding data for operation, and includes a total of 16 registers of R0 to R15. Although the special register 88 has two types for the user and the system, the general-purpose register 86 has only one type. Hereinafter, the data stored in the processing register 92 is referred to as "processing data".

The execution control circuit 90 outputs the processing data of the desired register in the processing register 92 to the arithmetic circuit 94 by the control signal (CTRL) of the output selector 98. The arithmetic circuit 94 performs operations on the processing data, that is, the instructions and variables. The result of the operation is output to the input selector 96. The execution control circuit 90 inputs the operation result to the desired register in the processing register 92 by the control signal (CTRL) to the input selector 96.

Further, the execution control circuit 90 reads data from the memory through the CPU data bus and appropriately loads it into the processing register 92 through the input selector 96. The execution control circuit 90 similarly records the processing data in the memory through the CPU data bus. The execution control circuit 90 performs the operation while updating the program counter of the special register 88.

When a work switching is generated, the execution control circuit 90 stores the processing data in the TCB of the area on the memory. Assume that job A performs a system call, resulting in a work switch from work A to work B. Since the RTOS acquires the CPU usage by taking the system call execution as an opportunity, the CPU 84 temporarily performs an operation in accordance with the program for the RTOS. The process is as follows.

(Storage of context information for Work A)

1. Execution control circuit 90 switches special register 88 from the user to the system. The processing data for RTOS processing is loaded into the special scratchpad 88 for the system.

2. Execution control circuit 90 stores the data of general purpose register 86 in a stack (not shown).

3. Execution control circuit 90 loads the processing data for the RTOS into a general purpose register 86 from a memory medium, such as another temporary memory, not shown. At this stage, the processing data of the processing register 92 is completely replaced with the processing data for the RTOS.

4. The RTOS self-memory detects the TCB of the work A, and writes the processing data stored in the stack to the TCB. Moreover, the user uses the processing data of the special register 88 to also write to the TCB as part of the context information. In this way, the processing data of job A is stored in the TCB. The action of the RTOS to move the work A from the "RUN" state to the "READY (or WAIT)" is stored in the TCB of the work A.

(Loading of context information for Work B)

1. The RTOS self-memory detects the TCB of the work B, and writes the context information of the TCB to the stack and the user-specific special register 88. The action of the RTOS to move the work B from the "READY" state to the "RUN" state is recorded in the TCB of the work B.

2. The RTOS stores the data for RTOS processing from the general purpose register 86 to a recording medium not shown.

3. Execution control circuit 90 loads the stacked context information into general purpose register 86. The control circuit 90 is executed to switch the special register 88 from the system to the user. In this way, the processing data of job B is loaded into the processing register 92.

Work switching can be achieved through the above process. In general, since there is only one type of general-purpose register 86, stacking is used in order to switch the processing data for work and the processing data for the RTOS. If the general purpose register 86 also has two types, it does not need to be stored and loaded through the stack, so that a faster work switching can be performed.

In this embodiment, by further retaining the temporary storage device 110 according to each work setting, a faster work switching can be realized. The work switching using the reservation register 110 is explained in detail in FIG. It can be seen that in the case of the CPU 84 and the general software RTOS illustrated in FIG. 3, access to the TCB is frequently generated when the operation is switched. In the above hypothetical example, although the work from the work A work to the work B is explained, in reality, the RTOS has to execute the majority of the work B to select the next work B to be executed. At this time, the RTOS frequently accesses the memory. The work processing apparatus 100 of the present embodiment realizes faster work switching in order to make the operation control circuit 200 to be described later dedicated to the work selection processing.

(hardware of RTOS of work processing apparatus 100)

Fig. 4 is a conceptual diagram of the RTOS of the present embodiment.

Unlike the general software RTOS, the RTOS of this embodiment is mainly implemented as another hardware different from the CPU. Hereinafter, the RTOS implemented by hardware is referred to as a "hard RTOS." Since the RTOS of the present embodiment is mainly another hardware different from the CPU, substantially no CPU usage right is required to execute the processing itself. That is, the RTOS will hardly compete with the use of the CPU. In the case of the general software RTOS shown in FIG. 2, the CPU is a circuit for executing the operation and is also an RTOS execution circuit. On the other hand, in the case of the hardware RTOS of the present embodiment, the CPU is clearly a work execution circuit, and the work scheduling function can be realized centering on the storage circuit 120 and the work control circuit 200 which will be described later.

Fig. 5 is a circuit diagram of the work processing apparatus 100 of the present embodiment.

The work processing apparatus 100 includes a storage circuit 120 and a work control circuit 200 in addition to the CPU 150. The CPU 150 is an execution body of the operation, and the storage circuit 120 and the operation control circuit 200 are circuits having the function of the RTOS shown in FIG. The work scheduling process is dominated by the work control circuit 200.

The CPU 150 includes an execution control circuit 152, a processing register 154, and an arithmetic circuit 160. The CPU 150 can also be a general CPU illustrated in FIG. However, the CPU 150 of the present embodiment and the CPU 84 shown in FIG. 3 have some modifications in the method of connecting the signal lines and the like. The following Figure 6 details the specific circuit configuration.

The work control circuit 200 includes a work switching circuit 210, a flag table 212, an event table 214, a work selection circuit 230, and a state memory unit 220. The flag table 212 and the event table 214 will be described in detail later with reference to FIG. The state memory unit 220 is a unit corresponding to each operation. Hereinafter, the state memory unit 220 corresponding to the job A is referred to as "state memory unit 220_A". Each state memory unit 220 holds the state data of the operation. The status data is the context information, especially the information indicating the work attributes such as work priority and status. The contents of the specific materials will be described in detail with reference to FIG. All status data for all jobs is output from the status memory unit 220 to the work selection circuit 230 at any time. The work selection circuit 230 is a circuit that performs various work selections such as selection of a RUN-operation based on state data of each job. The work selection circuit 230 will also be described in detail later with reference to FIG. The work switching circuit 210 performs an operation switching when detecting a system call signal (SC) received from the execution control circuit 152 and an interrupt request signal (INTR) from an external device.

The execution control circuit 152 transmits the system call signal (SC) to the work switching circuit 210 when the system call is executed. Further, when the work switching circuit 210 detects the interrupt request signal (INTR), the work switching circuit 210 transmits a stop request signal (HR) to the execution control circuit 152. The execution control circuit 152 transmits the stop end signal (HC) to the work switching circuit 210 when the operation of the CPU 150 is stopped. The CPU 150 and the work control circuit 200 are interlocked by the three types of signals.

The storage circuit 120 includes a load selection circuit 112 and a plurality of reserved registers 110. The reserved register 110 is also a unit corresponding to each work, and is a register for storing processing data of the processing register 154. Therefore, the reservation register 110 has the same data capacity as the processing register 154 or the processing register 154 or more. Hereinafter, the reservation register 110 corresponding to the job A is referred to as "reserved register 110_A". The load selection circuit 112 loads the data of any of the reserved registers 110 (hereinafter, the data held by the reserved registers 110 is referred to as "storage data") to the processing temporary when the instruction of the work switching circuit 210 is accepted. 154.

Each of the reserved registers 110 outputs the individual stored data to the load selection circuit 112 at any time. When the work switching circuit 210 inputs the work selection signal (TS) of the designated work ID to the load selection circuit 112, the load selection circuit 112 outputs the stored data of the reserved register 110 corresponding to the designated work to the process temporary storage. 154. Moreover, when the work switching circuit 210 inputs the write signal (WT) to the processing register 154, the stored data is actually loaded into the processing register 154.

On the other hand, all processing data of the processing register 154 is also output to all the reserved registers 110 at any time. When the work switching circuit 210 transmits a write signal (WT) to the desired scratchpad 110, the processing data is stored in the reserved register 110. Here, the number of bits that can be transmitted by the connection processing register 154 and the bus pool of each of the reserved registers 110 is set to transmit the processing data in parallel. Therefore, the work switching circuit 210 only transfers the write signal to the reserved register 110 once, and the processed data can be written to the reserved register 110 at a time. Further, the number of bits connecting the reservation register 110 to the load selection circuit 112 and the bus line connecting the load selection circuit 112 and the CPU 150 is also set in the same manner.

In the following, the system call and the interrupt request signal respectively describe the execution method of the work switching.

(1) System call execution

When the execution control circuit 152 of the CPU 150 executes the system call, the execution control circuit 152 stops the clock of the CPU 150 (hereinafter referred to as "CPU clock (CLK)"). The specific stopping method will be described in detail later with reference to FIG. 7 and the like. The execution control circuit 152 transmits a system call signal (SC) indicating the execution of the system call to the work switching circuit 210 of the work control circuit 200. Further, when the stop of CLK is ended, the execution control circuit 152 transmits a stop end signal (HC) to the operation switching circuit 210.

Nine signal lines for transmitting system call signals are connected between the CPU 150 and the work switching circuit 210. The nine signal lines correspond to the above nine types of system calls. The execution control circuit 152 transmits a digital pulse on any of the system call signal lines depending on the type of system call being executed. The work switching circuit 210 can detect the digital pulse according to which one of the nine system call signal lines, and immediately detects the type of the system call executed. The work switching circuit 210 selects necessary data from the output data of the work selection circuit 230 depending on the type of system call, and performs processing indicated by the system call. This processing is performed on condition that the HC is transmitted. The relationship between the work switching circuit 210 and the operation selection circuit 230 will be described in detail with reference to FIG. In addition, the parameters of the system call and the return value are written to the predetermined general purpose register 158 in the processing register 154. The work switching circuit 210 can perform parameter reading and return value writing to the general purpose register 158. Here, it is assumed that the RUN-work A performs a standby flag system call. Therefore, first, it is necessary to store the processing data of the work A.

(Storage of context information for Work A)

The execution control circuit 152 inputs the SC signal indicating the standby flag system call to the work switching circuit 210. The execution control circuit 152 stops CLK and transmits HC at the end of the stop. The work switching circuit 210 selects the next job B to be executed in addition to the flag ID of the flag of the standby object, which will be described later in the various selection circuits built in the operation selection circuit 230. The work switching circuit 210 writes the predetermined data to the state memory unit 220_A. For example, the status of the job A is changed from "RUN" to "READY" or "WAIT". More specifically, the job switching circuit 210 outputs the write signal (WT_A) to the state memory unit 220_A in addition to the "WAIT" output to all the state memory units 220 as the data indicating the operation state in the state data. . In this way, the status setting of the job A is changed.

Next, the work switching circuit 210 outputs a write signal (WT) to the reserved register 110_A. Since the processing data of the processing register 154 is output to each of the reserved registers 110 at any time, it is stored in the reserved register 110_A of the job A by the write signal (WT).

(Loading of context information for Work B)

When the work switching circuit 210 ends the change of the state data of the job A and the storage of the processing data, the job selection signal (TS_B) of the designated job B is output to the load selection circuit 112. Accordingly, the stored data of the reserved register 110_B is output to the processing register 154. When the work switching circuit 210 outputs the write signal (WT) to the processing register 154, the stored data of the work B is loaded into the processing register 154. Further, the work switching circuit 210 writes the predetermined data to the state memory unit 220 of the job B. For example, the status of the job B is changed from "READY" to "RUN". When the above processing is ended, the execution control circuit 152 restarts the CPU clock. The CPU 150 starts the execution of the operation B by restarting the CPU clock. Further details of the processing method will be described later with reference to Fig. 8(b).

(2) Interrupt request signal generation

The work switching circuit 210 detects an interrupt request signal (INTR) from a peripheral device. More specifically, the interrupt request signal (INTR) is transmitted to the work switching circuit 210 from an interrupt controller not shown. The parameter indicating the level of the interrupt request signal (INTR) is recorded in the scratchpad built into the interrupt controller. The work switching circuit 210 transmits a stop request signal (HR) to the execution control circuit 152, and the execution control circuit 152 stops the CPU clock. The work switching circuit 210 stores the RUN-work processing data in the reservation register 110 as in the case of the system call execution. Next, the work switching circuit 210 initiates a special job. Regardless of the parameters of the interrupt request signal, the special work to start is one type. Special work reads the INTR parameters from the built-in register of the interrupt controller and performs processing according to the parameters. The processing of special work execution may be performed for setting the event system call or setting the flag system call, or it may be the start of general work. Depending on the parameters, special work may end without special processing. Depending on the parameters of the INTR, what kind of processing is performed depends on the configuration of the particular job. When the execution of the special work ends, the next RUN-work is selected from the READY-work.

The work switching circuit 210 loads the processing data of the reservation register 110 corresponding to the special operation to the CPU 150. The time required to switch from general work to special work can be predicted based on the operating clock of the work control circuit 200. When the HR is transmitted to the execution control circuit 152, and the operation clock of the operation switching circuit 210 passes the timed pulse, the operation switching circuit 210 stops the transmission of the HR in order to cancel the stop of the CPU clock. When the execution control circuit 152 is stopped transmitting HR, the CPU clock is restarted. At this time, the work switching of the work switching circuit 210 from the normal work to the special work is ended. Details of the processing method will be described later with reference to Fig. 8(a).

Whatever the case,

(A) Processing and loading of processed data

(B) State transition of work and selection of RUN-work

The core processing of the work switching is implemented by hardware. Regarding (A) and (B), even if it is not necessary to access the TCB on the memory, the speed of the work switching is facilitated. Further, in order to realize the work processing apparatus 100, only the function of stopping and restarting the CPU clock may be added to the CPU 150. Moreover, these functions are implemented by hardware and do not limit the scope of the invention. For example, by implementing the main functions of (A) or (B) by hardware, in order to assist the hardware function, a part of the functions of the RTOS can also be implemented in software, which is understood by those having ordinary knowledge in the technical field to which the present invention pertains. thing.

FIG. 6 is a circuit diagram of the CPU 150 of FIG. 5.

Unlike the CPU 84 of FIG. 3, there is only one type of special register 156 and special register 158 in the processing register 154. In the processing register 154, an input bus from the load selection circuit 112, an output bus to the reserved register 110, and a signal line for the write signal (WT) from the operation switching circuit 210 are added. The execution control circuit 152 inputs the data of the desired register in the processing register 92 to the arithmetic circuit 160 by the control signal (CTRL) of the output selector 164. The result of the operation becomes an input to the input selector 162. The execution control circuit 152 inputs the operation result to the desired register in the processing register 154 by the control signal (CTRL) to the input selector 162. The execution control circuit 152 performs the operation while updating the program counter of the special register 156.

The processing data is not stored in the TCB on the memory, but stored in the reserved register 110. The processing data is output from the processing register 154 to each of the reserved registers 110 at any time. In fact, when the processing data is stored in the reservation register 110, as described above, it is controlled by the work switching circuit 210.

Rather than from the TCB on the memory, the stored data is loaded from the scratchpad 110 to the processing register 154. In fact, when the processing data of the reservation register 110 is sequentially loaded, as described above, it is controlled by the work switching circuit 210.

The connection processing register 154 and the load selection circuit 112, and the bus line connecting the processing register 154 and the reserved register 110 are capable of transmitting the bus bars of the number of bits of the processing data in parallel at a time. Therefore, the write and write can be performed at one time by the write signal (WT) of the work switching circuit 210. The general software RTOS must temporarily occupy the processing register 154 when the operation is switched. In contrast, the hardware RTOS of the embodiment does not need to load the special processing data for the work switching processing into the processing register 154. . When switching from the work A to the work B, since only the processing data of the work B is loaded after the processing data of the job A is stored, it is not necessary to divide the processing register 154 into two types for the system and the user, or to perform the transmission. Replacement processing of stacked data.

Fig. 7 is a circuit diagram showing a configuration in which the execution control circuit 152 stops the CPU clock.

The input of the second AND gate 174 is the output of the original clock (CLK0) and the first AND gate 172, the latter being negative logic. The output of the first AND gate 172 stops the end signal (HC). Since the stop end signal (HC) is normally 0, the second AND gate 174 directly outputs the input original clock (CLK0) as the CPU clock (CLK). The CPU 150 operates by receiving the CPU clock output from the second AND gate 174. When the output of the first AND gate 172 is "1", that is, when the stop signal (HC) = 1, the output of the second AND gate 174 is fixed to 0, and the CPU clock (CLK) is stopped.

The input of the first AND gate 172 is the output of the OR gate 176 and the output of the CPU busy signal (CBUSY), which is negative logic. CBUSY is a signal output from a known state machine that generates an internal cycle of the CPU 150, and is a signal of "1" when the CPU 150 is in a stop state. For example, the arithmetic circuit 94 ends the execution of the single instruction or the last instruction of the locked plurality of instructions, and is "0" when the CPU is in a stop state or when the supply of the CPU clock has stopped.

The input of the OR gate 176 is the output of the command decoder 170 (SC_DETECT) and the stop request signal (HR) from the work switching circuit 210. The instruction decoder 170 has a built-in latch circuit that holds SC_DETECT. The instruction decoder 170 takes as input the data (FD) read from the CPU 150, and outputs SC_DETECT=1 when the FD is a system call instruction. With the built-in latch circuit, the instruction decoder 170 outputs SC_DETECT=1 at any time even if the FD changes thereafter. The write signal (WT) of the work switching circuit 210 to the processing register 154 is also input to the instruction decoder 170. When the WT changes from 0 to 1, the action of loading the stored data into the processing register 154 is performed as described above. This WT is a pulse signal that returns from 1 to 0 after a predetermined time. When the WT changes from 1 to 0, the latch circuit of the instruction decoder 170 is reset, and the instruction decoder 170 stops transmitting SC_DETECT. The relationship between SC_DETECT and the write signal (WT) is explained in detail in FIG. 8(b). The instruction decoder 170 of the present embodiment is a device specially provided for executing the control circuit 152 in order to determine whether or not the execution target instruction is a system call. As a modification, the command decoder 170 may be common to the CPU decoder that is the decoding step of the CPU 150. At this time, the command decoder 170 can be realized by adding a function of SC_DETECT=1 when the CPU decoder adds a data to be decoded when the decoded data is a system call command.

When the interrupt request signal (INTR) is generated, the work switching circuit 210 transmits the stop request signal (HR) to the execution control circuit 152. That is, when the system call is executed or the stop request signal (HR) is transmitted, the output of the OR gate 176 is "1".

As described above, when a system call or an interrupt request signal is generated and the CPU busy signal is "0", the output of the first AND gate 172 is "1", and the CPU clock is not output from the second AND gate 174.

Fig. 8(a) is a timing chart showing the relationship of various signals when the interrupt request signal is generated.

In Fig. 8(a), first, at time t0, the operation switching circuit 210 detects an interrupt request signal (INTR) from the outside. The work switching circuit 210 transmits a stop request signal (HR) to the execution control circuit 152 for performing a special operation. The input timing t1 is approximately the same as the detection timing t0. At time t1, the state machine of the CPU 150 is "work in progress" and CBUSY=1. Since HR=1, the OR gate 176 outputs "1", but the CPU 150 does not stop because CBUSY=1. Therefore, even if the input HR=1, the CPU clock (CLK) is temporarily output in synchronization with the original clock (CLK).

After the elapse of time, it changes to CBUSY=0 at time t2. Since HR=1, the first AND gate 172 outputs HC=1, and the CPU clock output from the second AND gate 174 is fixed to zero. On the other hand, the work switching circuit 210 starts the operation switching from the normal work to the special work with the HC being transmitted as an opportunity. The details will be described later, but the time required for the operation switching is required to be several times in the operation clock of the operation control circuit 200. From the time when the HC is transmitted, the operation control circuit 200 stops the transmission stop request signal (HR) on the condition that the operation clock circuit changes the predetermined number of times of the operation control circuit 200 (time t3). Since HR=0, the execution control circuit 152 restarts the CPU clock (CLK). When the CPU 150 restarts the processing, the CPU 150 changes CBUSY from 0 to 1 (time t4). In this way, from the time t2 to the time t3 when the CPU clock is stopped, the work switching from the normal work to the special work is performed.

Further, another processing method may be used to stop the transmission of the HR by the condition that the operation control circuit 200 ends the operation switching, instead of the condition that the operation clock of the operation control circuit 200 changes by a predetermined number of times. Further, the execution control circuit 152 may stop the transmission of the HC on the condition that the HR is stopped. When HC = 0, the execution control circuit 152 restarts the CPU clock (CLK). In this way, the execution of the work can be resumed.

Figure 8(b) is a timing diagram showing the relationship of various signals when the system call is executed.

In FIG. 8(b), first, at time t0, the command decoder 170 detects a system call and changes SC_DETECT from 0 to 1. At time t0, the state machine of the CPU 150 is "work in progress" and CBUSY=1. Since SC_DETECT=1, the OR gate 176 outputs "1", but the CPU 150 does not stop because CBUSY=1. Therefore, even if the output SC_DETECT=1, the CPU clock (CLK) is temporarily output in synchronization with the original clock (CLK0).

After the elapse of time, it changes to CBUSY=0 at time t1. Since SC_DETECT=1 and CBUSY=1, the HC is stopped and the CPU clock is stopped. The operation switching circuit 210 starts the operation switching process when the input HC=0, and outputs the write signal (WT) to the CPU 150. At time t2 when the WT changes from 0 to 1, the stored data is loaded into the processing register 154. The write signal (WT) is changed to WT=0 at the time t3 after the pulse signal has passed at a predetermined time. By the falling detection of WT:1→0, the SC_DETECT latched in the instruction decoder 170 is reset (time t4). At this time, CBUSY changes from 0 to 1. Since CBUSY=1, HC=0, and then start the CPU clock. The operation switching is performed from the time t1 to the time t4 when the CPU clock is stopped.

Further, in another processing method, instead of the falling detection condition of WT:1→0, the operation control circuit 200 ends the operation switching, the transmission of the HR is stopped, and the execution control circuit 152 stops the transmission of the HC. Reset SC_DETECT with HC=0 as a condition. The execution control circuit 152 restarts the CPU clock (CLK) and changes CBUSY from 0 to 1.

In either case, the CPU 150 does not need to recognize the execution of the RUN-work switch during the CPU clock stop. Since the work switching circuit 210 performs the work switching process while the CPU clock is stopped, that is, the CPU 150 freezes (Freeze), the processing of the CPU 150 and the processing of the work control circuit 200 are separated in program control.

Fig. 9 is a schematic diagram for explaining the stop timing of the CPU clock of the pipeline processing.

The CPU 150 executes while executing a plurality of instructions from the memory sequentially to the processing register 154. The instructions of the execution unit of this work can be broken down into the following four stages.

1.F (Fetch: Read): Take the instruction from the memory.

2.D (Decode: Decode): Interpret the instruction.

3.E (Execution: Execution): Execute the instruction.

4.WB (Write Back: Write): Write the execution result to the memory.

When a certain operation is executed from the instruction 1 to the instruction 5 in sequence, after executing the F to WB of the instruction 1, the F of the instruction 2 may be executed. However, for efficient execution, the execution of the instruction 2 is mostly started during the execution of the instruction 1. This type of processing is called pipeline processing. For example, when instruction 1 is executed to stage D, the F phase of instruction 2 is started. When the instruction 1 is executed to the E stage, the D stage of the instruction 2 and the F stage of the instruction 3 are executed. In this way, by increasing the number of instructions executed per unit time, the execution time of each job can be reduced.

Furthermore, each stage can be subdivided into two stages. For example, the F phase is separated into two phases of F1:F2. When instruction 1 is executed to the F2 stage, the F1 phase of instruction 2 is started. When the instruction 1 is executed to the D1 phase, the F2 phase of the instruction 2 and the F1 phase of the instruction 3 are executed. By subdividing the stages, the computing resources of the CPU 150 can be utilized more efficiently. Fig. 9 is a diagram showing the CPU clock stop timing when a system call is made by subdividing each stage into two stages.

In Fig. 9, the command 1 starts processing at the timing of the CPU clock "0". At the timing of the CPU clock "4", the decoding of the command 1 is ended. Assume that instruction 1 is a system call. The instruction decoder 170 changes SC_DETECT from 0 to 1. Next, the condition that SC_DETECT returns from 0 to 0 is that the write signal (WT) from the work switching circuit 210 to the processing register 154 is changed from 1 to 0. Even if SC _- DETECT = 1, CBUSY = 1 because instructions 2 - 5 have been executed or have been executed. Therefore, the second AND gate 174 starts outputting following the CPU clock. However, the execution control circuit 152 temporarily stops the update of the program counter when SC _- DETECT = 1 so that the new instruction is not read. Therefore, after instruction 6, it will not be read from the memory and read.

Although the execution of the sequence command 1 of the CPU clock "8" is completed, since the commands 2 to 5 are being executed, the CPU busy signal is maintained at "1". The execution of the instruction 5 ends when the timing of the CPU clock "12" is reached. At this time, the CPU busy signal is "0". Thereafter, according to the processing of FIG. 8(b), the supply of the CPU clock is stopped. The work switching circuit 210 stores the processing data at the stage until the end of the command 5 in the reservation register 110. According to this stop method, the work switching can be performed without wasting the execution result of the instruction after the execution of the system call. When the work switching is completed, the CPU busy signal is set to "1" again, and the processing of the command decoder 170 is resumed. In this way, the CPU clock is supplied again.

In addition, another processing method, when the system call instruction is executed, sets the CPU busy signal to “0” to stop the supply of the CPU clock. At this time, other instructions executed simultaneously with the system call instruction are stopped during execution. The intermediate processing result of the instruction that has been stopped midway is recorded in the processing register 154 and stored in the reserved register 110. When this work becomes RUN-work next time, the subsequent processing of the instruction that is stopped midway is executed. For example, when an instruction stops in the middle of the end of reading, the instruction or operand read from the memory is stored in the reserved register 110. When the work resumes, the data of the reserved scratchpad 110 is loaded into the processing register 154, and subsequent processing is performed from the decoding step.

FIG. 10 is a circuit diagram showing the relationship between the state memory unit 220 and the operation switching circuit 210.

The state memory unit 220 includes a state register 250 and a timer 252, and the state memory unit 220 maintains the state data of the operation. Further, the timer 252 is a timer that starts when the operation transitions to the READY state or the WAIT state. The elapsed time after the work is moved to the READY state is called "READY elapsed time", and the elapsed time after the work is moved to the WAIT state is called "WAIT elapsed time". The value of the timer 252 is output as a TIM signal at any time. The work switching circuit 210, when a certain work becomes a READY state or a WAIT state when the work switching is performed, the timer 252 that drives the work restarts the time measurement.

The state memory unit 220 is a set of registers shown below.

(A) Work ID register 254: Keep the work ID. The ID signal indicating the job ID is output from the job ID register 254 to the job selection circuit 230 at any time. Hereinafter, the ID signal table outputted from the job ID register 254 of the job A to the job selection circuit 230 is referred to as "ID_A signal". The other signals output from the state memory unit 220 are also the same.

(B) Work Priority Order 256: Maintain work priority. The PR signal indicating the priority of the work is output from the work priority register 256 at any time. "0" is the highest priority, and the larger the value, the lower the job priority.

(C) Working Status Register 258: Indicates the operating status. One of STOP, READY, RUN, WAIT, and IDLE is output as an ST signal at any time. In addition, IDLE is the state before the work is initialized.

(D) Work Start Address Register 260: indicates the TCB address of the work in the memory. The output is an AD signal.

(E) Standby reason register 262: When the operation is in the WAIT state, it indicates the reason for the standby of one of the WAIT cancellation conditions. The standby reason is one of "flag waiting", "event waiting", and "mutual exclusion". The output is a WR signal.

(F) Flag ID register 264: When the job is in the WAIT state for the reason of waiting for the flag, the flag ID of the flag of the waiting object (hereinafter referred to as "standby flag") is held. The output is a SID signal.

(G) Mutually exclusive ID register 265: When the operation is in the WAIT state for the reason of mutual exclusion waiting, the mutual exclusion ID of the mutually exclusive object (hereinafter referred to as "standby mutual exclusion") is held. The output is a MID signal.

(H) Event ID register 266: An event ID of an event (hereinafter referred to as a "standby event") that holds a waiting object when the operation is in the WAIT state for the purpose of event waiting. The output is an EID signal.

(I) Standby flag register 268: When the operation is in the WAIT state for the reason of event waiting, the standby flag type is maintained. The output is the FL signal.

(J) Flag condition register 270: When the job is in the WAIT state for the reason of event waiting, the flag condition is maintained. The output is the FLC signal. The standby flag type and flag conditions will be described later.

(K) Flag Initialization Register 272: Holds data indicating whether or not there is a standby flag type. The output is an FLI signal.

(L) Pause counter 274: The call pause value in the WAIT system is designated as a variable. The pause counter 274 holds the pause value. The work switching circuit 210 periodically reduces the pause value of each of the pause counters 274. The output is a TO signal. Instead of the work switching circuit 210, the pause value is reduced, and the pause counter 274 itself autonomously periodically reduces its own pause value.

The job selection circuit 230 performs selection of an operation based on various signals output from the respective state memory sections 220. The work selection circuit 230 includes the circuit shown below.

(A) Execution selection circuit 232: When the operation is switched, the next RUN-operation is selected. The execution selection circuit 232 constantly selects any one of the operations as the RUN-operation by the state data outputted from the state memory unit 220 at any time. The input signals of the execution selection circuit 232 are four types of ID, ST, PR, and TIM. The output is the work ID of the next RUN-work. The detailed circuit configuration will be described in detail with reference to FIG.

(B) Flag selection circuit 234: Selects a job to be transitioned from the WAIT state to the READY state by releasing the execution of the flag system call. The flag ID of the flag for canceling the flag system call release (hereinafter referred to as "release flag") is input from the work switching circuit 210. The input signals from the state memory unit 220 are six types of ID, ST, W R, PR, SID, and TIM. The output signal is the work ID of the job moving from the WAIT state to the READY state. When the job does not exist, a predetermined value of -1 or the like is output. A more specific circuit configuration will be described in detail with reference to FIG.

(C) Event Selection Circuit 236: Selecting the transition from the WAIT state to the READY state by setting the execution of the event system call. The event ID by setting an event system call setting event (hereinafter referred to as "set event") is input from the work switching circuit 210. The input signals from the state storage unit 220 are six types of ID, ST, WR, EID, FL, and FLC. The output signal is the work ID of the work of transitioning from the WAIT state to the READY state, and the FL and FLC of the job.

(D) Pause detection circuit 238: The operation of suspending the counter 274 during the operation of detecting the WAIT state is 0. The pause detection circuit 238 is driven each time the pause value is updated. The input signals of the pause detecting circuit 238 are three types of ID, ST, and TO. The output signal is the work ID of the job. When the job does not exist, a predetermined value of -1 or the like is output.

(E) Mutual exclusion circuit 240: The operation of transitioning from the WAIT state to the READY state is selected by releasing the execution of the mutex system call. The mutual exclusion ID of the mutual exclusion of the mutual exclusion system call release (hereinafter referred to as "disarming") is input from the work switching circuit 210. The input signals from the state storage unit 220 are six types of ID, ST, WR, PR, SID, and TIM. The output signal is the work ID of the job moving from the WAIT state to the READY state. When the job does not exist, a predetermined value of -1 or the like is output.

(F) Retrieval circuit 242: When the work ID is input from the work switching circuit 210, all state data of the job is output.

Hereinafter, the RUN-operation selection, the flag, the event, the mutual exclusion, and the pause related to the work switching will be described, and in particular, the processing of the work selection circuit 230 will be mainly described and compared with the general technique.

(RUN-work selection)

(1) RUN-work selection of general software RTOS

Figure 11 is a diagram showing the work preparation sequence used in the RUN-operation selection of a general RTOS.

The work preparation sequence is formed in the memory, and the READY-working TCB is connected in series by an index. The priority indicator 280 is a front end address of the TCB that is set in accordance with each work priority order and indicates the work priority order. In the case of the work preparation sequence in FIG. 11, the priority order indicator 280 of the work priority order “0” points to the address of the TCB of the work A, and the priority order indicator 280 of the work priority order “1” points to the address of the TCB of the work B. . The TCB of Work A further points to the address of the TCB of Work D.

The general software RTOS scans this work preparation string while selecting the next RUN-work. At this time, the RTOS performs the following two stages of processing.

A. Migrate RUN-work from RUN to READY.

B. Select the next RUN-work and move the working state of this work from the READY state to RUN.

The processing of the decomposed software RTOS is as follows.

(RUN-work state transition)

Here, the RUN-work is described in Work J.

A1. The RTOS keeps the RUN-working ID in memory. According to this work ID, the address of the TCB of the work J is obtained.

A2. Access the TCB and get the work priority of the job J. Assume that the work priority order is "0".

A3. The priority order indicator 280 corresponding to the work priority order of the job J in the work preparation sequence shown in FIG. 11 is obtained.

A4. TCB indicated by the priority indicator 280 obtained by the detection. The TCB of job A is detected here.

A5. Detect the last TCB along the indicator of the TCB of Work A. In Figure 11, the work F is the last end.

A6. Set the indicator of the TCB of the work F to the address of the TCB pointing to the work J. In this way, the TCB of job J is appended to the work preparation list.

A7. Set the TCB of job J to "READY". Also, the processing data is copied to the register storage area of the TCB.

(READY-work state migration)

B1. The priority order indicator 280 of the RTOS detection work priority "0" indicates which TCB. When the TCB is not found, the priority index 280 of the detection work priority "1" indicates which TCB. Before you find the TCB, you can work at a specific level while reducing your work priorities. In Figure 11, specific work A.

B2. Remove Work A from the work preparation list. Specifically, the priority order indicator 280 of the work priority order "0" is overwritten with the address of the TCB that is not directed to the work A but to the work D. Also, the indicator of job A is set to NULL so as not to point to the address of the work D. In this way, the TCB of job A is removed from the work preparation list.

B3. Set the TCB of job A to "RUN". Moreover, the processing data stored in the scratchpad storage area of the TCB of the work A is loaded into the processing register.

In general software RTOS, work switching is performed by this type of work preparation. That is, the rules for the RTOS to select RUN-work from a plurality of READY-work are as follows.

1. Work for READY - (1st condition).

2. The work with the highest priority (READ 2) for READY-work.

3. When there are a plurality of jobs with the highest work priority order, the work that is the earliest in the READY state (the third condition).

These three conditions are collectively referred to as "RUN work selection conditions". The execution selection circuit 232 of the work processing apparatus 100 implements the work scheduling function of the RTOS by hardware.

(2) Selection of RUN-work of the hardware RTOS of this embodiment

FIG. 12 is a circuit diagram of the execution selection circuit 232.

Here, it is explained that RUN-operation is selected from eight operations of work 0 to work 7. The execution selection circuit 232 includes four first comparison circuits 290 (290a to 290d), two second comparison circuits 292 (292a, 292b), and one third comparison circuit 294. Further, eight determination circuits 296 (296a to 296h) are also included.

The determination circuit 296 receives the ST signal indicating the operation state as an input, and outputs a READY indicating "1" or a CID signal indicating "0" when the READY is not. The determination circuit 296 makes a determination based on the first condition in the RUN operation selection condition. The first comparison circuit 290 inputs the ID, PR, TIM, and CID signal from the decision circuit 296 of two operations.

The first comparison circuit 290a will be described with a focus. The first comparison circuit 290a compares the operation 0 with the operation 1, and selects a preferred operation based on the RUN operation selection condition.

First determination: First, the CID signals output from the determination circuit 296a and the determination circuit 296b are compared. When one of them is "1", that is, when only one of the operations is in the READY state, the first comparison circuit 290a outputs the ID, PR, and TIM of the job. When all are "0", that is, when any of the operations is not in the READY state, the first comparison circuit 290a outputs ID = PR = TIM = NULL. This means that no work has been selected. When all are "1", that is, when any of the jobs is in the READY state, the next second determination is made.

The second determination: comparing the PR signal of the work 0 with the PR signal of the work 1, and selecting the work with a higher priority of work. For example, when the job priority of job 0 is "1" and the job priority of job 1 is "2", the ID, PR, and TIM of job 0 are output. According to the second determination, the work with a high priority of work can be selected as a candidate for the RUN-work. When the work 0 and work 1 work priorities are the same, the next third decision is made.

The third decision: compare the TIM signal of the work 0 with the TIM signal of the work 1, and select the READY to work for a long time. When the READY elapsed time is the same, it is assumed that work 0 is selected. Since it can be determined only by comparing the elapsed time, there is no need to work in tandem TCB order management.

In this way, work 0 and work 1, work 2 and work 3, work 4 and work 5, work 6 and work 7 are respectively compared by the RUN work selection condition. The second comparison circuit 292 further filters the candidates of the RUN-operation by the outputs of the two first comparison circuits 290. The second comparison circuit 292a performs operation selection by the outputs of the first comparison circuit 290a and the first comparison circuit 290b. Therefore, the second comparison circuit 292a outputs the ID, PR, and TIM of the operations most suitable for the RUN operation selection condition from the work 0 to the work 3. The third comparison circuit 294 is also the same, and the third comparison circuit 294 outputs the operation ID of any of the operations 0 to 7.

According to this processing method, the RUN operation selection condition can be realized by hardware. Although the general software RTOS selects the RUN-operation while accessing the work preparation sequence, the execution selection circuit 232 of the present embodiment selects the RUN-operation by the status data output from the state memory unit 220 at any time. The processing of the integrated execution selection circuit 232 is as follows.

(RUN-work state transition)

Here, the RUN-work is described in Work J.

A1. The operation switching circuit 210 sets the operation state register 258 of the job J to "READY".

A2. The work switching circuit 210 sets the timer 252 of the job J to start measuring the READY elapsed time.

In this way, job J migrates from the RUN state to READY. As described above, the processing data is stored in the reservation register 110 of the job J. Since the connection processing register 154 and the bus bar of the reservation register 110 can transfer the processing data in parallel, the processing of A1 and A2 can be performed at one clock time.

(READY-Working state transition)

B1. The work switching circuit 210, when the state transition of the job J ends, the work ID output from the execution selection circuit 232 is specified to be RUN-operated. The work status register 258 of this job is set to "RUN".

In this way, the specific work is moved from the READY state to the RUN. The processing data for a particular job is loaded from the reservation register 110 to the processing register 154. Since the bus bar connecting the reservation register 110 and the processing register 154 is also the number of bits in which the processing data can be transferred in parallel, the processing of B1 can be performed at one clock time.

The software RTOS, when the work is switched, consumes more CPU CPU clock time due to access to the work preparation serial. On the other hand, the operation control circuit 200 of the present embodiment can end the operation switching with a slight time. Since the state memory unit 220 outputs the state data to the execution selection circuit 232 at any time, the execution selection circuit 232 outputs the job ID of any job at any time. Rather than starting the RUN-work selection process after the work switch is generated, the RUN-work selection is performed by executing the output of the selection circuit 232 when the work switch is generated, which also helps to increase the speed of the work switch. Here, although the operation is described as eight, by increasing the number of segments of the comparison circuit, it is possible to perform more work.

(flag processing)

Figure 13 is a diagram showing a list of standby flag numbers used for flag processing of a general RTOS.

Before describing the standby flag sequence, simply explain the flag. In the flag table 212, the flag ID is corresponding to the flag counter. The initial value of the flag counter is set to a finite number. For example, assume that the flag ID = 4 and the flag counter = 3 are set. When any of the jobs performs the standby flag system call with the flag of the flag ID=4 as the standby flag, the work switching circuit 210 reduces the flag counter of the standby flag. The flag counter is reduced each time it is requested to be acquired due to a standby flag system call, and becomes unavailable when it becomes 0. The flag of the flag counter is 0 as the standby flag to perform the operation of the standby flag system call, and the state transitions to the WAIT state.

On the other hand, when any of the operations is performed with the flag of the flag ID=4 as the release flag, the work switching circuit 210 increases the flag counter of the flag table 212. In summary,

When the flag counter>0: The work of executing the standby flag system call is moved from RUN to READY. At this point, reduce the flag counter.

When the flag counter = 0: The work of executing the standby flag system call is migrated from RUN to WAIT. Do not reduce the flag counter.

Performing a Standby Flag System Call In order to migrate from the WAIT state to the READY state, another job must perform a de-flag system call.

(1) General software RTOS flag processing

The general software RTOS manages the TCB in the WAIT state (hereinafter, particularly referred to as "flag waiting work") for the purpose of waiting for the flag by the standby flag string management. The standby flag series is formed in the same memory as the serial shape of the work preparation sequence of FIG. 11 and is formed on the memory. The TCBs whose flags are waiting to work are linked by indicators. The priority indicator 280 points to the front end address of the TCB waiting for the work priority flag.

The general software RTOS, when performing the un-flag system call, scans the standby flag sequence while selecting the flag to be migrated from the WAIT state to the READY state to wait for work. The processing of the RTOS during the standby flag system call and the release of the flag system call is as follows.

(execution of standby flag system call)

Here, the RUN-work is described in Work J.

A1. The RTOS keeps the RUN-working work ID in memory. According to this work ID, the address of the TCB of the work J is obtained.

A2. Detect the flag counter of the standby flag specified by the standby flag system call. In the following, the difference is handled by the value processing of the flag counter.

(When the flag counter > 0)

A3.RTOS reduces the flag counter of the standby flag.

A4. Set the TCB of the job J to "READY". At this time, the TCB of the job J is added to the work preparation sequence.

(When the flag counter = 0)

A3. Access the TCB to get the work priority of the work J. Assume that the work priority order is "0".

A4. Obtain the priority order indicator corresponding to the work priority order of the job J in the standby flag series.

A5. TCB indicated by the priority indicator obtained by the test. Here, the TCB of the work A is detected.

A6. Detect the last TCB along the indicator of the TCB of Work A. In Figure 13, the work F is the last end.

A7. Set the indicator of the TCB of the work F to the address of the TCB pointing to the work J. In this way, the TCB of the job J is appended to the standby flag string.

A8. Set the TCB of the job J to "WAIT". Also, the flag ID of the standby flag is set.

(Remove the execution of the flag system)

B1. The RTOS sequentially searches for the job with the work priority "0" to cancel the flag with the flag as the standby flag. When it does not exist, the work with the work priority order "1" is the search target. According to whether it is detected that the flag with the flag is the standby flag is awaiting work, the processing is divided.

(when detected)

B2. Explain that the detected work is work E. Set the TCB of job E to "READY". Also, the flag ID of the standby flag is cleared.

B3. Remove the TCB of the work E from the standby flag series.

B4. The state of the work of releasing the flag is moved from the RUN state to the READY. Add the TCB of this job to the work preparation list.

(when not detected)

B2. Increase the flag counter.

B3. Move the state of the work of releasing the flag from the RUN state to READY. Add the TCB of this job to the work preparation list.

The general software RTOS performs flag-related processing by managing such a list of standby flag numbers. When the flag is removed, the RTOS selects the READY-work rule from a plurality of WAIT-work as follows.

1. Work for WAIT- (1st condition).

2. For the WAIT-work, the work of releasing the flag as the standby flag (the second condition).

3. When there are a plurality of such jobs, the work with the highest priority of work (the third condition).

4. When there are a plurality of jobs with the highest work priority order, the work that becomes the earliest in the WAIT state time (the fourth condition).

These four conditions are collectively referred to as "flag standby cancellation conditions". The flag selection circuit 234 of the work processing apparatus 100 implements the work scheduling function of the RTOS by hardware.

(2) The flag processing of the hardware RTOS of this embodiment

FIG. 14 is a circuit diagram of the flag selection circuit 234.

Here, eight jobs from work 0 to work 7 are also explained. The flag selection circuit 234 includes four first comparison circuits 300 (300a to 300d), two second comparison circuits 302 (302a, 302b), and one third comparison circuit 304. Further, eight determination circuits 306 (306a to 306h) are also included.

The decision circuit 306 is a circuit that inputs the ST, WR, SID signals from the state memory unit 220 and the signals from the work switching circuit 210 indicating the flag ID. The flag ID entered here is the flag ID of the flag. The determination circuit 306 outputs a CID signal indicating that "1" is displayed when the flag is the flag of the standby flag, and "0" is not used when the flag is the flag of the standby flag. The determination circuit 306 is a circuit that outputs a determination result relating to the first condition and the second condition in the flag standby cancellation condition. The first comparison circuit 300 takes as input two IDs, PR, TIM, and CID signals from the decision circuit 306.

The first comparison circuit 300 is a circuit that performs determination regarding the third condition and the fourth condition in the flag standby cancellation condition. The second comparison circuit 302 is also the same as the third comparison circuit 304. As described above, the second condition and the third condition of the RUN operation selection condition are the same as the third condition and the fourth condition of the flag standby cancellation condition. Each of the comparison circuits that execute the selection circuit 232 is a circuit that compares the operational status data (PR, TIM). On the other hand, each comparison circuit of the flag selection circuit 234 is also a circuit for comparing the operational status data (PR, TIM). Therefore, the first comparison circuit 290 of the selection circuit 232 and the first comparison circuit 300 of the flag selection circuit 234 are internally built with the same logic and can be shared. In addition to the determination by the determination circuit 306 under the first condition and the second condition, each operation is also transmitted to the determination processing of the first comparison circuit 300. Thereafter, any of the job IDs is output from the third comparison circuit 304 by the same determination process as the execution of the selection circuit 232. The processing of the standby flag system call and the unloading system call execution is as follows.

(execution of standby flag system call)

Here, the RUN-work is described in Work J.

A1. The work switching circuit 210 detects the flag counter of the flag designated by the standby flag system call from the flag table 212. Hereinafter, the processing differs depending on the value of the flag counter.

(When the flag counter > 0)

A2. The work switching circuit 210 reduces the flag counter of the flag table 212.

A3. Set the working state register 258 of the job J to "READY". At this time, the work switching circuit 210 sets the RUN-operation timer 252 to start measuring the READY elapsed time.

(When the flag counter = 0)

A2. The operation switching circuit 210 sets the operation state register 258 of the operation J to "WAIT", the standby reason register 262 is set to "flag waiting", and the flag ID register 264 is set to the flag ID of the standby flag. The timer 252 is set to start measuring the WAIT elapsed time.

In this way, the work of executing the standby flag system call is migrated from the RUN state to READY or WAIT.

(Remove the execution of the flag system call)

B1. The work switching circuit 210 inputs the flag ID of the release flag to each determination circuit 306. Each of the determination circuits 306 determines whether or not the first condition and the second condition in the flag release condition are satisfied by using the flag ID as a target. Therefore, each of the first comparison circuits 300 selects an operation based on the third condition and the fourth condition.

(When any one of the determination circuits 306 outputs "1" and the third comparison circuit 304 outputs any one of the job IDs)

B2. The detected work status register 258 is set to "READY", the standby reason register 262 and the flag ID register 264 are cleared, and the READY elapsed time is measured by the timer 252.

B3. The work status register 258 for performing the system call operation is set to "READY", and the measurement of the READY elapsed time is started.

(Each of the determination circuits 306 does not output "1", and the third comparison circuit 304 does not output any of the operation IDs)

B2. The work switching circuit 210 increases the flag counter of the flag table 212.

B3. Migrate the state of the work of performing the system call from the RUN state to READY.

Since the state memory unit 220 outputs the state data to the flag selection circuit 234 at any time, when the work switching circuit 210 inputs the flag ID to the determination circuit 306, the flag selection circuit 234 can immediately perform the selection process.

(mutual exclusion processing)

The mutual exclusion is also the same as the flag, using the synchronization process of the workplace. Mutual exclusion and flag are different in the following points.

1. The flag counter can be set to an integer of 1 or more. In contrast, the mutex flag counter is a special flag of 1 or 0. When the flag counter is 2 or more, the same flag can be obtained for more than 2 jobs. However, when mutually exclusive, only one of the mutually exclusive jobs can be obtained.

2. The work of releasing the flag by canceling the flag system call is not limited to the work of obtaining the flag by calling the standby flag system. In contrast, the mutual exclusion operation can be cancelled by releasing the mutual exclusion system call, and only the mutual exclusion work is obtained by the standby mutual exclusion system call.

When the mutual exclusion is released, the rules for selecting READY-work from a plurality of WAIT-work are as follows.

1. Work for WAIT- (1st condition).

2. For the WAIT-work, the mutual exclusion is mutually exclusive (second condition).

3. When there are a plurality of such jobs, the work with the highest priority of work (the third condition).

4. When there are a plurality of jobs with the highest work priority order, the work that becomes the earliest in the WAIT state time (the fourth condition).

These four conditions are collectively referred to as "mutual exclusion standby cancellation conditions".

Therefore, the processing of the hardware RTOS of the present embodiment when the standby mutual exclusion system calls and releases the mutual exclusion system call is as follows. In the flag table 212, the mutex ID is held in correspondence with the possession status data indicating whether the mutex occupies any one of the jobs. Occupancy status data, when not occupied, sometimes "0", when it is occupied as a work ID that occupies a mutually exclusive work.

(Execution of standby mutual exclusion system call)

Here, the RUN-work is described in Work J.

A1. The work switching circuit 210 detects whether or not the exclusive exclusion of the standby mutual exclusion system call is occupied. In the following, depending on the state of possession of the mutual exclusion, the processing is divided.

(when there is no exclusive exclusion)

A2. The work switching circuit 210 records the work ID of the work for performing the system call as the mutually exclusive possession data.

A3. Set the working state register 258 of the job J to "READY". At this time, the work switching circuit 210 sets the RUN-operation timer 252 to start measuring the READY elapsed time.

(when possessing mutual exclusion)

A2. The operation switching circuit 210 sets the operation state register 258 of the operation J to "WAIT", the standby reason register 262 is set to "mutual exclusion wait", and the exclusive ID register 265 is set to standby mutual exclusion. The mutual exclusion ID, the timer 252 is set, and the WAIT elapsed time is measured.

(Unblocking the execution of the mutual exclusion system call)

B1. The work switching circuit 210 inputs the release flag ID to the exclusive circuit 240 on condition that the work of the system call is released from the mutual exclusion. Similarly to FIG. 14, the exclusive circuit 240 includes a comparison circuit that is connected in multiple stages and a determination circuit that determines whether or not the first condition and the second condition in the mutual exclusion standby cancellation condition are satisfied. This determination circuit is used for exclusive exclusion, and outputs "1" only when both the first condition and the second condition in the mutual exclusion standby release condition are satisfied. In addition, when the work of releasing the mutual exclusion system is performed without the work of releasing the mutual exclusion, the state of the operation is transferred from the RUN state to the READY.

(When any one of the determination circuits outputs "1" and the exclusive circuit 240 outputs any one of the job IDs)

B2. The detected work status register 258 is set to "READY", the standby reason register 262 and the exclusive ID register 265 are cleared, and the READY elapsed time is measured by the timer 252.

B3. The work status register 258 for performing the system call operation is set to "READY", and the measurement of the READY elapsed time is started.

(If either of the decision circuits does not output "1", the mutex circuit 240 does not output any of the job IDs)

B2. The work switching circuit 210 sets the mutual exclusion to the non-occupied state in the flag table 212.

B3. Migrate the state of the work of performing the system call from the RUN state to READY.

(event processing)

The event management of this embodiment will be briefly described. In the event table 214, the event ID is recorded in correspondence with the flag type (hereinafter, referred to as "current flag type"). The flag type is an 8-bit bit type.

Setting an event system call is a system call that changes the current flag type setting, with the event ID and flag type (hereinafter referred to as "set flag type") as parameters. When the set event system call is executed, the current flag type is changed to the logical sum of the set flag type for the event. For example, when the current flag type is "00001100" and the flag type is "00000101", the current flag type becomes "00001101". Hereinafter, each flag type is sequentially referred to as a 0th bit, a 1st bit, ..., a 7th bit from the left.

The standby event system call is a system call for waiting for the current flag type of the standby event to satisfy the predetermined condition, and the event ID, the flag type (hereinafter referred to as "standby flag type"), and the flag condition are parameters. When a standby event system call is performed, it is determined whether the flag condition is established between the current flag type and the standby flag type. The flag condition is a logical sum (OR) or a logical product (AND). When the flag condition is logical product (AND), the WAIT release condition is that all the bits of the standby flag type are "1", and the bit of the current flag type is also "1". When the flag condition is logical OR (OR), the WAIT release condition is any bit of the standby flag type "1", and the bit of the current flag type is "1". For example, when the current flag type is "00001101", the standby flag type is "00000011", and the flag condition is "logical (OR)", since the 6th and 7th bits of the standby flag type are The 7th bit of the current flag type is "1". Therefore, the WAIT release condition of the standby event system call is established at this time. On the other hand, when the flag condition is "AND", since the 6th bit of the current flag type is "0", the WAIT release condition is not established.

(1) Event processing of general software RTOS

Standby Event System Call and Set Event System The general RTOS processing when the call is executed is as follows. In order to manage events, the RTOS keeps the event table in memory. In this event table, not only the event ID, the current flag type, but also the work ID, standby flag type, flag of the work in the WAIT state (hereinafter, referred to as "event waiting work") for this event as a standby event. The conditions are correspondingly maintained.

(execution of standby event system call)

A1. The RTOS reads the current flag type of the event specified by the system call from the event table.

A2. Compare the current flag type with the standby flag type according to the flag condition, and determine whether the WAIT cancellation condition is established.

(When the WAIT cancellation condition is established)

A3. Migrate the working state of the work of performing the system call from the RUN state to READY.

(When the WAIT release condition is not established)

A3. Record the work ID of the work that performs the system call in the event table.

A4. Record the standby flag type in the event table.

A5. Record the flag conditions in the event table.

A6. Migrate the working state of the work of performing the system call from the RUN state to the WAIT.

(Setting the execution of the event system call)

B1. The RTOS records the current flag type, work ID, standby flag type, and flag condition from the event table for the specified event of the system call.

B2. Record the logical sum of the current flag type and the set flag type into a new current flag type.

(When the setting event does not exist, the event waits for work, or even if it exists, according to the standby flag type and the flag condition WAIT release condition is not established)

B3. Migrate the working state of the work of performing the system call from the RUN state to READY.

(When the event is set, the event is waiting for work, and the WAIT release condition is established)

B3. Migrate the working state of the standby event from the WAIT state to READY.

B4. Clear the standby work ID, standby flag type, and flag condition of the event table.

B5. Migrate the working state of the work of performing the system call from the RUN state to READY. And perform the RUN-work selection.

When performing a set event system call, the rules for selecting READY-work from a plurality of WAIT-work are as follows.

1. Work for WAIT- (1st condition).

2. For the WAIT-work, the event is set as the standby event (the second condition).

3. After comparing the standby flag type, the current flag type, and the flag condition, the WAIT release condition is established (the third condition).

These three conditions are collectively referred to as "event standby cancellation conditions".

(2) Event processing of the hardware RTOS of this embodiment

The standby event system call of the work processing apparatus 100 and the process of setting the event system call execution are as follows. In the flag table 212 built in the work processing apparatus 100, the event ID corresponds to the current flag type. Information such as the standby work ID and the standby flag type is stored in the state storage unit 220.

(execution of standby event system call)

A1. The work switching circuit 210 reads the current flag type from the event table 214.

A2. The work switching circuit 210 compares the current flag type with the standby flag type according to the flag condition, and determines whether the WAIT release condition is established.

(When the WAIT cancellation condition is established)

A3. The work status register 258 that performs the system call operation is set to "READY".

(When the WAIT release condition is not established)

A3. The work switching circuit 210 sets the work state register 258 for performing the system call operation to "WAIT", the standby reason register 262 to "event wait", and the event ID register 266 to the standby event. The event ID, the standby flag register 268 is set to the standby flag type, and the flag condition register 270 is set to the flag condition.

(Setting the execution of the event system call)

B1. The work switching circuit 210 reads the current flag type from the event table 214 and inputs the event ID of the set event designated by the system call to the event selection circuit 236.

B2. The work switching circuit 210 accumulates the set flag type logic to the current flag type of the event table 214.

B3. The event selection circuit 236 selects the event in which the event standby condition is established in response to the input event ID. At this time, regardless of the work priority and the WAIT elapsed time, a plurality of jobs can be selected.

(When the job that satisfies the event standby cancellation condition exists)

B4. The event waiting register 258 is set to "READY", and the event ID register 266, the standby flag register 268, and the flag condition register 270 are cleared.

B5. Migrate the working state of the work of performing the system call from the RUN state to READY.

(When the job that satisfies the event standby cancellation condition does not exist)

B4. Migrate the working state of the work of performing the system call from the RUN state to READY.

(suspended processing)

Move to the WAIT state and move to the READY state when the WAIT release condition is established. However, due to some external factors or application bugs, the WAIT release condition is prevented, and the work cannot leave the WAIT state. Therefore, in general, the pause value is set when the job is migrated to the WAIT state. The pause value is periodically decreased. When it is 0, the job can be moved from the WAIT state to the READY state even if the WAIT release condition is not established. That is, it is possible to prevent the work from being stopped for a time above the WAIT state pause value.

(1) Suspend processing of general software RTOS

In the case of a general RTOS composed of software, the TCB in the WAIT state works to set a pause value, which is periodically reduced. The RTOS periodically issues an interrupt to the processing of the CPU, checks all TCBs, and detects a WAIT-work with a pause value of zero. When such a job is detected, the RTOS migrates the working state of the job from the WAIT state to READY.

(2) Suspending processing of the hardware RTOS of this embodiment

On the other hand, in the case of the present embodiment, the work switching circuit 210 periodically reduces the pause value of each of the pause counters 274. The pause value is set as a parameter when the WAIT system call is executed, and the work switching circuit 210 sets the pause value in the pause counter 274 that performs the operation of the system call.

Since the CPU 150 does not intervene in the reduction processing of the pause value, the work switching circuit 210 can update the pause value independently of the job execution processing. Therefore, even when the CPU 150 is performing work, the work control circuit 200 autonomously performs the update of the pause value. Since the status data is input to the pause detecting circuit 238 at any time, the pause detecting circuit 238 can detect that the pause value becomes 0 at substantially the same timing as the pause value update timing. The pause detection circuit 238 outputs the work ID of such work. The work switching circuit 210, when inputting the work ID from the suspension detecting circuit 238, recognizes that a pause has occurred, and transmits HC to stop supplying the CPU clock. The work control circuit 200 migrates the WAIT-work that caused the pause to the READY state and transitions the RUN-work to the READY state. The work switching circuit 210 selects the next work to be performed from among the READY-work. Further, the work switching circuit 210 restarts the timer 252 which generates the pause operation, and measures the READY elapsed time.

According to this processing method, when the work is being executed, that is, when a pause occurs in the CPU clock operation, the CPU 150 can be immediately interrupted to perform the work switching. Further, in the work execution, the work switching circuit 210 can independently perform the update processing of the pause value without the processing capability of the CPU 150.

(Working circuit 210 of the finite state machine)

FIG. 15 is a state transition diagram of the work switching circuit 210.

In the initialization process (A1), all jobs are in the IDLE state. When the initialization process is completed (S10), any one of the jobs becomes the RUN-work and becomes the work execution state (A2). When the interrupt request signal is detected (S12), the special operation becomes RUN-operation and execution interrupt processing (A3). When the interrupt processing ends (S14), the work switching circuit 210 selects RUN-work from the normal operation and shifts to A2.

Further, during the execution of the work (A2), when the system call is executed (S16), the system call processing (A4) is executed. When the work switching, that is, the switching of the RUN-work is not generated (S18), it returns to A2. On the other hand, when the work switching is generated by the system call processing (A4) (S20), the work switching circuit 210 performs the selection of the RUN-operation in accordance with the output of the execution selection circuit 232 (A5). When the work switching ends (S22), the processing state moves to A2.

Finally, the case where only one of the storage circuit 120 and the work control circuit 200 of the main components of the work processing apparatus 100 is constructed will be described.

(Work processing apparatus 100 of the type not loaded with the work control circuit 200)

16 is a circuit diagram of the work processing apparatus 100 in which the work control circuit 200 is not loaded in the work processing apparatus 100 of FIG.

Instead of the unloaded work control circuit 200, the register switching control circuit 322 and the processed data holding unit 320 are added. Since the work control circuit 200 is not loaded, the work scheduling function is implemented by the software RTOS. Therefore, when the work is switched, the RTOS must temporarily obtain the use of the CPU 150. In general, the processed material holding unit 320 holds processing data for the RTOS. When the RTOS acquires the use of the CPU 150, the processing data holding unit 320 replaces the processing data for the RTOS of the processing material holding unit 320 and the processing data for the operation of the special temporary memory 156. Hereinafter, the processing will be described by switching from work A to work B.

A1. When Work A performs a system call, the system call variable and the system call ID are recorded in a portion of the general purpose register 158.

A2. The scratchpad switching control circuit 322 shifts the processing data of the job A to the processing data holding unit 320, and loads the processing data for the RTOS of the processing data holding unit 320 into the processing register 154. At this stage, the RTOS takes the right to use the CPU 150.

A3. The register switching control circuit 322 inputs the write signal to the reserved register 110a, and stores the work A processing data of the processed data holding unit 320 to the reserved register 110.

A4. The RTOS performs processing corresponding to the system call based on the variables and IDs of the system calls recorded in the general purpose register 158. Further, the work status data of the TCB of the work A is set to "READY", and the TCB of the work A is added in the work preparation series.

B1. Next, the RTOS selects RUN-work according to the above RUN work selection condition, where work B is selected.

The B2.RTOS instructs the scratchpad switching control circuit 322 to input the job selection signal of the designated job B to the load selection circuit 112. The processing data is moved from the reservation register 110b to the processing material holding unit 320.

B3. The scratchpad switching control circuit 322 replaces the processing data for the operation B of the processing data holding unit 320 and the processing data for the RTOS of the processing register 154. According to this, the work B obtains the use of the CPU 150.

According to this processing method, the overall circuit size of the work processing apparatus 100 can be reduced as compared with the work processing apparatus 100 of FIG. 5 in which the work control circuit 200 is mounted. Although the RTOS is implemented as a software, the loading and storing of the processing data can be controlled by the signal from the register switching control circuit 322. When the bus bars respectively connected to the processing register 154, the processing data holding unit 320, the load selection circuit 112, and the reserved register 110 are set to the number of bits in which the processing data can be transmitted in parallel, the processing data is stored as compared with TCB and loading processing data from TCB enable high-speed work switching.

(Work processing device 100 of the type not loaded with storage circuit 120)

17 is a circuit diagram of the work processing apparatus 100 in which the storage circuit 120 is not loaded in the work processing apparatus 100 of FIG.

Instead of the unloaded storage circuit 120, an interrupt interface circuit 324 is added. Since the storage circuit 120 is not loaded, the processing data is stored in the TCB of the memory. The loading and storage of processing data is realized by the RTOS of the software library. Therefore, when the work is switched, the RTOS must temporarily obtain the usage rights of the CPU 150. Hereinafter, the processing will be described by switching from work A to work B.

When a work switch is generated by executing a system call, first, the software RTOS stores the processing data of the work A in the TCB of the work A. Next, the processing data for the RTOS is loaded into the processing register 154. The processing method at this time is the same as that described with reference to FIG.

The software RTOS writes the parameters of the system call to the interrupt interface circuit 324. The execution control circuit 152 stops the CPU clock of the CPU 150. Interrupt interface circuit 324 causes work control circuit 200 to perform an operational switch. First, the work switching circuit 210 sets the operation state register 258 of the operation A to READY, and selects the next RUN-operation job B by the output from the operation selection circuit 230. The work switching circuit 210 instructs the interrupt interface circuit 324 to load the processing data of the job B. Here, the interrupt interface circuit 324 causes the execution control circuit 152 to restart the CPU clock. Also, the interrupt interface circuit 324 notifies the software RTOS that the work B has been selected. The software RTOS accesses the TCB of the work B, and loads the processing data of the work B into the processing register 154.

According to this processing method, the overall circuit size of the work processing apparatus 100 can be reduced as compared with the work processing apparatus 100 of FIG. 5 in which the storage circuit 120 is loaded. Although part of the functionality of the RTOS is implemented as software, the job selection process can be implemented by the work control circuit 200.

Compared with the software RTOS described with reference to FIGS. 2 and 3, the work processing apparatus 100 of FIGS. 16 and 17 can harden a part of the functions of the RTOS. As illustrated in FIG. 16, since the storage circuit 120 is present, the storage and loading of the processing data does not require access to the TCB. Therefore, the storage and loading processing of the processing data can be performed by the scratchpad switching control circuit 322. Further, as illustrated in FIG. 17, since the work control circuit 200 is present, the software RTOS can give the work selection function to the work control circuit 200.

As illustrated in FIG. 5, in the case of loading the storage circuit 120 and the work processing device 100 of the work control circuit 200, the RTS work scheduling function can be completely hardened. Since the TCB of the memory is not required to be accessed when the work is switched, the work switching process can be faster. According to the experiment of the present inventors, it was confirmed that the work processing apparatus 100 of the present embodiment can operate at a speed of about 100 times as compared with the general software RTOS described with reference to FIG.

(Modification 1)

When creating a computer program, the "Queue" is a fixed-use algorithm that uses a high frequency. Therefore, the speed of the processing of the queue helps the processing speed of the computer program to increase. However, even in the case of FIFO (First-In First-Out), there may be cases where LIFO (Last-In First-Out) action is required depending on the situation. Or, there may be cases where the FIFO operation is performed based on LIFO. In the first modification, the work processing apparatus 100 of the hardware configuration which can also correspond to the special array of LIFO (hereinafter referred to as "double-input type array algorithm") will be described.

The work processing apparatus 100 of the basic example loads a work scheduling function managed according to a timer. The basic work schedule is "the algorithm that assigns execution to the long-waiting work with priority when the work priorities are the same." Hereinafter, this work schedule is referred to as "fair work schedule".

In Fig. 11, a management method of the work preparation sequence according to the concept of fair work schedule is explained. When the RUN-working work J returns to the READY state, it is connected to the last working F. Since the job A becomes the RUN-work after the job J, the TCB of each job is linked to the priority index 280 of the work priority order "0" in the order of the work D, ..., the work F, and the work J. Work J, at least until the end of the execution of work F will not be given execution. The processing method of fair work scheduling is similar to FIFO, which is the algorithm of the queue. Due to the algorithm of time management, the fair work schedule can be hardware-structured by timer management.

On the other hand, in the software OS, "work schedules in which the execution right is preferentially assigned to the work that temporarily becomes the RUN-work is preferentially used only when the work priorities are the same." Hereinafter, this work schedule is referred to as "re-execution priority work schedule". When the priority work schedule is executed again, when the RUN-work job J returns to the READY state, it is not connected to the last end but is inserted into the front end. Since the job A becomes the RUN-work after the job J, the TCB of each job is linked to the priority index 280 of the work priority order "0" in the order of the job J, the job D, ..., and the work F. Work J, after the end of work A, is given the right to execute again before work D and work F. It is effective to perform a priority work schedule when there is a type of work that is only possible to perform the execution right after being temporarily given the execution right. Perform the prioritized work schedule, including LIFO, which is the stacked algorithm. In the first modification, the priority work scheduling is realized by the hardware configuration of the double-input type array algorithm which is based on the FIFO and can also correspond to the LIFO.

In addition, it is not limited to re-execute the priority work schedule, and the double-input queue algorithm is also useful for general applications. Therefore, the hardware configuration of the dual-input array algorithm is effective in improving the processing speed of various computer programs.

Fig. 18 is a circuit diagram of the work processing apparatus 100 of the first modification.

The work processing apparatus 100 of the first modification also includes a CPU 150, a storage circuit 120, and a work control circuit 200. However, the operation switching circuit 210 of the first modification includes the main circuit 400, the write circuit 402, the array control circuit 404, and the maximum value selection circuit 406. The main circuit 400 is provided with a circuit having substantially the same function as the operation switching circuit 210 of the basic example. Therefore, in the configuration of the work switching circuit 210 of the first modification, the write circuit 402, the queue control circuit 404, and the maximum value selection circuit 406 are added to the main circuit 400 of the work switching circuit 210 as a basic example. All state data of all the operations are outputted from the state memory unit 220 to the work selection circuit 230 at any time, and are output to the maximum value selection circuit 406 or the queue control circuit 404 at any time.

Fig. 19 is a circuit diagram showing a part of the operation control circuit 200 of the first modification.

The basic configuration of the operation control circuit 200 is substantially the same as that of the circuit shown in FIG. The status register 250 corresponding to each operation includes a work ID register 410, a work priority register 412, a queue sequential register 414, and a queue identification register 416. The state register 250 can also include other registers, but here is centered on the register group associated with the dual-input array algorithm.

(A) Work ID register 410: As a type of element ID, a job ID is stored. The same as the job ID register 254 shown in the basic example. The EID_S signal indicating the job ID is output from the job ID register 410 at any time.

(B) Work Priority Order 412: Store Work Priority (PR). It is the same as the work priority register 256 shown in the basic example. The PR_S signal is output at any time.

(C) Array Sequence Register 414: Stores "Order Value (ODR)" indicating the order in which the virtual queues described later are placed. The larger the order value is, the deeper it is placed into the virtual queue, which will be described later in detail. The sequence value is output as an ODR_S signal at any time.

(D) Array Discriminating Register 416: Stores the "Queue ID (QID)" for identifying the virtual queue. It is output as a QID_S signal at any time.

The work priority register 412, the queue sequential register 414, and the queue identification register 416 have a function of managing the queue register of the virtual queue.

The virtual queue is the queue corresponding to the working state. For example, a virtual queue with QID=0 (hereinafter, referred to as "virtual queue (0)") corresponds to the READY state, a virtual queue (1) corresponds to the flag wait state, and a virtual queue (2) corresponds to the mutual exclusion wait state. Alternatively, the virtual queue (1) corresponds to the flag waiting state of the flag ID=0, and the virtual queue (2) corresponds to the flag waiting state of the flag ID=1. The correspondence between the QID and the working state can be arbitrarily set by the software.

When the job A is in the READY state, the QID of the virtual queue corresponding to the READY state is set in the queue identifying buffer 416_A. The operation selection circuit 230 or the array control circuit 404 can determine the operation state of each operation by referring to each of the array identification registers 416. Therefore, the queue identifying buffer 416 has a working state register 258, a standby reason register 262, a flag ID register 264, a mutually exclusive ID register 265, and an event ID register. 266 and other similar functions.

It is important that the virtual queue is not physically present, and is conceptually imagined by the queued sequence register 414 or the array of identification registers 416. For example, when each of the queue identifying buffer 416 and the array sequence register 414 is set as described below,

Work A: QID=0, ODR=0

Work B: QID=0, ODR=1

Work C: QID=0, ODR=2

Work D: QID=1, ODR=0

It means that the work C, B, and A are placed in the virtual queue (0), and the work D is placed in the virtual queue (1). The number and size of the virtual queues can be flexibly changed according to the range of values of QID and ODR.

The job selection circuit 230 selects the operation to be migrated based on the status data output from the status register 250. The main circuit 400 inputs the CND signal to the work selection circuit 230. The CND is a signal indicating a job selection condition, and includes a QID_C indicating a queue ID and a PR_C indicating a job priority. For example, when the virtual queue (0) is to be taken out of the work, the main circuit 400 sets QID_C=0 at the CND. The job selection circuit 230 outputs the job ID of the operation (hereinafter, simply referred to as "takeout operation") of the specified virtual queue (0) to the EID_A1, and transmits the EID_A1_EN. Further, in PR_A1 and ODR_A1, the work priority order and the sequence value of the fetch operation are output. In this manner, the main circuit 400 specifies QID_C = Qn and interrogates the job selection circuit 230, thereby knowing the fetch operation of the virtual queue (Qn). The work selection circuit 230 has a function of selecting a take-out candidate circuit for taking out the work. More details will be described later with reference to FIG.

The CND signal is input from the main circuit 400 to the maximum value selection circuit 406. The maximum value selection circuit 406 outputs the maximum sequence value of the virtual queue (Qn) to the ODR _- A2 and transmits the EID-A2-EN when the QID _- C=Qn is specified by CND. More details will be described later with reference to FIG. 28.

The queue control circuit 404 controls the state transition of each operation by setting the state data of each state register 250. The CMD and EID _- C are input from the main circuit 400 to the array control circuit 404, and in addition, CND (QID-C, PR-C), ODR-A1, ODR-A2, ODR-A2-EN are input. Status data of each state register 250.

CMD is an instruction to operate a virtual queue. The queue ID of the virtual queue of the CMD object, the job ID of the job, and the work priority are specified by QID-C, EID-C, and PR-C, respectively. The command is one of three types of ENQ-TL, ENQ _- TP, and DEQ.

When the input is placed in the instruction ENQ _- TL, the job specified by the EID _- C signal is placed from the last end of the virtual queue. Hereinafter, the placement from the last end of the queue is referred to as "positive insertion". When the fetch instruction DEQ is input, the work is taken out from the front end of the virtual queue. The FIFO queue control is performed by ENQ _- TL and DEQ. When the reverse input command ENQ _- TP is input, the job specified by the EID _- C signal is placed from the front of the virtual queue. Hereinafter, such insertion from the front end of the array is referred to as "reverse insertion". Reverse insertion, not the FIFO, is a special placement method.

When the CMD is input from the main circuit 400, the write circuit 402 transmits the WT, and performs writing of the data output from the queue control circuit 404 to the state register 250. The array control circuit 404, the write circuit 402, the operation selection circuit 230, the maximum value selection circuit 406, and the like have a function of controlling the virtual array processing circuit of the virtual array.

The circuit configuration of the array control circuit 404 will be described in detail with reference to FIG. 20 below.

FIG. 20 is a circuit diagram of the train control circuit 404.

The queue control circuit 404 is an aggregate of a plurality of register value generation circuits 420. Each of the register value generating circuits 420 is the same circuit. The register value generating circuit 420 corresponds to each operation. It can also be said that it corresponds to each state register 250. The register value generating circuit 420_EN corresponds to the operation of the work ID = En (hereinafter, referred to as "operation (En)"). The job ID of this job is fixedly input to the scratchpad value generating circuit 420 as an ELM_ID signal.

ODR_S, QID_S, and PR_S are state data outputted from the state register 250, and represent order values, queue IDs, and work priorities, respectively. The sequence value, the queue ID, and the job priority of the operation (En) are input to the register value generation circuit 420_EN of the corresponding operation (En) as ODR_S_En, QID_S_En, and PR_S_En, respectively. CMD and EID_C are input from the main circuit 400. ODR_A2_EN and ODR_A2 are input from the maximum value selection circuit 406. The ODR_A2 indicating the maximum order value becomes a valid input when the ODR_A2_EN is transmitted. The ODR_A1 is input from the work selection circuit 230. ODR_A1 indicates the job ID of the job taken out. QID_C and PR_C are CND signals input from the main circuit 400, and represent QIDs and PRs as work selection conditions, respectively.

The register value generating circuit 420_EN outputs the order value of the operation (En), the queue ID, and the work priority order as QID_N_En, ODR_N_En, and PR_N_En, respectively. When the write circuit 402 transmits the WT, it writes to the state register 250_En. .

When the write circuit 402 transmits the WT, the QID_N_En, ODR_N_En, and PR_N_En of all the register value generating circuits 420 are written to all of the state registers 250. The scratchpad value generating circuit 420 related to the work affected by the CMD writes new data designated by the algorithm described later to the state register 250. On the other hand, the job-related register value generating circuit 420 which is not affected by the CMD also outputs the same material as the data written to the status register 250 again to perform writing.

In addition, the WT of the register value generating circuit 420 may be directly input to the array control circuit 404 instead of the state registers 250. At this time, among the scratchpad value generating circuits 420 built in the array control circuit 404, only the work related register value generating circuit 420 for the state change due to the CMD writes new data to the state temporarily. The memory 250 is also available.

The specific processing contents of the register value generating circuit 420 will be described later.

Figure 21 is a conceptual diagram showing the relationship between a virtual queue and work.

Here, it is assumed that two virtual queues of the virtual queue (Q0) and the virtual queue (Q1). The virtual queue (Q0) is used to put the priority queue for the work priority PR=0 (hereinafter, the table is referred to as "priority queue (Q0:0)") and is used to put the work priority PR= The priority of the work of 1 (Q0:1) is a set of two priority queues. The virtual queue (Q1) is also the same, assuming that there are essentially four priority queues. For example, the virtual queue (Q0) corresponds to the READY state, and the virtual queue (Q1) corresponds to the WAIT state.

Each virtual queue is placed on the left side of the illustration and the right side is the exit line. Put it into the work from the left side and put it in the reverse direction. Take out the work and keep it from the right side.

In the same figure, four jobs of work ID=E0, E1, E2, and E3 are placed in the virtual queue. Work (E0), work (E2), and work (E3) are placed in the virtual queue (Q0). Among them, since the work (E0) and the work (E3) work in the work priority order PR=0, the priority queue (Q0:0) is placed. Since the work (E2) is a work of PR=1, the priority queue (Q0:1) is placed. The order value ODR of the work (E3), work (E2), and work (E0) placed in the virtual queue (Q0) is 2, 1, and 0. The work (E1) with the work priority PR=0 is placed in the virtual queue (Q1). ODR is "0".

FIG. 22 is a data structure diagram corresponding to the state register 250 of FIG. 21.

The put-in state of each job for the virtual queue shown in FIG. 21 is represented by the setting of the state register 250. In the state shown in Fig. 21, among the operations (E0) to (E7), the virtual queue is placed as the work (E0) to the work (E3). Therefore, the other work queues 412 are set to indicate "Non" that is not placed. The queue discrimination register 416 of the work (E0), the work (E3), and the work (E2) placed in the virtual queue (Q0) is set to "Q0". Further, the queue discrimination register 416 of the operation (E1) in which the virtual queue (Q1) is placed is set to "Q1". By identifying the setting contents of the register 416, it is indicated which work is placed in which virtual queue.

The three sequence (E0), the work (E3), and the work (E2) queue order register 414 are placed in the virtual queue (Q0), and 0, 2, and 1 are set as the ODRs, respectively. In the work of placing the virtual queue (Q1), since only the work (E1) is performed, the order value is set to the minimum "0". The position of each of the virtual queues is represented by the setting contents of the queue sequential register 414.

The work priority order PR of work (E0), work (E1), and work (E3) is "0". Therefore, the job priority register 412 is set to "0" in these jobs. Since the work priority order PR of the work (E2) is "1", "1" is set in the work priority register 412_E2. By the setting of the work priority register 412, it is indicated which priority queue is placed for each job.

According to the above settings, the processing contents of the forward insertion, the reverse insertion, and the removal are described in detail.

(put in the direction)

Fig. 23 is a conceptual diagram when the work (E4) is placed in the virtual queue of Fig. 21 in the forward direction.

Here, a case where the work (E4) of the work priority order PR=0 is placed in the virtual queue (Q1) will be described. The main circuit 400, CMD = ENQ_TL (direct input command), sets EID_C = E4, QID_C = Q1, PR_C = 0. The register value generating circuit 420_E4 built in the queue control circuit 404 outputs QID_N_E4=QID_C=Q1, ODR_N_E4=0, and PR_N_E4=PR_C=0 when EID_C=ELM_ID=E4 is detected. QID_N_E4 is the work order (E4) in which the QID and ODR_N_E4 of the virtual queue are placed, and the order of the PR_N_E4 system (E4) is prioritized. The ODR_N related to the job placed in the forward direction is always set to "0". This is the order value for the most recent placement of the queue.

Not only the scratchpad value generating circuit 420_E4 but also the register value generating circuit 420_En of QID_S_En = QID_C = Q1. The register value generating circuit 420_En outputs ODR_N_En=ODR_S_En+1. Here, the register value generating circuit 420_E1 detects that QID_S_E1=QID_C=Q1, and outputs ODR_N_E1=0+1=1. ODR_N_E1 is the sequence value after the work (E1) is placed. The work that has been placed in the work (E4) is placed in the virtual queue (Q1) of the object, and the order value is affected. After this process, the status data of the work (E4) and work (E1) of the elements of the virtual queue (Q1) are adjusted.

FIG. 24 is a data structure diagram corresponding to the state register 250 of FIG.

In the same figure, the portion to which the bottom line is attached is the portion where the setting contents of the state register 250 shown in Fig. 22 are changed. Since the work (E4) is placed in the forward direction of the virtual queue (Q1), the queue identification register 416_E4 is set to "Q1" by QID_N_E4. The ODR of the work (E4) is "0" and the PR is "0". Since the work (E4) is placed in the forward direction, the ODR of the work (E1) that has been placed in the virtual queue (Q1) is increased from "0" to "1". The state of the virtual queue (Q1) shown in Fig. 23 is expressed by the setting contents of the state register 250 after the change.

Fig. 25 is a conceptual diagram when the work (E5) is placed in the virtual queue of Fig. 23 in the forward direction.

Here, a case where the work (E5) of the work priority order PR=1 is placed in the virtual queue (Q0) will be described. The main circuit 400, CMD=ENQ_TL (direct input instruction), sets EID_C=E5, QID_C=Q0, PR_C=1. The register value generating circuit 420_E5 outputs QID_N_E5=QID_C=Q0, ODR_N_E5=0, and PR_N_E5=PR_C=1.

Not only the scratchpad value generating circuit 420_E5, the register value generating circuit 420_En of QID_C=QID_S_En=Q0, but when detecting QID_C=QID_S_En, the output ODR_N_En=ODR_S_En+1. In this example, it is a register value generating circuit 420 corresponding to the work (E0), the work (E2), and the work (E3). In this way, the status data of the work (E5) and work (E0), work (E2), and work (E3) of the elements of the virtual queue (Q0) are adjusted.

FIG. 26 is a data structure diagram corresponding to the state register 250 of FIG. 25.

In the same figure, the portion to which the bottom line is attached is the portion where the setting contents of the state register 250 shown in Fig. 24 are changed. First, since the work (E5) puts the virtual queue (Q0) in the forward direction, the queue identification register 416_E5 is newly set to "Q0". The ODR of the work (E5) is "0" and the PR is "1". Since the work (E5) is placed in the forward direction, the ODRs of the work (E0), the work (E1), and the work (E3) that have been placed in the virtual queue (Q0) are respectively increased.

Figure 27 is a flow chart showing the processing of the forward insertion.

The main circuit 400 sets the loading condition (S10) related to the work of the forward insertion (hereinafter referred to as "the forward loading operation"). Specifically, CMD=ENQ_TL, and EID_C, QID_C, and PR_C are set. Among the queue control circuit 404, a register value generating circuit 420 corresponding to the forward direction is placed, and the work priority order register 412, the queue sequential register 414, and the queue identification are placed in the forward direction. The registers 416 are set to PR_C, 0, and QID_C, respectively (S12).

When the virtual queue (QID_C) has been put into other work (Yes in S14), the ODR is added to each work that has been placed (S16). In the case of the example shown in Fig. 25, the ODR is added to the work (E0), the work (E2), and the work (E3). The processing of S12, S14, and S16 is performed substantially simultaneously in time.

(reverse insertion)

28 is a circuit diagram of a portion of the maximum value selection circuit 406.

The maximum value selection circuit 406 is a circuit for performing the reverse insertion processing and being driven by the main circuit 400. The maximum value selection circuit 406 outputs the maximum sequence value of the virtual array (Qn) to the ODR_A2 and transmits the ODR_A2_EN when the QID_C=Qn is input as the CND signal. The maximum value selection circuit 406 is the same as the execution selection circuit 232 and the flag selection circuit 234 shown in the basic example, and is constituted by a comparison circuit of a plurality of stages. The maximum value selection circuit 406 includes four first comparison circuits 422 (422a, 422b, etc.), two second comparison circuits 424 (424a, etc.), and one third comparison circuit (not shown). Further, eight decision circuits 426 (426a, 426b, 426c, 426d, etc.) are included.

The description will be focused on the first comparison circuit 422a. The first comparison circuit 422a compares the operation 0 and the operation 1, and when both of them are placed in the virtual queue (Qn), the operation with a large sequence value is selected. The work ID and the sequence value of the work 0 and the work 1 are input to the first comparison circuit 422a as EID_S and ODR_S.

First determination: The determination circuit 426a transmits EID_11A_EN if the operation 0 has been placed in the virtual queue (Qn). The decision circuit 426b transmits EID_11B_EN if the job 1 has been placed in the virtual queue (Qn). The first comparison circuit 422a first refers to the EID_11_EN signals output from the determination circuit 426a and the determination circuit 426b, respectively. When one of them is "1", only one of the jobs has been placed in the virtual queue (Qn). At this time, the first comparison circuit 422a outputs the work ID (EID_S) and the order value (ODR_S) of the work in which the virtual queue (Qn) has been placed as EID_21A and ODR_21A, and transmits EID_21A_EN.

When both the decision circuit 426a and the decision circuit 426b output "0", neither of the two jobs is placed in the virtual queue (Qn). At this time, the transmission of the EID_21A_EN is stopped, and thereafter, neither the operation 0 nor the operation 1 is considered as the second comparison circuit 424a.

When both the determination circuit 426a and the determination circuit 426b output "1", both operations are placed in the virtual queue (Qn), and at this time, the next second determination is executed.

The second determination: comparing the ODR_S_0 of the work 0 with the ODR_S_1 of the work 1, and selecting the work with a large sequence value. The first comparison circuit 422a outputs the operation ID (EID_S) and the sequence value (ODR_S) of the operation having a large sequence value as EID_21A and ODR_21A, respectively, and transmits EID_21A_EN.

The processing contents of the other first comparison circuit 422 are also the same, and the work 0 and the work 1, the work 2 and the work 3, the work 4 and the work 5, the work 6 and the work 7 are respectively compared. The second comparison circuit 424 further selects an operation having a large sequence value from the outputs from the two first comparison circuits 422. The second comparison circuit 424a will be described with a focus. The second comparison circuit 424a compares the output signal of the first comparison circuit 422a with the output signal of the first comparison circuit 422b, and selects an operation having a large sequence value. EID_21, ODR_21, and EID_EN are input from the first comparison circuit 422a and the first comparison circuit 422b to the second comparison circuit 424a, respectively. The second comparison circuit 424 selects the operation in which the order value is the largest among the virtual queues (Qn) among the operations 0 to 3. The other second comparison circuit 424 is also the same. Finally, the maximum sequence value of the virtual queue (Qn) is output as the ODR_A2 signal. When any one of the jobs is selected, the ODR_A2_EN is transmitted, and when any of the jobs does not exist in the virtual queue (Qn), the transmission of the ODR_A2_EN is stopped.

Further, the PR invalid signal for invalidating the priority order determination may be input to the first comparison circuit 422, the second comparison circuit 424, and the third comparison circuit. When the PR invalid signal is transmitted, each comparison circuit selects the priority by removing the priority order from the determination condition. The comparison circuits shown in Fig. 32 are also the same.

Fig. 29 is a conceptual diagram when the work (E6) is reversely placed in the virtual queue of Fig. 25.

Here, a case where the work (E6) of the work priority order PR=1 is reversely placed in the virtual queue (Q0) will be described. First, the main circuit 400 inputs the QID=Q0 of the placed object to the maximum value selection circuit 406 by the QID_C signal. The maximum value selection circuit 406 outputs the maximum sequence value of the virtual matrix (Q0) as the ODR_A2 to the array control circuit 404, and transmits the ODR_A2_EN. As shown in FIG. 25, since the maximum order value of the virtual queue (Q0) is "3" of the operation (E3), ODR_A2 = 3.

Next, the main circuit 400, CMD=ENQ_TP (reverse insertion command), sets EID_C=E6, QID_C=Q0, and PR_C=1. At this time, the scratchpad value generating circuit 420_E6 built in the queue control circuit 404 outputs QID_N_E6=QID_C=Q0, ODR_N_E6=ODR_A2+1=3+1=4, PR_N_E6=PR_C=1 when EID_C=ELM_ID=E6 is detected.

When CMD=ENQ_TP (reverse input instruction), only the register value generation circuit 420 corresponding to the operation specified by EID_C operates. Therefore, only the status data of the work (E6) placed in the reverse direction is changed.

FIG. 30 is a data structure diagram corresponding to the state register 250 of FIG.

In the same figure, the portion to which the bottom line is attached is the portion where the setting contents of the state register 250 shown in Fig. 26 are changed. First, since the work (E6) is placed in the reverse direction of the virtual queue (Q0), the queue identifying buffer 416_E6 is newly set to "Q0". The ODR of the work (E6) is "4" and the PR is "1". Due to the reverse placement of work (E6), the status data of other jobs is not affected.

Figure 31 is a flow chart showing the processing of the reverse insertion.

The main circuit 400 first inputs QID=Qn, which is reversely placed in the virtual queue of the object, to the maximum value selection circuit 406 (S20). The main circuit 400 outputs the maximum order value of the virtual queue (Qn) to the array control circuit 404 (S22). The main circuit 400 sets a loading condition (S24) related to the reverse insertion operation (hereinafter referred to as "reverse insertion operation"). Specifically, CMD=ENQ_TP (reverse insertion command) sets EID_C, QID_C, and PR_C. Among the array control circuits 404, the register value generating circuit 420 corresponding to the reverse loading operation is respectively placed in the work priority order register 412, the queue sequential register 414, and the queue identification temporary storage. The 416 sets PR_C, maximum order value +1, and QID_C (S26). However, when the maximum order value = 0 and the transmission of the ODR_A2_EN is stopped, that is, when the operation is not placed in the virtual queue (Qn), the order sequence register 414 is set to indicate the initial value "0".

As described above, when placed in the forward direction, adjustment of the order value of other work may occur, but such adjustment is not required in the reverse insertion. When observing the virtual queue on the premise of FIFO, the earlier the job is set, the larger the order value is set. That is, the deeper the work order value is, the deeper the virtual queue is placed. Conversely, the smaller the work order value that is set to be placed in the virtual queue, the smaller. At this time, when the forward direction is placed, adjustment of the order value of other work is not required, but adjustment of the order value of other work may occur at the time of reverse insertion.

(take out)

32 is a circuit diagram of a portion of the operation selection circuit 230.

The basic configuration of the work selection circuit 230 is as shown in the basic example of FIG. The job selection circuit 230 of the modified example 1 performs a specific take-out operation when receiving an inquiry from the main circuit 400. Here, a circuit configuration related to the configuration for specifying this take-out operation will be described. When the QID_C=Qn is input as the CND signal, the work selection circuit 230 selects the work from the priority queue with the highest priority in the virtual queue (Qn), and extracts the job ID, work priority, and sequence value respectively. Output to EID_A1, PR_A1, ODR_A1, and transmit EID_A1_EN. The operation selection circuit 230 is the same as the execution selection circuit 232 and the flag selection circuit 234 shown in the basic example, and is constituted by a comparison circuit of a plurality of stages. The operation selection circuit 230 includes four first comparison circuits 430 (430a, 430b, etc.), two second comparison circuits 432 (432a, etc.), and one third comparison circuit (not shown). Further, eight determination circuits 434 (434a, 434b, 434c, 434d, etc.) are included.

The first comparison circuit 430a will be described with a focus. The first comparison circuit 430a compares the operation 0 and the operation 1, and when both are placed in the virtual queue (Qn), the operation with the highest priority is selected. When the work priorities are the same, select a job with a large order value. The work ID, the work priority, and the sequence value of the work 0 and the work 1 are input to the first comparison circuit 430a as EID_S, PR_S, and ODR_S.

First determination: The determination circuit 434a transmits EID_11A_EN if the operation 0 has been placed in the virtual queue (Qn). The decision circuit 434b transmits EID_11B_EN if the job 1 has been placed in the virtual queue (Qn). The first comparison circuit 430a first refers to the EID_11_EN signals output from the determination circuit 434a and the determination circuit 434b, respectively. When one of them is "1", only one of the jobs has been placed in the virtual queue (Qn). At this time, the first comparison circuit 430a outputs the work ID (EID_S), the work priority order (PR_S), and the order value (ODR_S) of the work in which the virtual queue (Qn) has been placed as EID_21A, PR_11A, and ODR_21A, respectively. EID_21A_EN.

When both the decision circuit 434a and the decision circuit 434b output "0", neither of the two jobs are placed in the virtual queue (Qn). At this time, the transmission of the EID_21A_EN is stopped, and thereafter, neither the operation 0 nor the operation 1 is considered as the second comparison circuit 432a.

When both the determination circuit 434a and the determination circuit 434b output "1", both operations are placed in the virtual queue (Qn), and at this time, the next second determination is executed.

The second determination: comparing the PR_S_0 of the work 0 with the PR_S_1 of the work 1, the work priority is selected to be high, that is, the PR_S is small. The first comparison circuit 430a outputs the work ID (EID_S), the work priority order (PR_S), and the order value (ODR_S) of the work having the highest priority of operation as EID_21A, PR_21A, and ODR_21A, and transmits EID_21A_EN. When the work priorities of the two jobs are the same, the next third decision is executed.

The third determination: comparing the ODR_S_0 of the work 0 with the ODR_S_1 of the work 1, and selecting the work with a large sequence value. The first comparison circuit 430a outputs the operation ID (EID_S), the operation priority (PR_S), and the sequence value (ODR_S) of the operation having a large sequence value as EID_21A, PR_21A, and ODR_21A, and transmits EID_21A_EN.

The processing contents of the other first comparison circuit 430 are also the same, and the work 0 and the work 1, the work 2 and the work 3, the work 4 and the work 5, the work 6 and the work 7 are respectively compared. The second comparison circuit 432 further locks the candidates for the fetch operation from the outputs from the two first comparison circuits 430. Finally, the job is selected from the highest priority queue in the virtual queue (Qn). EID_A1_EN is transmitted when any one of the jobs is selected, and EID_A1_EN is stopped when any of the jobs does not exist in the virtual queue (Qn).

Fig. 33 is a conceptual diagram when the work (E3) is taken out from the virtual queue of Fig. 29.

Here, a case where one job is taken out from the virtual queue (Q0) will be described. The main circuit 400 inputs QID _- C = Q0 to the operation selection circuit 230. As shown in FIG. 29, the work (EO) of the order value "1" and the work of the order value "3" are placed in the priority queue (QO: 0) of the highest priority among the virtual queues (Q0). (E3). The work selection circuit 230 selects the work (E3) having a large sequence value as the take-out work. The operation selection circuit 230 sets EID _- A1 = E3, PR _- A1 = 0, ODR - A1 = 3, and transmits EID-A1 - EN.

Next, the main circuit 400, CMD = DEQ (fetch instruction), sets EID _- C = EID - A1 = E3, QID - C = QO. The register value generating circuit 420-E3 outputs QID-N-E3=Non, ODR-N-E3=0 (reset), and PR-N-E3=0 (reset). In this manner, the relationship between the operation (E3) and the virtual queue (Q0) is released in the state register 250.

Not only the register value generating circuit 420-E3, QID-S- En = QID-C = Q0 of register value generating circuit 420 _- En, is detected when the QID _- when C = QID-S-En, is determined ODR -S-En>ODR-A1. Here, the ODR-A1 is the sequence value before the take-out operation (E3) is taken out. If ODR _- S _- En > ODR _- A1, that is, the register value generating circuit 420-En of the operation (En) whose order value is larger than the order value of the fetch operation, the output ODR-N-En=ODR-S- En-1. The example shown in Fig. 29 corresponds to the register value generating circuit 420-E6 of the operation (E6). The register value generating circuit 420-E6 outputs ODR-N-E6=ODR _- S _- E6-1=4-1=3. In this way, the status data of the work (E6) of the elements of the virtual queue (Q0) is adjusted.

FIG. 34 is a data structure diagram corresponding to the state register 250 of FIG.

In the same figure, the portion to which the bottom line is attached is the portion where the setting contents of the state register 250 shown in Fig. 30 are changed. First, since the operation (E3) is taken out from the virtual queue (Q0), "Non" is newly set in the queue identifying buffer 416_E3. Further, "0" is set as the reset value in the queue sequential register 414 and the work priority register 412, respectively. Due to the take-out work (E3), the work (E0), work (E2), work (E5), and work (E6) that were originally placed in the virtual queue (Q0) is larger than the take-out work (E3). Work (E6) has a reduced ODR.

Figure 35 is a flow chart showing the process of taking out.

The main circuit 400 first inputs QID=Qn of the virtual queue of the extracted object to the work selection circuit 230 (S30). The job selection circuit 230 selects the fetch operation from the virtual queue (Qn) (S32). When the main circuit 400 inputs the work ID=En of the fetch operation to the train control circuit 404, the train control circuit 404 clears QID=Qn from the state data of the fetch operation (En) (S34). At this time, the PR and ODR are reset to "0", but they may not be reset.

When the virtual queue (Qn) is also placed in other work (YES in S36), when the work of ODR_S_En>ODR_A1 exists (YES in S38), the order value of the job is reduced (S40). Further, the processing shown from S30 to S40 does not have to be performed in sequence, and may be performed in parallel in time.

In the construction, the work can also be taken out from the virtual queue. For example, in Fig. 33, the necessity of taking out the work (E2) from the center of the virtual queue (Q0) is generated. The work (E2) is a work that can be operated under the condition that a flag A is set to be on. When this flag A is disconnected, the necessity to take out the work (E2) from the virtual queue (Q0) is generated. Alternatively, when the predetermined waiting time for the work (E2) is suspended, the necessity of taking out the work (E2) from the virtual queue (Q0) is also generated. At this time, the QID of the work (E2) is cleared, and the work (E2) can be taken out from the virtual queue (Q0) by reducing the ODR of the work whose sequence value is larger than the order value "2" of the work (E2). In the case of Fig. 33, the ODR of the work (E6) becomes "2". Since the virtual array is formed so as not to be physically restricted by the hardware, the insertion and removal processing can be performed from the middle of the queue.

According to the virtual queue control shown above, a special queue based on FIFO and implementing LIFO action can be realized by hardware logic. If the double-input type array algorithm is configured in a soft body, it is usually a structure in which a series is connected. However, as long as it is processed by the software, it is necessary to generate a payload accompanying the management of the access and address of the memory. On the other hand, the virtual queue control shown in the first modification is realized by hardware logic, so that particularly simple and high-speed control can be realized. In particular, in a time-critical RTOS, the dual-input-type array algorithm is very important for hardware assembly. Next, a mode in which the priority work scheduling is re-executed by the above-described virtual queue control method will be described.

Fig. 36 is a first conceptual diagram showing the relationship between the virtual queue and the work in the re-execution of the priority work schedule.

Here, assume that the virtual queue (Q0) corresponding to the READT state and the two virtual queues of the virtual queue (Q1) corresponding to the WAIT flag state. The virtual queue (Q0) is used to put the priority queue of the work priority PR=0 (hereinafter, the table is referred to as "priority queue (Q0:0)") and is used to put the work priority PR= The priority queue of the work of 1 (Q0:1) is a collection of two priority queues. The virtual queue (Q1) is also the same, assuming that there are essentially four priority queues.

In the same figure, the operation (E1) of PR=1 is the RUN state, and the operation (E0) and the operation (E2) of the same PR=1, and the priority queue (Q0:1) stands by in the READY state. Further, the work of PR=0 (E3) stands by in the priority queue (Q1:0) in the WAIT flag state. Here, it is assumed that the work (E1) is a work that is preferentially executed after execution.

First, the RUN state operation (E1) executes the canceling the flag system call and returns to the READY state (S1). Since the work (E1) is a work that is performed only quickly, the "reverse put" priority queue (Q0: 1). On the other hand, by releasing the flag system call, the WAIT release condition of the work (E3) is established. The work (E3) is taken out from the priority queue (Q1:0), and the priority queue (Q0:0) (S2) is placed in the forward direction. Next, the work selection circuit 230 selects a new RUN-work. The work selection circuit 230 selects the work (E3) having the highest work priority from the work in the READY state as the take-out work. In this way, the operation (E3) of moving from the WAIT state to the READY state is taken out from the priority queue (Q0:0) to become a new RUN-work. According to this work schedule, work with a high priority of work can obtain execution rights faster when the WAIT release condition is established.

Fig. 37 is a second conceptual diagram showing the relationship between the virtual queue and the work in the re-execution of the priority work schedule.

When the work (E3) executes the standby flag system call, the work (E3) is placed in the priority queue (Q1:0) (S4). Next, the work selection circuit 230 selects a new RUN-work. The work selection circuit 230 selects the work with the highest work priority from the work of the READY state, but the work priorities of the work (E0), the work (E2), and the work (E1) are the same. At this time, the job (E1) is taken out from the priority queue (Q0:1) (S5). Work (E1) becomes the new RUN-work. According to this processing method, although it is not set to the work priority order PR=0, it is possible to correspond to an operation (E1) which is only possible to be continuously executed after execution.

The priority work schedule is executed again, and the forward and reverse insertions are respectively used according to the execution status and the work type, thereby controlling the execution order of the work. Therefore, the characteristics of the high-speed processing performance of the work processing apparatus 100 shown in the basic example can be maintained, and a more elaborate work schedule can be realized.

(Modification 2)

Next, as an improvement example 2, the speeding up of the auxiliary processing of the work processing apparatus 100 is demonstrated. In the work processing apparatus 100 of the second modification, the HWF (Hardware Function Module) performs auxiliary processing. Here, HWF is a so-called auxiliary processor and has a function of an auxiliary processing circuit. The auxiliary processing is performed as part of the work, such as floating point arithmetic, DMA transfer, encryption and decryption processing, coordinate calculation of 3D video, and the like, and various processing contents are available.

First, a control method of the general auxiliary processing of the software OS will be described. Next, a control method of the auxiliary processing of the work processing apparatus 100 of the second modification will be described.

Fig. 38 is a view showing a general circuit configuration when the auxiliary processing is executed by the software OS.

The CPU 84 is connected to the HWF 500 via a CPU bus 512 and a memory (not shown). Further, the CPU 84 is connected to the interrupt controller 502. The interrupt controller 502 receives various interrupt signals from the HWF 500 or the like, and transmits an interrupt signal (INTR) to the CPU 84. After receiving the interrupt signal (INTR), the CPU 84 appropriately performs the processing of the corresponding interrupt signal (INTR) by special work.

As shown in FIG. 2, the CPU 84 executes the software OS, and performs general work or special work at its upper level.

The auxiliary processing can be broadly classified into two types of "serial type auxiliary processing" and "parallel type auxiliary processing". In the case of tandem type auxiliary processing, other work cannot be performed during execution. In the case of side-by-side auxiliary processing, other work can be performed side by side even during execution.

Fig. 39 is a timing chart showing a control method of the general serial type auxiliary processing.

First, the job A issues an "interrupt prohibition command" as a system call for occupying the HWF 500 (S100). Here, the target HWF 500 is an FPU (Floating Point Arithmetic Unit). When the "interrupt prohibition command" is issued, the operation switching is stopped until the "interrupt release command" is issued later. Hereinafter, a period in which the interrupt prohibition command is set to the interrupt prohibition until the interrupt disable command is released by the interrupt cancel command is referred to as an "interrupt prohibit period". Even if an interrupt signal (INTR) is input during the interrupt disable period, special work will not start. During the interrupt prohibition period, the work A monopolizes the use of the CPU 84. Therefore, work outside of Work A will not access HWF500, or FPU.

After the software OS setting interrupt is disabled, the job A returns to processing (S102). The job A instructs the HWF 500 to perform the auxiliary processing (S104). In order to suppress the payload accompanying the auxiliary processing control, the work A does not directly write the parameters to the built-in register of the HWF 500 through the software OS, and instructs the execution of the auxiliary processing. The HWF 500 performs the auxiliary processing indicated by the work A.

Work A, while periodically checking the built-in scratchpad of the HWF500 while waiting for the end of the auxiliary processing. When it is detected that the auxiliary processing is completed (S106), the work A issues an interrupt release command (S108). After receiving the interrupt release command, the software OS releases the interrupt prohibition (S110). In this way, the interrupt prohibition period is ended. The software OS performs a work switching, and selects the next work to be executed, such as job B (S112). After that, the execution right is assigned to work B. Work B can also utilize HWF500 in the same way.

It is assumed that when the auxiliary processing is performed by the commissioning HWF 500 of the work A, another work, such as special work overwriting the built-in register of the HWF 500, the work A cannot receive the correct processing result. Therefore, it is necessary to strictly control the possession of the HWF500 in an exclusive manner. However, the HWF500 can be accessed even if the software does not pass through the software OS. For example, at S104, Work A does not directly access the HWF 500 through the software OS. Therefore, in order to enable the software OS to properly manage the possession of the HWF 500, an "interrupt prohibition command" and an "interrupt release command" are issued for the job. The software OS can prevent the work switching from occurring in the auxiliary processing in advance by the interrupt prohibition instruction. In this way, when the work A uses the HWF 500, there is no other work to obtain the use rights of the CPU 84 and interfere with the HWF 500. In the case of FIG. 39, the interrupt prohibition period is reached from the timing of S102 to the timing of S110.

In the case of tandem type auxiliary processing, during the interrupt prohibition period, substantially no other work can be performed. That is, in the tandem type auxiliary processing, other work cannot obtain the use right of the CPU 84 in the auxiliary processing. Therefore, the auxiliary processing that can be ended in a short time like floating-point operation is preferable to the tandem type auxiliary processing.

Fig. 40 is a timing chart showing a control method of the general side-by-side auxiliary processing.

First, the job A issues a WAIT system call such as a standby flag system call or a standby exclusive system call with the use right of the HWF 500 as a waiting condition (S120). Here, the standby mutual system call is described as an object. This standby mutual exclusion system call is issued as an instruction to request possession of the HWF500. Further, the HWF 500 to be used here is a DMAC (DMA controller). When the software OS receives the standby mutual system call, the HWF 500 that operates other than the work A is accessed by mutual exclusion, that is, the DMAC is prohibited from being accessed (S122). In this way, the HWF 500 is temporarily occupied by the work A. The software OS selects the next work to be performed. Here, the description is continued by selecting the work A again. The job A instructs the HWF 500 to perform the auxiliary processing (S124). Here, the work A does not directly perform the auxiliary processing on the HWF 500 through the software OS. The HWF 500 performs the auxiliary processing indicated.

The job A ends the standby processing as a standby condition, and issues a WAIT system call such as a standby event system call (S126). Work A migrates to the WAIT state. The software OS performs a work switch and selects the next RUN-one work, such as work B (S128). Work B is executed in parallel with the auxiliary processing. However, since the HWF500 is occupied by the work A, the work B cannot use the HWF500.

The HWF 500 transmits an interrupt signal (INTR) when the auxiliary processing ends (S130). When the software OS detects the interrupt signal (INTR), it starts a special operation as an interrupt handler (S132). In the special work, first, by setting a call to the SET system such as an event system call, the auxiliary processing ends the event notification (S134). In this way, the standby condition of the standby event system call issued by the work A is established. Again, the execution right moves from the software OS to the special job (S136). After the special work performs the remaining processing, it moves to the STOP state (S138). After the software OS obtains the execution again, the work switching is performed after the special work is completed (S140). Here, work A is selected again.

Since the auxiliary processing of the work A delegation has ended, the work A reads the processing result from the built-in register of the HWF 500 (S142). Or, the work A reads the processing result of the HWF 500 writing to the predetermined area of the memory. Work A issues a disengagement system call (S144). After receiving the call to release the mutual exclusion system, the software OS releases the possession of the work A to the HWF 500 (S146). The software OS performs a work switching and selects the next work to be performed, such as job C (S148). Later, the execution is assigned to work C. Since the possession of the HWF500 has been removed, Work C can also utilize the HWF500 in the same way.

Even in the side-by-side type, the point at which the general work directly accesses the HWF 500 is the same as that of the tandem type. In the parallel type auxiliary processing, although the HWF500 cannot be used for other work in the auxiliary processing, it is possible to obtain the use of the CPU 84 by other work itself. In this way, when Work A uses the HWF500, other work does not interfere with the HWF500.

In the execution of the parallel type auxiliary processing, other work can be performed in parallel as shown in S128. However, due to the system call of S126 or S134, the start of special work, etc., the payload of the tandem type auxiliary processing is larger. Therefore, DMA transfer is more time-consuming auxiliary processing, and parallel-type auxiliary processing is preferred.

In the case of the tandem type auxiliary processing shown in Fig. 39, it is necessary to make a system call 2 times in total. Also, after the auxiliary processing starts, the HWF 500 must also be checked periodically to detect whether the auxiliary processing is finished. Actually, the timing at which the auxiliary processing ends and the timing at which the work detection is completed are liable to cause "deviation", and as a result, the processing efficiency is lowered.

In the case of the parallel type auxiliary processing shown in Fig. 40, the work A must issue a system call a total of four times. Further, when the auxiliary processing ends, in order to notify the work A that the auxiliary processing is completed, it is necessary to start a special work.

In general, a system call takes 500 to 1000 CPU cycles per call. Auxiliary processing is a high-frequency processing, and it is an important design issue to be able to suppress such a payload to an RTOS with strict time requirements.

Fig. 41 is a view showing the circuit configuration when the auxiliary processing control shown in Figs. 38 to 40 is realized by the work processing apparatus 100 of the basic example.

As explained in the basic example, the work processing apparatus 100 mainly includes a CPU 150, a storage circuit 120, and a work control circuit 200. In the case of the general circuit configuration shown in Fig. 38, the CPU 84 executes both the software OS and the operation. On the other hand, in the work processing apparatus 100, the CPU 150 performs an operation, and the function of the OS is realized by the storage circuit 120 and the operation control circuit 200. By externalizing the functions of the OS from the CPU 150, the overall processing efficiency is greatly improved as explained in the basic example. In FIG. 41, the CPU 150 is also connected to the HWF 500 through the CPU bus 512.

In the case of the hardware OS of the work processing apparatus 100, the system call execution, particularly the work switching, is speeded up by the software OS. In order to perform a system call, the work processing device 100 requires only 12 clock cycles. Therefore, even with the circuit configuration of Fig. 41, by the work processing apparatus 100 executing the auxiliary processing control shown in Figs. 39 and 40, the payload associated with the auxiliary processing can be greatly suppressed.

In the second modification, by re-examining the relationship between the work processing apparatus 100 and the HWF 500, particularly the CPU 150 and the HWF 500, the auxiliary processing can be further speeded up.

Fig. 42 is a circuit configuration diagram showing the relationship between the work processing apparatus 100 and the HWF 500 of the second modification.

In the same figure, a plurality of HWFs 500 (HWF500_0, ..., HWF 500_k: k are arbitrary natural numbers) are connected to the work control circuit 200 without being connected to the CPU 150. Each HWF500 is a dedicated circuit designed corresponding to different auxiliary processes. For example, HWF500_0 is FPU, and HWF500_1 is DMAC. Each HWF 500 is intentionally identified by a HWFID ranging from 0 to k.

With the work performed by the CPU 150, the HWF 500 is caused to perform auxiliary processing through the work control circuit 200. Work can not directly access the HWF500's built-in scratchpad. In the second modification, the work control circuit 200 manages each of the HWFs 500 in unary.

Fig. 43 is a circuit diagram showing the relationship between the state memory unit 220 and the operation switching circuit 210 of the second modification.

The HWF standby selection circuit 510 is added to the operation selection circuit 230 of the second modification. Further, a plurality of HWFs 500 are newly connected to the work switching circuit 210.

The basic configuration of the operation control circuit 200 is substantially the same as that of the basic example shown in FIG. In addition to the work ID register 254, the work priority register 256, and the like, the state register 250 corresponding to each work adds the HWFID register 504, the queue sequential register 506, and the queue identification. 508.

(A) HWFID register 504: When a certain work instruction performs auxiliary processing, the HWFID of the HWF 500 of the execution subject of the auxiliary processing is set. The HWFID is output as a HID_S signal at any time. In the second modification, in the HWFID register 504, the HWFID is written only in the parallel type auxiliary processing.

(B) Array Sequence Register 506: Stores the "Order Value (ODR)" indicating the order in which the work of the virtual queue is placed. The larger the order value, the deeper it is placed into the virtual queue. The sequence value is output as an ODR_S signal at any time. The order value ODR of the second modification is the same as the "order value ODR" described in the first modification.

(C) Alignment Discriminator 508: Stores the "Queue ID (QID)" for identifying the virtual queue. It is output as a QID_S signal at any time. The queue ID is the same as the "queue ID (QID)" described in the first modification.

The virtual queue is the same as the virtual queue shown in the modified example 1, and is a virtual queue corresponding to the working state. In this way, the correspondence between the queue ID and the working state does not need to be fixed to the hardware configuration. The work selection circuit 230 can determine the operating state of each job by referring to each of the queues identifying the register 508.

The job selection circuit 230 selects the operation to be migrated based on the state data output from the state register 250. After the work switching circuit 210 inputs the HWFID to the HWF standby selection circuit 510, the HWF standby selection circuit 510 outputs the operation ID of the operation set by the HWFID register 504 corresponding to the HWFID. That is, the "work waiting for the processing of the designated HWF 500 to end" is notified to the work switching circuit 210. If the designated HWF 500 is not being processed, that is, if no processing is requested for any of the jobs, the HWF standby selection circuit 510 outputs a predetermined value such as "-1".

Each HWF 500 is directly connected to the work switching circuit 210. Each of the HWFs 500 is connected to the six types of signal lines shown below by the work switching circuit 210. Hereinafter, i is an arbitrary number from 0 to k.

a. HFi_REQ: The work switching circuit 210 transmits HFi_REQ when the HWF 500_i is instructed to perform auxiliary processing.

b.HFi_ARG[m-1:0]: Transfer the parameters of the auxiliary processing. There are various HFi_ARG[m-1:0] sizes depending on the content of the auxiliary processing, and there are also various parameters. When HFi_REQ is transmitted, HFi_ARG[m-1:0] is written to the built-in register of HWF500_i.

c. HFi_RQACK: After transmitting HFi_REQ and writing HFi_ARG[m-1:0], HWF500_i starts auxiliary processing. When the auxiliary processing starts, the HWF500_i transmits HFi_RQACK. With HFi_RQACK, the work switching circuit 210 recognizes that the auxiliary processing is started.

d.HFi_CMPLT: After the auxiliary processing ends, the HWF500_i transfers the HFi_CMPLT in addition to writing the result of the auxiliary processing to the built-in scratchpad. The work switching circuit 210 recognizes the end of the auxiliary processing by HFi_CMPLT.

e.HFi_RSLT[m-1:0]: indicates the return value of the result of the auxiliary processing. There are various HFi_RSLT[m-1:0] sizes depending on the content of the auxiliary processing, and there are also various numbers of return values. The returned value of the write to the HWF500_i's built-in scratchpad. The work switching circuit 210 obtains the return value of HFi_RSLT[m-1:0] after transmitting HFi_CMPLT.

f. HFi_CMPACK: The work switching circuit 210 transmits HFi_CMPACK after obtaining the return value. With HFi_CMPACK, HWF500_i recognizes that the return value is normally obtained.

Fig. 44 is a timing chart showing a control method of the tandem type auxiliary processing in the second modification.

In the work processing apparatus 100 of the second modification, a "HWF call" is added in addition to the nine system calls described in the basic example. "HWF Call" is a system call that indicates the execution of auxiliary processing.

First, the job A issues an HWF call with the type of the auxiliary processing to be the object (S100). For example, the type of the auxiliary processing is specified by a floating point arithmetic instruction, a DMA transfer instruction, an encryption processing instruction, or the like. The work switching circuit 210 selects the target HWF 500 based on the auxiliary processing designated as the parameter, and specifies the HWFID. In addition, it is also possible to issue a HWF call by using the HWFID itself as a parameter. Here, the description is made with a specific HWFID=i. As a parameter of the HWF call, the argument of the auxiliary processing may also be specified. Such parameters are written to the predetermined general purpose register 158 of the CPU 150. The work switching circuit 210 reads the parameters from the general purpose register 158 when receiving the HWF call.

The work switching circuit 210 instructs the HWF 500_i to execute the auxiliary processing (S102). The work switching circuit 210 stops the CPU 150 by the HC signal. Therefore, the work A is forced to stop in the RUN state.

In S102, instead of operating A to access the HWF 500 as shown in FIG. 39, the work switching circuit 210 instructs the HWF 500 to perform auxiliary processing. Specifically, the argument is set in HFi_ARG[m-1:0] and HFi_REQ is transmitted. HWF500_i, start auxiliary processing, and transmit HFi_RQACK. Since the CPU 150 has stopped, the work A in the auxiliary processing is not executed. Of course, other work that includes special work will not be performed.

After the auxiliary processing ends, the HWF500_i outputs a return value to HFi_RSLT[m-1:0] and transmits HFi_CMPLT. The work switching circuit 210 receives the return value and transmits HFi_CMPACK (S104). The work switching circuit 210 records the return value in the processing register 92. The work switching circuit 210 stops the transmission stop request signal (HR) and restarts the execution of the work A (S106).

In the case of the tandem type auxiliary processing of the second modification, only one system call is required. Further, since the CPU 150 is stopped during the execution of the auxiliary processing, power consumption can be suppressed. Further, the work A for requesting the auxiliary processing does not need to inquire the HWF 500 about the end timing of the auxiliary processing, and therefore the timing at which the auxiliary processing ends is almost not deviated from the timing at which the work processing apparatus 100 detects the end of the auxiliary processing.

In the second modification, the work cannot directly access the HWF 500, but the work switching circuit 210 accesses the HWF 500. Therefore, by interrupting the disable instruction or the interrupt release instruction, the operation does not need to be used to control the interrupt during the OS control interrupt. After receiving the HWF call, the work processing device 100 controls the CPU clock to stop and restarts only by the stop request signal (HR). The work processing device 100 writes the result of the auxiliary processing to the processing register 92 as a return value. Therefore, the work A for requesting the auxiliary processing is in a state in which the result of the auxiliary processing is obtained when the execution is restarted. Since the work A does not need to inquire about the result of the auxiliary processing of the HWF 500 or the work control circuit 200, not only the processing efficiency is improved, but also the code of the work A can be simplified.

Fig. 45 is a timing chart showing a control method of the parallel type auxiliary processing in the second modification.

Here, it is assumed that the target HWF 500 is an FPU (Floating Point Arithmetic Unit). Further, the HWFID of the HWF 500 corresponding to the FPU is "i". First, the job A issues a standby mutual exclusion system call with the use right of the FPU as a waiting condition (S120). The ownership of each HWF is managed by mutual exclusion and slogan. There is no need for exclusive control of HWF such as mutual exclusion. For example, as long as it is a HWF that uses only a specific job, no exclusive control is required.

If it is not set that the HWF 500_i is occupied by the exclusive exclusion, the work processing apparatus 100 prohibits access to the HWF 500_i by the work other than the exclusive setting work A (S122).

In this way, the HWF500_i is temporarily occupied by the work A. Next, the job A issues a HWF call (S124). Work A migrates from the RUN state to the WAIT state. The condition for the WAIT release is the end of the auxiliary processing of the HWF500_i. The work switching circuit 210 sets HWFID=i to the HWFID register 504 of the work A when receiving the HWF call.

In the second modification, the work return circuit A is not executed as shown in FIG. 40, and the work switching circuit 210 itself instructs the HWF 500 to start the auxiliary process (S126). HWF500_i starts the auxiliary processing. The work switching circuit 210 selects the next RUN-work, such as work B (S128). Work B is executed side by side with auxiliary processing. However, Work B cannot use HWF500_i. The reason is that Work A ensures the possession of HWF500_i by mutual exclusion.

After the auxiliary processing ends, the HWF500_i outputs a return value to HFi_RSLT[m-1:0] and transmits HFi_CMPLT. The work switching circuit 210 receives the return value and transmits HFi_CMPACK (S130). Work B transitions from the RUN state to the READY state. Specifically, the work processing apparatus 100 transmits a stop request signal (HR) to request to stop the CPU clock, waits for the stop end signal (HC) transmission, and retains the processing data of the work B to the reserved register. Work B is reversely placed into a virtual queue corresponding to the READY state. The work switching circuit 210 inputs HWFID=i to the HWF standby selection circuit 510, and acquires the work ID of the job A that has requested the auxiliary processing for the HWF 500_i. Next, the return value indicating the result of the auxiliary processing is recorded in the reserved register corresponding to the work A, and the operation A is set in the READY state. Here, as shown in the first modification, the operation A may be reversely placed in the virtual queue corresponding to the READY state. The work switching circuit 210 selects the next work to be performed, such as job A (S132). Later, the execution rights are assigned to Work A. When the auxiliary processing ends, the work A that has requested the auxiliary processing must be selected. According to this work switching rule, the efficiency of the work of entrusted auxiliary processing can be improved. The work A releases the possession of the HWF 500_i by releasing the mutual exclusion system call (S134). The work processing apparatus 100 performs the work switching again, and selects the next work to be executed, for example, the work B performed at S128 to S130 (S136). In the future, the execution will be assigned to work B. By releasing the possession of HWF500_i, Work B can also utilize HWF500_i in the same way.

In the side-by-side auxiliary processing shown in Fig. 40, a total of 4 system calls are issued. On the other hand, the system call count of the parallel type auxiliary processing in the second modification is three times of "standby exclusive system call", "disarming system call", and "HWF call". Therefore, according to the modified example 2, the payload accompanying the system call can be controlled once. Also, no special work is required. By writing the return value to the reserved register, the job A does not need to interrogate the HWF 500 or the work control circuit 200 for the result of the auxiliary processing.

In the past, various methods have been tried in order to execute a software including an OS at high speed. Most of the above attempts are for the increase in the number of CPU clocks, the increase in the memory capacity or the scratchpad capacity, or the parallel processing of a plurality of CPUs, and the large-scale and complicated processing such as network distributed processing.

On the other hand, in the case of the work processing apparatus 100 shown in this embodiment, by adding the storage circuit 120 or the work control circuit 200 to the existing CPU 150, the processing efficiency is greatly improved. In the case of the software OS, in order to perform processing such as job switching that is to be performed, it is necessary to perform additional processing such as management of the TCB or the work preparation serial. On the other hand, in the work processing apparatus 100, since the work switching, the state management of the operation, and the interrupt processing are realized by the hardware logic, the payload unique to the software can be released. Therefore, it is possible to configure an ideal system that suppresses power consumption and cost increase and achieves high speed.

Further, according to the auxiliary processing control shown in the second modification, the payload associated with the auxiliary processing can be greatly suppressed. Conventionally, in order to perform auxiliary processing such as DMA transfer at a high speed, a program that directly operates the built-in register of the HWF 500 without the software OS is provided. However, when such a program generates a defect, the overall operation of the system becomes unstable.

In the work processing apparatus 100 of the second modification, the operation of directly operating the HWF 500 becomes a physically impossible configuration. By the high-speed processing performance of the work processing apparatus 100 itself and the reduction in the number of system calls, the high-speed auxiliary processing can be realized even if the work is configured to request the auxiliary processing by the work processing apparatus 100. According to the work processing apparatus 100 of the second modification, the auxiliary processing control can be made safe and high speed.

Hereinabove, the present invention has been described based on the embodiments. The embodiment is exemplified, and various modifications can be made to the combination of these components and the respective processing steps, and such modifications are also within the scope of the present invention, which should be understood by those having ordinary knowledge in the technical field to which the present invention pertains. thing.

The functions to be achieved by the respective constituent elements described in the claims are achieved by the single elements of the functional blocks shown in the present embodiment, or the linkages thereof, which are also understood by those having ordinary knowledge in the technical field to which the present invention pertains. Things.

Further, various determination circuits will be described with reference to FIGS. 12, 14, 28, and 32. These determination circuits select the operation to be compared and selected by the comparison circuit group.

For example, the execution selection circuit 232 of FIG. 12 is used to select a RUN-operating circuit, but can be a RUN-worker for READY-operation. Therefore, the decision circuit 296 of Fig. 12 outputs the CID signal "1" on the condition that the READY-operation is performed. The comparison circuit group that executes the selection circuit 232 selects the next RUN-operation based on the work priority order PR or the READY elapsed time TIM only for the operation of the CID signal "1", that is, the READY state operation.

The flag selection circuit 234 of FIG. 14 is used to select a circuit to be cancelled when the flag is released. To cancel the work of waiting for the flag, it is to work in the WAIT state to release the flag as the standby flag. Therefore, the decision circuit 306 of Fig. 14 outputs the CID signal "1" on the condition that the WAIT-operation in which the flag is the standby flag is released. The comparison circuit group of the flag selection circuit 234 is selected only for the operation of the CID signal "1", that is, "the WAIT-operation with the flag is the standby flag", and the time preference TIM is selected according to the work priority order PR or WAIT. Unlock the work waiting for the flag.

When the logic of the decision circuit is changed, the execution selection circuit 232 and the flag selection circuit 234 can share the comparison circuit group. The same is true for mutual exclusion or events. The same applies to the maximum value selection circuit 406 of FIG. 28 and the operation selection circuit 230 of FIG. In this way, if the logic of the determination circuit is added or changed, various selection logics can be constructed in the form of a shared comparison circuit group. Hereinafter, two examples will be described.

1. Rotate the system call

This system call is used to change the system call of the work queue of the virtual queue corresponding to the READY state, that is, the READY-Work Order Value (ODR). For example, as shown in FIG. 29, the virtual queue (Q0) corresponding to the READY state is placed in the order of work (E6), work (E3), work (E2), work (E0), and work (E5). 5 jobs. Here, the RUN-work specifies the work priority PR = 1 to issue a rotating system call.

Next, the operation (E6) at the front end of the priority queue (Q0:1) corresponding to PR=1 is temporarily taken out, and is placed in the forward direction after the operation (E5). That is, the order value (ODR) of the work (E6) becomes "0", and the order values of other jobs are also adjusted.

The system call is rotated, and the priority queue (Q0:1) corresponding to the work priority sequence PR=1 specified by the parameter is changed, and the order of the front end operation is changed to the last system call. According to the rotating system call, the order value (ODR) of the work placed in the virtual queue (Q0) can be externally controlled.

The determination circuit for realizing the call of the rotating system may output "1" as a condition in the "READY state and the operation of the designated work priority PR". Next, by comparing the circuit group, the operation in which the output signal of the determination circuit becomes "1" is selected, and the operation of maximizing the order value (ODR) is selected as the object of rotation.

2. Functional expansion of the virtual queue corresponding to the WAIT state

Generally, when a certain flag is released, in the virtual queue (Qn) corresponding to the flag waiting, the work to be obtained is selected from the highest priority queue (Qn: Pn) of the work priority PR. However, regardless of the work priority PR, the special flag to be obtained (hereinafter, referred to as "special flag") may be set by the work having the largest order value (ODR).

In order to construct a special flag, the "WAIT state, and the work of releasing the flag as the standby flag" is prepared to output a determination circuit of "1". The decision circuit 434 of FIG. 32 is a circuit for inputting and outputting an EID_EN signal by QID_S and CND. This change is assumed to be a decision circuit that outputs a work priority order PR_S in addition to QID_S and CND, and outputs EID_EN and PR_A. This determination circuit outputs a predetermined value x to PR_A when the special flag is released, and directly outputs PR_S as PR_A when the normal flag is released. Therefore, in the comparison circuit group, when the special flag is released, all the work priority sequences PR of the respective jobs are recognized as the predetermined value x. As a result, the comparison circuit group is independent of the duty priority PR of each job, and the operation in which the order value (ODR) is the smallest is selected from the operation in which the output signal of the determination circuit becomes "1".

Various aspects of the inventions obtained from the above embodiments and modifications, and those disclosed in the claims are exemplified as follows. The following invention can be recognized from Modification 1.

C1. A virtual queue processing circuit, comprising:

a queue control circuit that controls the insertion and removal of a plurality of elements identified by the element ID for a virtual array of plural types identified by the queue ID;

A plurality of queue registers are set corresponding to each element, so that the queue ID of the virtual queue placed in the object is maintained corresponding to the order value indicating the placement order;

The queue control circuit,

When the forward input instruction of the specified element ID and the queue ID is input, the end register of the specified element ID is set to indicate the end of the virtual queue corresponding to the specified queue ID. The end sequence value and the specified queue ID;

When the reverse placement instruction of the specified element ID and the queue ID is input, the array register of the specified element ID is set to indicate the position of the virtual queue corresponding to the specified queue ID. The front end order value and the specified queue ID;

When the fetch instruction of the specified queue ID is input, the queue ID is cleared from the queue register storing the specified queue ID and the front end order value, and the element is taken as the object to be extracted, according to each queue register The setting information is used to manage the virtual queue of the plural type.

C2. The virtual queue processing circuit of C1, wherein the queue control circuit adjusts the storage of the specified queue ID by the instruction when inputting one of the forward insertion instruction or the reverse insertion instruction The order value of the queue.

C3. The virtual queue processing circuit according to C1, further comprising: a take-out candidate circuit that refers to the queue ID and the sequence value outputted in parallel from the plurality of queue registers when the queue ID is specified , output the feature ID corresponding to the queue ID and the front end order value;

The queue control circuit clears the queue ID from the queue register of the element ID output from the extraction candidate circuit.

C4. The virtual queue processing circuit of C1, wherein the virtual queue is further defined as a set of a plurality of priority queues according to the priority of the extraction;

The queue register also stores the priority for the particular priority queue;

The queue control circuit,

When a specified element ID, a queue ID, and a priority direction input instruction are input, the priority of the specified element ID is also set to the priority of the specified register;

When the reverse input instruction of the specified element ID, the queue ID, and the priority is input, the priority of the designated element ID is also set to the priority of the specified register;

When the fetch instruction of the specified queue ID is input, the specified queue ID is stored, and the highest priority is set therefrom, and the queue register with the sequence value closest to the front end is set to clear the queue ID.

C5. The virtual queue processing circuit according to C4, wherein the queue control circuit adjusts a sequence value of another queue register storing the specified queue ID when the instruction for specifying the queue ID is input.

C6. The virtual queue processing circuit according to C5, further comprising: a take-out candidate circuit that, when specifying the queue ID, outputs the queue ID and the sequence value in parallel from the plurality of queue registers And priority, storing the specified queue ID, outputting the element ID corresponding to the highest priority set therein, and storing the sequence register value closest to the front end;

The queue control circuit clears the queue ID from the queue register of the element ID output from the extraction candidate circuit.

C7. A work processing apparatus, comprising:

Processing the scratchpad to temporarily store the data used to perform the work;

Executing a control circuit, loading instructions and operands from the memory into the processing register, and performing operations according to the instructions and the operation elements of the processing register;

a plurality of state registers, which are temporary registers for storing state data of the work schedule, corresponding to a plurality of jobs respectively;

The work switching circuit controls a plurality of types of virtual queues corresponding to the execution state of the work, and controls the execution and execution of the plurality of jobs by the work ID to manage the execution state of the work;

The work selection circuit takes as input the state data output from the plurality of state buffers in parallel, and selects the work by the predetermined selection condition;

The state register holds the queue ID of the virtual queue corresponding to the execution state of the work and the sequence value indicating the order in which the virtual queue is placed, as part of the status data;

The execution control circuit transmits the predetermined system call signal to the work switching circuit when the first operation in execution executes the predetermined system call instruction;

The job selection circuit stores a column ID of the preparation queue corresponding to the virtual queue corresponding to the READY state and a state register indicating the previous order value of the front end position of the preparation queue, corresponding to the specific state The second job selection of the scratchpad is selected as the next execution object;

The work switching circuit clears the queue ID from the state register of the second operation when receiving the system call signal, and sets the state register of the first job to correspond to another execution state different from the RUN state. The queue ID and the sequence value of the virtual queue are such that the data of the processing register is retained in the predetermined memory area, and the data retained in the memory area related to the second job is loaded into the processing register.

C8. The work processing apparatus according to C7, wherein the operation switching circuit sets the preparation queue to the state register of the first operation when the first operation is moved to the READY state to be the other execution state. Queue ID and front end order value.

(C9) The work processing device according to C7, wherein the operation selection circuit stores the standby queue as a virtual queue of a WAIT state in a standby state corresponding to a WAIT release condition, and when the WAIT release condition is satisfied, storing the The status register of the queue ID and the front end sequence value of the standby queue selects the work;

The operation switching circuit sets a queue ID of the preparation queue and a terminal sequence value indicating the end of the preparation queue for the selected state register.

C10. The work processing apparatus of C7, wherein the state register stores a work priority as part of the status data;

The work selection circuit sets the highest priority of work among the plurality of jobs for setting the queue ID when the switch is to be performed, and sets the order closest to the front end among the ones. The work selection of the value is the execution object.

According to the present invention, execution control of a more efficient work can be realized in multiplex processing.

84. . . CPU

86. . . Universal register

88. . . Special register

90. . . Execution control circuit

92. . . Processing register

94. . . Operation circuit

96. . . Input selector

98. . . Output selector

100. . . Work processing device

110. . . Reserved register

110_0~110_n. . . Reserved register

112. . . Load selection circuit

120. . . Storage circuit

150. . . CPU

152. . . Execution control circuit

154. . . Processing register

156. . . Special register

158. . . Universal register

160. . . Operation circuit

162. . . Input selector

164. . . Output selector

170. . . Instruction decoder

172. . . 1st gate

174. . . 2nd gate

176. . . OR gate

200. . . Work control circuit

210. . . Working switching circuit

212. . . Flag table

214. . . Event table

220. . . State memory

220_0~220_n. . . State memory

230. . . Work selection circuit

232. . . Execution selection circuit

234. . . Flag selection circuit

236. . . Event selection circuit

238. . . Pause detection circuit

240. . . Mutual exclusion circuit

242. . . Detection circuit

250,250_0,250_1,250_2,250_3. . . Status register

252. . . Timer

254. . . Job ID register

256. . . Work priority register

258. . . Working state register

260. . . Work start address register

262. . . Standby reason register

264. . . Flag ID register

265. . . Mutually exclusive ID register

266. . . Event ID register

268. . . Standby flag register

270. . . Flag condition register

272. . . Flag initialization register

274. . . Pause counter

280. . . Priority indicator

290a～290d. . . First comparison circuit

292a, 292b. . . Second comparison circuit

294. . . Third comparison circuit

296a～296h. . . Decision circuit

300a ~ 300d. . . First comparison circuit

302a, 302b. . . Second comparison circuit

304. . . Third comparison circuit

306a～306h. . . Decision circuit

320. . . Processing data retention department

322. . . Register switch control circuit

324. . . Interrupt interface circuit

400. . . The main circuit

402. . . Write circuit

404. . . Queue control circuit

406. . . Maximum selection circuit

410_0,410_1,410_2,410_3. . . Job ID register

412_0,412_1,412_2,412_3. . . Work priority register

414_0,414_1,414_2,414_3. . . Queue sequential register

416_0,416_1,416_2,416_3. . .辨 column discriminator

420_0,420_1. . . Register value generating circuit

422a, 422b. . . First comparison circuit

424a. . . Second comparison circuit

426a～426d. . . Decision circuit

430a, 430b. . . First comparison circuit

432a. . . Second comparison circuit

434a～434d. . . Decision circuit

500. . . HWF

500_0～500_k. . . HWF

502. . . Interrupt controller

504. . . HWFID register

506. . . Queue sequential register

508. . .辨 column discriminator

510. . . HWF standby selection circuit

512. . . CPU bus

Figure 1 is a state transition diagram of the work.

Figure 2 is a conceptual diagram of a general RTOS.

Figure 3 is a circuit diagram of a general CPU executed by the software RTOS.

Fig. 4 is a conceptual diagram of the RTOS of the present embodiment.

Fig. 5 is a circuit diagram of the work processing apparatus of the embodiment.

Figure 6 is a circuit diagram of the CPU of Figure 5.

Fig. 7 is a circuit diagram showing a configuration in which the execution control circuit 152 stops the CPU clock.

Fig. 8(a) is a timing chart showing the relationship of various signals when the interrupt request signal is generated.

Figure 8(b) is a timing diagram showing the relationship of various signals when the system call is executed.

Fig. 9 is a schematic diagram for explaining the stop timing of the CPU clock of the pipeline processing.

Fig. 10 is a circuit diagram showing the relationship between the state memory unit and the operation switching circuit.

Figure 11 is a diagram showing the work preparation sequence used in the RUN-operation selection of a general RTOS.

Figure 12 is a circuit diagram of a selection circuit.

Figure 13 is a diagram showing a list of standby flag numbers used for flag processing of a general RTOS.

Figure 14 is a circuit diagram of the flag selection circuit.

Figure 15 is a state transition diagram of the work switching circuit.

Figure 16 is a circuit diagram of a work processing apparatus in which the work control circuit is not loaded in the work processing apparatus of Figure 5.

Figure 17 is a circuit diagram of a work processing apparatus in which the storage circuit is not loaded in the work processing apparatus of Figure 5.

Fig. 18 is a circuit diagram of the work processing apparatus of the first modification.

Fig. 19 is a circuit diagram showing a part of the operation control circuit of the first modification.

Figure 20 is a circuit diagram of a train control circuit.

Figure 21 is a conceptual diagram showing the relationship between a virtual queue and work.

Figure 22 is a data structure diagram corresponding to the state register of Figure 21.

Fig. 23 is a conceptual diagram when the work (E4) is placed in the virtual queue of Fig. 21 in the forward direction.

Figure 24 is a data structure diagram corresponding to the state register of Figure 23.

Fig. 25 is a conceptual diagram when the work (E5) is placed in the virtual queue of Fig. 23 in the forward direction.

Figure 26 is a data structure diagram corresponding to the state register of Figure 25.

Figure 27 is a flow chart showing the processing of the forward insertion.

Figure 28 is a circuit diagram of a portion of the maximum selection circuit.

Fig. 29 is a conceptual diagram when the work (E6) is reversely placed in the virtual queue of Fig. 25.

Figure 30 is a data structure diagram corresponding to the state register of Figure 29.

Figure 31 is a flow chart showing the processing of the reverse insertion.

Figure 32 is a circuit diagram of a portion of the operational selection circuit.

Fig. 33 is a conceptual diagram when the work (E3) is taken out from the virtual queue of Fig. 29.

Figure 34 is a data structure diagram corresponding to the state register of Figure 33.

Figure 35 is a flow chart showing the process of taking out.

Fig. 36 is a first conceptual diagram showing the relationship between the virtual queue and the work in the re-execution of the priority work schedule.

Fig. 37 is a second conceptual diagram showing the relationship between the virtual queue and the work in the re-execution of the priority work schedule.

Fig. 38 is a view showing a general circuit configuration when the auxiliary processing is executed by the software OS.

Fig. 39 is a timing chart showing a control method of the general serial type auxiliary processing.

Fig. 40 is a timing chart showing a control method of the general side-by-side auxiliary processing.

Fig. 41 is a view showing the circuit configuration when the auxiliary processing control shown in Figs. 38 to 40 is realized by the work processing apparatus of the basic example.

Fig. 42 is a circuit configuration diagram showing the relationship between the work processing apparatus of the modified example 2 and the HWF.

Fig. 43 is a circuit diagram showing the relationship between the state memory unit and the operation switching circuit of the second modification.

Fig. 44 is a timing chart showing a control method of the tandem type auxiliary processing in the second modification.

Fig. 45 is a timing chart showing a control method of the parallel type auxiliary processing in the second modification.

100. . . Work processing device

120. . . Storage circuit

150. . . CPU

200. . . Work control circuit

500_0～500_k. . . HWF

502. . . Interrupt controller

512. . . CPU bus

Claims (11)

A work processing apparatus includes: a processing register that temporarily stores data for performing work; and an execution control circuit that loads instructions and operands from a memory to the processing register, according to the processing The instruction and the operation unit of the memory perform the work; the state register is used to store the state data indicating the execution state of the work; the work switching circuit is used to control the execution state of the work; and the work selection circuit is based on the state data. Selecting the work by the predetermined selection condition; and assisting the processing circuit to perform the predetermined auxiliary processing as part of the work; the execution control circuit transmitting the predetermined system call signal to the work switching circuit when executing the predetermined system call instruction; Selecting a circuit to select a job to be the next execution target from among the operations indicating that the standby state is the READY state of the executable state; the work switching circuit selects the output of the work selection circuit when receiving the system call signal to become the next Execute the work of the object, and retain the data of the processing register in the established memory. a domain, and changing the status data of the work in execution from the RUN state setting indicating the execution of the job to another state, and loading the data retained in the memory area into the processing register for the selected work, and The status data of the operation is changed from the READY state to the RUN state, thereby switching to the operation of the execution target; and the execution control circuit executes the auxiliary processing instruction as the system call instruction for executing the predetermined auxiliary processing when the execution is performed. The work switching circuit instructs the auxiliary processing circuit to perform the auxiliary processing. The work processing apparatus of claim 1, wherein the work switching circuit sets, when instructing execution of the auxiliary processing, a possession of a first operation of the auxiliary processing command to the auxiliary processing circuit, and The second operation different from the first operation is set to the RUN state, and the possession of the first operation is canceled on the condition that the auxiliary processing circuit receives the auxiliary end signal indicating the completion of the auxiliary processing. The work processing apparatus of claim 2, wherein the execution control circuit executes a system call instruction that occupies the occupation request circuit as the first operation request; the work switching circuit performs the auxiliary processing The circuit does not set the possession of other work as a condition, and the possession of the first operation to the auxiliary processing circuit is set; and in the execution control circuit, the first operation is performed on the condition that the possession of the auxiliary processing circuit is successfully obtained. This auxiliary processing instruction. The work processing device according to claim 1, wherein the work switching circuit records the predetermined data in a state register that executes the first operation of the auxiliary processing command to set the first job to wait for the auxiliary processing. End of the processing of the circuit; the work selection circuit notifying the work switching circuit of the operation of recording the predetermined data in the state register; the work switching circuit receiving an auxiliary end signal indicating the end of the auxiliary processing from the auxiliary processing circuit At this time, the first operation notified from the operation selection circuit is set to the RUN state again. The work processing device of claim 1, wherein the auxiliary processing circuit respectively sets a plurality of auxiliary processing, wherein the execution control circuit performs the work in the execution with the type of the auxiliary processing as a parameter. When the processing command is assisted, the operation switching circuit selects an auxiliary processing circuit corresponding to the auxiliary processing designated as the parameter from among the plurality of auxiliary processing circuits, and instructs the selected auxiliary processing circuit to execute the auxiliary processing. The work processing apparatus of claim 5, wherein the work switching circuit selects the auxiliary processing circuit to record an auxiliary processing circuit for identifying the selected auxiliary processing circuit for the state register that performs the operation of the auxiliary processing instruction Processing the ID to set the execution of the auxiliary processing instruction to wait for the processing of the selected auxiliary processing circuit to end, and receiving the auxiliary processing of the selection when receiving the auxiliary end signal indicating the completion of the auxiliary processing from the selected auxiliary processing circuit The auxiliary processing ID of the circuit notifies the work selection circuit; the work selection circuit selects an operation of recording the auxiliary processing ID of the notification; and the work switching circuit sets the selected operation to the RUN state again when receiving the auxiliary end signal . The working processing device of claim 1, further comprising: a plurality of reserved registers corresponding to the plurality of jobs for retaining the data of the processing register; the working switching circuit receiving the predetermined system When the signal is called, the data of the processing register is retained in the reserved register corresponding to the work in execution, and the data of the reserved register corresponding to the work of the next execution object is loaded to This handles the scratchpad. The work processing device of claim 7, wherein the work switching circuit receives, from the auxiliary processing circuit, an auxiliary end signal indicating that the auxiliary processing is completed, and obtains, from the auxiliary processing circuit, a result indicating the auxiliary processing. The return value is written to the reserved register that performs the work of the auxiliary processing instruction to notify the execution of the auxiliary processing instruction of the result of the auxiliary processing. The work processing device according to claim 1, wherein the work switching circuit receives the auxiliary end signal indicating that the auxiliary processing is completed from the auxiliary processing circuit, and sets the operation of executing the auxiliary processing command to the RUN state again. . The work processing device according to claim 1, wherein the work switching circuit selects the work to be the next execution target and sets the condition to be received from the auxiliary processing circuit to receive the auxiliary end signal indicating the completion of the auxiliary processing. The RUN state is to prevent the execution of the auxiliary processing from performing the operation on the execution control circuit. The work processing device of claim 10, wherein the work switching circuit transmits a stop request signal to the execution control circuit when the auxiliary processing command is executed; the execution control circuit stops after receiving the stop request signal Providing an execution clock for executing an execution program of the work to temporarily stop execution of the operation of the auxiliary processing instruction; the work switching circuit transmitting a stop release signal to the execution control circuit when receiving the auxiliary end signal After receiving the stop release signal, the execution control circuit releases the supply stop of the execution clock to restart the execution of the operation of the auxiliary processing command.