TW200937294A - Task processor - Google Patents

Abstract

A task processor (100) comprises a CPU (150), a saving circuit (120) and a task control circuit (200). A plurality of HWF (500) are connected to the task control circuit. When a task requests an auxiliary processing, the task processor (100) instructs HWF (500) of execution of the auxiliary processing and changes setting of the task in the middle of execution from a RUN state to a different state. When the auxiliary processing is completed, a task becoming a next execution object is selected and it is set to the RUN state.

Description

200937294 VI. Description of the Invention: [Technical Field] The present invention relates to a function of an OS (Operating System), particularly regarding control of a co-processor. [Prior Art] ❹ ❹ It is not limited to general-purpose devices such as personal computers, and special-purpose devices such as mobile phones are required to have a high level of functionality. In particular, 〇s (hereinafter, this type of OS is referred to as "multiplex 〇s") that can perform a plurality of operations with one CPU (Central Processing Unit) is mounted on most electronic devices. The multiplexer divides the processing time of the CPU into unit time (time slice: Time Slice), and sequentially allocates time segments to a plurality of jobs. Each work can only use cpu when it is allocated by os. Perform a job at each time segment. Since the time segment is very short for the user = therefore multiple work feelings seem to be performed simultaneously. According to this processing method, 'Work A becomes the input standby state and is temporarily not needed.】 When the ability is executed, the right is executed for another job... The two functions are used: The second is 1, the so-called execution right and the use right of the cpu Synonymous. Work Switcher::Time = The '(4) action is called "work switching". The fragments of the Yuyu are produced at the time of passage or at the time. Multiplexes (^ in the ^ 仃 仃 疋 疋 疋 疋 疋 之 上下文 上下文 上下文 上下文 上下文 上下文 上下文 上下文 上下文 上下文 上下文

Control Block). The upper and lower diameter blocks: the data of the Task register and the data stored in the CPU during the work execution. τ ^ is the area that is guaranteed by the memory in order to protect the information inherent to the work of 200937294. The multiplexer stores the context information of the work of the execution order in the TCB, selects the next job with the execution right, reads the context information from the TCB of the guard, and loads it into the CPU register. In this way, each job gradually performs its own processing in units of time segments. Although the multiplexed OS has the advantage of being able to perform a plurality of tasks efficiently, it also has the disadvantage of newly generating contextual information storage and loading overhead. However, in general, multiplexed OS has many advantages even if the work is accompanied by a payload. Patent Document 1: Japanese Patent Laid-Open No. 272-480 Patent Document 2: Japanese Laid-Open Patent Publication No. 2001-75820 Patent Document 3: Japanese Laid-Open Patent Publication No. 2343〇2 Patent Literature 4: Japanese Patent Laid-Open No. 2000-1 〇 〇 〇 〇 专利 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "The implementation of a real-time operating system for embedded control system", Tokyo Metropolitan Industrial Technology Research Institute, Sakamoto, August 4, 2005, p. 55-58 [Invention] In recent years, strict requirements The instant 〇s (hereinafter referred to as "RTOS (Real-Time Operating System)"), which has been processed in a certain period of time, has been popularized with the embedded system (Embedded System). In this time requirement 200937294 Strict RTOS, the payload of the work switching may have a big impact on the overall performance of the system. In addition, there are many cases where one part of the work is handed over to an auxiliary processor other than the CPU. The auxiliary processor includes, for example, a DMAC (Direct Memory Access Controller), a floating-point arithmetic unit (FPU), a cryptographic processing unit, and the like. Hereinafter, an operation in which the auxiliary processor executes processing is referred to as "auxiliary processing". The auxiliary processor is a dedicated circuit that is specifically assisted in processing. Therefore, in general, the same auxiliary processing is performed by the CPU to assist the processor to execute faster. However, a unique payload is generated when utilizing multiple hardware resources of the CPU and the auxiliary processor. In order to further improve the performance of rtqs, an important issue is to suppress the payload accompanying the auxiliary processing. The present inventors have completed the present invention in light of the above-mentioned points of view, and a main object thereof is to provide a technique for performing control work with higher efficiency in multiplex processing, and in particular to provide a technique for speeding up auxiliary processing. The form of the invention is a work processing device. This device has the processing to temporarily cry, 斩 斩 Μ Μ 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂Data: state temporary state, control work bar-shaped work switching circuit, root selection circuit m according to the selection condition selection work selection circuit 〗 〖Auxiliary processing auxiliary processing circuit. The execution control circuit 'notifies the work switching circuit when the system call instruction is executed. The work selection circuit, READY (preparation) state is not selected (the machine is selected as the execution target among the executable states. 5 200937294 Work switching circuit, work selection by system call instruction execution = output selection becomes the next execution The work of the object will be processed in the established memory area, and the work of setting the change execution, the data, and the selection work will remain in the memory area; material: _ state, thereby taking the second When the processing is assisted, the 'work switching circuit refers to the data of the processing unit Γ 入 into the processing register' can be an instruction (i_ue-and-transport)

Fand), * instructions with operands, or simple data such as program counters and heaps. According to this processing method, due to the state of the / management work, the work-reservoir circuit, the power-changing H is changed according to the work selection. When the work requires the execution of auxiliary processing, the worker and the circuit receive the execution request in a one-dimensional manner, and the second=help T is available. At this time, the auxiliary processing control is managed by the circuit capable = * million. Record =:=== combination, or method, valid. The present invention has been implemented as a form of the present invention: according to the present invention, the implementation of the multiplex processing can achieve higher efficiency. [Embodiment] First, the electronic circuit will be implemented by the electronic circuit. Work Schedule Job 200937294 Processing Device 1 〇〇 Description is "Basic Example". Then, the hardware configuration of the "double-input array algorithm (described later)" which is preferable to the work processing apparatus 1 of the second modification is described as "modified example i". Finally, the work processing apparatus 1 which speeds up the auxiliary processing is described as "Modification 2". The following description of the "Example J" indicates in principle "Basic Example", "Modified Example 1" and "Modified Example 2". (Basic Example) The work processing apparatus 100 shown in this embodiment realizes a work scheduling function of a plurality of work s with an electronic circuit. Before explaining the work processing apparatus 1 in detail, first, the state transition of the operation will be described with reference to Fig. 1 . Here, although the state transition of the general multiplex OS operation is described, the state transition of the operation of the work processing apparatus 100 is also the same. Also, the system call executed by the work processing apparatus 1 is also outlined. The processing method of the work processing apparatus 100 of this embodiment will be described in detail with reference to Figs. 4 to 1 in addition to the design concept of a general multiplexed OS as shown in Figs. 2 and 3. Furthermore, the related processing of the Semaphore, the Mutex, and the event is appropriately compared with the general technique to describe the features of the processing apparatus 100. (State transition of work) Figure 1 is a state transition diagram of the work. In multiplex processing, each job has a "state". Each work moves between a plurality of states, and becomes a state-of-state. The state transition mechanism is the "system call execution" and "interrupt request signal detection". System squeak is a special instruction in the instructions for each job execution. The interrupt request signal is a signal generated when the predetermined data is received from the peripheral device 7 200937294 by pressing the keyboard, tapping the mouse, receiving communication data, and the like. Of course, the time segment assigned to each job will also result in a state transition. The work is broadly divided into two categories: "general work" and "special work." The general work is the usual work performed by the system call. The special work is the work performed by the detection of the interrupt request signal. This is called the Interrupt Handler. First, after explaining the various operating states, various system call commands will be described. (1) STOP status (stop status) Indicates that the operation is stopped. Both normal work and special work may become STOP. Hereinafter, the work in the STOP state is referred to as "STOP - Work". 1 — 1. GENERAL OPERATION When the job execution indicates a system call for another job start (hereinafter referred to as “start system call”), the general operation in the STOP state transitions to the READY state described later. 1 — 2. Special work Special work is usually in STOP. When the interrupt request signal is detected by the operation switching circuit 210 described later, the special operation shifts from the STOP state to the RUN state described later. At this time, the work that was originally in the RUN state migrates to the READY state. (2) RUN status (execution status)

Indicates that work is in progress. That is, a state in which a time segment is allocated to a job and a usage right of the CPU is obtained. Both normal work and special work may become RUN. Hereinafter, the work in the RUN state is referred to as "RUN 200937294 One Work". In a plurality of jobs, there is only one job that can be in the RUN state, and two jobs cannot be in the RUN state at the same time. 2 _ 1. General operation The general work in the RUN state, when the scheduled system call is executed, transitions from the RUN state to the READY state or the WAIT state described later. The general work in the RUN state also migrates to the READY state after the time segment has elapsed. In either case, the general work in the READY state transitions to the RUN state to replace the normal work that was originally in the RUN state. When the © interrupt request signal is detected, RUN—work transitions to the READY state. At this time, the special work in the STOP state transitions to the RUN state. When RUN-work performs a system call that ends itself (hereinafter referred to as "end system call"), RUN-work transitions to the STOP state. 2 — 2. Special operation The special operation of transitioning from the STOP state to the RUN state due to the interrupt request signal returns to the STOP state when the processing itself is finished. The state in which special work may become is only the STOP state and the RUN state. ® (3) READY state (executable state) Indicates that the job is in an executable state. The work in the READY state can be migrated to the RUN state when the execution right is given by the 0S. Only general work may become a READY state. Hereinafter, the work in the READY state is referred to as "READY - Work". READY—Work transition 9 200937294 to RUN state when the general operation in the RUN state transitions to a state other than the RUN state by the execution of the system call, or when the special operation completion in the RUN state is processed to the STOP state. Normal work only moves from the READY state to the RUN state. When there are multiple jobs in the READY state, according to the work priority of a part of the context information, one of the READYs - the work migrates to the RUN state. When the work priority is the same as READY—there are multiple jobs, the work that was moved to the READY state at the earliest moves to the RUN state. (4) WAIT state (standby state) Indicates that the operation is waiting for the state in which the predetermined WAIT release condition is established. When the WAIT release condition is established, the work in the WAIT state transitions to the READY state. Only general work may become a WAIT state. Hereinafter, 工作 The work in the WAIT state is called "WAIT - Work". The WAIT release conditions will be described in detail later. In summary, each job can only use the CPU to perform its own processing when it is in the RUN state. RTOS—Manages the status of multiple jobs while properly switching RUN—work. According to this, it is possible to realize a processing form in which the CPU executes any work at any time. (System Call) Next, the system call is explained. System calls are roughly classified into three types: "Startup System", ® "WAIT System", and "SET System". (1) Start system system call System call related to the migration between STOP status and READY status. 1 — 1. Start system call

RUN—Working Work A causes another general work B to start a system call. At this time, the general work B in the STOP state transitions to the READY state. 10 200937294 1 — 2. End system call, perform the work of this system call, end its own processing, and move from the surrounding state to the STOP state. Ending a beer can also be an instruction to end another job for a job. (2) WAIT system system calls the system call related to the migration between the R u N state and the W Α ί τ state. 2 — 1. Waiting for a few flag system calls Ask for a system call with a flag (described later). 2 — 2 • Several Mutually Exclusive System Calls Request a system call that is mutually exclusive (described later). 2 — 3. Waiting for several events The system calls a system call that is awaiting an event (described later). In addition to the event ID, the flag type (described later) and the flag condition (described later) are also executed as variables. In either case, various WAIT release conditions are set by the WAIT system system call. When the WAIT system system call is executed, the system call is performed to the READY state when the release condition is established. On the other hand, when the WAIT release condition is not established, the UN job migrates to the WAIT state in which the WAIT release condition is established. (3) The SET system system calls the system call related to the migration between the WAIT state and the READY state. The execution of the SET system system call is the establishment of the WAIT release condition. 3 — 1. Release the system call of the flag. 11 200937294 3 — 2. Unring Mutual System Calls Unbind system calls. 3—3. Setting the Event System Call Set the system call for the current flag type (described later) of the event. 3 — 4. Clear Flag System Call A system call used to clear the current flag type to zero. In the present embodiment, a description will be given of the total of nine types of system calls, but it is of course possible to construct various system calls. (General RTOS design idea) Figure 2 is a conceptual diagram of a general RTOS. This RTOS is a multiplexed OS. The general RTOS is implemented as software. The case where the RUN_work is switched from the work A to the work B will be described as an example. Since the work A occupies the CPU, the RTOS issues an interrupt to the CPU and takes back the CPU usage right from the work A. In addition, the context information of Work A is stored in the TCB. The RTOS selects Work B as the next RUN-work, loading context information from the TCB of Work B to the scratchpad of the CPU. At the end of the load, the RTOS hands over the use of the CPU to Work B. In this way, the RTOS temporarily acquires the usage rights of the CPU, and performs the work switching from work A to work B. The implementation of special work is also the same. At this time, the RUN-work context information is stored in the TCB, and the CPU usage right is given to the special work to achieve the work switching. Since the RTOS is implemented as software, it is necessary to use the CPU in order to perform its own processing. That is, the RTOS competes with the use of the CPU in its work. In the following, the RTOS implemented by software in this way is called 200937294 "Software RTOSj. rP=t: Circuit diagram of the general CPU executed by the RTOS. Execution control circuit 2 system access and execution of instructions, etc. The context of the register 92, and the operation of the various types of bedding, such as the 捍 £ fa 及 及 及 及 运算 。 。 。 。 。 。 。 。 。 。 86 86 86 86 86 86 86 86 86 86 86 σ , roughly divided into special register 88 and general register 86. Special register _ 』 ❹ 旗 flag 箄 了; leased number, stack indicator, flag phase temporary storage &amp; (4) The memory (4) memory, including the total of 16 R/R5 for R0~Rl5 (4), has a user-supplied I-storage register. Although the special register has two types for the user and the system, The state of the temporary register is only one type. The following data is stored in the processing register 92 as "processing data". The execution control circuit 90 outputs the processing data of the human memory in the processing register 92 to the arithmetic circuit 94 by means of a control signal (CTRL) to the output selector 98. The arithmetic circuit 94 operates on the data, that is, the command disk variable: row operation. The result of the operation is output to the input selector %. The execution control circuit %' inputs the operation result to the desired register in the processing register 92 by the control signal (ctrl) to the input selector 96. Further, the 'execution control circuit 90 reads the data from the memory through the cpu data bus' through the input selector 96 and appropriately loads it into the processing register &amp; the execution control circuit 90, and similarly processes the data through the CPU data bus. Properly recorded in memory. The execution control circuit 9 执行 performs the work while updating the program counter of the special register 88. When a work switching is generated, the execution control circuit 9 stores the processing data in the TCB of the area on the memory. Suppose Work A performs a system call, and the work is switched from Work A to Work B. Since the RTOS acquires the right to use the CPU by taking the system call execution as an opportunity, the CPU 84 temporarily performs an operation in accordance with the program for the RT0S. The process is as follows. (Storage of context information of job A) 1. The control circuit 90 is executed to switch the special register 88 from the user to the system. The processing data for RT0S processing is loaded into the special register 88 for the system. 2. Execution control circuit 90 stores the data of general purpose register 86 in a stack (not shown). 3. Execution control circuit 90 loads the processing data for the RTOS into a general purpose register 86 from a memory medium, such as another temporary memory, not shown. At this stage, the processing data of the processing register 92 is completely replaced with the processing data for the RTOS. 4. The RTOS self-memory detects the TCB of the work A, and writes the processing data stored in the stack to the TCB. In addition, the user uses the processing data of the special register 88 to write to the TCB as part of the context information. In this way, the processing data of job A is stored in the TCB. The action of the RTOS to move the work A from the "RUN" state to the "READY (or WAIT)" is stored in the TCB of the work A. (Loading of context information of work B) 1. The RTOS self-memory detects the TCB of the work B, and writes the following information on the TCB to the stack and the user-specific special register 88. The action of the RTOS to move the work B from the "READY" state to the "RUN" state is recorded in the TCB of the work B. 14 200937294 Unsuccessful 9S: The data used for RT〇S processing is stored from the storage register 86 to the recording medium of the map. 3. Execution control circuit 9 〇 ' ^ iL <Context information is loaded into the general-purpose register 86. The control circuit E is executed to switch the special register 88 from the system to the user. In this way, the processing data of B is loaded into the processing register 92. Work switching can be achieved through the above process. In general, since there are only a few types of registers 86, the stacking is used to switch the processing data for the work and the processing data for the RTOS. If the universal register % has two types, then there is no need to store and plant people through the stack, so a faster work switching can be performed. In this embodiment, by further retaining the register 1 according to each work setting, a faster work switching can be realized. The operation switching using the reserved register 110 is explained in detail with reference to FIG. It can be seen that in the case of the CPU 84 and the general software RTOS illustrated in Fig. 3, access to the TCB is frequently generated when the operation is switched. In the above hypothetical example, although the problem is switched from work A to work B, in practice, RT〇s is required to execute the majority of the instructions for selecting the next work to be performed. At this time, the RTOS frequently Access memory. The work processing apparatus 100 of the present embodiment realizes faster work switching in order to make the operation control circuit 200 described later dedicated to the work selection processing. (Hardification of RT〇S of Work Processing Apparatus 1) Fig. 4 is a conceptual diagram of RT〇s of the present embodiment.

Unlike the general software RTOS, the RTOS of this embodiment is mainly implemented as another hardware different from the CPU. Hereinafter, the RTOS 15 200937294 implemented by hardware is referred to as "hardware RT0S". Since the Rtgs of this embodiment is mainly another hardware different from the CPU, substantially no CPU usage right is required to execute the processing itself. That is, the RTOS and the work on the CPU will hardly become a competitive relationship. The general software RT0S shown in Fig. 2, the CPU for the work execution circuit is also the RT〇s execution circuit. On the other hand, in the case of the hardware RT0S of the present embodiment, the CPU is clearly a work execution circuit, and the work scheduling function can be realized centering on the storage circuit 120 and the work control circuit 200 which will be described later. Fig. 5 is a circuit diagram of the work processing apparatus 1A of the present embodiment. The work processing apparatus 100 includes a storage circuit 120 and a work control circuit 2 in addition to the CPU 15 (). The execution body of the cpui5 system, the storage circuit 120 and the work control circuit 2 are circuits having the function of RT 〇 s shown in FIG. Work scheduling is dominated by the work control circuit 2 (9). The CPU 150 includes an execution control circuit 152, a processing register 154, and an arithmetic circuit 160. The CPU 150 can also be a general CPU as illustrated in FIG. However, the CPU 150 of the present embodiment and the cpu 84 shown in Fig. 3 have some changes in the connection method of the signal line. The following Figure 6 details the specific circuit configuration. The work control circuit 200 includes a work switching circuit 21A, a flag table 212, an event table 214' work selection circuit 23A, and a state memory portion 22A. The flag table 2丨2 and the event table 2丨4 will be described in detail later in FIG. The state memory unit 220 is a unit corresponding to each operation. Hereinafter, the state memory unit 220 corresponding to the job a is referred to as "state memory unit 22A_A". Each status record 16 200937294 ❹

The memory unit 220 maintains the status data of the work. Status data, which is context information, especially information about work attributes such as work priorities and status. The Z material details the contents of the specific materials. All of the state resources of all the jobs are output from the state memory unit 220 to the work selection circuit track selection circuit 23, and various types of work selection circuits such as the selection of the run operation are executed based on the state data of each job. The selection circuit 230 will be described in detail later. The work switching circuit 21 执行 performs a work switching when detecting the system beer call signal (sc) received from the execution control circuit 152 and the external device interrupt request signal (INTR). Execution control circuit 152, when the system call is executed, when the system call signal (SC) is transmitted to the work switching circuit 21Gm switching circuit 21 and the interrupt request signal (INTR) is detected, the work switching power s 21G stops transmitting to the execution control circuit 152. Request signal (HR). The control circuit is executed, and when the operation of the CPUU0 is stopped, the stop end signal (HC) is transmitted to the work switching circuit 2IG. By the three types of signals, the CPU 15G and JL act as control circuits 200 to generate interlocking actions. The storage circuit 120 includes a load selection circuit 112 and a plurality of reserved registers 110. The reserved register 110 is also a unit corresponding to each work, and is a register for storing processing data of the processing register 154. Therefore, the reservation register 110 has the same data capacity as the processing register 154 or the processing register 154 or more. Hereinafter, the reservation register 110 corresponding to the job A is referred to as "reserved register 110-A". The selection circuit ιΐ2 is loaded, and when the instruction of the work switching circuit 210 is accepted, any data of the reserved register} ι〇 (hereinafter, the data held by the holding buffer 11 is referred to as “storage 17 200937294 material”). Loaded into the processing register 154. Select=Save::Save...Save data with _ to manned=:Two switch circuit 210 inputs the work selection signal (TS) of the specified... to the load selection (1) The reserved register 12^ corresponding to the specified work "Selecting the circuit to the processing register 154. Further, when the stored data output iiisd of the work cut is input to the processing register (5) and the write signal (WT) is input to the processing register (5), the temporary storage 154. Loading all the processing data to the processing register 154 is also available at any time. ==Retaining the register&quot;&quot;Working circuit η. For the desired reservation 写 4 Writer When T) is continued, the processing data is stored in the reserved register &quot; ο. Here, the number of bits that can be transmitted by the connection processing register 154 and each reserved register = bus is set to be parallelizable. Therefore, the work switch...10 only transfers the write signal to the reserved 110-times' to process the data-write to the reserved register 10, and then connects the reserved register u〇 with the load selection circuit. 112, and the number of bits connected to the bus bar of the selection circuit 112 and the CPU 15G are also the same as below, respectively (1) System Call Execution When the execution control circuit 152 of the CPU 150 executes a system call, the execution control circuit 152 causes the clock of the CPU 150 (hereinafter, referred to as "CPU clock ( CLK)") stops. The specific stopping method will be described in detail later with reference to FIG. 7 and the like. The control circuit 152' transmits a system call signal (sc) indicating the execution of the system call to the work switching circuit 21A of the work control circuit 2A. Further, when κ is stopped to the bundle, the execution control circuit i 52 transmits the stop end signal (HC) to the operation switching circuit 2 10 . 9 9 signal lines for transmitting system call signals are connected between the CPU 150 and the work switching circuit 21A. The nine signal lines correspond to the above nine types of system calls. The execution control circuit 152 transmits a digital pulse on any of the system call signal lines depending on the type of system call being executed. The working switching circuit 21〇' can detect the digital pulse according to which of the 9 lines (four) called the signal line, and immediately detects the type of the system being executed. The work switching circuit 210' selects the necessary information from the output data of the work selection circuit 2 to perform the processing instructed by the system call. This processing is performed on condition that the HC is transmitted. The relationship between the work switching circuit 210 and the operation selection circuit 23A will be described in detail with reference to FIG. In addition, the system call parameters and return values are written to the predetermined general purpose register 158 in the processing register 154. The work switching circuit 21() can perform parameter reading and return value writing to the (4) register 158. Here, it is assumed that the RUN-work operation Α performs a standby flag system call. Therefore, first, it is necessary to store the processing data of the work A. (Storage of Context Information of Work A) The execution control circuit 152 inputs an SC signal indicating a call of the standby flag system to the work switching circuit 21A. The execution control circuit M2 stops the coffee, and transmits the HCe operation switching circuit 21A at the end of the stop, except that the various selection circuits built in the operation selection circuit 230 cause the flag selection circuit 234 to output the flag m of the flag of the standby object, Also choose the next - 19 200937294 pending work B. The work switching circuit 210 writes the predetermined data to the state memory unit 22A. For example, 'Change the status of job A from "RUN" to "READY" or "WAIT". More specifically, the 'work switching circuit 210' outputs the write signal (WT_A) only to the state memory unit 220_A in addition to outputting "WAIT" to all of the state memory units 220 as data indicating the operation state in the status data. . In this way, the status setting of the job A is changed. Next, the job switching circuit 210 outputs a write signal (WT) to the reserved register 11A_a. Since the processing data of the processing register 154 is output to the respective reserved registers 110' at any time, it is stored in the reserved register 11〇_Α of the work A by the write signal (WT). (Loading of context information of job B) When the work switching circuit 2 1 ends the change of the state data of the work a and the storage of the processing data, the work selection signal (Ts B) of the designated job B is output to the load selection circuit. 112. Accordingly, the stored data of the reserved register u 〇 B is output to the processing register 154β. When the working switching circuit 21 outputs the write signal (WT) to the processing register 154, the stored data of the working memory is ◎ is loaded into the processing register 154. Further, the work switching circuit 21A writes the predetermined data to the state memory unit 220 of the operation β. For example, set the Β 熊 从 from "READY" to "咖". When the above processing is ended: The execution control circuit 152 restarts the CPU clock eCpui5 to start the execution of the operation B by restarting the cpu clock. Further details of the processing method will be described later with reference to Fig. 8(8). (2) Generation of the interrupt request signal 20 200937294 The work switching circuit 210 detects the request signal (job) from the peripheral device. More specifically, the interrupt request signal (intr) is transmitted to the operation switching circuit 210 from an interrupt controller not shown. The parameter indicating the level of the interrupt request signal (INTR) is recorded in the _discontinued (four) built-in temporary storage = the work switching circuit 21G stops the request signal _ is transmitted to the execution control circuit 152' to execute the control circuit 152 to make the (10) clock stop. The same as the system call execution, the work switching circuit 21 will be the RUn-worker

Q: Stored in the reserved scratchpad, and then the work switching circuit 2 works. Regardless of the parameters of the interrupt signal, the special work to start = type. The special work reads the bribe from the built-in register of the interrupt controller, and performs processing according to the parameters. The handling of special work execution may be the execution of a two-piece system call or setting a flag system call, or it may be a special start. Special work based on parameters may not be performed without special care. According to the parameters of the job, what kind of processing is performed depends on the construction of the work. When the execution of the special red work ends, choose the next run-work from the mediocrity-work. The switching circuit 21G will hold the register 110 corresponding to the special guard; when the switch is switched from the normal work to the special work to the binding control circuit 152, the work switching circuit 21 3 = timing At the time of the pulse division, the work switching circuit 210 stops the transmission of the HRB in order to cancel the stop of the cpu pulse... The control circuit 152 is stopped from transmitting the normal clock. At this time, the work switching of the special operation of the work switching circuit 210 is ended. Then, the details of the method of 21 200937294 are explained in Fig. 8(4). In either case, (A) processing of data storage, loading (B) state transition of work, and RUN-work selection, the core processing of work switching is achieved by hardware. Regarding (A) and (B) ', even if it is not necessary to access the TCB on the memory, the speed of the work switching is facilitated. Further, in order to realize the work processing apparatus 1, only the function of stopping and restarting the CPU clock may be added to cpui5(). In addition, these functions are borrowed

The invention is implemented by hardware and does not limit the scope of the invention. For example, by implementing the main functions of (A) or (B) by hardware, in order to assist the hardware function, the -part function of the RTOS can also be implemented in software, which is understood by those having ordinary knowledge in the technical field to which the present invention pertains. Things. 6 is a circuit diagram of the CPU 150 of FIG.

Unlike the CPU 84 of FIG. 3, there is only one type of special register 156 and special register 158 in the processing register 154. In the processing register, an input bus from the load selection circuit 112, an output bus to the reserved memory no, and a signal line from the operation switching circuit 21/signal (wt) are added. The execution control circuit 152 inputs the data of the processor in the processing register 92 to the arithmetic circuit (10) by the control signal (CTRL) to the inverter 164. The result of the operation becomes the input to the input selection: (6). Execution control circuit 152, by means of the input, :: control signal (CTRL), the operation of the sister &amp; Λ + 62 έ "he into the processing register 154" desired register. Execution control circuit 152 _ side / The program counter performs the work on the side. The memory device 15 22 ❹ ❹ 200937294 The processing data is not stored in the memory and the temporary register 110. The processing data is stored at any time from the processing =: on: when the data is stored in the sequence The register U0 is reserved, and the above is controlled by the work switching circuit 21. Instead of loading the data from the TCB on the memory, the data is loaded into the processing register 154, and the device 110 processes the remaining register. The data is loaded, such as: 俜 = timing, which is controlled by 21 。. The switch is connected to the processing register register 154 and the load selection circuit u2, and the connection processing register 154 and the reserved register 110. The bus, the parallel-transmission: the bus that processes the number of bits of the data. Therefore, by the write signal (WT) of the work switching circuit 210, it can be fetched and written. The general software RT0S, When the work is switched, the processing register 154 must be temporarily occupied. In contrast, The hardware RTOS' of this embodiment does not need to be specially used for work switching processing.

The data is loaded into the processing register 154. When switching from job A to job B, only the processing data of job B is loaded after the processing data of job A is stored. Therefore, it is not necessary to divide the process temporary stomach 154 into two types for system use and user use, or to perform transmission. Replacement processing of stacked data. Fig. 7 is a circuit diagram showing a configuration in which the execution control circuit 152 stops the cpu clock. &amp; The input of the second AND gate 174 is the output of the original clock (CLK〇) and the ΐΑΝβ gate 172, the latter being negative logic. The output of the first AND gate 172 stops the end signal (HC). Since the stop end signal (HC) is normally 〇, the second AND 174 turns the input original clock (CLK0) directly as the cpu 23 200937294 clock (CLK). The CPU 150 operates by receiving the CPU clock output from the second AND gate 174. When the output of the first AND gate 172 is "1", that is, when the stop end signal (HC) = 1, the output of the second AND gate 174 is fixed to 0, and the CPU clock (CLK) is stopped. The input of the first AND gate 172 is the output of the OR gate 176 and the output of the CPU busy signal (CBUSY), which is negative logic. CBUSY is a signal output from a known state machine that generates an internal cycle of the CPU 150, and is a signal of "1" when the CPU 150 is in a stop state. For example, the arithmetic circuit 94 ends the execution of the single instruction in execution or the last instruction of the locked plurality of instructions, and is "0" when the CPU is in a stop state or when the supply of the CPU clock has stopped. The input of the OR gate 176 is the output of the command decoder 170 (SC_DETECT) and the stop request signal (HR) from the work switching circuit 210. The instruction decoder 170 has a built-in latch circuit that holds SC_DETECT. The instruction decoder 170 takes as input the data (FD) read from the CPU 150, and outputs SC_DETECT = 1 when the FD is a system call instruction. With the built-in latch circuit, the instruction decoder 1 70 outputs SC_DETECT = 1 at any time even after the FD changes. The write signal (WT) of the work switching circuit 210 to the processing register 154 is also input to the instruction decoder 170. When the WT changes from 0 to 1, the action of loading the stored data into the processing register 154 is performed as described above. This WT is a pulse signal that returns from 1 to 0 after a predetermined time. When the WT changes from 1 to 〇, the latch circuit of the instruction decoder 170 is reset, and the instruction decoder 170 stops transmitting SC_DETECT. The relationship between SC_DETECT and the write signal (WT) is explained in detail in Fig. 8(b). The instruction decoding 200937294; 170' of this embodiment is specifically (9) for determining whether the execution target instruction is a system call: the execution of the control circuit 152 is performed. As a modification, the command decoder 2/load may be shared by the CPU 150 in the decoding step ❸cpu decoder. At this time, the 'heart order decoder 17G' can be operated by the cpu decoder to add the function of SC_DETECT=1 when the decoded data is the system beer call command to realize the interrupt generation request signal (UNTR). The stop request signal (HR) is passed to the execution control circuit 152. That is, when the system is called, or the stop request signal (HR) is transmitted, the output of the GR close 176 is "1". As described above, when a system call or an interrupt request signal is generated and the CPU busy signal is "〇", the output of the first AND gate 172 is "i", and the CPU clock is not output from the second AND gate 1 74. Fig. 8(a) is a timing chart showing the relationship of various signals when the interrupt request signal is generated. In Fig. 8(a), first, at time t0, the operation switching circuit 210 detects an interrupt request signal (Intr) from the outside. The work switching circuit 210 transmits a stop request signal (HR) to the execution control circuit 152 for performing special work. The input timing t' is approximately the same as the detection timing t〇. At time t1, the state machine of the CPU 150 is "work in progress" and CBUSY==丨. Since HR = 1, the OR gate 176 outputs "1", but since CBUSY = 1, the CPU 150 does not stop. Therefore, even if the input HR = 1, the CPU clock (CLK) is temporarily output in synchronization with the original clock (CLK).

After the passage of time, it changes to CBUSY = 0 at time t2. Since HR 25 200937294 = Bu, the 1st AND gate 172 outputs HC = 1, and the CPU clock output from the 2nd AND gate 174 is fixed to 0. On the other hand, the work switching circuit 210 starts the work switching from the normal work to the special work with the HC being transmitted as an opportunity. The details will be described later, but the time required for the operation switching is required to be several times in the operation clock of the operation control circuit 200. When the HC is transmitted, the operation control circuit 200 stops the transmission stop request signal (HR) on the condition that the operation clock circuit changes the predetermined number of times of the operation control circuit 200 (time t3). Since HR = 0, the execution control circuit 152 restarts the CPU clock (CLK). When the CPU 150 restarts the processing, the CPU 150 changes CBUSY from 0 to 1 (time t4). In this way, from the time t2 to the time t3 when the CPU clock is stopped, the work switching from the normal work to the special work is performed. Further, another processing method replaces the condition that the operation clock of the operation control circuit 200 changes by a predetermined number of times, and the operation control circuit 200 ends the operation switching condition, and the transmission of the HR is also stopped. Further, the control circuit 1 52 is executed, and the transmission of the HC may be stopped on the condition that the HR is stopped. When HC == 0, the execution control circuit 152 restarts the CPU clock (CLK). In this way, the execution of the work can be resumed. Ο Figure 8(b) is a timing diagram showing the relationship of various signals when the system calls are executed. In Fig. 8(b), first, at time t0, the command decoder 170 detects a system call and changes SC_DETECT from 0 to 1. At time t0, the state machine of the CPU 150 is "work in progress" and CBUSY = 1. Since SC_DETECT =1, the OR gate 176 outputs "1", but since CBUSY = 1, the CPU 150 does not stop. Therefore, even if the output SC_DETECT = 1, the CPU clock (CLK) 26 200937294 is temporarily output synchronously with the original clock (CLK0). After the elapse of time, it changes to CBUSY = 0 at time tl. Since SC_DETECT= 1 and CBUSY= 1, HC is stopped and the CPU clock is stopped. The work switching circuit 210 starts the work switching process when the input HC = 0, and outputs the write signal (WT) to the CPU 150. At time t2 when the WT changes from 0 to 1, the stored data is loaded into the processing register 1 54. The write signal (WT) is changed to WT = 0 at the time t3 after the pulse signal has passed at a predetermined time. With the falling detection of WT : 1 - 0, the SC-DETECT latched in the instruction decoder 〇 170 is reset (time t4). At this time, CBUSY changes from 0 to 1. Since CBUSY = 1, HC = 0, and then start the CPU clock. The operation switching is performed from time t1 to time t4 at which the CPU clock is stopped. Further, another processing method, instead of the falling detection condition of WT: 1-&gt; 0, ends the operation switching by the operation control circuit 200, stops the transmission of HR as a condition, and the execution control circuit 152 stops transmitting the HC. Reset SC-DETECT with HC = 0. The execution control circuit 152 restarts the CPU clock (CLK) and changes CBUSY from 0 to 1.不论 Regardless of the situation, the CPU 150 does not need to recognize the execution of the RUN-work switching during the CPU clock stop. Since the work switching circuit 210 performs the work switching process while the CPU clock is stopped, that is, the CPU 150 freezes (Freeze), the processing of the CPU 150 is separated from the work control circuit 200 by program control. Fig. 9 is a diagram for explaining the stop timing of the CPU clock of the pipeline processing. The CPU1 50 - sequentially reads a plurality of instructions from the memory to the processing temporary 27 200937294 The execution unit of the job 154 is executed to perform the work 7 and can be decomposed into the following four stages. l.F (Fetch: Read): Take the instruction from the memory. 2 'D (Decode: Decode): Interpret the instruction. 3. E (Execution: Execution): Execute the instruction. 4. WB (Write Back: Write): Write the command* into the memory. When a certain operation is executed from the instruction 丨 in the execution of the instruction F to WB, the instruction 2&lt;f 圭#- is also used, however, for the Gaoji

The rate is stubborn, and most of them are executed during the execution of the command. This method of foaming is called pipeline processing. For example, 'F phase of instruction 2 is started when instruction i is executed to stage D. When the referral batch > ” r (4) 1 is executed to the E stage, the execution phase: the phase, the instruction... phase. In this way, each instruction can be reduced by increasing the number of instructions executed per bit time. The execution time. In addition, the stages can be subdivided into two phases. For example, the F phase is separated into two phases of F1:F2. When the instruction! is executed to the ρ2 phase, the phase of the instruction 2 is started. When i executes to stage (1), it executes again

Command... 2 stages, command stage. By subdividing the stages, the calculation of the CPU 15G can be utilized more efficiently. Fig. 9 is a diagram showing the CPU clock stop timing when the pipeline processing is performed by subdividing each stage into two stages, and the CPU clock stop timing is generated. In the command, the processing starts at the timing of the coffee time "G". At the timing of the CPU clock 4", the decoding of the command i is ended. Assume that Command 1 is a system call. The instruction decoder 170 causes SC_DETECT &amp; 〇 to become! . Next, the condition of "SC-DETECT" is returned to 〇, and the write signal (WT) &amp; i from the work switching circuit Chuan 28 200937294 to the processing register 1S4 becomes 〇. Even if SC_DETECT^, cBUSY=1 because instruction 2~5 has been executed or has been executed. Therefore, the 2nd idle 174 starts outputting along with the cpu clock. However, the execution control circuit 152, when sc_detect = i, temporarily stops the update of the program counter so that the new instruction is not read. Yes It will not be read from the memory after the instruction 6 is read. ❹ 虽 Although the execution of the timing command i of the CPU clock "8" is completed, since the commands 2 to 5 are being executed, the CPU busy signal remains "丨". To ^^. The execution of the command 5 is completed at the timing of the clock "12". At this time, the CPU busy signal is "〇". Thereafter, according to the processing of FIG. 8(b), the supply of the cpu clock is stopped. The work switching circuit 210 stores the processing data at the stage until the end of the instruction 5 in the reservation register 110. According to this stop method, the work switching can be performed without wasting the execution result of the instruction after the system call = line. When the work switching is completed, the CPU busy signal is read and set to "丨", and the processing of the command decoder (7) is resumed. In this way, the CPU clock is supplied again. The other processing method 'At the end of the execution of the system call instruction, the CPU busy signal is "〇", and the supply of the CPU clock is stopped; the other instructions of the system call instruction are executed at the same time. The intermediate processing result of the instruction is recorded in the processing 54 and stored in the reserved register 11A.

Rim—When you work, you will be able to follow the instructions of the instruction that the person becomes a gamma a. For example, if you stop at the end of the reading phase, the instructions or operands will be stored in the reserved temporary. The memory u is read; the data of the read retention register U is loaded into the processing register 154, and the subsequent processing is executed from the solution: step 29 200937294. Fig. 10 shows the state memory unit 220 and the work switching circuit 21 The state memory unit 220 includes a state register 25 and a timer 252, and the state memory unit 220 holds the status data of the operation. Further, the timer 252 is the time when the operation transitions to the READY state or the WAIT state. The time elapsed after the work is moved to the READY state is called "READY elapsed time", and the elapsed time after the work is migrated to the WAIT state is called "elapsed time". The value of the timer 252 is output as a TIM signal at any time. The Q work switching circuit 210, when a job is switched to a READY state or a WAIT state when a work switching is performed, the timer 252 that drives the operation restarts the time measurement. The state memory unit 220 is a set of registers shown below. (A) Work ID register 254: Keep the work ID. The ID signal indicating the work id is output from the work id register 254 to the work selection circuit 230 at any time. Hereinafter, the ID signal output from the job ID register 254 of the job a to the job selection circuit 230 is referred to as "ID_A signal". The other signals output from the status memory unit 220 are also the same. (B) Work Priority Order 256: Keep work priority. The PR signal indicating the priority of the work is output from the work priority register 256 at any time. "0" is the highest priority, and a larger value indicates a lower priority for work. (C) Working status Register 258 ·• indicates the working status. One of STOP, READY, RUN, WAIT, and IDLE is used as the ST signal and is output with 30 200937294 in addition to the state before the IDLE system is initialized. (D) Work Start Address Register 26〇: Indicates the TCB address of the work in the memory. The output is an AD signal. (E) Standby reason register 262: When the operation is in the state of the puncture, it indicates the reason for the standby of the WAIT release condition. The reason for standby is "flag waiting", "event waiting", and "mutual exclusion". The output is the WR signal. % (F) The flag i d is crying. &lt; / . a ❹ Ο WAIT H, (4) f ^, the nickname ID of the recipe for the taste and the object (hereinafter referred to as "standby flag ..."). The output is the sm signal. (G) Mutually exclusive ID for temporary storage and WMT status, the mutual exclusion ID of the material that is in the ._ ', mutual exclusion of the object (hereinafter referred to as "standby mutual exclusion") . Turn out for the MID signal.事二1D register 266: The work is based on the event waiting for the reason: the event of waiting for the object (hereinafter, the event IE^ called "standby" is the EID signal. WAir waits for the temporary storage 11 268: The work is in the standby flag type for the reason of event waiting. "For the FL signal. WAIT-like = piece temporary storage 11 27G: The guard is in the flag for the event waiting: =, keep the flag condition. Output signal. The standby flag type and flag conditions will be described later. (K) The flag initializes the temporary data. The output is FU signal. Indicates whether there is a standby flag class (L). Suspend counter 274: The WAITU call pause value is referred to 31 200937294, is a variable. The pause counter 274 holds the pause value. The work switching circuit 2i periodically reduces the pause value of each pause counter 274. The output is a τ〇 signal. Instead of the work switching circuit 210, the pause value is decreased, and the counter 274 is paused. The self-discipline itself may periodically reduce its own pause value. The work selection circuit 230 performs work selection based on various signals output from the respective state memory units 22. The work selection circuit 23 includes the following circuits. (Α) Execution selection circuit 232: When the operation is switched, the next run is selected. The execution selection circuit 232 selects any one of the operations from the state memory unit 220 to select any one of the operations as RUN-operation. The input signals of 232 are 4 types of ID, ST, PR, and TIM. The output is the next RUN-working work ID. The detailed circuit configuration is detailed in Fig. 12. (B) Flag selection circuit 234: by releasing the flag system The execution of the call 'selects the work to be moved from the WAIT state to the READY state. The flag ID of the flag for canceling the flag system call release (hereinafter referred to as "release flag") is input from the work switching circuit 2 1 . The input signals of the memory unit 22 are 6 types of ID, ST, WR, PR, SID, and TIM. The output signal is the work ID of the work from the WAIT state to the READY state. When the job does not exist, the output is The specified value is described in more detail in the figure. (C) Event selection circuit 236: Selecting the transition from the WAIT state to the READY state by setting the execution of the event system call In the case of setting an event system call setting event (hereinafter referred to as "setting event"), the 200937294 piece ID is input from the work switching circuit 2 1 0. The input signals from the state memory unit 220 are ID, ST, WR. 6 types of EID, FL, and FLC. The output signal is the work ID of the work from the WAIT state to the READY state, and the FL and FLC of the operation. (D) Suspend detection circuit 238: In the operation of detecting the WAIT state, pause The counter 274 has a pause value of 0. The pause detection circuit 238 is driven every time the pause value is updated. The input signals of the pause detection circuit 238 are three types of ID, ST, and TO. The output signal is the work ID of the job. When the 〇 job does not exist, a predetermined value of one or the like is output. (E) Mutual exclusion circuit 240: Selects the operation from the WAIT state to the READY state by releasing the execution of the mutex system call. The mutual exclusion ID of the mutual exclusion system call release (hereinafter referred to as "disarming") is input from the work switching circuit 2 10 . The input signals from the state memory unit 220 are six types of ID, ST, WR, PR, SID, and TIM. Output Signal The job ID of the job that migrated from the WAIT state to the READY state. When the job does not exist, a predetermined value of one is output.

〇 (F) Retrieval circuit 242: When a job ID is input from the work switching circuit 210, all state data of the job is output. Hereinafter, the RUN-work selection, flag, event, mutual exclusion, and pause associated with the work switching will be described, and in particular, the processing of the work selection circuit 230 will be centered and compared with the general technique. (RUN - Operation Selection) (1) RUN-Working Selection of General Software RTOS Figure 11 is a diagram showing the RUN-operation selection of the general RTOS. The work preparation sequence is formed on the memory, and the READY-working TCB is linked by an index. The priority indicator 280 is a front end address of the TCB that is set in accordance with each work priority order and indicates the work priority order. In the case of the work preparation sequence in FIG. 11, the priority order indicator 280 of the work priority order "指向" points to the address of the TCB of the work A, and the priority order indicator 280 of the work priority order "1" points to the address of the TCB of the work B. . The TCB of Work A further points to the address of the TCB of Work D. General software RTOS - while scanning this work, prepare the list and select the next RUN - work. At this time, the RTOS performs the following two stages of processing. A. Migrate RUN—work from RUN to READY » B. Select Next RUN—Work to migrate the working state of this job from READY to run. The processing of the decomposed software RTOS is as follows. (RUN-work state transition) Here's RUN—the job is described in job j.

Al·RTOS keeps the RUN-work ID in memory. Root 取得 Get the address of the TCB of job J based on this work ID. A2. Access the TCB and get the work priority of the job j. Assume that the work priority is "〇". A3. The priority index corresponding to the priority of the work of the job j in the work preparation sequence shown in Fig. 11 is obtained. 280 A4 The TCB indicated by the priority index 280 obtained by the detection is obtained. The TCB of job A is detected here. 34 200937294 A5. Detect the last TCB along the indicator of the TCB of Work A. In Figure 11, the work F is the last end. A6. Set the indicator of the TCB of the work F to the address of the TCB pointing to the work J. In this way, the TCB of job J is appended to the work preparation list. A7. Set the TCB of job J to "READY". Also, the processing data is copied to the register storage area of the TCB. (READY - State transition of the job) B 1. The priority order indicator 280 of the RTOS detection work priority "0" © indicates which TCB. When the TCB is not found, the priority index 280 of the detection work priority "1" indicates which TCB. Before you find the TCB, you can work at a specific level while reducing your work priorities. In Figure 11, the specific work A. B2. Remove Work A from the work preparation list. Specifically, the priority order indicator 280 of the work priority order "〇" is overwritten with the address of the TCB that does not point to the work A but to the work D. Also, the indicator of job A is set to NULL so as not to point to the address of job D. In this way, the © TCB of job A is removed from the work preparation list. B3. Set the TCB of job A to "RUN". Further, the processing data stored in the scratchpad storage area of the TCB of the work A is loaded into the processing register. The general software RTOS, through this type of work preparation, performs work switching. That is, the RTOS selects RUN from a plurality of READY-work--the rules of the work are as follows. 1. READY - work (1st condition). 35 200937294 2. For READY - work with the highest priority in work (Article 2). 3. When there are a plurality of jobs with the highest work priority order, the work that becomes the READY state is the earliest (the third condition). These three conditions are collectively referred to as "RUN work selection conditions". The execution selection circuit 232 of the work processing apparatus 100 implements the work scheduling function of such an RTOS by hardware. (2) Selection of RUN-Operation of Hardware RTOS of the Present Embodiment FIG. 12 is a circuit diagram of the execution selection circuit 232. Here, it is explained that RUN_operation is selected from eight jobs of work 0 to work 7. The execution selection circuit 23 2 includes four first comparison circuits 290 (290a to 290d), two second comparison circuits 292 (292a, 292b), and one third comparison circuit 294. Further, eight determination circuits 296 (296a to 296h) are also included. The determination circuit 296 takes an ST signal indicating the operation state as an input, and outputs a READY indicating "1" or a CID signal indicating "0" when the READY is other than READY. The determination circuit 296 makes a determination based on the first condition in the above-described RUN operation selection condition. The first comparison circuit 290 inputs the ID, PR, TIM, and CID signal from the decision circuit 296 of two operations. The first comparison circuit 290a will be described with a focus. The first comparison circuit 290a compares the operation 工作 with the operation 1, and selects a better operation based on the RUN operation selection condition described above. First determination: First, the CID signals output from the determination circuit 296a and the determination circuit 296b are compared. When one of them is "1", that is, when only one of the operations is in the READY state, the first comparison circuit 290a inputs the 200937294 TIM. When they are all "〇", that is, any work

When the ID of the job and the pR tone are not in the READY state, the Jth comparison circuit 2 outputs (1) two pR = τιμ = NULL. This department indicates that Ren Wei Wei has not been selected. When all are "1", that is, when the work is in the READY state, the next second determination is made.

The second judgment. Compare the pR signal of the work 与 with the pR signal of the work ,, and select the work order of work priority 3. For example, when the priority of the guardship α is 1" and the priority of the work 1 is "2", the ID, PR, and TIM of the work order are output. According to the second determination, the work with a high priority of work can be selected as a candidate for RUN-I. When the work G and the job work are in the same priority order, the next third decision is made. The third judgment: comparing the TIM signal of the work 与 with the 耵^ signal of the work i, and selecting the READY to work for a long time. The READY elapsed time is the same, assuming that the work is selected. Since only the elapsed time is compared, it can be judged that 'there is no need to work in tandem Tcb order management. In this way, work 〇 work 1, work 2 and work 3, work 4 and work 5, work 6 and work 7 are respectively compared by the RUN work selection condition. The second comparison circuit 292 further filters the candidates for the RUN-operation by the wheels of the two ith comparison circuits 29A. The second comparison circuit 292 &amp; performs the operation by the outputs of the first comparison circuit 290a and the first comparison circuit 290b. Therefore, the second comparison circuit 292a outputs the id, Pr, and TIM of the operation of the most RUN operation selection condition among the work 〇 to the work 柞 α 丄 j. The J comparison circuit 294 is also the same, and the third comparison circuit 294 outputs the work ID of the work 〇~工*r 7 . 37 200937294 According to this processing method, the RUN operation selection condition can be realized by hardware. Although the general software RTOS - side access operation preparation sequence selects the run - operation, the execution selection circuit 232 of the present embodiment selects RUN - operation by the status data output from the status memory unit 220 at any time. The processing of the integrated execution selection circuit 232 is as follows. , (RUN - state transition of work) Here, RUN - the work is described by job j. A1. The work switching circuit 21 sets the operation state register 258 of the job j to "READY". A2. The operation switching circuit 21 〇 setting operation timer 252 starts measuring the READY elapsed time. In this way, job j migrates from the RUN state to READY. As described above, the processing data is stored in the reserved register 11 of the job j. Since the connection processing register 154 and the bus bar of the reserved register 11 are capable of transmitting the processing data in parallel, the processing of A1 and A2 can be performed at one clock time. (READY - State transition of operation) B1. The job switching circuit 21A, when the state transition of the job j is completed, the job ID specified from the execution selection circuit 232 is specified to be RUN-operated. The work status register 258 of this job is set to "run". In this way, the specific work is moved from the REady state to the RUN. The processing data of the special work is loaded from the reservation register 11 to the processing register 154. Since the bus pool connecting the reservation register 110 and the processing register 154 is also the number of bits in which the processing data can be transferred in parallel, the processing of B 1 can be performed at one clock time. 38 200937294 Software simplification, when the work is switched, due to the access to the work preparation string, 4 CPU CPU clock time is more. In contrast, the work control circuit 本 can end the work switching with a slight time. Since the state memory unit 22G outputs the state data to the execution selection circuit m at any time, the execution selection circuit 232 outputs the work m of any work at any time. The b does not start the deletion process after the work switching is started, but the execution of the selection circuit 232 is performed at the time of the work switching to perform the selection of the __❹, which also helps to increase the speed of the switching. . Here, the operation is 8 ', but by increasing the number of segments of the comparison circuit, it is also possible to correspond to more work" (flag processing). Fig. 13 is a diagram showing the standby sequence used for the general flag processing. Before describing the standby flag sequence, simply explain the flag. In the flag table 212 ‘flag ID corresponds to the flag counter. The initial value δ of the flag counter 〇 is also determined to be a finite number. For example, assume that the flag ID = 4, the flag number -3 is set. When any job performs the standby flag system call with the flag of flag = 1 = 4 as the standby flag, the work switching circuit 21 reduces the flag counter of the standby flag. The flag counter is reduced when it is requested to be acquired due to the standby flag number, and is not available when it becomes 〇. Take the flag. The tensor is used as the standby flag to perform the standby flag system call, and the state transitions to the WAIT state. In addition, when the work is performed with the flag of the flag ID = 4 as the release number, the work switching circuit 210 increases the flag counter of the table No. 29 200937294. In summary, the flag counter &gt; 0 ····································· At this point, reduce the flag counter. Flag Counter = 〇: The job of executing the standby flag system call from RUN to WAITe does not reduce the flag counter. The guard performing the standby flag system call migrated from the Wait state to the UEADY state. Another job must perform the un-flag system call. (1) General software RTOS flag processing The general software RT〇S manages the TCB in the (four) state (hereinafter, particularly referred to as "flag waiting work") by waiting for the flag to wait for the reason of the flag waiting. The standby flag series is formed in the same memory as the series prepared in the figure u, and is formed on the memory. The cafés that are waiting for work are linked by indicators. The priority indicator 28() points to the front-end address of the TCB waiting for the flag of the guard priority. The general software RTOS' waits for the flag to be moved from the WAIT state to the anal tear state while performing the unloading of the flag system. Standby flag system call and release flag system The processing of Rtos during call execution is as follows. (Execution of standby flag system call) Here, RUN—work is described by job j. A1.RT0s keeps the face-work work 1 in memory. According to this work ID, the address of the TCB of the job j is obtained. ★ A2·Detected in the standby flag system call the designated flag of the standby flag. In the following, the difference is handled by the value processing of the flag counter. 200937294 (Flag counter &gt; 0) A3.RTOS reduces the flag counter of the standby flag. Α 4. Set the TCB of job J to "READY". At this time, the TCB of the job j is added to the work preparation sequence. (When the flag counter = 0) A3. Access the TCB to get the job priority. Assume that the work priority is "〇".

A4. Obtain the priority index corresponding to the work priority order in the standby flag series. A5. Detect the tcb indicated by the priority indicator obtained. Here, the TCB of the work A is detected. The A6JI is working on the TCB of the work VIII to detect the τα at the last end. In Figure 13, the work F is the last end.

A7· Set the indicator of TCB of work F to point to I; the address of TCB. In this way, the workers' TCBs are added to the standby flag series. A8. Set the TCB of job j to "". The flag of the flag is IDe and it is won (the execution of the flag system is removed). In addition to the flag order, the Guardian of the priority order "G" is searched to release the flag, and the flag of the standby flag is shun 1 ^ Ύ does not exist. , with the job ID as the subject of retrieval. According to Wei Test 4, the flag is released as the standby flag flag (4), and the handling is divided. (When detected) 乂 The work detected is the work Ε to explain. Set the work 41 41 200937294 to "READ Υ". Also, the flag ID of the standby flag is cleared. B3. Remove the TCB of the work E from the standby flag series. B4. Move the status of the work to release the flag from the RUN state to READY. Add the TCB of this job to the job preparation sequence. (When not detected) B2. Increase the flag counter. B3. Move the status of the work to remove the flag from the RUN state to READY. Add the TCB of this job to the work preparation list. The general software RTOS performs flag correlation processing by managing such a standby flag sequence. When the flag is removed, the RTOS selects the READY_work from a plurality of WAIT-work rules as follows. 1. Work for WAIT (1st condition). 2. For WAIT - work to release the flag as the standby flag (2nd condition). 3. When there are multiple such jobs, the work with the highest priority of work (the third condition). 4. When there are a plurality of jobs with the highest work priority order, the work that becomes the earliest in the WAIT state time (the fourth condition). These four conditions are collectively referred to as "flag standby cancellation conditions". The flag selection circuit 234 of the work processing apparatus 100 implements the work scheduling function of such an RTOS by hardware. (2) Flag processing of the hardware RTOS of the present embodiment Fig. 14 is a circuit diagram of the flag selection circuit 234. Here, eight jobs from work 0 to work 7 are also explained. Flag selection power 42 200937294 Road 234 includes four comparator comparison circuits 3〇〇(3〇〇a~3〇〇d), two second comparison circuits 302 (302a, 302b), and i third comparison circuits 3〇 4. Eight decision circuits 306 (306a to 306h) are also included. The 判定 判定 determination circuit 306 is a circuit that inputs signals from the state memory unit 22, the Wei, SID signal, and the signal (1) from the guard switching circuit 21 (). The flag ID entered here is the flag of the unloaded flag. ^ The decision circuit 306 (4) indicates that the flag is the flag of the standby flag when the flag is released, and the flag is called "M", and the flag is not the flag of the standby flag. The determination circuit 3〇6 is a circuit that outputs a determination result related to the i-th condition and the second condition in the flag standby cancellation condition. The comparison control circuit m the CID signal from the determination circuit 306 with m pRH of two operations is The first comparison circuit is a circuit that determines the third condition and the fourth condition in the money cancellation condition. The second comparison circuit is the same as the third comparison circuit 304. As described above, the work selection condition is deleted. The third condition and the fourth condition are the same as the third condition and the fourth condition of the flag standby cancellation condition. The comparison circuit for executing the selection circuit is a circuit for comparing the status data (PR, TIM) of the flag. Each of the comparison circuits of the selection power 234 is also a circuit for comparing the status data (4) and τ of the operation. 1 is the first ratio of the ith comparison circuit 29A and the number selection circuit 234 of the execution selection circuit 232. Compared with the circuit 3, the same logic can be shared. The work is judged by the decision circuit 306 under the conditions of the first and second conditions, and is also passed to the first! After that, by the same determination process as the execution selection circuit 232, 43 200937294 outputs any -... from the third comparison circuit 304. The processing of the standby flag system call and the release flag system call execution is as follows. (Standby flag system call Execution) Here, the RUN-work is detected by the job j 212 below the standby flag number, according to the flag counter A1. The work switching circuit 21〇 calls the flag counter from the flag of the flag list. Divergence. (Flag counter &gt; 0)

A2. The work switching circuit 21 () reduces the flag counter of the flag table 212. A3. Set the working state i state register 258 of the job J to "ready". At this time, the "work switching circuit 21" sets the timer of the coffee-operation (5), and starts measuring the READY elapsed time. (A flag counter = 〇) A2. The operation switching circuit 21G sets the U operating state register 258 to "W·", and the standby reason register 262 is set to "flag waiting",

The flag 1D register 264 is set to the flag ID of the standby flag, and the timer 252 is set to start measuring the WAIT elapsed time. With this side, the work of executing the standby flag system call is moved from the RUN state to READY or WAIT. (Release execution of the flag system call) B1. The work switching circuit 210 inputs the flag ID of the release flag to each of the decision circuits 3G6. Each of the determination circuits 3G6 determines whether or not the first condition and the 帛2 condition in the flag release condition are satisfied by the flag m. Therefore, each of the first comparison circuits selects an operation based on the third condition and the fourth condition. 44 200937294 The third comparison circuit 304 (when any of the determination circuits 306 is rotated by 」" to output any of the job IDs) "B2. Set the detected operation state register 258 to READY" "Clear the standby reason register" As with the flag (1) register 264, the READY elapsed time is measured by the timer 252. B 3. The system call will be executed, and the working state register 258 is set to ready, and the eady elapsed time is measured. ❹ ❹ 3 未 未 未 306 306 306 306 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 = = = = = = = = = = = = = = = = READY. The status of the system call job is transferred from the RUN state to the circuit memory, and the status data is output to the flag selection at any time. When the work switching circuit 210 inputs the flag (1) to the decision circuit 306, the flag selection circuit 2 is executed. Choose to process. The mutual exclusion is also the same as the flag, and the use of the banner of the workplace differs in the following points. Step processing. The mutual exclusion and I flag counters can be set to the upper integer. The flag number counter is i or 〇(4), and, when mutually exclusive, more than two jobs can obtain the same flag. The number of devices is 2 to obtain a mutually exclusive work blame only (10). ..., and, when mutually exclusive, 2. Can be removed by the flag (4) to cancel the flag by the standby flag (four) material (four) to get the (four) of the work of the 'four is not limited to this, can be borrowed 45 200937294 by the mutual exclusion The system calls the demutation work only to obtain mutually exclusive work by calling the mutual exclusion system call. When the mutual exclusion is removed, the rules for working from _ READY from multiple WA. are as follows. 1. Work for WAIT (I-condition). Condition) 2^Wei Bu work to remove mutual exclusion as the work of mutual exclusion (the second is the work with the highest priority of work 3. When there are multiple such work, do (the third condition).

4. When there are a plurality of jade works with the highest priority of work, it is the earliest work in the AIT state (the fourth condition). These four conditions are collectively referred to as "mutual exclusion standby cancellation conditions". Therefore, when the standby mutual exclusion system calls and releases the mutual exclusion system call execution: the processing of the hardware RT〇S of the present embodiment is as follows. In the flag table 212, mutual

Relative to Kang and Table 7, the mutual exclusion, whether the possession status data of any job is ten should be maintained. Occupation status data, when not occupied, is sometimes "〇", and is occupied as the work ID of the work that is mutually exclusive. (Execution of Standby Mutual System Call) Here, RUN—work is described by job j. 2. The work switching circuit 21 detects whether it is occupied by the standby mutual exclusion system «疋 mutual exclusion. In the following, according to the exclusive state of the exclusive state, the processing generates a branch (when the exclusive exclusion is not occupied)

The ID A work switching circuit 21G records the work of performing the line call as the exclusive possession data. 46 200937294 A3. Set the working state register 258 of the job J to "rEady". At this time, the "work switching circuit 21" sets the run-operating timer 252 to start measuring the READY elapsed time. (when the exclusive exclusion is performed) A2. The work switching circuit 21A sets the operation state register 258 of the job j to "WAIT", and the standby reason register 262 is set to "mutual exclusion wait" and the exclusive ID register. 265 is set to the mutually exclusive mutual exclusion ID, the timer 252 is set, and the WAIT elapsed time is measured. (Release the execution of the mutual exclusion system call) B1. The work switching circuit 21〇 inputs the release flag 1〇 to the exclusive circuit 24〇 on the condition that the work of the system call is performed to remove the mutual exclusion. Similarly to Fig. 14, the exclusive circuit 240 includes a comparison circuit for multi-segment connection and a determination circuit for determining whether or not the i-th condition and the second condition in the standby cancellation condition are satisfied. The discriminating circuit is based on the mutual exclusion, and outputs "only when the condition "and the condition" and the second condition are satisfied in the mutually exclusive standby solution $ condition. In addition, when the non-existing mutual exclusion is performed, the execution of the mutual exclusion is performed. When the system call is rejected, the state of the operation is shifted from the RUN state to the ready state. (Any decision circuit outputs "1", and the mutex circuit 240 rotates any work ID) "B2. Temporarily detects the working state of the work. The memory 258 is set to J. In addition to the standby reason register 262 and the exclusive id register 265, the REady elapsed time is measured by the timer 252. The operation status register 258 for performing the system call operation is set to "READY". "' Start measuring the READY elapsed time." 47 200937294 (When any of the determination circuits are not turned out, when one of the operations (1) is performed), the vertical circuit 240 is not output, and the B2·operation switching circuit 21 is in the occupied state. , flag table 212, set the mutual exclusion to non-B3. The system call READY will be executed. The state of the transition from the RUN state to (event processing) briefly describes the event of this embodiment

Spotted sister chooses 卜* Bu Yin 1 dry s reason. In the event table 214, the event ID ❹ is recorded in correspondence with the flag type (hereinafter referred to as "current flag type transmission 8 # _ '"). The type of bit that shows the difficulty of 1俅8 digits. The event system call is changed, and the current system call is changed, and the event 10 and the flag type are used as parameters. When the ...... 设定 设定 设定 设定 设定 设定 」 ) ) ) ) ) ) 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 盥 。 。 。 When 00000101", the current flag type becomes ^0001 1 "" from the left to the following, for each flag type, 〇 = bit, first bit, ..., 7th bit. The temple machine event "Call H is waiting for standby type. Under the current flag of the system that meets the established conditions, &amp; the event ID, the flag type (with the ::machine flag type), and the flag condition are parameters. ==call time' determines whether the flag condition is true between the current flag type and the standby flag type. The flag condition is logic = machine: flag wide_accumulation (,...release = all bits in the standby flag type is..., the current flag type of the 48

200937294 is Fl". When the flag condition 4 logical sum (GR), (4) τ release condition, the standby flag type is "the type of the solution - so ", any of the I 兀 'current flag 榡 " 〇 ;; for example, when When the current flag type is 〇lj, the standby flag type is "000000U", and the flagpole is "logical" (OR), the zirconium is the starting condition.. ^ ; f is the 6th of the standby flag type. In the bit and the seventh, the current flag type of the 7th room name 111 70 is M", therefore, the WAiT release condition of the system call is established at this time. On the other hand, when the flag is "AND", the WAIT cancellation condition is not established because the sixth flag of the current flag type is "〇". d) Event processing of the general software RTOS Standby event system beer call and set event system call execution (4) S processing is as follows. In general, in order to manage the incident, the event: ^ is held on the body. In this event table, not only the event 1D, the current flag class ^ is the event of the standby event in the WAIT state (hereinafter, referred to as "event waiting for work"), the maintenance m, the standby flag type standard condition Corresponding to keep. (Execution of standby event system call) A1. The RTOS reads the event type specified from the event table. See line A2. Compare the current flag type and the standby flag type according to the flag condition. Determine whether the WAIT cancellation condition is established. (When the WAIT release condition is established) A3. Move the work status of the execution of the system beer call from r to READY. 49 200937294 (When the WAIT release condition is not established) A3. Record the work ID of the work of executing the system call in the event table. A4. Record the standby flag type in the event table. A5. Record the flag conditions in the event table. A6. Move the working status of the work performing the system call from the RUN state to the WAIT. (Setting the execution of the event system call) B 1. The RTOS reads the current flag type, work ID, standby flag type, and flag condition from the event table for the specified event of the system call. B2. Record the logical sum of the current flag type and the set flag type into a new current flag type. (When the setting event does not exist, the event waits for work, or even if it exists, according to the standby flag type and the flag condition WAIT release condition is not established) B3. Move the working state of the system call operation from the RUN state to READY. (When the event is set to wait for an event and the WAIT release condition is established) B3. The operation status of the standby event is moved from the WAIT state to READY. B4. Clear the standby work ID, standby flag type, and flag condition of the event table. B5. Move the working state of the work of performing the system call from the RUN state to READY. And execute RUN - the choice of work. When performing a set event system call, select READY from multiple WAITs - Work - the rules for working are as follows. 50 200937294 Work (1st condition). In the work, the event is set as the standby event (the second WAT 2 is the comparison of the standby flag type, the current flag type, and the flag condition, and the cancellation condition is established (the third condition}. These three conditions are collectively called It is "event standby release condition". (2) Event processing of hardware RT〇s in this embodiment Ο 1. WAIT — 2. is WAIT-~ condition) 待机 Processing device 100 standby event system call and setting event The processing of the system call execution is as follows. The H processor ΠΗ) built-in number table 2 1 2 event ID corresponds to the current flag type. Information such as the standby work ID and the standby flag type is stored in the status memory. (Execution of Standby Event System Call) The switching circuit 210 reads the current flag type from the event table 214. A2. The work switching circuit 21 compares the current flag type with the standby flag type according to the flag condition, and determines that the WAIT release condition is W. (When the WAIT release condition is satisfied) A3. The work status register 258 that performs the system call operation is set to "READY". (When the WAIT release condition is not satisfied) A3. The work switching circuit 21A sets the work state register 258 for performing the system call operation to "WAIT", and the standby reason register 262 is set to "event wait" and event ID. The register 266 is set to the event ID of the standby event, the standby flag register 268 is set to the standby flag type, and the flag 51 200937294 conditional register 270 is set to the flag condition. (Setting the execution of the event system call) The current flag $214 is read from the event table 214. The event m of the set event designated by the system beer is input to the selection circuit 236. The switching circuit 210' accumulates the set flag type logic to the current flag type of the one-piece table 214. B3. Event selection circuit 236, the work for which the input condition is established. At this time, V Chu chooses things "

At this time, do not work fine and WAIT q how long, choose a number of jobs. (When the job that satisfies the event standby cancellation condition exists) Β4. Set the event status register 258 of the event waiting operation to the flag wise' wide event 1D register 266, the standby flag temporary register flag condition temporary storage 270. Β 5. Move the work of performing the system call to READY.

(When the job that satisfies the event standby cancellation condition does not exist)

Run state moves. Moves the work status of the system call to READY. t胥怦恿) Move to the WAIT state's work' when WAn^ is in the READY state except when the condition is met. However, * is subject to certain external factors or application bugs, which prevent the WAIT release condition from being established. Therefore, in general, move the work to 2 52 200937294 to set the pause value. The pause value is periodically decreased. When it is 0, the job can be moved from the WAIT state to the READY state even if the WAIT release condition is not established. That is, it is possible to prevent the work from being stopped above the WAIT state pause value. (1) Suspend processing of general software RTOS In the case of a general RTOS composed of software, the TCB in the WAIT state is set to a pause value, which is periodically reduced. The RTOS periodically issues an interrupt to the processing of the CPU, checks all TCBs, and detects WAITs that have a pause value of 0. When such a job is detected, the RTOS migrates the working state of the job from the WAIT state to READY. (2) Suspend processing of the hardware RTOS of the present embodiment On the other hand, in the case of the present embodiment, the work switching circuit 2 10 periodically reduces the pause value of each pause counter 274. The pause value is set as a parameter when the WAIT system call is executed, and the work switching circuit 210 sets a pause value in the pause counter 274 that performs the operation of the system call.

Since the CPU 150 does not intervene in the reduction processing of the pause value, the work switching circuit 2 10 can update the pause value independently of the job execution processing. Therefore, even if the CPU 1 50 is performing work, the work control circuit 200 also autonomously performs the update of the pause value. Since the status data is input to the pause detecting circuit 23 8 at any time, the pause detecting circuit 23 8 can detect that the pause value becomes 0 at the same timing as the pause value update timing. The pause detection circuit 238 outputs the job ID of such work. The work switching circuit 210, when inputting the work ID from the suspension detecting circuit 238, recognizes that a pause has occurred, and transmits HC to stop supplying the CPU clock. The work control circuit 200 migrates the WAIT 53 200937294, which has a pause, to the READY state, and migrates the run-work to the READY state. The work switching circuit 210 selects the next ___ to be executed from the READY - work. Further, the work switching circuit 21 restarts the timer 252 which generates the pause operation, and measures the READY elapsed time. According to this processing method, when the work is being executed, that is, when a pause occurs in the CPU clock operation, the CPU 15 can immediately issue an interrupt to perform the work switching. Further, in the work execution, the work switching circuit 2 can independently perform the update processing of the pause value without the processing capability of the CPU 150.

(The operation switching circuit 21 of the finite state machine) Q Fig. 15 is a state transition diagram of the operation switching circuit 21 〇. In the initialization process (A1), all jobs are in the IDLE state. When the initialization process ends (sίο), any one of the jobs becomes RTJN-work and becomes the work execution state (A2). When the interrupt request signal is detected (s丨2), the special operation becomes RUN-work, and the interrupt processing (A3) is executed. When the interrupt processing ends (S14), the work switching circuit 21 selects the RUN-work from the normal operation and shifts to A2. Further, during the execution of the work (A2), when the system call is executed (S16), the system call processing (A4) is executed. When no work switching, that is, RUN-work switching is not generated (S18)', A2 is returned. On the other hand, when the work switching is generated by the system call processing (A4) (S2), the work switching circuit performs the RUN-operation selection (A5) in accordance with the output of the execution selection circuit 232. When the work switching ends (S22), the processing state moves to a2. Finally, the case where only one of the storage circuit 120 and the operation control circuit 2 of the main components of the work processing apparatus 100 is constructed will be described. 54 200937294 1Do not teach the work control electric diagram] 6 series of the work processing device of Figure 5 __ 2 processing device _ circuit 200 of the work processing device (10) circuit is not installed work control instead of not installed b (four) circuit coffee, additional road 322 and processing data holding unit 32〇. The control power 200 is changed by ^, so the work schedule and the load work control circuit are switched by the body 1&quot; Therefore, in the case of ❹ ,, the processing of the bait protects the right to use the CPU 150. - The processing of the Beco holding unit 320 maintains the RT0 RTOS to obtain the CPUl5 processing resources. When the data is used, the processing data holding unit 320 replaces the processing data for the RT0S of 156 and the processing data for the special register. In the following, the processing is explained by the work switching from work A to work B. A1. When Work A performs a system call, the system call variable and the system call 1D are recorded in a portion of the general purpose register 158. The A2· scratchpad switching control circuit 322 shifts the processing data of the job a to the processing data holding unit 32G' to carry the RT〇s processing data of the processing data holding unit 32() to the processing register 154. At this stage, RT〇s takes the right to use the CPU 150. A3. The register switching control circuit 322 inputs the write signal to the reserved register 1 l〇a, and stores the processing data for the work A of the processed data holding unit 32 to the reserved register 110. A4. The RTOS performs processing corresponding to the system call based on the variables and IDs of the system calls recorded in the general purpose register 158. In addition, the work status data of the tcb of the work a is set to "READY", and the TCB of the work A is added to the work preparation list.

Β1· Next, the RTOS selects RUN_Working 'here' to select the job B according to the above RUN job selection condition. The B2.RTOS instructs the scratchpad switching control circuit 322 to input the job selection signal of the designated job b to the load selection circuit 112. The processing data is moved from the retention register 110b to the processing data holding unit 32A. B3. The register switching control circuit 322 replaces the processing data holding unit

The work is processed by the processing data and the RT0S of the processing register 154. According to this, the work B obtains the right to use the CPU 150.

According to this processing method, the overall processing circuit size of the work processing apparatus 1 can be reduced as compared with the load processing control circuit 2 〇〇 ^. Although the RTOS is implemented as a software, the loading and storing of the processing data can be controlled by the signal from the register switching control circuit 322. When the network knife is connected to the processing register 154, the processing data holding unit 32, the loading and unloading circuit 112, and the holding buffer 11 is set to be parallel to the processing, the number of bits 7L of the processing is compared with The processing data is stored in (3) and the processing data is loaded from the TC £, enabling high-speed work switching. (Work processing device pair of the type in which the storage circuit 120 is not loaded) Fig. 17 is a circuit diagram of the work processing device 100 in which the storage circuit is not loaded in the work processing device 1A of Fig. 5. The interrupt interface circuit 324 is added to the unloaded storage circuit 120. From the processing 2 storage circuit 120, the processing data is stored in the TCB of the memory. The planting and storage of the material is realized by the RTOS of the software library. Therefore, in time, 'RTQS&amp; must temporarily obtain the right to use mmo. The process of switching from Work A to Guard B is explained in 56 200937294. When a work switching is performed by executing a system call, first, the software RTOS stores the processing of the work A in the TCB of the work A. Next, the processing data for the RTOS is loaded into the processing, and the processing is entered into the processing register I54. The processing method at this time is the same as that described with reference to Fig. 3. ❹ ❹ The software RTOS writes the parameters of the system call to the interrupt interface circuit. The execution control circuit 152 stops the cp clock. The t-break interface circuit 324 causes the work control circuit 200 to perform an operation switch. First, the work switching circuit 210 sets the work state register 258 of the worker #A to READY, and selects the next RUN-work job B by the output from the work selection circuit 23A. The work switching circuit 21 is provided. The interrupt interface circuit 324 is instructed to load the processing data of the job B. Here, the interrupt interface circuit restarts the CPU clock if the execution control circuit 152 is started. Also, the interrupt interface circuit 324 notifies the software RT0S that the operation is selected. The software rt〇s# takes the TCB of the work B, and the processing data of the work B is loaded into the processing register 15 [according to this processing method, the working processing device of the figure $ of the loading storage circuit 12 is shrinkable W is the overall circuit size of the processing device (10). Although the function of the RTOS is partially implemented as software, the work selection process can be implemented by the work control circuit 200. Compared with the software RT〇s illustrated in Figs. 2 and 3, the work processing apparatus 100 of Figs. 16 and p can harden a part of the function of the RT〇s. As illustrated in Fig. 16, since there is a load circuit 12, there is no need to store $TCB for the storage and loading of the processing data. Therefore, the storage and loading processing of the processing data can be performed by the scratchpad switching control circuit 322. Moreover, as shown in Fig. 57, 200937294, because of the existence of the work control circuit, the software RT〇s 让 gives the work selection function to the work control circuit. FIG. 5 illustrates the case where the load storage circuit and the work control circuit 靡2 are used as the processing device 1GG, and the work scheduling function of the RT〇s can be completed. Since the TCB of the memory is not required to be switched when the g operation is switched, the operation is performed. Switching processing can be faster. According to the experiment of the present inventors, it was confirmed that the satellite processing apparatus 100 of the present embodiment can operate at a speed of about 1 相 as compared with the general software RT 〇s explained in Fig. 3 and the like.

(Modification 1) When creating a computer program, "Queue" is an algorithm that is used and used at a high frequency. Due to the high speed of K-Ning's processing, it helps to improve the processing speed of computer programs. However, even F (four) (first in, first out:

Fim-In First_0ut), depending on the situation, there may be occasions when you want to delete (Last_In Fim_〇ut) or sometimes you want to use LIFO as the basic FIF〇 The situation of the action. In the improved example i, Xiao can also correspond to the special series of LIF〇; 寅 algorithm (below,

The work processing apparatus 100 of the hardware configuration called "double insertion type array algorithm" will be described. The work processing device of the mine is loaded with the work scheduling function according to the timer management. The basic work schedule is an algorithm that "only assigns execution rights to work with long wait time when the work priority order is the same". The following 'refers to this work schedule as a "fair work schedule."

In Fig. 11, 'the management method of the work-prepared tandem according to the concept of fair work schedule is explained. When the RUN-work job J returns to the REDM 58 200937294 state, it is connected to the last-end work F. Since work A becomes RUN-work after work, the TCB of each job is linked to the priority order of work priority "〇" in the order of work D, ..., work F, and work J. Work j, at least until the end of the execution of work F, will not be assigned to the execution of the &amp; flat work schedule, which is similar to FiF〇, which is the algorithm of the queue. Because of the time management algorithm, the fair work schedule can be hardware-built by timer management. ❹ ❹ On the other hand, in the software OS, most of the work schedules of "only when the work priorities are the same, the execution rights are preferentially assigned to work that is temporarily RUN-work" are used. The following 'this work schedule is called 're-execution priority work schedule'. When the priority work schedule is executed again, when t RUN-work j returns to the READY state, it is not connected to the last end but inserted to the front end. Since after work j is work A becomes face-work', so the TCB of each job, according to work, work D, ..., work? The order is linked to the priority index of the work priority order "〇". Work After the end of work A, the lights are again given before work D and work F. It is effective to execute the priority work schedule when there is a work that is temporarily assigned the execution right and only the total execution =. Execute again

The priority work is quiet, and the spoon TTt?M A匕3 UF〇, which is the stacking algorithm. In the improvement calculation: the hardware configuration of the U algorithm, which is based on _, can also be used to implement the priority work scheduling. Second, it is not limited to re-execute the priority work schedule. The hardware structure of the double-input type is also useful. Therefore, the double-input type (four) calculus structure is effective in processing speed of various computer programs. 59 200937294 0 ❹ FIG. 18 is a circuit diagram of the work processing apparatus ι00 of the modified example 1. The working processing apparatus of the modified example 1 100 also includes a CPU 150, a storage circuit 120, and a work control circuit 200. However, the operation switching circuit 210 of the first modification includes the main circuit 400, the write circuit 402, the array control circuit 404, and the maximum value selection circuit 406. The main circuit 400' has a circuit having substantially the same function as the basic operation switching circuit 210. Therefore, the configuration of the operation switching circuit 210 of the first modification is a write circuit 402, a line control circuit 404, and a maximum value selection circuit 406 which are added to the main circuit 400 of the operation switching circuit 210 as a basic example. All state data of all the operations are outputted from the state memory unit 220 to the operation selection circuit 23A at any time, and are output to the maximum value selection circuit 406 or the queue control circuit 4〇4 at any time. Fig. 19 is a circuit diagram showing a part of the operation control circuit 2 of the modification i. The basic configuration of the work control circuit 200 is substantially the same as that of the circuit shown in Fig. 1A. Corresponding to the status register of each job 25〇, including work (1)

The register 410, the work priority register 412, the queue sequential register 414, and the queue identification register 416. The state register 25() may also contain a direct register, but here the center is described centering on the register group associated with the dual-input queue algorithm. (A) Work ID register 410: As one type of element (1), the storage ID is the same as the guard register m of the basic example. The (10)_S signal indicating ... is rotated from the register 410 at any time. (B) Work Priority Order Register 412: Store Work Priority (PR) 60 200937294 Read-out at the same time The PR_S signal is the same as the work priority register shown in the basic example. () The sequence register 414: stores the "order value (〇DR)" indicating the order of insertion of the dummy string to be described later. The larger the sequence value is, the larger the value is placed in the virtual row, and the details will be described later. The sequence value is output as a 〇dr_s signal at any time. (D) Array Discriminating Register 416: Stores the "Queue ID (QID)" for identifying the virtual queue. It is output as a QID_S signal at any time. The work priority register 412, the queue sequential register 414, and the queue identification register 416' have the function of managing the queue register of the virtual queue. Queue. For example, the virtual knowledge column of qid = 〇 (hereinafter, the table s is "virtual child column (〇)") corresponds to the READ γ state, the virtual queue (1) corresponds to the flag waiting state, and the virtual queue (2) corresponds to the mutual exclusion. Waiting state. Alternatively, the virtual queue (1) corresponds to the flag waiting state of the flag ID=〇, and the virtual queue (2) corresponds to the flag waiting state of the flag ID=1. The correspondence between the qID and the working status can be arbitrarily set by the software. When the work A is in the READY state, the queue identifying the register 416_A s corresponds to the qid of the READY-shaped vain virtual queue. The operation selection circuit 230 or the array control circuit 404 can determine the operation state of each operation by referring to each of the array identification registers 4 to 6. Therefore, the queue identifying buffer 416 has a working state register 258, a standby reason register 262, a flag ID register 264, a mutually exclusive ID register 265, and an event id register. 266 and other similar functions. 61 200937294 The virtual character string does not exist physically. It is very important to imagine the green character column by the sequence register 4i4 or the identification of the register 416. For example, when the following settings are made by the 夂俨 夂俨 红 d 辨 辨 辨 416 416 416 416 416 416 416 416 414 414 414 414 414 414 414 , 工作 工作 工作 工作 工作 工作 = = = = = = = = 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 , 〇DR= 1 Work c: QID= 〇, 〇DR= 2 Work D: QID = 1, 〇DR= 〇

It means that the virtual character column (G) is placed in the order of c, B, and A, and the virtual column (1) is placed only in the work D. According to the numerical range of QID and 〇DR, the number and size of the virtual Suining column can be flexibly changed.

The second work selection circuit 230 selects the state transition to the state based on the state data 'outputted from the state register 25'. The main circuit side inputs the CND signal to the work selection circuit 230. The CND is a signal indicating a job selection condition, and includes a pR c indicating a work priority order of the queue (1). For example, when the virtual queue (0) is to be taken out of the work, the main circuit 4 sets QID_C_〇 at cnd. The work selection circuit 23 轮 rotates the work of the designated virtual queue (7) into the operation (hereinafter, simply referred to as "take-out operation") to EID-A1, and transmits EIDA1EN. Further, in pRA1, 〇DR_乂, the work priority order and the sequence value of the fetch job are output. In this manner, the main circuit 400, designating QID - c = Qn and inquiring the work selection circuit 23, thereby knowing the fetch operation of the virtual queue (Qn). The work selection circuit 23 has a function of selecting a take-out candidate circuit for taking out the work. More details will be described later with reference to FIG. The CND signal is input from the main circuit 4〇〇 to the maximum value selection circuit 4〇6. 62 200937294 The maximum value selection circuit 406 outputs the maximum sequence value of the virtual queue (Qn) to ODR_A2 and transmits EID_A2_EN when QID_C=Qn is specified by CND. More details will be described later with reference to FIG. 28. The queue control circuit 404 controls the state transition of each operation by setting the state data of each state register 250. The CMD and EID_C are input from the main circuit 400 to the array control circuit 404, and in addition, CND (QID_C, PR_C), 0DR_A1, ODR_A2, ODR_A2_EN and status data of each state register 250 are also input. 〇 CMD is an instruction to operate a virtual queue. The queue ID of the virtual queue, the job ID of the job, and the work priority are specified by QID_C, EID-C, and PR_C, respectively. The command is one of three types of ENQ-TL, ENQ-TP, and DEQ. When the input is placed in the instruction ENQ_TL, the job specified by the EID_C signal is placed from the last end of the virtual queue. Hereinafter, the placement from the last end of the queue is referred to as "positive insertion". When the fetch instruction DEQ is input, the work is taken out from the front end of the virtual queue. The queue control of FIFO ^ is performed by ENQ_TL and DEQ. When the reverse input command ENQ_TP is input, the job specified by the EID_C signal is placed from the front of the virtual queue. Hereinafter, the insertion from the front end of the array is referred to as "reverse insertion". Reverse insertion, not a FIFO, is a special placement method. When the CMD is input from the main circuit 400, the write circuit 402 transmits the WT, and executes the writing of each of the data output from the array control circuit 404 to the state register 250. The array control circuit 404, the write circuit 402, the operation selection circuit 230, the maximum value selection circuit 406, and the like have functions for controlling the virtual matrix of the virtual circuit. The circuit configuration of the array control circuit 404 will be described in detail with reference to Fig. 20 next. FIG. 20 is a circuit diagram of the train control circuit 404. The queue control circuit 404 is an aggregate of a plurality of register value generating circuits 420. Each of the register value generating circuits 420 is the same circuit. The register value generating circuit 420 corresponds to each operation. It can also be said to correspond to each state register 250. The register value generating circuit 420_EN corresponds to the operation of the work ID = En (hereinafter, referred to as "operation (En)"). The job ID of the job is fixedly input to the scratchpad value generating circuit 420 as an ELM_ID signal. ODR_S, QID_S, and PR_S are state data outputted from the state register 250, which respectively represent the sequence value, the queue ID, and the work priority. The order value, the queue ID, and the job priority of the operation (En) are input to the register value generation circuit 420_EN of the corresponding operation (En) as ODR_S_En, QID_S_En, and PR_S_En, respectively. CMD and EID_C are input from the main circuit 400. ODR_A2_EN and ODR_A2 are input from the maximum value selection circuit 406. 〇DR_A2, which represents the maximum sequence value, becomes a valid input when ODR_A2_EN is transmitted. 0DR_A1 is input from the work selection circuit 230. ODR-A1 indicates the work ID of the work to be taken out. QID_C and PR_C are CND signals input from the main circuit 400, respectively indicating QID and PR as job selection conditions. The register value generating circuit 420_EN outputs the order value, the queue ID, and the work priority of the operation (En) as QID_N_En, ODR_N_En, and PR_N_En, respectively, and writes to the state temporary storage when the write circuit 402 transmits the WT.器200937294 250_Εη 〇When the write circuit 4〇2 transmits WT B#, the Qj·-1矸 of all the register value generation circuits 420 QID N En, 〇dr n En, PR μ p is done - ~ Ν-· ^η, PR-N-En is written to all state registers 250. The scratchpad value generating circuit associated with the work affected by the CMD writes new data designated by the algorithm described later to the state register 250. On the other hand, the work-related scratchpad value generating circuit 420' which is not affected by the CMD also outputs the same material as the data written to the state register 250 again to perform writing. Further, the WT which temporarily stores the hard-to-generate circuit 42 is directly input to the slave train control circuit 404 instead of the state register 25. At this time, the register value generating circuit 42 is built in the register value generating circuit 404, and only the work register value generating circuit 42 corresponding to the change of the state is changed, and the new data is written to the state. The memory 250 is also available. The specific processing contents of the register value generating circuit 420 will be described later. Figure 21 is a conceptual diagram showing the relationship between a virtual queue and work. Here, it is assumed that there are two virtual queues of the virtual queue (Q0) and the virtual queue (Q1). The virtual tenant column (Q0) is used to put the work priority list pR = 伫 work priority column (hereinafter, the table is marked as "priority queue (Q〇: 〇)") and used to put work priority The set of the two priority queues of the priority queue (Q〇:丨) of the work of PR=i. The virtual queue is also the same, assuming there are essentially four priority queues. For example, the virtual queue (Q〇) corresponds to the READY state, and the virtual queue (Q1) corresponds to the WAIT state. For each virtual queue, the left side of the figure is the entrance and the right side is the queue of the extraction port. Put it into the work from the left side in the forward direction, and put it into the work from the side of the right 65 200937294 in the reverse direction. Take out the work and keep it from the right side. In the same figure, four jobs with job ID=EO, El, E2, and E3 are placed in the virtual queue. Work (EO) and work (E2), work (E3) are placed in the virtual queue (Q0). Among them, work (EO) and work (E3) work in the order of priority PR =0, so the priority queue (q〇 : 〇) is placed. Since the work (E2) is the work of PR== 1 ', the priority queue (q〇 :丨) is placed. The order value ODR of the work (E3), work (E2), and work (EO) placed in the virtual queue (Q0) is 2, 1, and 0. The work priority PR=: 工作 work (E1) is placed in the virtual queue (Q1). The ODR is "〇". © Fig. 22 is a data structure diagram corresponding to the state register 250 of Fig. 21. The put-in state of each job for the virtual queue shown in Fig. 21 is represented by the setting of the state register 250. In the state shown in Fig. 21, in the work (E〇)~Work (E7), the virtual queue is placed for work (E0)~work (E3). Therefore, the "other work" list discriminator 416 is set to indicate "Non" which is not placed. The job list discriminator 416 of the work (E〇), work (E3), and work (E2) placed in the virtual queue (q〇) is set to "q〇". Further, the queue discrimination register 416 of the operation (E1) placed in the virtual queue (Q1) is set to "Q1". By identifying the setting contents of the register 416, it is indicated which work is placed in which virtual queue. The three sequence (E〇), the work (E3), and the work (E2) queues 412 ’ placed in the virtual queue (Q0) are set to 〇, 2, and 1, respectively. The work of placing the virtual queue (Q1), because there is only work (E丨), the sequence value is set to the minimum "0". The position of each of the virtual queues is represented by the setting contents of the sequence register 414. 66 200937294 Work (E0), work (E1), work (E3) work priority PR is 〇" ° so 'the work priority register 412 is set to 0 in these jobs" ° due to work (E2) work Since the priority PR is "1", "1" is set in the work priority register 412_E2. The priority of the job is placed by the setting of the job priority sequence register 412. According to the above settings, the processing contents of the forward insertion, the reverse insertion, and the removal are described in detail. (Follow-in) Fig. 23 is a conceptual diagram when the work (E4) is placed in the virtual queue of Fig. 21 in the forward direction. Here, the case where the work priority order PR=〇 work (E4) is placed in the virtual queue (Q 1) will be described. The main circuit 4〇〇, CMD = ENQ_TL (forward put command) is set to EID_C=E4, QID_C=Q1, and PR_C=0. The register value generating circuit 420_E4 built in the slave column control circuit 404 outputs Qid_n_E4=QID_C = Q1, ODR_N_E4 = 〇, PR_n_E4 = PR_C = 0 when detecting E to EID_c=ELM_ID=E4. QID N-E4 system work (E4) The qID of the virtual queue to be placed, the order value when 〇DR_N_E4 is placed, and the work priority of PR_N_E4 system work (E4)" ODR_N related to the work of the forward insertion , the constant setting is "〇". This is the order value for the most recent placement of the queue. Not only the scratchpad value generating circuit 420_E4 but also the register value generating circuit 42A_En of QID_S_En = QID_C = Q1. The register value generating circuit 420_En 'outputs ODR_N_En = 〇DR_S_En + 1. Here, the register value generating circuit 420_E1 detects that qid_s_E1 = QID_C = Q1, 67 200937294 outputs ODR_Ν_Ε1 = 〇+ 1= !. 〇DR_N—E1 is the order value after the insertion (8)). The work that has been placed in the work (E4) is placed in the virtual queue (Q1) of the object, and the order value is affected. After this process, the status data of the work (E4) and work (E1) of the elements of the virtual queue (Q1) are adjusted. Figure 24 is a data structure diagram corresponding to the state register 25A of Figure 23. In the same figure, the portion of the add-on bottom line is the portion of the state register 250 shown in Fig. 22 where the content of the 疋 。 is changed. Since the work (E4) puts the forward direction of the virtual queue (1)]), the queue identification register 4丨6_E4 is set to "Q1" by qID_n_E4. After work (E4), DR is "〇" and PR is "〇". From the forward direction of work (E4), the ODR of the work (E1) that has been placed in the virtual queue (q) is increased from "〇" to "丨". The state of the virtual queue (q 1) shown in Fig. 23 is expressed by the setting contents of the changed state register 25A. Fig. 25 is a conceptual diagram when the work (E5) is placed in the virtual queue of Fig. 23 in the forward direction. Here, the case where the work priority (PR) of the work priority order PR = i is placed in the virtual queue (Q0) will be described. The main circuit 400, CMD = ENQ_TL (direct input command), sets EID_C = E5, QID_C = Q〇, PR C = 1. The temporary buffer value generating circuit 420_E5, the output QID_n_E5 = QID C = Q0, ODR N - E5 = 0, PR N E5 = PR C = 1 〇 - __ 鼍 not only the register value generating circuit 420 E5, QID_C = QID_S The register value generation circuit 420_En of En = Q0 outputs ODR_N_En = ODR_S_En + 1 when qid_C = QID_S_En is detected. In this example, it is a register value generating circuit 420 corresponding to the work (E0), the work (E2), and the work (E3). For example, the status data of the work (E5) and work (E0), work 68 200937294 (E2), and work (E3) of the elements of the virtual train (Q0) are adjusted. FIG. 26 is a data structure diagram corresponding to the state register 250 of FIG. 25. In the same figure, the portion to which the bottom line is attached is the portion where the setting contents of the state register 250 shown in Fig. 24 are changed. First, since the work (E5) puts the virtual queue (Q0) in the forward direction, the queue identification register 4丨6_E5 is newly set to "Q0". The ODR of the work (E5) is "〇" and the PR is M". Due to the forward placement of the work (E5), the work (E〇), work (E1), and work (E3) that have been placed in the virtual queue (q〇) are increased respectively. Figure 27 is a flow chart showing the processing of the forward insertion. The main circuit 400' sets the insertion condition (s 1 〇) associated with the forward insertion operation (hereinafter referred to as "forward placement work"). Specifically, CMD = ENQ TL '6 and 疋 EID C, QID_c, PR_C. Among the array control circuit 404, the register value generating circuit 42A corresponding to the forward direction is placed in the work priority order register 412, the queue sequential register 414, and the column identification. The register 416 is set to pr_c, 〇, qid c (s12), respectively. When the virtual queue (QID_C) has been put into other work (Yes in S14), the ODR (S16)e is added to the work that has been placed, and the example shown in Fig. 25 is performed, and the work (others) and work (E2) are performed. Work (E3) increases 〇DR. The processing of su, sm, and si6 is performed substantially simultaneously in time. (Reverse Insertion) FIG. 28 is a circuit diagram of a portion of the maximum value selection circuit 4〇6. The large value selection circuit 406 is a circuit for performing the reverse insertion processing and being driven by the main circuit 400. The maximum value selection circuit 4〇6, when a Qn is input as the CND signal, outputs the maximum order value of the virtual queue (Qn) to 69200937294 to ODR_A2, and transmits ODR_A2_EN. The maximum value selection circuit 406 is the same as the execution selection circuit 232 and the flag selection circuit 234 shown in the basic example, and is constituted by a comparison circuit of a plurality of stages. The maximum value selection circuit 406 includes four first comparison circuits 422 (422a, 422b, etc.), two second comparison circuits 424 (424a, etc.), and one third comparison circuit (not shown). Further, eight decision circuits 426 (426a, 426b, 426c, 426d, etc.) are included. The description will be focused on the first comparison circuit 422a. The first comparison circuit 422a compares the operation 工作 with the job 1, and when both are placed in the virtual queue (Qn), the operation with a large sequential value is selected. The job ID and the sequence value of the job 0 and the job 1 are input to the first comparison circuit 422a as 〇 EID_S and ODR_S. First determination: The determination circuit 426a transmits the EID-11A_EN if the operation is placed in the virtual queue (Qn). The decision circuit 426b transmits EID_11B-EN if the job 1 has been placed in the virtual queue (Qn). The first comparison circuit 422a first refers to the EID_11_EN signals output from the determination circuit 426a and the determination circuit 426b, respectively. When one of them is "j", only one of the jobs has been placed in the virtual queue (Qn). At this time, the first! The comparison circuit 422 &amp; outputs the work ID (EID_S) and the order value ◎ (ODR_S) of the work placed in the virtual queue (Qn) as EID-21A, 〇DR_21A, and transmits EID_21A_EN. When both the decision circuit 426a and the decision circuit 42 output "〇", neither of the two jobs are placed in the virtual queue (Qn). At this time, the transmission of the EID 21A EN is stopped, and thereafter, the work is not considered to be the object of the second comparison circuit 424a, fch π, and A from the scam. When both the determination circuit 426a and the determination circuit 426b output "丨", the two 70 200937294 jobs are placed in the virtual queue (Qn), and at this time, the next second determination is executed. The second determination is to compare the work 〇 DR_S_0 with the work 1 〇 DR-S_i ’ selection order value. The i-th comparison circuit 422a outputs an operation ID (EID_S) and a sequence value (〇DR-S) of the operation having a large sequence value as EID-21A and 〇DR_21A, respectively, and transmits EID_21A_EN.

The processing contents of the other first comparison circuit 422 are also the same, respectively comparing work 0 with work 1, work 2 and work 3, work 4 and work 5, work 6 and work 7. The second comparison circuit 424 further selects an operation having a large sequence value from the outputs from the two first comparison circuits 422. The second comparison circuit 424a will be described with a focus. The second comparison circuit 424a compares the output signal of the ith comparison circuit 422a with the output signal selection order value of the ith comparison circuit (4). EID-2 〇DR_2丨, eid_en are input from the ith comparison circuit and the U comparison circuit 422b to the second comparison circuit 424a, respectively. The f 2 comparison circuit 424 selects the work g to the work 3, and the second comparison circuit 424 having the largest order value among the virtual queues (Qn) is also the same, and finally, the virtual queue (Qn) The maximum sequential value output is used as the ODR-A2 signal. When you select any of the guards, the transfer surface—Μ, does not exist for any work; ^ _ 4 stops when the virtual queue (Qn) stops transmitting ODR A2 EN.

Further, the PR invalid signal for determining the priority order I 疋 ... can also be input to the first comparison circuit 422, the ninth private &amp; music 2 comparison circuit 424, and the third comparison circuit. When the PR invalid signal is transmitted, each of the private &amp; comparison circuits removes the priority order from the decision condition to select a job. Figure 32a is also the same for each comparison circuit. Figure 29 is a concept when the work (Ε6) is reversed into the virtual row of 囫25. 71 200937294 Figure. Here, a case where the work (E6) of the work priority order PR = 1 is reversely placed in the virtual queue (Q0) will be described. First, the main circuit 400 inputs the QID=Q0 of the placed object to the maximum value selection circuit 406 by the QID_C signal. The maximum value selection circuit 406 outputs the maximum sequence value of the virtual matrix (Q0) as the ODR_A2 to the array control circuit 404, and transmits the ODR_A2_EN. As shown in Fig. 25, since the maximum order value of the virtual queue (Q0) is "3" of the operation (E3), ODR_A2 = 3. Next, the main circuit 400, CMD = ENQ_TP (reverse input command), sets EID - C = E6, QID_C = Q0, PR_C = 1. At this time, the register value generating circuit 420_E6 built in the slave column control circuit 404 outputs QID_N_E6 = QID_C = Q0, ODR_N_E6 = ODR_A2 + 1 = 3 + 1 = when EID_C = ELM_ID = E6 is detected. 4. PR_N_E6= PR_C= 1. When CMD = ENQ_TP (reverse input command), only the register value generating circuit 420 corresponding to the operation specified by EID-C operates. Therefore, only the status data of the work (E6) placed in the reverse direction is changed. FIG. 30 is a data structure diagram corresponding to the state register 250 of FIG. In the same figure, the portion to which the bottom line is attached is the portion where the setting contents of the state register 250 shown in Fig. 26 are changed. First, since the work (E6) is placed in the reverse direction of the virtual queue (Q0), the queue identifying buffer 416_E6 is newly set to "Q0". The ODR of the work (E6) is "4" and the PR is "1". Due to the reverse placement of work (E6), the status data of other jobs is not affected. Figure 3 is a flow chart showing the process of reverse insertion.

The main circuit 400 first inputs QID 200937294 = Qn, which is placed in the virtual queue of the object, to the maximum value selection circuit 406 (S20). The main circuit 400 outputs the maximum order value of the virtual matrix (Qn) to the array control circuit 4〇4 (S22). The main circuit 400 sets the insertion condition (S24) associated with the reverse insertion operation (hereinafter referred to as "reverse insertion work"). Specifically, CMD = ENQ TP (Reverse Insertion Command)' sets EID_C, QID_C, and PR_C. Among the queue control circuit 404, the register value generating circuit 42A corresponding to the reverse insertion operation is respectively placed in the work priority register 412, the queue sequential register 414, and the queue identification The register 416 sets pR_c, maximum order value + Bu® QID-C (S26). However, when the maximum order value = 0 and the transmission of ODR_A2 - EN is stopped, that is, when the work is not placed in the virtual queue (Qn), the sequence order register 414 is set to indicate the order value of the initial insertion. "〇". As described above, when placed in the forward direction, it is possible to produce an adjustment of the order value of other work, but such adjustment is not required in the reverse insertion. When FIF〇 is used to observe the virtual queue, the earlier the work is set, the larger the order value is. That is, the deeper the work order value is, the deeper it is placed into the virtual character column. Conversely, it is also sighing that the deeper the work order value is, the smaller the value is placed. At this time, when the forward direction is placed, the adjustment of the order value of other work is not required, but the adjustment of the order value of other work may occur in the reverse insertion. (Removal) Fig. 32 is a circuit diagram of a portion of the operation selection circuit 23. The basic configuration of the work selection circuit 230 is as shown in the basic example of (4). The modified example 1 is J/p · * ς ε ^ Λ , and the circuit 23 is selected. When receiving the S from the main circuit 400, the specific sampling is performed. Here, the configuration of the Lei Zheng JLtt Vs circuit for specifying the structure of the take-out work will be described. The work selection circuit 230, when inputting 73 200937294 QID_c = Qn as the CND signal, selects the work in the virtual queue (Qn) from the highest priority column of the work priority order, and takes the job ID work priority order, The sequence values are output to EID-A1, PR_A1, 〇DR_A1, respectively, and EID-A1_EN is transmitted. The operation selection circuit 23 is the same as the basic selection control circuit 232 and the flag selection circuit 234, and is composed of a plurality of comparison circuits. The operation selection circuit 23A includes four ith comparison circuits 43G (43Ga, 4鸠, etc.), two second comparison circuits 432 (4 仏, etc.), and 1 (four) third comparison circuits (not shown). Further, eight decision circuits 434 (434a, 434b, 434c, 434d, etc.) are included. Focus on the first! The comparison circuit 43A will be described. The first! When the comparison circuit 43 〇 &amp; comparison work 〇 and work 〗 〖 are placed in the virtual queue (8) η), the work with high priority is selected. When the work priorities are the same, select a job with a large order value. The work m and work i, the work priority, and the sequence value are input to the 帛1 comparison circuit 430a as EID_S, PR_S, and 0DR_S. The first determination: the determination circuit 434a, if the operation 0 has been placed in the virtual queue (Qn) ), then send EID_1 1 A_EN. The decision circuit 434b transmits EID_UB_EN if the job i has been placed in the virtual queue (Qn). The first comparison circuit 430a first refers to the EID-n_EN signals output from the determination circuit 434 and the determination circuit 434b, respectively. When one of them is Γι, only one of the jobs has been placed in the virtual queue (Qn). At this time, the i-th comparison circuit 43Aa outputs the work ID (EID_s), the work priority order (PR_S), and the order value (ODR_s) of the work placed in the virtual queue (Qn) as eid_21A, PR, respectively. One 11A, ODR_21 A, transmits EID 21A ΕΝ. 74 200937294 When both the decision circuit 434a and the decision circuit 434b turn "〇", neither work is placed in the virtual queue (Qn). At this time, the stop transmission EID_21A_ENm is not considered as the second comparison circuit 432a. When both the determination circuit 434a and the determination circuit 434b output "丨", both jobs are placed in the virtual queue (Qn), and at this time, the next second determination is executed. ❹ Ο 2nd judgment: Comparing pR_s of work 〇 with pR of work ι, select work with high priority, ie, 'pR-s is small. The completion comparison circuit 430a' outputs the work priority ((10)", the work priority order (PR_S), and the sequence value (〇DR_s) of the work with high priority order as eid-2 i A, PR-21A, 〇DR_21A, respectively. , Eid_21a-EN is transmitted. When the work priorities of the two jobs are the same, the next third judgment is executed. The third judgment: comparing the work 〇 DR_s_〇 and the work 丄 ODR_S, select the order value Large work. 帛i compares the circuit, and outputs the work WD (EID_S), work priority (pR S), and sequence value (ODR_S) of the sequence value as eid_2ia, pR HA, 〇DR_21A, respectively, and transmits eiD 21a_en - The processing contents of the other first comparison circuit 430 are also the same, respectively comparing the work 0 with the work work 2 and the work 3, the work 4 and the work 5, the work 6 and the work 7. The second comparison circuit is cut, from the 2 First, compare the output of the electric H 'to further lock the candidate for the fetching work. Finally, from the virtual crayin to the highest priority in the work priority order (four), select the work out:. When you select any job, pass $(10)-A, and stop when any work does not exist in the virtual queue (Qn). (4) EID_A[en. 75 200937294 Fig. 33 is a conceptual diagram when the work (E3) is taken out from the virtual queue of Fig. 29. Here, a description will be given of a case where one job is taken out from the virtual queue (Q0). The main circuit 400 inputs QID_C = Q0 to the operation selection circuit 230. As shown in FIG. 29, in the priority queue (Q0: 0) corresponding to the highest priority among the virtual queues (Q0), the work of the order value "1" (E0) and the order value "3" are placed. (E3). The work selection circuit 230 selects the work (E3) having a large sequence value as the take-out work. The operation selection circuit 230 sets EID_A1 = E3, PR_A1 =0, ODR_Al = 3, and transmits EID_A1_EN. Next, the main circuit 400, CMD = DEQ (fetch instruction), sets EID_C = EID_A1 = E3, QID_C = Q0. Register value generation circuit 420-E3, output QID_N_E3= Non, ODR_N_E3=0 (reset), PR_N_E3 = 〇 (reset). In this manner, the state register 250 deactivates the relationship between the operation (E3) and the virtual queue (Q0). Not only the scratchpad value generating circuit 420_E3, QID_S_En = QID_C = Q0, the scratchpad value generating circuit 420_En, when detecting QID_C = QID_S_En, it is determined to be ODR_S_En &gt; ODR_Al. Here, ODR_Al is the order value before the take-out operation (E3) is taken out. If ODR_S_En &gt; ODR_A1, that is, the register value generating circuit 420_En of the operation (En) whose sequence value is larger than the order value of the fetch operation, the output ODR_N_En = ODR_S_En-1. The example shown in Fig. 29 corresponds to the register value generating circuit 420_E6 of the operation (E6). The register value generating circuit 420_E6 outputs ODR_N_E6 = ODR_S_E6 - 1 = 4 - 1 = 3. In this way, the status data of the work (E6) of the elements of the virtual queue (Q0) is adjusted. FIG. 34 is a data structure diagram corresponding to the state register 250 of FIG. 200937294 The portion of the 'attachment of the bottom line' in the same figure is the portion where the setting contents of the state register 250 shown in Fig. 3A are changed. First, since the operation (E3) is taken from the virtual queue (4), the "N〇n" is newly set in the queue identifying buffer 416_E3. Further, "伫" is set as the reset value in the queue sequential register 414 and the work priority register 412, respectively. Due to the removal work (E3), the work that was originally placed in the virtual queue (Q0) (E〇), work (E2), work (E5), and work, the order value is larger than the work (E3). The 〇DR of E6) is reduced. Figure 35 is a flow chart showing the process of taking out. The main circuit 400' first inputs Qm = Qn of the virtual queue of the extracted object to the work selection circuit 23 (S3). The job selection circuit 23A selects the fetch operation from the virtual chopping block (Qn) (S32). The main circuit 4〇〇, when the work ID ID of the take-out operation is input to the sorting control circuit 4〇4, the control circuit buckle 4 is cut, and the state data of the take-out operation (En) is cleared QID=Qn (S34). At this time, PR and ODR are reset to "〇", but they may not be reset. In the virtual queue (Qn) is also put into other work (S36 is), when the work of DR_s En &gt; 〇dr_a1 exists (S38 is), the order value of the work is reduced (S4〇h, in addition, from S3〇 The processing shown in S4〇 does not have to be performed in sequence, and can be performed in parallel in time. In the configuration, the work can also be taken out from the virtual queue. For example, in Figure 33, the generation is to be from the virtual queue ( Q0) The necessity of taking out the work (E2) in the center of the work. (E2) is a work that can be operated under the condition that a flag A is set to be on. When the flag A is disconnected, it is generated from the virtual character. When the job is taken out on the way (Q〇) (the necessity or the waiting time of the work (E2) is paused, the necessity of taking out the work 77 200937294 (E2) from the virtual queue (Qq) is also generated. At this time, (10) of the clearing work (E2) can also take out the work (Ε2) β from the way of the virtual train (Q0) by reducing the work of the order which is larger than the order value "2" of the work (E2). In the case of Fig. 33, the ODR of the work (10) is "2". Since the virtual (four) system is formed to be free from the physical limit of the hardware. Therefore also be carried out on the way into the queue, fetch process.

According to the virtual queue control shown above, a special array based on FIFO and implementing LIF〇 operation can be realized by hardware logic. If the double-input type array algorithm is configured in software, it is usually the structure of the link_column. However, as long as it is handled by the software, it is necessary to generate a payload accompanying the management of the access and address of the memory. On the other hand, the virtual matrix control shown in the modified example is realized by hardware logic, so that particularly simple and high-speed control can be realized. In particular, in the time-critical RT〇s, it is very important to put the double-input type array algorithm into the hardware assembly. Next, the form of re-execution of the priority work schedule is realized by the above-described virtual queue control method. Fig. 36 is a first conceptual diagram showing the relationship between the virtual queue and the work in the re-execution of the priority work schedule. Here, it is assumed that two virtual queues of the virtual queue (q0) corresponding to the READT state and the virtual queue (qi) corresponding to the state of the WAIT flag are assumed. The virtual character column (Q0) is used to put the priority of the job with the work priority PR= ( (the following table is marked as “priority queue (Q0: 〇))) and used to put the work priority PR= The priority queue of the work of 1 (Q〇: 1) is a collection of two priority queues. The virtual queue (Q1) is also the same, assuming that there are essentially four priority queues. In the same figure, the work of PR=1 (E1) is in the RUN state, and the same work of PR=丄 78 200937294 (E0) and work (E2), and the priority queue (QO: 1) stands by in the READY state. Also, the work of PR=0 (E3) stands by in the priority queue (Q1: 0) in the WAIT flag state. Here, it is assumed that the work (El) is a work that is collectively prioritized after execution. First, the RUN state operation (E1) performs the canceling of the flag system call and returns to the READY state (S1). Since the job (E1) is a work that is performed only quickly, the "reverse put" priority queue (Q0: 1). On the other hand, by releasing the flag system call, the WAIT release condition of the work (E3) is established. Take the work (E3) from the priority queue (Q1: 〇) and put the priority queue (Q0: 0) (S2) in the forward direction. Next, the work selection circuit 230 selects a new RUN_work. The work selection circuit 230 selects the work (E3) having the highest priority in the work from the READY state as the take-out work. In this way, the work from the WAIT state to the READY state (E3) is taken out from the priority queue (Q0: 0) to become the new RUN-work. According to this work schedule, work with a high priority order can be executed quickly when the WAIT release condition is established. ® Figure 37 shows the second conceptual diagram showing the relationship between the virtual queue and the work in the re-execution of the priority work schedule. When the work (E3) executes the standby flag system call, the work (E3) is placed in the priority queue (Q1: 〇) (S4). Next, the work selection circuit 230 selects a new RUN-work. The work selection circuit 230 selects the work having the highest work priority from the work of the READY state, but the work priorities of the work (E0), the work (E2), and the work (E1) are the same. At this time, the work (E1) (S5) is taken out from the priority queue (Q0: 1). Work (E1) becomes the new RUN-work. 79 200937294 According to this processing method, although it is not set to the work priority order PR = 0, it can correspond to the work (El) which is only possible to be continuously executed after execution. The priority work schedule is re-executed, and the forward and reverse insertions are used according to the execution status and the work type, thereby controlling the execution order of the work. Therefore, the characteristics of the high-speed processing performance of the work processing apparatus 100 shown in the basic example can be maintained, and a more refined work schedule can be realized. (Modified Example 2) Next, as an improvement example 2, the speed of the auxiliary processing of the work processing apparatus 100 will be described. In the work processing apparatus 100 of the second modification, the HWF (Hardware Function Module) performs auxiliary processing. Here, the HWF is a so-called auxiliary processor and has a function of an auxiliary processing circuit. Auxiliary processing is performed as part of the work, such as floating point arithmetic, DMA transfer, encryption and decryption processing, coordinate calculation of 3D images, etc., and has various processing contents. First, a control method of the general auxiliary processing of the software OS will be described. Next, a control method of the auxiliary processing of the work processing apparatus 100 of the second modification will be described. Fig. 38 is a view showing the configuration of a general circuit when the auxiliary processing is executed by the software OS. The CPU 84 is connected to the HWF 500 via a CPU bus 512 and a memory (not shown). Further, the CPU 84 is connected to the interrupt controller 502, the interrupt controller 502, receives various interrupt signals from the HWF 500 or the like, and transmits an interrupt signal (INTR) to the CPU 84. After receiving the interrupt signal (INTR), the CPU 84 appropriately performs the processing of the corresponding interrupt signal (INTR) by special work. As shown in Fig. 2, the CPU 84 executes the software OS, and performs general work or special work at its upper level 200937294. J and "parallel auxiliary" are not available for execution. Even in the course of execution, the auxiliary processing can be divided into two types: "serial-type auxiliary processing and processing". In the case of tandem auxiliary processing Perform other work. In the case of side-by-side auxiliary processing, other work can be performed in parallel. Figure 39 shows the timing of the control method for general serial auxiliary processing.

First, the job A issues an "interrupt prohibition command" as a system call (sl〇〇) for occupying the hWF500. Here, the target is the FPU (Floating Point Unit). When the "interrupt prohibition command" is issued, the operation switching is stopped before the "interrupt release command" is issued later. In the following, the interrupt prohibition command is set to interrupt the money, and the period until the command is released is "J Lang is the interrupt prohibition period". Special work does not start even if the input interrupt signal (INtr) is lost during the interrupt prohibition period. In the interrupt prohibition period, the work A monopolizes the use right of the CPU 84. Therefore, work outside of Work A will not access hwf5〇〇, Secretary. After the software 0S sets the interrupt prohibition, the 'work A return processing (8) 〇 2). Work A instructs the HWF 500 to perform an auxiliary process (sl〇4). In order to suppress the payload associated with the auxiliary processing control, the work A does not directly write the parameters to the built-in register of the HWF 500 through the software (10), instructing the execution of the auxiliary processing. The HWF 500 performs the auxiliary processing indicated by the work A. Work A, while periodically checking the built-in scratchpad of hwf5〇〇 while waiting for the auxiliary processing to end. After the completion of the auxiliary processing is detected (S106), the operation A issues an interrupt release command (S1〇8). After the software 〇s receives the interrupt release command, 81 200937294 cancels the interrupt prohibition (8) bucket ends the interrupt in this way. os performs the work switching, and writes a software to be executed, such as work (). After that, the execution rights are assigned to the work Β. The same method uses the HWF500. When the work is commissioned by Hwf to perform auxiliary processing, another work, such as special work overwriting hwfsdo recognizes π», you can't receive the correct processing result. Therefore, there is an exclusive way to control HWF5. . The possession 'however, each = software os can also access HWF5〇〇. For example, in si〇4, work j directly accesses HWF500 through software os

Proper management of HWF500's possession description # In order to enable the software 〇S to have the right, an "interrupt prohibition command" and a break release command are issued for the job. Software 0S, by interrupting the prohibition command, it can be prevented in advance from the auxiliary processing. You can use the __ 吐 this way to work A. In the case of 胄', there will be no other work to obtain the right to use the CPU 84, dry the HWF500. In the case of Fig. 39, the period from the timing of (4) 2 to the timing of Chuanxiong becomes the interrupt prohibition period. ❹ The case of the tandem type auxiliary processing 'is substantially other work during the interrupt prohibition period. That is, in the tandem type auxiliary The processing is as short as the auxiliary _ = the usage right of the CPU 84 cannot be obtained. Therefore, the auxiliary processing in which the floating point operation can be completed over time is preferably the serial type auxiliary processing. Fig. 40 shows the general parallel type auxiliary processing. Timing diagram of control method 0 First work A takes the use right of HWF500 as the waiting condition, and issues a standby flag system call or standby mutual exclusion system call, etc. &lt; (4) Ding system 82 200937294 call (S 120). Here, standby The system call is used as an object. This standby mutex system call is issued as an instruction to request the possession of the HWF500. In addition, the HWF500 which is the object here is set to DMAC (DMA controller). When the software OS receives the standby mutex system call, the HWF 500 that works outside the work A is accessed by mutual exclusion, that is, the DMAC is prohibited from being accessed (S122). In this way, the HWF 500 is temporarily occupied by the work A. The OS selects the next work to be performed. Here, the description is continued by selecting the work A again. The work A instructs the HWF 500 to perform the auxiliary processing (S124). Here, the work A also directly performs the auxiliary instruction to the HWF 500 through the software OS. Processing. HWF5 00 performs the indicated auxiliary processing. Work A ends the auxiliary processing as a standby condition, and issues a WAIT system call such as a standby event system call (S 126). Work A moves to the WAIT state. The software OS performs work switching, selecting The next RUN_work, for example, work B (S128). Work B is executed in parallel with the auxiliary processing. However, since HWF500 is occupied by work A, work B cannot use HWF500. HWF500, transmits interrupt signal INT (INTR) when auxiliary processing ends (S130) When the software 0S detects the interrupt signal (INTR), the special operation as the interrupt processing program is started (S132). Special work, first, by setting The SET system call such as the event system call, and the auxiliary processing ends the event notification (S134). In this way, the standby condition of the standby event system call issued by the work A is established. Again, the execution right is moved from the software 0S to the special work. (S 13 6). After the special work has executed the remaining processing, it moves to the STOP state (S 13 8). The software 0S acquires the execution right again, and after the special work is finished, the work switching is performed (S 140). Here, select again. Work A. 83 200937294 Since the auxiliary processing of the work A delegation has ended, the work A reads the processing result from the built-in register of the HWF500 (S142). Or, the work A reads the HWF5〇〇 and writes the result to the predetermined area of the memory Zhao. Work A issues a repelling system call (S144). After the software 〇S receives the call to release the mutual exclusion system, the work A is released from the HWF5 ( (3146). The software 〇s performs a work switch and selects the next work to be performed, such as worker # C(8) 48). In the future, the right to hold is assigned to work C. Since the possession of HWF5〇〇 has been removed, 'Work C can also use HWF5〇〇 in the same way.

P is in parallel type, and the point of direct access to HwF5 in general work is also the same as the serial type. For the side-by-side auxiliary processing, although the HWF500 cannot be used for other work in the auxiliary processing, it is possible for him to work for the CPU 84. In this way, when working with the HWF500, other work does not interfere with the HWF500. π sub-column type subsidy and 'system call due to _ or 8134: special: 〇 ==”=:: help processing the payload is more "this, 曰1 auxiliary processing, parallel-type auxiliary processing is better. The case of the tandem type auxiliary processing shown in :39 issues a system call. X, after the start of the auxiliary processing, page 2 2 Detecting whether the auxiliary processing is assisted or not, and the timing of the completion of the processing __ assist processing is 2, and =, the processing efficiency is lowered. Difference J, the side-by-side auxiliary shown in Figure 40, makes a system call 4 times. Furthermore, at the end of the auxiliary processing,: =: 84

❹ 200937294 Notification of the end of the auxiliary processing, special work must be started. - Proverbs 'm (four) called flower f 5 (10) ~ coffee degree degree =. Auxiliary department consumes a high frequency of processing, and the requirements between the materials are strict = 〇S, 'How much can this kind of payload be suppressed? The design is important. Figure 41 shows the work of the basic example. A diagram showing the circuit configuration when the processing device 100 realizes the auxiliary processing control as shown in FIGS. 38 to 40. As explained in the basic example, the work processing apparatus 1 is mainly c-cut, the storage circuit 120, and the work control circuit eagle. 38: In the case of the general circuit configuration, the CPU 84 executes both the software 〇s and the operation. In the work processing apparatus 100, the CPU 150 performs the operation, and the function of the 〇s is performed by the storage circuit 12 and the operation control. Circuit_implementation. f The external processing of the function of 〇s from CP_, the overall processing efficiency is greatly improved as explained in the basic example. In Fig. 41, cpui5Q is also connected to the HWF 500 through the CPU bus 512. In the case of the hardware OS of the work processing apparatus 100, the system call is executed, and the switching is performed at a relatively large speed with the software 〇s. Work Processing Unit 1 In order to perform 1 system call, the CPU clock only needs 12 clocks. Therefore, even with the circuit configuration of Fig. 41, by the work processing apparatus 1 executing the auxiliary processing controller J shown in Fig. 39 &amp; 40, the payload accompanying the auxiliary processing is greatly suppressed. In the second modification, the relationship between the work processing apparatus 1 and the HWF 5, in particular, the relationship between the CPU 150 and the HWF 500, can further increase the speed of the auxiliary virtual memory. 85 200937294 Fig. 42 is a circuit configuration diagram showing the relationship between the work processing apparatus 100 and the HWF 500 of the second modification. In the figure, a plurality of HWFs 500 (HWF500-0, ..., HWF 500_k: k are arbitrary natural numbers) are not connected to the CPU 1 50 but to the work control circuit 200. Each HWF500 is a dedicated circuit designed for different auxiliary processing. For example, HWF500_0 is FPU and HWF500_1 is DMAC. Each HWF 500 is identified by HWFID in the range of 0 to k. With the work performed by the CPU 150, the HWF 500 is caused to perform auxiliary processing through the work control circuit 200. Work cannot directly access the built-in 暂 register of the HWF500. In the second modification, the work control circuit 200 manages each HWF 500. Fig. 43 is a circuit diagram showing the relationship between the state memory unit 220 and the operation switching circuit 210 of the second modification. The HWF standby selection circuit 510 is added to the operation selection circuit 230 of the second modification. Further, a plurality of HWFs 500 are newly connected to the work switching circuit 210. The basic configuration of the operation control circuit 200 is substantially the same as that of the basic example shown in Fig. 10. The state register 250 corresponding to each work includes the HWFID register 504, the queue sequential register 506, and the queue in addition to the work ID register 254, the work priority register 256, and the like. The register 508 is identified. (A) HWFID register 504: When a certain work instruction performs auxiliary processing, the HWFID of the HWF 500 of the execution subject of the auxiliary processing is set. The HWFID is output as a HID_S signal at any time. In the second modification, in the HWFID register 504, the HWFID is written only in the parallel type auxiliary processing. 86 200937294 (B) Array Sequence Register 506: Stores the "Order Value (ODR)" indicating the order in which the work of the virtual queue is placed. The larger the order value, the deeper the placement into the virtual queue. The sequence value is output as a 〇DR_s signal at any time. The order value 〇dr of the modified example 2 is the same as the "order value 〇DR" described in the modified example. (CM 辨 辨 暂 暂 508 508 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 508 储存 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 508 The same concept is used. The virtual queue is the same as the virtual array shown in the modified example 1, and is a virtual queue corresponding to the working state. In this way, the correspondence between the queue ID and the working state need not be fixed to be hard. The work selection circuit 23 can determine the operating state of each job by referring to each of the queues identifying the register 508. The work selection circuit 230 selects the state transition based on the state data output from the state register 250. The work switching circuit 2 丨〇 inputs hwfid to the HWF standby selection circuit 510, and the H WF standby selection circuit 5 〇 outputs the work ID set by the HWFID register 5〇4 corresponding to the HWFID. That is, the operation of "waiting for the end of the processing of the designated HWF 500" is notified to the work switching circuit 210. If the designated HWF 500 is not processed, that is, the processing is not requested, the Hwf standby selection circuit 510 outputs " One 1" Each HWF 500 is directly connected to the operation switching circuit 210. Each of the HWFs 500 is connected to the following six kinds of signal lines by the operation switching circuit 2 。. Hereinafter, i is an arbitrary number of 0 to k. HFi_REQ: The work switching circuit 210 transmits the HFi_REQ » b. HFi_ARG[m - 1 : 0]: the parameters of the transmission auxiliary processing when the HWF500 is instructed to perform the auxiliary processing of the 200937294 line. There are various HFi_ARG[m- according to the contents of the auxiliary processing. The size of 1 : 0] also has the number of various parameters. When transmitting HFi_REQ, write HFi_ARG[m-1 : 0] to the built-in register of HWF500_i. c. HFi_RQACK : Transfer HFi_REQ, write HFi_ARG After [m-1: 〇], the HWF500_i starts the auxiliary processing. When the auxiliary processing starts, the HWF500_i transmits the HFi_RQACK. With the HFi_RQACK, the work switching circuit 210 recognizes that the auxiliary processing is started. d. HFi_CMPLT: After the auxiliary processing ends, the HWF500" The result of the processing is written to the outside of the built-in register, and HFi_CMPLT is transmitted. By HFi_CMPLT, the work switching circuit 210 recognizes the end of the auxiliary processing. e. HFi_RSLT[m - 1: 〇]: indicates the return of the result of the auxiliary processing There RSLT [m - 1: 0] based on the contents of various auxiliary processing HFi_ number of dimensions, also a variety of built-in return value registers HWF500 "the transfer of the return value is written. The work switching circuit 210 obtains a return value of HFi_RSLT [m-1: 0] after transmitting HFi_CMPLT. f. HFi_CMPACK: The work switching circuit 210 transmits HFi_CMPACK after obtaining the return value. With HFi_CMPACK, HWF500-i recognizes that the return value is normally obtained. Fig. 44 is a timing chart showing a control method of the tandem type auxiliary processing of the second modification. In the work processing apparatus of the second modification, the "HWF call" is added in addition to the nine system calls described in the basic example. "HWF Call", Departmental 200937294 Indicates a system call that performs auxiliary processing. First, the job A issues an HWF call (S 1 00) with the type of the auxiliary processing to be the object as a parameter. For example, the type of the auxiliary processing is specified by a floating point arithmetic instruction, a DMA transfer instruction, an encryption processing instruction, or the like. The work switching circuit 210 selects the HWF 500 to be the target according to the auxiliary processing designated as the parameter, and specifies the HWFID. In addition, the HWFID itself may be used as a parameter to issue an HWF call. Here, the description is made with a specific HWFID = i. As a parameter of the HWF call, the arguments for the auxiliary processing can also be specified. Such parameters are written to the defined general purpose register 158 of the CPU 150. The work switching circuit 210 reads the parameters from the general purpose register 158 when receiving the HWF call. The work switching circuit 210 instructs the HWF 500_i to perform auxiliary processing (S102). The work switching circuit 210 stops the CPU 150 by the HC signal. Therefore, the work A is forced to stop in the RUN state. In S102, instead of operating A to access the HWF 500 as shown in FIG. 39, the work switching circuit 210 instructs the HWF 500 to perform auxiliary processing. Specifically, the argument is set in HFi_ARG[m - 1 : 0] and HFi_REQ is transmitted. © HWF500_i, start the auxiliary processing and transmit HFi_RQACK. Since the CPU 150 has stopped, the work A in the auxiliary processing will not be executed. Of course, other work that includes special work will not be performed. After the auxiliary processing ends, the HWF500_i outputs a return value to HFi_RSLT[m- 1 : 0] and transmits HFi_CMPLT. The work switching circuit 210 receives the return value and transmits HFi_CMPACK (S104). The work switching circuit 210 records the return value in the processing register 92. The work switching circuit 2 10 stops transmitting the stop request signal (HR) and starts the execution of the work A again (S 106). 89 200937294 In the case of the tandem type auxiliary processing of the modified example 2, only the system call is required. Further, since cpui5 is stopped during the execution of the auxiliary processing, power consumption can be suppressed. Further, the operation A of the request assist processing does not need to read the end timing of the auxiliary processing, so the timing of the completion of the auxiliary processing is hardly deviated from the timing of the completion of the auxiliary processing by the work processing apparatus 10 (M贞).改良 In the improved example 2', the Hw touch is not directly accessible, but the work switching circuit 210 accesses the chat 500. Therefore, the operation by the interrupt disable command or the interrupt release command does not need to be used to control the interrupt during the interrupt prohibition period. After receiving the HWF beer call, the work processing device (10) controls the CPU clock to stop and restarts only by stopping the request signal (HR). The work processing device 1〇〇 writes the result of the auxiliary processing as a return value to The processing register 92' thus requests the work A of the auxiliary processing to become the state of obtaining the auxiliary processing when the execution is restarted. Since the work A does not need to query the result of the auxiliary processing for the deletion or the work control material 2G, Not only the processing efficiency is improved, but also the code of the work A can be simplified. Fig. 45 is a timing chart showing the control method of the parallel type auxiliary processing of the modified example 2. The HWF5 that is the target is the Fpu (floating point unit). The HWFID of the HWF500 corresponding to the FPU is "匕. First, the work A sends a standby mutex system call with the use right of the FPU as a waiting condition ( S120). The ownership of each HWF is managed by mutual exclusion and flag. There is no need for exclusivity control such as exclusive exclusion. For example, 'as long as it is only using HWF for specific work, no exclusive control is required. 90 200937294 If not set to When the HWF 500_i is occupied by the exclusive exclusion, the work processing apparatus 100 prohibits access to the HWF 500_i by the work other than the exclusive setting work A (S122). In this way, the HWF 500 is temporarily occupied by the work A. Then, the work A issues an HWF call ( S 124). Work A transitions from the RUN state to the WAIT state. The WAIT release condition is terminated by the HWF500_i auxiliary processing. The work switching circuit 2 1 0, when receiving the HWF call, sets the HWFID to the HWFID register 504 of the work A. i. In the second modification, the execution right return operation A is not performed as shown in FIG. 40, and the work switching circuit 210 itself instructs the HWF 500 to start the auxiliary processing (S126). The HWF500_i starts the auxiliary processing. 210 selects the next RUN-work, such as work B (S 128). Work B and auxiliary processing are performed side by side. However, work B cannot use HWF500_i. The reason is that work A ensures the possession of HWF500_i by mutual exclusion. After the end, the HWF 500_i outputs a return value to HFi_RSLT [m-1: 0], and transmits HFi_CMPLT. The work switching circuit 210 receives the round-trip value and transmits HFi_CMPACK (S130). Work B moves from the RUN state to the READY state. Specifically, the work processing apparatus 100 transmits a stop request signal (HR) to stop the CPU clock, waits for the stop end signal (HC) transmission, and retains the processing data of the work B to the reserved register. Work B is reversed into the virtual queue corresponding to the READY state. The work switching circuit 210 inputs HWFID = i to the HWF standby selection circuit 510, and obtains the work ID of the job A that is entrusted to the HWF5 00_i. Next, the return value indicating the result of the auxiliary processing is recorded in the insurance corresponding to the work A 91 200937294

The hold register 'sets the work A to the READY state. Here, as shown in the first modification, the operation A may be reversely placed in the virtual hunting corresponding to the READY state. The work switching circuit 21 〇 selects the next job to be executed, for example, job A (S 132). In the future, the execution rights are assigned to work a. At the end of the auxiliary processing, the work A that has entrusted the auxiliary processing must be selected. According to such a work switching rule, the efficiency of the work of the entrusted auxiliary processing can be improved. In operation A, by canceling the mutual exclusion system call, the possession of hwf5〇〇-丨 is released (S134). The work processing apparatus 1 〇〇 performs the work switching again, and selects the next work to be executed, for example, the work B (sn6) executed at sl28~su〇. In the future, the execution rights are assigned to work B. Work B can also be utilized in the same way due to the disclaimer of HWF5.

In the side-by-side auxiliary processing shown in Fig. 40, the total number of "systems that are owed is called: in contrast to the system of the side-by-side auxiliary processing that improves W2, the number is "standby mutual exclusion system beer", " Disarmed the system call "HWF beer call" three times. Therefore, according to the modified example 2, the payload accompanying the call can be made one time. Also, no special work is required. Borrow: Write the return value to the reserved register, and the work A does not need to query the hwf_ or the work control circuit 200 for the result of the auxiliary processing. In the past, in order to execute the software including 〇S at high speed, try various methods to try to increase the number of clocks of most 4 CPUs, memory capacity or temporary storage; increase the amount, or parallel processing of multiple CPUs, and then network Road points: Large-scale, complicated people. On the other hand, in the case of the work processing apparatus 1 shown in the present embodiment, the processing power is additionally increased by the addition of the existing CPU 15G as control power and 92 200937294, thereby greatly improving the processing efficiency. In the case of the software 〇s, in order to realize the processing such as the work switching that is originally intended to be performed, it is necessary to perform additional processing such as management of tcb or work preparation series. In contrast, the work processing apparatus 100 can realize the work switching, the state management of the operation, and the interrupt processing by the hardware logic, so that the payload unique to the software can be released. Therefore, it is possible to construct an ideal system that suppresses power consumption and cost increase and achieves high speed. Further, according to the auxiliary processing control shown in the second modification, the payload associated with the auxiliary processing can be greatly suppressed. In the past, in order to perform high-speed DMA transfer and other auxiliary processing, it is often provided to directly operate the built-in register of the device without the software 〇s. "When such a program generates a defect, the overall operation of the system becomes unstable.

In the work processing apparatus 1 of the second modification, the operation of directly operating the HWF 500 becomes a physically impossible configuration. By the high-speed processing performance of the work processing apparatus 100 itself and the reduction in the number of system calls, it is possible to realize high-speed auxiliary processing even if the work is configured to the auxiliary processing of the work processing apparatus. According to the work processing apparatus 1 of the second modification, the auxiliary processing control can be made safe and high speed. Hereinabove, the present invention has been described based on the embodiments. The embodiment is exemplified, and various modifications can be made to the combination of these components and the respective processing steps, and such modifications are also within the scope of the present invention, which should be understood by those having ordinary knowledge in the technical field to which the present invention pertains. thing. The functions to be achieved by the respective constituent elements described in the claims are achieved by the single elements of the functional blocks shown in the present embodiment, or the linkages thereof, which are also understood by those having ordinary knowledge in the technical field to which the present invention pertains. 93 200937294 things. Further, various determination circuits will be described with reference to Fig. 12, group, &lt; m solid, Fig. 14, Fig. 28, and Fig. 32. These determination circuits select the operation to be compared and selected by the comparison circuit group. The execution selection circuit 232 of FIG. 12 is used to select the circuit for run_, but can be RUN-worker for READY-operation. Therefore, the decision circuit of Fig. 12 carries the signal that the CH_ signal is output as ready-working. The comparison circuit group that executes the selection circuit 232 is only in the operation of the CID signal "1", which is the work of the lj, that is, the ready state.

According to the work priority pRst READY elapses time TI next RUN-work.旗 The flag selection circuit 234 of Fig. 14 is a circuit for waiting for the flag to be released when the flag is released. To cancel the work of the flag, the work of releasing the flag as the standby flag and in the WAIT state. Therefore, in Fig. 2: the fixed circuit 306, in order to release the flag as the face of the standby flag: for the condition 'output (10) signal.... The flag selection circuit (3): the circuit group, only the work that becomes the CID signal, that is, the WAIT with the flag as the standby flag, the working PR or the WAIT elapsed time TM' selects the logic to be released if the decision circuit is to be canceled, then performs the selection selection. Circuitry 234 can share a comparison circuit group. For each other, the same flag. The same is true for the maximum value selection circuit 406, Fig. 32, or event of Fig. 28. In this way, the material addition, the work selection circuit, and the logic of the circuit, 94 200937294 can form various selection logics in the form of a common comparison circuit group. Below, two examples are given. 1. Rotating System Call This system call is used to change the system group of the virtual queue corresponding to the READY state, that is, the READY-Operational Order Value (ODR) system call. For example, as shown in FIG. 29, in the virtual queue (Q0) corresponding to the rEadY state, five jobs are placed in the order of work (E6), work (E3), work, work (E0), and work (E5). . Here, RUN - job specified work priority © first sequence PR = 1 to issue a rotating system call. Next, the operation (E6) at the front end of the priority queue (Q〇: 1) corresponding to PR = 1 is temporarily taken out, and is placed in the forward direction (E5). That is, the order value (ODR) of the work (E6) becomes "〇", and the order values of other jobs are also adjusted. The rotating system call 'pairs the priority sequence (q〇: i) corresponding to the work priority order PR-1 specified by the parameter, and changes the order of the front-end work to the last-end system call. The external control places the order value (ODR) of the work into the virtual queue (Q0). The determination circuit for realizing the call of the rotating system may output "丄" as a condition of "ready state and operation of the designated work priority pR". Then, by comparing the circuit group, the operation of the maximum value of the sequence value (〇DR) is selected as the object of rotation from the operation in which the output signal of the determination circuit becomes "1". 2. Function expansion of the virtual queue corresponding to the WAIT state In general, when a certain flag is released, the virtual queue (Qn) corresponding to the flag waits with the highest priority from the work priority pR (1)^ : 95 In 200937294, 'choose the work to be acquired. However, regardless of the work priority PR, the special flag to be obtained (hereinafter, referred to as "special flag") may be set by the work with the highest order value (0DR). In order to construct a special flag, the "WAIT state, and the work of releasing the flag as the standby flag" is prepared to output a determination circuit of "1". Figure

The circuit 434' is a circuit that inputs qid_S, CND, and outputs an EID-EN signal. This change is assumed to be a decision circuit that outputs EID_EN Xiao pR_A in addition to qid_s and CND.

When the circuit cancels the special flag, the output value of PR_A is χ, and the normal flag is released, and PR_S is directly output as PR Α. Therefore, in the comparison circuit group, the special flag is released, and the priority PR of each work is recognized as a predetermined value. As a result, the comparison circuit group is selected so that the priority value (ODR) is the smallest among the operations in which the output signal of the determination circuit becomes "1" regardless of the priority PR.

a Various forms of the invention to be grasped by the soil embodiment and the modification. Those who have not disclosed the scope of the patent application are exemplified as follows. The following invention can be recognized from the modification 1. The inner-side processing circuit 'is characterized by: U(four) Μ 'the pseudo-column of the plural types discriminated by the (four) ID 'controls the plurality of elements identified by the element „3; A plurality of queues of the virtual queues of the temporary storage array are held; the device is set corresponding to each element, so that the input pair ID corresponds to the order value of the presentation order. 96 200937294 The queue control circuit, when When the forward input command of the specified element iD and the queue ID is input, the end of the virtual element (four) corresponding to the specified queue ID is set to the end register of the specified element ID. The sequence value and the specified queue ID; when the reverse input instruction of the specified element ID and the queue m is input, the pair of the specified element ID is set to indicate the pair and the specified The front end order value of the virtual queue corresponding to the column ID and the specified queue ID; when the fetch instruction of the specified queue ID is input, the designated J ID and the end order value are stored from the library. The column register clears the queue 1 by using the As the object to be extracted, the virtual queue of the plural type is managed according to the setting information of each of the queues. C2. The virtual array processing circuit described in C1, wherein the control circuit inputs the forward direction The input instruction or the reverse input instruction is one of the following: 'The order value stored in the order such as $+ &gt; is adjusted by the instruction. (4) The material "(4) 1 of its riding column register. As shown in C1, the virtual queue processing circuit, the candidate circuit, the Fusui Mountain, you and the squirrel take the candidate circuit, when you specify the queue ID, you can see the multiple temporary storage thin Single ##山麦... From the J register, the output of the ID and the order value should refer to the element of the ID and the front-end order value. The control circuit of the slave line is temporarily stored from the candidate circuit. The virtual queue column processing circuit of IDe 1 is described by Q, wherein the virtual queue 97 200937294 is further defined as a set of a plurality of priority queues according to the priority of the extraction; The priority for the specific priority queue is also stored; the queue control circuit inputs the specified element ID, the queue ID, and the priority direction of the pointer to the specified element ID. The column register also sets the priority of the designation; when the specified element ID, the column ID, and the reverse direction of the priority command are input, 'the column ID of the specified element ID is also set. Specify the priority of ❹; when entering the fetch instruction specifying the queue ID The 'store the specified queue ID' is set to the highest priority from which the highest priority is set, and the queue register with the sequence value closest to the front end is set to clear the queue ID. C5. The virtual queue processing circuit as described in C4, wherein the queue control, power=, when inputting the fetch instruction of the specified queue (1), adjusting the other queue register storing the queue ID of the indicator Order value. C6. The virtual queue processing circuit according to C5, further comprising: a zero-out candidate circuit, wherein when the queue 1 is specified, the array ID is output in parallel from the plurality of queue registers, The order value and the priority 'storage the specified queue ID' output correspond to the element ID of the queue register in which the highest priority is set and the order value closest to the front end is stored; 'the train control circuit, from The queue register of the elements output by the take-out candidate circuit clears the queue ID. 98 200937294 C7. A work processing apparatus, comprising: processing a temporary register to temporarily store data for performing work; and executing a control circuit to load instructions and operands from a memory to the processing register 'According to the instruction of the temporary register and the operation of the operation unit; a plurality of state registers, which are used to store the state data of the work schedule, corresponding to a plurality of jobs respectively; a virtual array of plural types corresponding to the execution state I of the guard, controlling the work of the plurality of jobs by the work ID to determine the execution state of the work and the work selection circuit, and the work selection circuit to The state data of the parallel output of the state register is input as an input, and the work is selected by the predetermined selection condition; the state register is set to make the virtual ID of the execution state corresponding to the execution state of the queue and the representation virtual (4) The sequence order of the release order is maintained as 'as part of the status data; the execution control circuit, when performing the third job, performs the scheduled system call In order to transmit the predetermined system call signal to the work switching circuit, the work selection circuit specifically stores the queue ID of the preparation queue corresponding to the virtual state of the READY state and indicates the front end of the preparation queue The status register of the previous order value of the position, the second operation selection corresponding to the specific status register is taken as the next execution target; the work switching circuit receives the system call signal from the second work The state register clears the queue ID, and sets the queue ID and sequence value of the virtual queue corresponding to the other execution states different from the RUN state to the state register of the third job, so that the processing register is The data is retained in the established 99 200937294 memory area' and the data retained in the memory area associated with the data is loaded into the processing register. C8. The work processing apparatus according to C7, wherein the operation switching circuit sets the preparation queue to the state register of the first operation when the first operation is moved to the READY state to be the other execution state.伫 List and front-end order values. C9. The work processing apparatus according to C7, wherein the operation selection circuit stores the standby queue as a virtual queue of a WAIT state in a standby state corresponding to a WAIT release condition, and when the WAIT release condition is satisfied, storing the The status register of the queue ID and the front end order value of the standby queue selects the operation; the work switching circuit sets the preparation state queue for the selected state register and indicates the preparation 伫The end sequence value at the end of the column. C1〇. The work processing device according to C7, wherein the state register stores a work priority as part of the state data; and the work selection circuit sets the queue ID of the queue after the switch operation When there are a plurality of jobs, the highest work priority is set among the above, and the work selection in which the order value closest to the front end is set among the objects is selected as the execution target. According to the present invention, the execution control of the work of higher efficiency can be realized in the multiplex processing. [Simple diagram of the diagram] 100 200937294 Figure 1 is a state transition diagram of the work. Figure 2 is a conceptual diagram of a general RTOS. Figure 3 is a circuit diagram of a general CPU executed by the software RTOS. Fig. 4 is a conceptual diagram of rt〇s of the present embodiment. Fig. 5 is a circuit diagram of the work processing apparatus of the embodiment. Figure 6 is a circuit diagram of the CPU of Figure 5. ❹ Fig. 7 is a circuit diagram showing a configuration in which the execution control circuit 丨52 stops the cpu clock. Fig. 8(a) is a timing chart showing the relationship of various signals when the interrupt request signal is generated. Figure 8 (b) shows the relationship between various signals when the system calls execution. Figure 9 is a diagram for explaining the stop timing of the cpu clock of the pipeline processing. Figure 10 shows the state memory. Circuit diagram 11 relating to the duty switching circuit is a diagram showing the RUN of the general RTOS - the work preparation sequence. Figure 12 is a circuit diagram of a selection circuit. The figure shows the general rt〇s eve # # * • column diagram. The standby flag used in the processing of the flag of the Qingqing Figure 14 is the circuit diagram of the flag selection circuit. Figure 15 is a state transition diagram of the work switching circuit. Figure 16 is a circuit diagram of the work processing apparatus of Figure 5, the work processing apparatus of the unloaded work control circuit 101 200937294. Figure 17 is a circuit diagram of a work processing apparatus in which the storage circuit is not loaded in the work processing apparatus of Figure 5. Fig. 18 is a circuit diagram of the work processing apparatus of the first modification. Fig. 19 is a circuit diagram showing a part of the operation control circuit of the first modification. Figure 20 is a circuit diagram of a train control circuit. Figure 21 is a conceptual diagram showing the relationship between virtual queues and work. Figure 22 is a data structure diagram corresponding to the state register of Figure 21. Fig. 23 is a diagram showing the concept of placing the work (E4) in the virtual queue of Fig. 21 ◎. Figure 24 is a data structure diagram corresponding to the state register of Figure 23. Fig. 25 is a conceptual diagram when the work (E5) is placed in the virtual queue of Fig. 23 in the forward direction. Figure 26 is a data structure diagram corresponding to the state register of Figure 25. Figure 27 is a flow chart showing the processing of the forward insertion. Figure 28 is a circuit diagram of a portion of the maximum selection circuit. Figure 29 is a concept of placing the work (E6) in the reverse direction of the virtual array of Figure 25 ◎ 圏. Figure 30 is a data structure diagram corresponding to the state register of Figure 29. Figure 31 is a flow chart showing the processing of the reverse insertion. Figure 32 is a circuit diagram of a portion of the operational selection circuit. Fig. 33 is a conceptual diagram when the work (E3) is taken out from the virtual queue of Fig. 29. Figure 34 is a data structure diagram corresponding to the state register of Figure 33. Figure 35 is a flow chart showing the process of taking out. 102 200937294 Figure 36 is the first conceptual diagram showing the relationship between the virtual train and the work in the execution of the priority jade schedule. Fig. 37 is a second conceptual diagram showing the relationship between the virtual train and the work in the execution of the prioritized work schedule.糸 A diagram showing the general circuit configuration when the auxiliary processing is executed by the software 0S. Fig. 39 is a timing chart showing the control method of the general serial type auxiliary processing. Fig. 40 is a timing chart showing the control method of the general parallel type auxiliary processing. Fig. 41 is a view showing the circuit configuration when the auxiliary processing control shown in Figs. 38 to 40 is realized by the work processing apparatus of the basic example. Fig. 42 is a circuit diagram showing the relationship between the work processing apparatus of the modified example 2 and hwf. Fig. 43 is a circuit diagram showing the relationship between the state memory portion and the operation switching circuit of the second modification. Fig. 44 is a timing chart showing the control method of the tandem type auxiliary processing of the second modification. Fig. 45 is a timing chart showing the control method of the parallel type auxiliary processing of the second modification. [Main component symbol description]

84 CPU 86 Universal Register 103 200937294 88 Special Register 90 Execution Control Circuit 92 Processing Register 94 Operation Circuit 96 Input Selector 98 Output Selector 100 Work Processing Unit 110 Reserved Register 110 - _0~110_n Reserved 112 Load selection circuit 120 storage circuit 150 CPU 152 execution control circuit 154 processing register 156 special register 158 general purpose register 160 arithmetic circuit 162 input selector 164 output selector 170 instruction decoder 172 first AND gate 174 2AND gate 176 OR gate 200 working control circuit

104 200937294

210 work switching circuit 212 flag table 214 event table 220 state memory unit 220__0~220_n state memory unit 230 operation selection circuit 232 execution selection circuit 234 flag selection circuit 236 event selection circuit 238 suspension detection circuit 240 mutual exclusion circuit 242 detection circuit 250, 250_0, 250_1, 250_2, 250 252 Timing 254 Working ID Register 256 Working Priority Register 258 Working Status Register 260 Working Start Address Register 262 Standby Reason Register 264 Flag ID Register 265 Mutual斥ID register 266 event ID register 268 standby flag register 270 flag condition register status register 105 200937294 272 flag initialization register 274 pause counter 280 priority indicator 290a~290d 1 Comparison circuit 292a, 292b Second comparison circuit 294 Third comparison circuit 296a to 296h Decision circuits 300a to 300d First comparison circuit 302a, 302b Second comparison circuit 304 Third comparison circuit 306a to 306h Decision circuit 320 processes data holding portion 322 Register switch control circuit 324 interrupt interface circuit 400 main circuit 402 write circuit 404 Column control circuit 406 maximum value selection circuit 410_0, 410_1, 4102, 410_3 412_0, 412_1, 412 2, 412 3 4140, 4141, 414 2, 414 3 416_0, 416_1, 416 2, 416 3 420_0, 420_1 register value generation 422a, 422b first comparison circuit

❹ Work ID register work priority register register sequence register # % discrimination register memory 106 200937294 424a second comparison circuit 426a to 426d decision circuit 430a, 430b first comparison circuit 432a second comparison circuit 434a~434d decision circuit

500 HWF 500_0 ~500_k HWF 502 Interrupt Controller 504 HWFID Register 506 Array Sequence Scratchpad 508 辨 Column Discriminator 510 HWF Standby Select Circuit 512 CPU Bus ❹ 107

Claims (1)

200937294 VII. Patent application scope: 1. A work processing device, comprising: processing a temporary storage device for temporarily storing data for performing work; and executing a control circuit for loading instructions and operation elements from the memory to the The processing register is operated in accordance with the instructions and operations of the processing register; the cancer register is used to store state data indicating the execution state of the work; the work switching circuit is used to control the execution state of the work. ❹ The work selection circuit 'selects the work according to the state selection data by the predetermined selection condition; and the auxiliary processing circuit performs the predetermined auxiliary process as part of the work; the execution control circuit, when the uranium 仵 ― 么 么 么 么 么 么 么When the system calls the command, the predetermined system call signal is transmitted to the work switching circuit; the work selection circuit selects the work of the next execution object from the work of the REady state in which the standby is not standby to the executable state. The work switching circuit borrows the work selection circuit when receiving the system call signal The output selection becomes the work of the next _ 〇谇 attack for the next execution object, and the data of the processing register is retained in the 己 己 己 , 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Φ The RUN status setting in the stub is changed to another status. For the selection work, Luo Weifang #文文马到到,四(四)Μ The data retained in the memory area is loaded = processing register' and The shape of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ When referring to the system call instruction of the auxiliary processing, the worker 108 ❹ ❹ 200937294 is used as the switching circuit to indicate the auxiliary 2. If the application is (4) auxiliary processing. a switching circuit for instructing execution of the auxiliary processing device, wherein, in the processing of the i-th work pair of the processing command, setting a possession of the second work 1 to the circuit that assists the first work is performed, and ^ ? φ 乍 乍 成 RUN RUN , , , , 乍 , , , , 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 乍 RUN RUN RUN RUN RUN RUN RUN RUN RUN RUN RUN The work light control circuit of the item executes the line command command for occupying the demand instruction, the middle part has the auxiliary processing circuit, and the request is occupied by the work switching circuit, so as to do not set other work for the right D auxiliary processing circuit = has the right to set the first work to the auxiliary processing circuit == system, the first operation, the acquisition of the auxiliary processing circuit is conditional on the condition that the auxiliary processing instruction is executed. The working processing device of the invention of claim 2, wherein the tool and the circuit record the predetermined data in a state register that executes the first processing instruction of the auxiliary processing instruction, to receive the third security device and the like. The processing of the auxiliary processing circuit ends; the work selection circuit 'notifies the work switching circuit of the operation of recording the predetermined data in the state register; the work switching circuit receives, from the auxiliary processing circuit, the end of the auxiliary processing When the auxiliary end signal is received, the first operation notified from the work selection circuit is set to the RUN state again. 109 200937294 5. If the work processing auxiliary processing circuit of the patent application scope item is injured, the damage is eight, which is straight, In addition to the heat ~ several kinds of auxiliary processing to set a plurality of 丨; I line control circuit, when the work in the implementation to assist the category as the parameter of the stick 呤 稀 稀 稀 稀 稀 稀 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助a plurality of auxiliary processing circuits t(four)#, the auxiliary auxiliary processing circuit, the auxiliary processing corresponding processing, and the auxiliary processing circuit of the material selection instructing execution of the auxiliary 6. The working processing device of the fifth application of the patent scope is used as the switching circuit. , select the 呤 MbA old one of the 'the work 指令 command ... circuit when 'to perform the auxiliary processing, ' ~ register record Identifying the auxiliary ribs of the selected circuit to assist the processing of the auxiliary processing ID to set the execution of the auxiliary ribs to wait for the selection of the auxiliary ribs. The processing of the circuit ends, and the auxiliary processing circuit receives the selected processing circuit. It is indicated that the ^^0#, Jiang兮啰 arrived at ^u, and the auxiliary signal of the auxiliary processing circuit selected by the σ bundle is the auxiliary processing circuit. , the author # + τ ... selects the Ύτ that records the auxiliary processing ID of the notification, ❹ the work switching circuit receives the auxiliary 々士土 ^ ^ 忑 subsidy end signal, and sets the selected work again. Into the RXJN state. 7. If the work of the third paragraph of the patent application is reserved to retain the data processing device of the processing register, further comprising a plurality of reserved registers corresponding to the plurality of jobs respectively; Switching circuit, when receiving the .^ ^ system call signal, 'retain the data of the processing register in the reservation corresponding to the work in the execution order. 200937294 The register will be the next execution object. The data corresponding to the reserved scratchpad is loaded into the processing register. 8. The work processing apparatus according to claim 7, wherein the work switching circuit receives, from the auxiliary processing circuit, an auxiliary end signal indicating that the auxiliary processing is completed, and obtains the auxiliary wire from the auxiliary processing circuit. The returned value of the result is written to the reserved register that performs the work of the auxiliary processing instruction to notify the execution of the auxiliary processing instruction of the result of the auxiliary processing. φ φ 9. The work processing apparatus of claim i, wherein the work 7 is a circuit, and when the auxiliary processing circuit receives a help end signal indicating the auxiliary processing, the auxiliary processing instruction is executed. The work is set to the RUN state again. For example, if the processing of the third paragraph of the patent application is handled, the work switching circuit is connected to the circuit of the 兮 # + + + + 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四^ ^ ^ &quot; to prevent the execution of the auxiliary processing from being executed by the binding control circuit. The processing device of the iQ item of the patent scope, wherein the switching circuit is executed, when the auxiliary processing is performed Refers to the 7 μ circuit transmission stop request message &amp; 7 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 : : : : : Executing a clock for temporarily stopping execution of the operation of the phase 7; the work switching circuit, when receiving the auxiliary termination signal, transmits a stop release signal to the control circuit of the control circuit 111; the execution control circuit receives the After the stop signal is stopped, the supply of the execution clock is stopped, and the execution of the operation of the auxiliary processing instruction is resumed. /&quo t;V, schema · (such as the next page) ❹ 112