TWI474025B - Protective semiconductor device for secondary cell - Google Patents

Description

Protective semiconductor device for secondary battery

The present invention relates to a protective semiconductor device for a secondary battery.

Battery packs that are easy to handle are widely used in mobile electronic devices. Such a battery pack is formed by one or more secondary battery packages. For the secondary battery, a high-capacity battery such as a lithium battery, a lithium polymer battery, a nickel-hydrogen battery or the like is used. If overcharge, overdischarge, excessive current, etc. are generated, it is likely to evolve into ignition due to high temperature heat, because these high capacity batteries have a large amount of energy.

Therefore, the protective semiconductor device that prevents overcharging, overdischarging, excessive charging current, excessive discharging current, short-circuit current, abnormal overheating, and the like is included in the battery package of the secondary battery. The protective semiconductor device also prevents deterioration of the secondary battery while preventing overheating and ignition from occurring by blocking the connection of the charger or the load device if necessary.

In recent years, protective semiconductor devices have been developed which protect the secondary batteries by connecting a plurality of secondary batteries in series. However, in the conventional protective semiconductor device, which protects the secondary batteries by connecting the secondary batteries in series, there is a problem that occurs in a part of the connection between the secondary battery and the protective semiconductor device Cannot be detected when disconnected.

In order to detect disconnection between a secondary battery and a protective semiconductor device, a method for comparing a charge and discharge current flow and a current flow is disclosed in Japanese Patent Application Publication No. 2008-027658 (Patent Document 1). Battery voltage at the time. However, with the method as disclosed in Patent Document 1, the disconnection occurring in the connection between the secondary battery and the protective semiconductor device when the secondary battery is used cannot be detected.

It is an object of the present invention to provide a protective semiconductor device if a secondary battery and protection When a disconnection occurs in a portion of the connection between the semiconductor devices, the occurrence of the disconnection is reliably detected.

In order to achieve the above object, an embodiment of the present invention is a protective semiconductor device capable of detecting a voltage state of a plurality of secondary batteries connected in series, the protective semiconductor device comprising: a plurality of terminals, which are connectable to An electrode of each secondary battery; a plurality of first resistors, which detect the voltage of each secondary battery, are disposed to correspond to each of the secondary batteries, and are connected to a high voltage side and a low voltage side of each of the electrodes Between the terminals; a plurality of comparators, which are arranged to correspond to each of the secondary batteries and are capable of detecting whether the voltage of each of the secondary batteries is within a reference voltage range according to the voltages obtained by the first resistors; a series circuit, each of which is composed of a second resistor and a first switching element, is disposed to correspond to each of the secondary batteries, and is connected between the terminals; and a control circuit that controls each Opening/closing of the first switching element, the first switching element is connected to the second resistor between the connecting ends by opening, the first switching element being closed by The second resistor is disconnected from the connecting ends, and the control circuit sequentially turns on the first switching elements while maintaining an open state of the disconnection test signal, and the control circuit is switched from corresponding to open The output signal of the comparator of the first switching element detects disconnection between the secondary batteries and the terminals.

1, 2‧‧‧ Protective semiconductor devices

10, 20‧‧‧ Fault detection circuit

11, 12, 13, 14‧‧ ‧ comparator

15‧‧‧NAND circuit

100, 300‧‧‧ Internal resistance change circuit

101, 102, 103, 104‧‧‧ Pressure change circuit

110, 210, 410‧‧‧ control circuit

120, 320‧‧‧ judgment circuit

121‧‧‧Logic Circuit A

122‧‧‧Logic Circuit B

123‧‧‧Delay circuit

124, 125‧‧‧AND circuit

126, 127‧‧‧ inverter circuit

140‧‧‧XOR circuit

142, 144, 148, 355, 356‧‧ ‧ inverter

145‧‧‧NAND circuit

146‧‧‧NOR circuit

150‧‧‧Factor

201, 202, 203, 204‧‧‧ voltage detection circuit

220‧‧‧Battery discharge control circuit

322‧‧‧NOR circuit

324, 325‧‧‧AND circuit

326‧‧‧Inverter circuit

327‧‧‧Selection circuit

351, 352, 353, 354‧‧‧ lag forming circuit

BAT1, BAT2, BAT3, BAT4‧‧‧ secondary batteries

CB1, CB2, CB3, CB4, CBx‧‧‧ terminals

CBCTL‧‧‧ control signal

Cf1, Cf2, Cf3, Cf4‧‧‧ capacitor

DLY1, DLY2‧‧‧ delayed output

LCout‧‧‧ disconnected detection signal

LTDet‧‧‧Disconnect detection operation signal

LTEST‧‧‧ disconnect test signal

M1, M2, M3, M4, M11, M12, 13, M14‧‧‧ PMOS transistors

M31, M32, M33, M34‧‧‧ NMOS transistors

Mcb1, Mcb2, Mcb3, Mcb4‧‧‧ external NMOS transistors

Rcb1, Rcb2, Rcb3, Rcb4‧‧‧ external resistor

Rs11, Rs12, Rs21, Rs22, Rs31, Rs32, Rs41, Rs42, R11, R21, R31, R41, Rf1, Rf2, Rf3, Rf4, Rs13, Rs23, Rs33, Rs43‧‧

Rsw1, Rsw2, Rsw3, Rsw4, Rs14, Rs24, Rs34, Rs44‧‧‧ control signals

Tcb‧‧‧ timing

Tpw‧‧‧ time period width

Twait‧‧‧fixed time interval / disconnected test interval

VC1, VC2, VC3, VC4‧‧‧ battery connection

VDD‧‧‧ power supply terminal

VHDet‧‧‧High-voltage detection operation signal

VHout‧‧‧High voltage detection signal

VHoutb‧‧‧ inverted signal

VHS‧‧‧ detection signal

VHsens‧‧‧High pressure detection level

VHhys‧‧‧ high pressure lag

VG1, VG2, VG3, VG4‧‧‧ control signals

Vr11, Vr21, Vr31, Vr41‧‧‧ reference voltage

VSS‧‧‧ grounding terminal

Vvc1, Vvc2, Vvc3, Vvc4‧‧‧ voltage

1 is a schematic view showing a protective semiconductor device and a secondary battery according to a first embodiment of the present invention; and FIG. 2 is a view showing an example of a control signal of a control circuit in the protective semiconductor device according to the first embodiment of the present invention; Figure 3 is a timing chart showing the operation of the protective semiconductor device in the first embodiment of the present invention for detecting high voltage; Figure 4 is a protective semiconductor of the first embodiment (meaning that the second embodiment is not applied) of the present invention. FIG. 5 is a schematic view showing a protective semiconductor device and a secondary battery according to a second embodiment of the present invention; 6 is a view showing an example of a control signal of a control circuit in a protective semiconductor device according to a second embodiment of the present invention; and FIG. 7 is a view showing a schematic configuration of a protective semiconductor device and a secondary battery according to a second embodiment of the present invention; FIG. 8 is a schematic view showing the configuration of the protective semiconductor device in the second embodiment of the present invention; FIG. 9 is a schematic view showing the protective semiconductor device and the secondary battery according to the third embodiment of the present invention; FIG. 11 is a schematic diagram showing a control signal of a control circuit of a third embodiment of the present invention; FIG. 11 is a view showing a control signal of a control circuit of a protective semiconductor device according to a third embodiment of the present invention; 12 is a timing chart showing the operation of the protective semiconductor device according to the third embodiment of the present invention; and FIG. 13 is a circuit diagram showing the input and output portions of the judging circuit of the protective semiconductor device according to the first to third embodiments of the present invention; Figure 14 is a schematic view showing a protective semiconductor device and a secondary battery according to a fourth embodiment of the present invention; and Figure 15 is a view showing the protection of the fourth embodiment of the present invention The circuit configuration of the input and output portions of the judgment circuit of the semiconductor device.

The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

<First Embodiment>

The present invention relates to a protective semiconductor device that protects a plurality of series connected secondary batteries and has the following structure.

The protective semiconductor device includes a voltage sensitive resistor in parallel with the secondary battery for detecting a voltage. At a fixed time interval, a resistor having a resistance value smaller than the resistance value of the pressure sensitive resistor is temporarily connected in parallel to the pressure sensitive resistor. If disconnection does not occur between the protective semiconductor device and the secondary battery, voltage fluctuation of the secondary battery does not occur at the connection end where the protective semiconductor device is connected to the secondary battery. On the other hand, if there is a disconnection between the protective semiconductor device and the secondary battery, At the connection end where the secondary battery is disconnected, the voltage fluctuates with fluctuations in the resistance value, wherein the fluctuation of the resistance value is caused by the temporary generation of the above-described parallel resistance. The protective semiconductor device detects the voltage fluctuation caused by the resistance fluctuation due to the disconnection.

1.1 Structure of protective semiconductor device

Fig. 1 is a schematic view showing a protective semiconductor device and a secondary battery according to a first embodiment of the present invention. The protective semiconductor device 1 includes a fault detecting circuit 10 that performs detection of high-voltage and disconnection, an internal resistance changing circuit 100, a control circuit 110, and a judging circuit 120. It is noted that the fault detection circuit 10 can include a low voltage detection circuit, an overcurrent detection circuit, and the like. Further, the number of secondary batteries is shown as four in FIG. 1, but the number of secondary batteries used in the protective semiconductor device of the first embodiment is not limited to this number.

The protective semiconductor device 1 includes battery connection terminals VC1 to VC4 and a ground terminal VSS for connecting four secondary batteries. The positive electrode of the first secondary battery BAT1 is connected to the battery connection terminal VC1, and the negative electrode of the first secondary battery BAT1 and the positive electrode of the second secondary battery BAT2 are connected to the battery connection terminal VC2. The negative electrode of the second required battery BAT2 and the positive electrode of the third secondary battery BAT3 are connected to the battery connection terminal VC3. The negative electrode of the third secondary battery BAT3 and the positive electrode of the fourth secondary battery BAT4 are connected to the battery connection terminal VC4. The negative electrode of the fourth secondary battery BAT4 is connected to the ground terminal VSS. The power supply terminal VDD is connected to the power supply of the circuit (not shown) and the battery connection terminal VC1.

The failure detecting circuit 10 is a circuit that detects a high voltage of the secondary battery or a disconnection between the secondary battery and the protective semiconductor device 1. The fault detecting circuit 10 is composed of comparators 11, 12, 13, 14; reference voltages Vr11, Vr21, Vr31, Vr41: local resistors Rs11, Rs12, Rs21, Rs22, Rs31, Rs32, Rs41, Rs42 and NAND circuit 15. Among them, the comparator 11, the resistors Rs11, Rs12, and the reference voltage Vr11 constitute a circuit for detecting the high voltage and the disconnection of the secondary battery BAT1. Resistors Rs11 and Rs12 are connected in series and between the battery terminals VC1 and VC2. A connection point of the resistors Rs11 and Rs12 is connected to the inverting input terminal of the comparator 11. The reference voltage Vr11 is connected between the non-inverting input of the comparator 11 and the battery connection terminal VC2. Note that the resistors Rs11 and Rs12 are the voltage sensitive resistors associated with the first secondary battery BAT1.

The failure detecting circuit 10 of the second to fourth batteries BAT2 to BAT4 has the same structure as the failure detecting circuit 10 of the first secondary battery BAT1, and thus the description is omitted here.

All of the outputs of the comparators 11, 12, 13, 14 are connected to the input of the NAND circuit 15, and the detection signal VHS as an output from the NAND circuit 15 is connected to the input of the decision circuit 120.

The internal resistance change circuit 100 is composed of PMOS transistors M1 to M4 and resistors R11 to R41. Among them, the PMOS transistor M1 and the resistor R11 constitute a series circuit that changes the internal resistance of the first secondary battery BAT1, thereby detecting disconnection. The PMOS transistor M1 and the resistor R11 are connected in series, and are further connected between the battery terminals VC1 and VC2. The control signal VG1 coming out of the control circuit 110 is connected to the gate of the PMOS transistor M1.

The internal resistance change circuit 100 of the second to fourth secondary batteries BAT2 to BAT4 is the same as the internal resistance change circuit 100 of the first secondary battery BAT1, and a description thereof will be omitted.

The resistance values of the resistors R11 to R41 are the same and smaller than the resistance values of the resistors Rs11 to Rs42, wherein the resistors Rs11 to Rs42 form part of the fault detecting circuit 10.

The control circuit 110 is input with the high voltage detection operation signal VHDet and the high voltage detection signal VHout, and outputs the control signals VG1, VG2, VG3, VG4 to the PMOS transistors M1 to M4 of the internal resistance change circuit 100 and the output disconnection test signal LTEST, respectively. Logic circuit B 122. Further, a clock, an external trigger, or the like not shown in the figure is connected as an input to the control circuit 110, thereby generating control signals VG1 to VG4 and a disconnection test signal LTEST.

The judging circuit 120 is a circuit that judges whether the fault detecting circuit 10 has detected a high voltage or is turned off. The judging circuit 120 includes: a logic circuit A 121; a logic circuit B 122; a delay circuit 123; an AND circuit 124; an AND circuit 125; an inverting circuit 126; and an inverting circuit 127.

The AND circuit 124 is input as the detection signal VHS from the output of the failure detecting circuit 10 and the disconnection test signal LTEST which is input inverted by the inverter circuit 126, and outputs the high voltage detecting operation signal VHDet. The AND circuit 125 is input as the detection signal VHS from the output of the failure detecting circuit 10, is input to the disconnection test signal LTEST, and is input to the high-voltage detection operation signal VHDet inverted by the inverter circuit 127, and outputs the disconnection detection operation signal. LTDet. By the action of the AND circuits 124, 125, the disconnection detection is not performed when the high voltage detection is performed, and the high voltage detection is not performed when the disconnection detection is performed.

The logic circuit A 121 is input with the high voltage detection operation signal VHDet and the delay output DLY1 from the delay circuit 123, and outputs the high voltage detection signal VHout to the delay circuit 123 and an internal circuit (not shown).

The logic circuit B 122 is input with the off detection operation signal LTDet and the delay output DLY2 from the delay circuit 123, and outputs the off detection signal LCout to the delay circuit 123 and the internal circuit (not shown).

The delay circuit 123 is input with the high voltage detection operation signal VHDet, the disconnection detection operation signal LTDet, the high voltage detection signal VHout, and the disconnection detection signal LCout. Furthermore, the delay circuit 123 outputs the delayed output DLY1 to the logic circuit A 121, and delays the output DLY2 to the logic circuit B 122.

The judging circuit 120 can have any structure as long as it can be judged whether a high voltage or a disconnection has been detected.

The delay circuit 123 is a circuit that configures the delay time of detection/return to prevent false detection caused by noise or the like. When the fault detecting circuit 10 detects the high voltage, once the high voltage detecting operation signal VHDet outputted from the AND circuit 124 is changed from the "low level" to the "high level" delay circuit 123, the high voltage detecting operation signal VHDet is "high level". The delay circuit 123 outputs a high level-pulse to the output DLY1 until the end of the predetermined period. To return from the high voltage detection mode, once the high voltage detection operation signal VHDet output from the AND circuit 124 changes from "high level" to "low level", the delay circuit 123 starts execution, and if the high voltage detection operation signal VHDet is "low level", The delay circuit 123 outputs a high level-pulse until the end of the predetermined period. The judgment of the detection/return is performed based on the high voltage detection signal VHout. For example, the high-voltage detection signal VHout "high level" is judged as "probe" and the "low level" is judged as "return".

When the fault detecting circuit 10 has detected the disconnection, once the disconnection detecting operation signal LTDet output from the AND circuit 125 is changed from "low level" to "high level", the delay circuit 123 starts execution, and if the detecting operation signal is turned off When LTDet is "high level", the delay circuit 123 outputs a high level-pulse to delay output DLY2 until the end of the predetermined period. To return to the disconnection detection mode, once the disconnection detection operation signal LTDet output from the AND circuit 125 is changed from "high level" to "low level", the delay circuit 123 starts execution, and if the disconnection detection signal LTDet is "high" Quasi", the delay circuit 123 outputs a high level-pulse until the end of the predetermined period. The judgment of the detection/return is performed in accordance with the disconnection detection signal LCout. For example, the disconnection detection signal LCout "high level" is judged as "probe" and the "low level" is judged as "return".

It is noted that these high pressure detection times, return times from high pressure, disconnection detection, and predetermined periods of return time from disconnection need not be the same, and may be different from each other. Further, the delay circuit 123 can have any structure, such as a counter and a constant power if the circuit operates in the same manner. The capacitance of the flow.

1.2 Operation of protective semiconductor devices during disconnection detection

Fig. 2 is a view showing an example of a control signal of a control circuit in the protective semiconductor device of the first embodiment of the present invention. The operation of the protective semiconductor device will be described below based on the operation of the control circuit 110. The control circuit 110 generates the control signals VG1 to VG4 based on the incoming clock or the like and turns off the test signal LTEST, thereby controlling the connection test between the secondary battery and the protective semiconductor device at a fixed time interval twait.

As shown in FIG. 2, the control circuit 110 causes the output of the disconnection test signal LTEST, during the time period width tpw of the fixed time interval twait, the disconnection test signal LTEST informs the decision circuit 120 that the test is turned off to become "high". quasi".

Regarding the control signals VG1 to VG4, one of them becomes "low level" as the test signal LTEST is turned off and turns on the PMOS transistors M1 to M4 connected to the respective control signals VG1 to VG4, and then based on these turned on PMOS The crystals M1 to M4 connect the resistors R11 to R41 in parallel to the voltage sensitive resistor.

In the circuit shown in Fig. 1, it is assumed that disconnection between the battery connection terminal VC2 and the secondary battery occurs. At this time, it is assumed that the disconnection test signal LTEST becomes the "high level" state, and the control signal VG1 becomes the "low level" state. Then, between the battery terminals VC1 and VC2, the series resistance is formed by a connection with the first parallel resistor composed of the first series resistor, the resistors Rs11 and Rs12, and the resistor R11 (ie, the series resistance is The first parallel resistor and the second series resistor are formed). If the resistance values of the resistors Rs11 and Rs12 are the same, and the resistance values of the resistors Rs12 and Rs22 are the same, the second series resistor is greater in resistance value than the first parallel resistor.

Then, the voltage across the second series resistors (resistors Rs21 and Rs22) is greater than the voltage before the disconnection between the battery connection terminal VC2 and the secondary battery occurs. This "greater" is detected by the comparator 12 and via the NAND circuit 15, the decision circuit 120 is informed by the detection signal VHS in the "high level" state. At this time, in response to the "high level" state of the disconnection test signal LTEST, the judgment circuit 120 outputs the disconnection detection signal LCout in the "high level" state.

Assuming that the disconnection test signal LTEST becomes the "high level" state, the control signal VG2 becomes "low level" when the battery connection terminal VC2 and the secondary battery are disconnected. Then, between the battery terminals VC1 and VC2, the series resistance is formed by a connection with a second parallel resistor composed of the second series resistor, the resistors Rs21 and Rs22, and the resistor R21 (ie, the series resistance is Second parallel The resistor and the first series resistor are formed). At this time, the first series resistance is greater than the second parallel resistance in the resistance value.

Then, the voltage across the first series resistors (resistors Rs11 and Rs12) is greater than the voltage before the disconnection between the battery connection terminal VC2 and the secondary battery occurs. This "greater" is detected by the comparator 11 and via the NAND circuit 15, the decision circuit 120 is informed by the detection signal VHS in the "high level" state. At this time, in response to the "high level" state of the disconnection test signal LTEST, the judgment circuit 120 outputs the disconnection detection signal LCout in the "high level" state.

If a disconnection occurs between a battery connection terminal (e.g., the VC3 terminal) and the secondary battery, the disconnection is detected in the same manner, and the judging circuit 120 outputs the disconnection detection signal LCout in the "high level" state.

It is noted that the off test interval twait and the off test time period width tpw may be any period, but the off test period period width tpw should be shorter than the delay time generated by the delay circuit 123.

Furthermore, the disconnection test interval twait of the test disconnection and the off test time period width tpw of the disconnection test signal LTEST in the "high level" state may be generated in any manner, that is, the external trigger input to the protective semiconductor device 1 An embedded oscillating circuit or the like in the protective semiconductor device 1.

1.3 Operation of protective semiconductor devices when detecting high voltage

According to the first embodiment, the high voltage detecting operation of the protective semiconductor device of the present invention will be described below with reference to Figs. 3 to 1. Fig. 3 is a timing chart showing the operation of the protective semiconductor device in the first embodiment of the present invention for detecting high voltage. In the timing diagram, only the signals necessary for the description are displayed. In the following, it will operate as described in time series.

[Sequence T1]: The secondary battery starts charging at a certain point, and the voltage VBAT1 of the secondary battery BAT1 exceeds the high-voltage detection level VHsens at the timing T1.

[Number 1] VHsens is as follows.

[Equation 1] VHsens=(Rs11+Rs12)/Rs12 x Vr11

Since the voltage VBAT1 of the secondary battery BAT1 exceeds the high voltage detection level VHsens, the output of the comparator 11 is inverted and becomes "low level", and therefore, the detection signal VHS outputted from the failure detecting circuit 10 is inverted and becomes "High level." Since the disconnection test is not in the process (the output of the disconnection test signal LTEST is "low level"), the AND circuit 124 in the decision circuit 120 will be high voltage. The detection operation signal VHDet is inverted from "low level" to "high level". Since the disconnection test is not in the process, the AND circuit 125 in the decision circuit 120 retains the disconnection detection operation signal LTDet as "low level".

[Sequence T2]: The disconnection test interval twait elapses, but the control circuit 110 does not enter the disconnection test process because the high voltage probe operation signal VHDet is still "high level". That is, the control circuit 110 retains the disconnection test signal LTEST with the "low level" as the output.

[Sequence T3]: In response to the delay time of detecting the high voltage, the delay circuit 123 outputs the high level-pulse to the output DLY1, and thus, the logic circuit A 121 inverts the high voltage detection signal VHout from the "low level" to the "high level". Since the protective semiconductor device 1 comes to the high voltage protection detection mode, the operation of the control circuit 110 is blocked by the high voltage detection signal VHout.

[Sequence T4]: When the VBAT1 voltage of the secondary battery BAT1 drops to the high voltage detection level VHsens or less, the output of the comparator 11 is inverted and becomes "high level". Therefore, the detection signal VHS outputted from the failure detecting circuit 10 is inverted and becomes "low level". The high voltage detection operation signal VHDet is inverted as the detection signal VHS and becomes "low level".

[Sequence T5]: In response to the delay time returning from the high voltage detection mode, the high level pulse is output from the output DLY1 of the delay circuit 123, so the logic circuit A 121 inverts the high voltage detection signal VHout from the "high level" to " Low level." Since the protective semiconductor device 1 is no longer in the high voltage detection mode, the execution of the control circuit 110 is restarted.

1.4 Summary of the first embodiment

As described above, in the first embodiment, in the protective semiconductor device of the secondary battery, the resistor is connected in series and temporarily to the resistance of the comparator formed in each of the secondary batteries, wherein the comparator for detecting the voltage fluctuation is established In a secondary battery connected in series. The disconnection between each of the secondary batteries and the protective semiconductor device can be detected by comparing the fluctuation of the voltage between the connection terminals of the respective parallel-connected secondary batteries and the protective semiconductor device using a comparator.

<Second embodiment>

A problem with the protective semiconductor device according to the first embodiment of the present invention is that if the device is connected to be anti-noise by a low-pass filter, a voltage generated at both ends of the resistor forming the low-pass filter may cause Even if there is no disconnection, the problem of erroneous detection of disconnection between the secondary battery and the protective semiconductor device occurs. Therefore, according to the second embodiment of the present invention, the protective semiconductor device is characterized by reducing erroneous detection of the comparator, and these features will be obtained in the following manner. By separately connecting the resistors in series with the respective pressure-sensitive resistors of all the secondary batteries, and the resistor having a smaller resistance value is also temporarily connected in parallel with the voltage-sensing resistor, the comparator of the voltage-sensitive resistor is reverse-phased ( Inversion level) is raised.

2.1 The purpose of the second embodiment

First, the object of the second embodiment of the present invention will be described. Fig. 4 is a schematic view showing the construction of a protective semiconductor device of only the first embodiment (meaning that the second embodiment is not applied) of the present invention.

The protective semiconductor device is not directly connected to the secondary battery in actual use, but is often connected by a low-pass filter as a method of noise resistance (formed by resistors Rf1 to Rf4 and capacitors Cf1 to Cf4) as shown in FIG. .

The problem that arises when the second embodiment is not applied will be described below with reference to FIG. The problem is that, during the disconnection test, the disconnection between the secondary battery and the protective semiconductor device 2 can be detected because the voltage generated on both ends of the resistor forming the low-pass filter is generated even if the disconnection is not generated. To.

For convenience of explanation, it is assumed that the voltages VBAT1 to VBAT4, the resistances Rs11 to Rs42, and the resistances Rf1 to Rf4 of the secondary batteries BAT1 to BAT4 satisfy the following conditions (Conditions 1 to 5).

VBAT1=VBAT2=VBAT3=VBAT4 (Condition 1)

Rs11+Rs12=Rs21+Rs22=Rs31+Rs32=Rs41+Rs42 (Condition 2)

Rf1=Rf2=Rf3=Rf4 (Condition 3)

Rs11+Rs12>>Rf1 (Condition 4)

Rs11+Rs12>>R11 (Condition 5)

Thereafter, the state of the disconnection test interval twait is shown in FIG. 2, and the control signal VG1 is changed to "low level" and the PMOS transistor M1 is turned on. At this time, since the resistor R11 is connected in parallel with the resistors Rs11 and Rs12, the current I1 between the battery terminals VC1 and VC2 satisfies the following equation (1-1).

I1=VBAT1/(((Rs11+Rs12)xR11/(Rs11+Rs12+R11))+Rf1+Rf2) (1-1)

Now, the conditional equation (condition 3) and the conditional equation (condition 4) are substituted into the equation (1-1), and the current I1 is expressed as the following equation (1-2).

Also, since it is connected in series with the resistors Rs21 and Rs22, the current I2 between the battery terminals VC2 and VC3 is expressed by the following equation (1-3).

I2=VBAT2/(Rs21+Rs22+Rf2+Rf3) (1-3)

The conditional equation (condition 3) and the conditional equation (condition 4) are substituted into the equation (1-3) in the same manner as in the equation (1-1), and the current I2 is as shown in the following equation (1-4).

Furthermore, the conditional equation (condition 1) and the conditional equation (condition 2) are substituted into the equation (1-4) as shown in the following equation (1-5).

Using equations (1-2) and (1-5), it is found that the current I1 between the battery terminals VC1 and VC2 is greater than the current I2 between the battery terminals VC2 and VC3, and the value of the phase difference is as follows (1- 6) shown.

I3=I1-I2=VBAT1/R11 (1-6)

The current calculated by the equation (1-6) leaks into the secondary battery through the battery connection terminal VC2 and the resistor Rf2 forming the low-pass filter. Therefore, the voltage generated in both ends of the resistor Rf2 and the voltage Vvc2 between the battery terminals VC2 and VC3 become larger than the voltage VBAT2 of the secondary battery BAT2. At this time, the voltage Vvc2 between the battery terminals VC2 and VC3 is as shown in the following equation (1-7).

If the voltage VBAT2 of the secondary battery BAT2 causes the following equations (1-9) and (1-10) to satisfy the high-voltage detection level VHsens calculated by the equation (1-8), the output of the comparator 12 is inverted and the fault detecting circuit The output VHS of 20 outputs "high level". At this time, since the disconnection test signal LTEST is "high level", the judging circuit 120 judges that the connection between the secondary battery and the protective semiconductor device 1 is off and outputs a "high level" expressing the disconnection detection mode.

VHsens=(Rs21+Rs22)/Rs22xVr21 (1-8)

VBAT2+(VBAT1/R11)xRf2>VHsens (1-9)

VHsens>VBAT2 (1-10)

That is, during the disconnection test, even if the disconnection does not occur, the voltage of the secondary battery generated according to the voltage across the both ends of the resistor forming the low-pass filter, between the protective semiconductor device and the secondary battery The disconnection can also be detected. Note that if the voltage VBAT2 of the secondary battery BAT2 satisfies the following equation (1-11), neither the open nor the high voltage can be detected, and if the voltage VBAT2 satisfies the following equation (1-12), a high voltage is detected.

VBAT2+(VBAT1/R11)xRf2<VHsens (1-11)

VHsens<VBAT2 (1-12)

The object of the second embodiment of the present invention is to solve the problem that the protective semiconductor is generated according to the voltage of the secondary battery generated by the voltage across the both ends of the resistor forming the low-pass filter, even if the disconnection does not occur during the disconnection test. The disconnection between the device and the secondary battery can also be detected.

2.2 Structure of protective semiconductor device

Fig. 5 is a schematic view showing a protective semiconductor device 1 and a secondary battery according to a second embodiment of the present invention. The structure of the protective semiconductor device according to the second embodiment has a structure similar to that of the first embodiment of the present invention. Therefore, the difference between the two will be described.

The fault detecting circuit 10 of the protective semiconductor device 1 according to the second embodiment of the present invention includes: comparators 11, 12, 13, 14; reference voltages Vr11, Vr21, Vr31, Vr41; local resistors Rs11, Rs12, Rs21, Rs22, Rs31, Rs32, Rs41, Rs42; NAND circuit 15; and voltage change changing circuits 101, 102, 103, 104. Among these elements, the comparator 11, the resistors Rs11, Rs12, the reference voltage Vr11, and the pressure sensitive changing circuit 101 constitute a circuit for detecting the high voltage and the disconnection of the first secondary battery BAT1. The resistors Rs11, Rs12 and the pressure sensitive changing circuit 101 are connected in series and further connected between the battery terminals VC1 and VC2. A connection point between the resistors Rs11 and Rs12 is connected to the inverting input of the comparator 11. The reference voltage Vr11 is connected between the non-inverting input of the comparator 11 and the battery connection terminal VC2. Note that the resistors Rs11 and Rs12 form the voltage sensitive resistor of the first secondary battery BAT1.

The pressure sensitive change circuit 101 is composed of a parallel PMOS transistor M1 and a resistor Rs13. The gate of the PMOS transistor M11 is connected to the control signal Rsw1 from the control circuit 110. The voltage change changing circuit 101 is a circuit in which the resistor Rs13 is connected in series with the resistors Rs11 and Rs12, thereby changing the inverting voltage of the comparator during the disconnection test, wherein the resistors Rs11 and Rs12 are voltage sensitive resistors.

The fault detecting circuit 10 of the second to fourth secondary batteries BAT2 to BAT4 has the same structure as the first secondary battery BAT1.

The control circuit 110 is input with the high voltage detection operation signal VHDet and the high voltage detection signal VHout, and outputs the control signals VG1, VG2, VG3, VG4 to the PMOS transistors M1 to M4 of the internal resistance change circuit 100 and the output disconnection test signal LTEST to the logic circuit. B 122. Furthermore, the control circuit 110 outputs the control signals Rsw1, Rsw2, Rsw3, Rsw4 to the gates of the PMOS transistors M11 to M14 of the voltage sensitive changing circuits 101 to 104. Again, in the picture A clock, an external trigger, or the like that is not displayed is input to the control circuit 110, thereby generating control signals VG1 to VG4, a disconnection test signal LTEST, and control signals Rsw1, Rsw2, Rsw3, and Rsw4.

2.3 control circuit control signal

Fig. 6 is a view showing an example of a control signal of the control circuit 110 in the protective semiconductor device of the second embodiment of the present invention. First, in order to describe the operation of the protective semiconductor device, the operation of the control circuit 110 will be described as background information. The control circuit 110 generates control signals VG1 to VG4, Rsw1 to Rsw4, and a disconnection test signal LTEST or the like from the incoming clock, thereby performing a connection test between the secondary battery and the protective semiconductor device at a fixed time interval twait.

As shown in Fig. 6, in the time period width tpw of the fixed time interval twait, the control circuit 110 causes the disconnection test signal LTEST output to become "high level" to inform the judgment circuit 120 that the disconnection test is being executed.

Regarding the control signals VG1 to VG4, one of them becomes "low level" with the disconnection test signal LTEST and turns on the PMOS transistors M1 to M4 connected to the respective signals, and then turns on the PMOS transistor M1 according to these To M4, the resistors R11 to R41 are connected in parallel with the voltage-sensitive resistor.

Regarding the control signals Rsw1 to Rsw4, these signals all become "high level" with the disconnection test signal LTEST and turn off the PMOS transistors M11 to M12 respectively connected thereto, and then based on the turned off PMOS transistors, which leads to the resistors Rs13, Rs23 , Rs33, Rs43 series pressure resistors.

The disconnection test interval twait and the off test time period width tpw may be any period, but the off test period period width tpw should be shorter than the delay time generated by the delay circuit 123.

2.4 Operation of protective semiconductor devices

Fig. 7 is a view showing the operation of the protective semiconductor device and the secondary battery of the second embodiment of the present invention. The protective semiconductor device 1 shown in Fig. 7 is also connected as a noise-resistant method by a low-pass filter composed of resistors Rf1 to Rf4 and capacitors Cf1 to Cf4, as shown in Fig. 4.

In the second embodiment, the resistors Rs13, Rs23, Rs33, and Rs43 are connected in series to each of the pressure sensitive resistors of the fault detecting circuit 10 by the pressure sensitive changing circuits 101 to 104 only during the off-detection process. This improves the comparator's anti-phase accuracy by setting the high-voltage detection level VHsens, and solves the problem of not applying The problem that arises in the second embodiment (see Fig. 4), wherein the high voltage detection level VHsens is higher than the disconnection detection level LTsens.

The operation of the protective semiconductor device in the second embodiment will be described with reference to FIG. For convenience of explanation, it is assumed that the voltages VBAT1 to VBAT4, the resistances Rs11 to Rs43, and the resistances Rf1 to Rf4 of the secondary batteries BAT1 to BAT4 satisfy the following conditions (Conditions 6 to 11).

VBAT1=VBAT2=VBAT3=VBAT4 (Condition 6)

Rs11+Rs12=Rs21+Rs22=Rs31+Rs32=Rs41+Rs42 (Condition 7)

Rf1=Rf2=Rf3=Rf4 (Condition 8)

Rs11+Rs12>>Rf1 (Condition 9)

Rs11+Rs12>>R11 (Condition 10)

Rs13=Rs23=Rs33=Rs43 (Condition 11)

Thereafter, in a state where the disconnection test interval twait shown in FIG. 6 elapses, the description of the control signal VG1 becomes "low level" and the PMOS transistor M1 is turned on, and at the same time, the control signals Vsw1 to Vsw4 become "high level" And the PMOS transistors M11 to M14 are turned off. At this time, since the resistors Rs11 and Rs12 are connected in series to the resistor R13 and the resistor R11 is connected in parallel, the current I1 between the battery terminals VC1 to VC2 satisfies the following equation (2-1).

I1=VBAT1/((Rs11+Rs12)xR11/(Rs11+Rs12+Rs11)+Rf1+Rf2) (2-1) Now, the conditional equation (condition 8) and the conditional equation (condition 9) are substituted into the equation (2- 1) The current I1 is expressed as follows (2-2).

Also, since the resistor Rs23 is connected in series with the resistors Rs21 and Rs22, the circuit I2 between the battery terminals VC2 and VC3 is expressed as the following equation (2-3).

I2=VBAT2/(Rs21+Rs22+Rs23+Rf2+Rf3) (2-3)

The conditional equation (condition 8) and the conditional equation (condition 9) are substituted into the equation (2-3) in the same manner as in the equation (2-1), and the current I2 is as shown in the following equation (2-4).

Furthermore, the conditional equation (condition 6) and the conditional equation (condition 7) are substituted into the equation (2-4) as shown in the following equation (2-5).

Using equations (2-2) and (2-5), find the electricity between the battery terminals VC1 and VC2 The current I1 is larger than the current I2 between the battery terminals VC2 and VC3, and the difference is as shown in the following equation (2-6).

I3=I1-I2=VBAT1/R11 (2-6)

The current calculated by the equation (2-6) leaks into the secondary battery through the battery connection terminal VC2 and the resistor Rf2 forming the low-pass filter. Therefore, a voltage is generated in both ends of the resistor Rf2, and the voltage Vvc2 between the battery terminals VC2 and VC3 is larger than the voltage VBAT2 of the secondary battery BAT2. At this time, the voltage Vvc2 between the battery terminals VC2 and VC3 is as shown in the following equation (2-7).

The description up to now is the same as that described in FIG. However, the inverse phase of the comparator is not the high-voltage detection level VHsens calculated by the above equation (1-8), but the off-detection level LTsens calculated by the following equation (2-8).

LTsens=(Rs21+Rs22)/Rs22xVr21+(Rs23/Rs22)xVr21 (2-8)

If the resistor Rs23 is set to satisfy the following equation (2-9), since the voltage VBAT2 of the secondary battery BAT2 does not satisfy the comparison even if the voltage VBAT2 of the secondary battery BAT2 satisfies the equations (1-9) and (1-10) The following equation (2-10) of the condition that the output of the device 12 is inverted is reversed, so the error detection of the disconnection shown in Fig. 4 is prevented.

(Rs23/Rs22)xVr21>(VBAT1/R11)xRf2 (2-9)

VBAT2+(VBAT1/R11)xRf2>LTsens (2-10)

If disconnection occurs between the battery connection terminal VC2 and the secondary battery, after considering the conditional equation (condition 9), the voltage Vvc2 between the battery connection terminals VC2 and VC3 is a voltage value that can be calculated by the following equation.

Vvc2=(Rs21+Rs22+Rs23)/(R11x(Rs11+Rs12+Rs13)/(R11+Rs11+Rs12+Rs13)+Rs21+Rs22+Rs23)x(VBAT1+VBAT2) (2-11)

Next, the conditional equation (condition 7) and the conditional equation (condition 10) are substituted into the equation (2-11), and the following equation (2-12) is obtained.

That is to say, there is no difficulty in detecting the disconnection, even if the judgment condition of the comparator changes to the disconnection detection level LTsens higher than the high-voltage detection level VHsens during the disconnection detection process.

2.5 Detection of the operation of the protective semiconductor device when disconnected

The disconnection detecting operation of the protective semiconductor device will be described below with reference to Figs. 8 and 5. Figure 8 is a timing chart showing the operation of the protective semiconductor device in the second embodiment of the operation detecting disconnection of the present invention. In the timing diagram, only the signals necessary for the description are displayed. For convenience of explanation, it is assumed that the values of the voltages VBAT1 to VBAT4 of the secondary batteries BAT1 to BAT4 and the resistance values of the resistors Rs11 to Rs43 satisfy the following conditional equations (conditions 31 to 33).

VBAT1=VBAT2=VBAT3=VBAT4 (Condition 31)

Rs11+Rs12=Rs21+Rs22=Rs31+Rs32=Rs41+Rs42 (Condition 32)

Rs13=Rs23=Rs33=Rs43 (Condition 33)

In the timing chart shown in Fig. 8, an example is explained in which the protective semiconductor device and the secondary battery are first "connected", secondarily "disconnected", and finally "connected". Hereinafter, it will be described in chronological order.

[Sequence T1]: It is assumed that the secondary battery and the battery connection terminal VC2 are disconnected. At this time, the voltage between the battery terminals VC2 and VC3 is obtained by the local resistances Rs11 to Rs22, and the voltage V2A calculated according to the following equation (3-1) is derived.

V2A=(Rs21+Rs22)/(Rs11+Rs12+Rs21+Rs22)x(VBAT1+VBAT2) (3-1)

Referring to the conditional equations (Condition 31 to Condition 33), it was found that the voltage V2A between the battery terminals VC2 and VC3 is the same as the voltage VBAT2 before the disconnection. Therefore, any of the outputs of the comparators 11 to 14 are fixed.

[Sequence T2]: The disconnection test signal LTEST output from the control circuit 110 changes from the "low level" output to the output "high level" output, and informs the judgment circuit 120 that the disconnection test is being executed. At the same time, the control signal VG1 changes from "high level" to "low level" and the PMOS transistor M1 is turned on. Furthermore, the outputs of the self-control signals Rsw1 to Rsw4 are changed from "low level" to "high level" and all PMOS transistors M11 to M14 are turned off. Therefore, the resistor Rs13 is connected in series with the resistors Rs11 and Rs12 and in parallel with the resistor R11. Since the resistor Rs23 is connected in series with the resistors Rs21 and Rs22, the voltage between the battery terminals VC2 and VC3 is the voltage V2B calculated according to the following equation (3-2).

V2B=(Rs21+Rs22+Rs23)/(R11x(Rs11+Rs12+Rs13)/(R11+Rs11+Rs12+Rs13)+Rs21+Rs22+Rs23)x(VBAT1+VBAT2) (3-2)

The voltage between the battery terminals VC2 and VC3 is substantially equal to the voltage V2C calculated according to the expression (3-3) below, if the resistance R11 is compared with the sum of the resistors Rs11, Rs12 and Rs13 Small enough.

Using equations (3-2) and (3-3), the voltage at the battery connection terminal VC2 is pulled up close to the voltage at the battery connection terminal VC1, which is the positive terminal of the secondary battery BAT1. That is, the voltage between the battery terminals VC2 and VC3 increases, and therefore, the output of the comparator 12 becomes a "low level" indicating the detection state. Therefore, the detection signal VHS outputted by the failure detecting circuit 10 is changed from "low level" to "high level".

Since the disconnection test is being performed (ie, the output of the disconnection test signal LTEST is "high level"), even if the detection signal VHS changes from "low level" to "high level", the AND circuit 124 in the decision circuit 120 will still be high voltage. The detection operation signal VHDet is kept at "low level" (ie, high voltage detection is not performed at this time). That is, the control circuit 110 maintains the disconnection test signal LTEST at "low level." Since the disconnection test is being operated, the other AND circuit 125 in the judging circuit 120 changes the disconnection detection operation signal LTDet from "low level" to "high level" as the detection signal VHS changes from "low level" to "high level". quasi",.

[Sequence T3]: Since the detection signal VHS will maintain the "high level" until the end of the predetermined period, the delay circuit 123 in the decision circuit 120 delays the high level-pulse output output DLY2. The high level-pulse of the delayed output DLY2 from the delay circuit 123 is outputted while the test signal VHS outputting the test signal LTEST is "high level" and the fault detecting circuit 10 is "high level", the logic circuit B 122 judges the occurrence of the disconnection, and changes the disconnection detection signal LCout to "high level" to indicate the disconnection detection state.

[Sequence T4]: The disconnection test signal LTEST becomes "low level", the control signal VG1 changes from the output "low level" to "high level", and thus the PMOS transistor M1 returns to the off state, and the control signals Rsw1 to Rsw4 are outputted. The "high level" becomes "low level", and thus the PMOS transistors M11 to M14 are returned to the on state. The voltage between the battery terminals VC2 and VC3 is returned to the voltage V2A calculated according to the above equation (3-1). Therefore, the detection signal VHS outputted from the failure detecting circuit 10 changes from "high level" to "low level", but since the disconnection test signal LTEST is "low level", the output from the logic circuit B 122 is broken. The open detection signal LCout remains at "high level" and does not change.

[Sequence T5]: The disconnection test signal LTEST output from the control circuit 110, from the output "lower bit" The quasi" becomes "high level", and the judgment circuit 120 is informed that the disconnection test is being executed. At the same time, the output of the control signal VG2 is changed from "high level" to "low level", and thus the PMOS transistor M2 is turned on. The outputs of signals Rsw1 through Rsw4 change from "low level" to "high level" and all PMOS transistors M11 through M12 are turned off.

Thus, the resistor Rs13 is connected in series to the resistors Rs11 and Rs12. Since the resistor Rs23 is connected in series to the resistors Rs21 and Rs22 and the shunt voltage R21, the voltage between the battery terminals VC2 and VC3 is the voltage V2D calculated according to the following equation (3-4).

V2D=(R21x(Rs21+Rs22+Rs23)/(R21+Rs21+Rs22+Rs23))/(Rs11+Rs12+Rs13+(R21x(Rs21+Rs22+Rs23)/(R21+Rs21+Rs22+Rs23))) x(VBAT1+VBAT2) (3-4)

If the voltage R21 is sufficiently smaller than the sum of the resistors Rs21, Rs22, and Rs23, the voltage between the battery terminals Vc2 and VC3 is substantially equal to the voltage V2E calculated according to the following equation (3-5).

Using equations (3-4) and (3-5), it is found that the voltage at the battery connection terminal VC2 is pulled down to the voltage of the battery connection terminal VC3, and the battery connection terminal VC3 is the positive terminal of the secondary battery BAT2. That is, when the voltage between the battery terminals VC2 and VC3 is lowered, the voltage V1A between the battery terminals VC1 and VC2 is increased, which is expressed by the following equation (3-6). Therefore, the comparator 11 detects the high voltage and its output becomes "low level" indicating the high voltage detection state. Therefore, the detection signal VHS outputted by the failure detecting circuit 10 is changed from "low level" to "high level".

V1A=VBAT1+VBAT2-V2E (3-6)

Further, when the test operation is turned off (that is, when the disconnection test signal LTEST is "H"), the detection signal VHS outputted from the failure detecting circuit 10 is changed from "low level" to "high level", but from the logic circuit The disconnection detection signal LCout output by B122 is already "high level" and does not change.

[Sequence T6]: In the same manner as the timing T4, the disconnection test signal LTEST becomes "low level", and the output of the control signal VG2 changes from "low level" to "high level", and thus the PMOS transistor M1 returns to the off state. And the outputs of the control signals Rsw1 to Rsw4 are changed from "high level" to "low level", and thus the PMOS transistors M11 to M14 are returned to the on state. The voltage between the battery terminals VC2 and VC3 is returned to the voltage V2A calculated according to the above equation (3-1). Thus, the detection signal VHS outputted from the failure detecting circuit 10 changes from "high level" to "return" to "low" The level is "," and since the disconnection test signal LTEST is "low level", the off detection signal LCout output from the logic circuit B122 remains at "high level" and remains unchanged.

[Timing T7]: Now, assume that the point of disconnection is fixed.

[Sequence T8]: The disconnection test signal LTEST output from the control circuit 110 is changed from "low level" to "high level", and the logic circuit B 122 is notified that the disconnection test is being executed. At the same time, the control signal VG1 changes from "high level" to "low level" and the PMOS transistor M1 is turned on. Furthermore, the outputs of the control signals Rsw1 to Rsw4 are changed from "low level" to "high level" and all of the PMOS transistors M11 to M14 are turned off. Therefore, the resistor Rs13 is connected in series with the resistors Rs11 and Rs12, and the resistor R11 is connected in parallel. Furthermore, the resistor Rs23 is connected in series with resistors Rs21 and Rs22. However, unlike [Timing T2] to [Timing T3], or [Timing T4] to [Timing T5], since the battery connection terminal VC2 is connected to the secondary battery, the voltage between the battery connection terminals VC2 and VC3 is not from the voltage VBAT2 change. Thus, the output of the fault detection circuit VHS is fixed.

[Sequence T9]: When the detection signal VHS is maintained at the "low level", the delay circuit 123 in the judgment circuit 120 delays the high level-pulse output output DLY2 until the end of the predetermined period. When the disconnection test signal LTEST is "high level" and the detection signal VHS output from the fault detecting circuit 10 is "low level", the high level-pulse is output from the delayed output DLY2 of the delay circuit 123. Thus, the logic circuit B 122 determines that the protective semiconductor device has returned from the off and turns the off detection signal LCout to "low level" to indicate returning from the off detection state.

[Sequence T10]: The disconnection test signal LTEST outputted from the control circuit 210 is changed from "high level" to "low level" to inform the logic circuit B122 that the disconnection test has ended. At the same time, the output of the control signal VG1 changes from "low level" to "high level", so the PMOS transistor M1 returns to the off state, and the outputs of the control signals Rsw1 to Rsw4 change from "high level" to "low level", thus the PMOS The transistors M11 to M14 are returned to the on state. As with [Time Series T8], since the battery connection terminal VC2 is connected to the secondary battery, the voltage between the battery connection terminals VC2 and VC3 does not change from the voltage VBAT2.

This is an example of the operation of the protective semiconductor device when a disconnection occurs between the secondary battery and the battery connection terminal VC2. For the disconnection of other battery terminals (e.g., VC3 or VC4) and the secondary battery, the operation is the same as that of the above example, and thus the description is omitted.

2.6 Summary of the second embodiment

As described above, in the second embodiment, in the protective semiconductor device of the secondary battery, The comparator for detecting voltage fluctuations is mounted in a series connected secondary battery, and the other resistors are sequentially and temporarily connected to the resistance of the comparator forming each secondary battery, and at this time, the comparator detects two The voltage on each end between the secondary battery and the protective semiconductor device fluctuates. When the above resistors are connected in parallel, and at the same time other resistors are connected in series to each of the resistors of the comparators forming all of the respective secondary batteries, the opposite phase of the comparator becomes high. According to this mode, even if the protective semiconductor device is connected through the low-pass filter to be anti-noise, the problem of erroneous detection of disconnection between the secondary battery and the battery connection terminal can be prevented.

<Third embodiment>

According to the second embodiment of the present invention, if a circuit including a smaller value resistor is connected in parallel to each secondary battery in order to level the voltages of the plurality of secondary batteries, the protective semiconductor device sometimes fails to operate normally to turn off the detection. Thus, the protective semiconductor device according to the third embodiment of the present invention can normally operate the disconnection detection by not using a smaller value of resistance when the detection is turned off.

3.1 Structure of protective semiconductor device

Fig. 9 is a schematic view showing a protective semiconductor device and a secondary battery according to a third embodiment of the present invention. Fig. 10 is a schematic view showing the configuration of a protective semiconductor device and a secondary battery according to a third embodiment of the present invention. The protective semiconductor device 1 as shown in Fig. 10 also passes through a low-pass filter (formed by resistors Rf1 to Rf4 and capacitors Cf1 to Cf4) to be anti-noise, as shown in Fig. 7.

The protective semiconductor device 1 according to the third embodiment basically has the same structure as the protective semiconductor device 1 shown in FIG. Therefore, only the differences between the two are described with reference to FIG. 9, FIG. 10, and FIG.

If a function of connecting a smaller value resistor to each secondary battery is added, according to the protective semiconductor device of the second embodiment, sometimes the disconnection detection does not operate normally. According to the configuration of the protective semiconductor device of the third embodiment, the disconnection detection can be made to operate normally while solving this problem.

First, an example in which an additional function is obtained by connecting a resistor having a small value on each secondary battery will be described. In the circuits shown in FIGS. 9 and 10, external resistors Rcb1 to Rcb4, external NMOS transistors Mcb1 to Mcb4, and terminals CB1 to CB4 that output control signals to control the opening or closing of the external NMOS transistors Mcb1 to Mcb4. It was added to the circuit shown in Figure 5. Furthermore, voltage detecting circuits 201 to 204 and battery discharge control circuit 220 are added to the circuit to control external NMOS transistors Mcb1 to Mcb4 in the protective semiconductor device 1. Turn it on or off. The control circuit 110 shown in Fig. 5 is replaced by a control circuit 210 which additionally controls the battery discharge control circuit 220 in the circuits shown in Figs. 9 and 10 by the control signal CBCTL. The external resistors Rcb1 to Rcb4, the external NMOS transistors Mcb1 to Mcb4, the terminals CB1 to CB4, the voltage detecting circuits 201 to 204, and the battery discharging control circuit 220 are circuits for obtaining the above-described additional functions.

The circuit that obtains the above additional function performs a function of leveling the voltages of a plurality of secondary batteries. First, the voltage detecting circuits 201 to 204 are voltage detecting circuits for setting voltage levels to trigger the external NMOS transistors Mcb1 to Mcb4. For example, when the voltage of the secondary battery BAT1 exceeds 4.0 V, the output of the voltage detecting circuit 201 is "low level". This signal is then transmitted to the battery discharge control circuit 220. In response to the outputs from the voltage detecting circuits 201 to 204, the battery discharging control circuit 220 is a control circuit output to the terminals CB1 to CB4 in accordance with the state of the protective semiconductor device 1. For example, when the output of the voltage detecting circuit 201 is "low level", if the battery discharging control circuit 220 determines that the "high level" can be output to the terminal CB1 according to the state of the protective semiconductor device 1, the "high level" signal is output to Terminal CB1. Therefore, the "high level" signal is input to the NMOS transistor Mcb1, and the resistor Rcb1 having a smaller resistance value shunts the positive terminal and the negative terminal of the secondary battery BAT1. By loading a current on the path containing the resistor Rcb1, if the voltage of each secondary battery exceeds 4.0 V, the secondary battery discharges an excessive charge exceeding 4.0 V. The voltage of a plurality of secondary batteries can be leveled by discharging until the voltage of all the secondary batteries reaches 4.0V.

As described above, the circuit that obtains an additional function performs the function of leveling a plurality of secondary battery voltages. The circuit configuration that achieves this function has a relatively small value of resistance. For these resistors Rcb1 to Rcb4, resistances equal to or smaller than the resistors R11 to R41 are often used. Therefore, if a large amount of current is loaded in the path including the resistors Rcb1 to Rcb4, the disconnection detection is performed using the connection resistors Rcb1 to Rcb4, and the operation of the disconnection detection does not operate normally. Similarly, if the voltage detecting circuits 201 to 204 output "low level" as the detection is turned off, the operation of the disconnection detection does not normally operate, and in response, the battery discharge control circuit 220 turns on the NMOS transistor. Mcb1 to Mcb4 connect the resistors Rcb1 to Rcb4.

The control circuit 210 outputs a "low level" to the control signal CBCTL just before the start of the disconnection detection. In order not to turn on the external NMOS transistors Mcb1 to Mcb4, the control circuit 210 transmits to the control circuit 220 to inform that the disconnection detection is about to start. In this way, the disconnected probe can be performed normally.

Note that the circuit for obtaining an additional function is not limited to the function of performing a leveling of a plurality of secondary battery voltages. Also, any circuit that obtains this additional function can be applied to the third embodiment of the present invention, for example, by connecting a smaller value resistor to each secondary battery.

3.2 Control circuit control signal

Fig. 11 is a view showing an example of a control signal of the control circuit 210 of the protective semiconductor device of the third embodiment of the present invention. The resistors Rcb1 to Rcb4 are connected to the circuit of the third embodiment shown in Figs. 9 and 10, wherein the resistors Rcb1 to Rcb4 are smaller than the resistors R11 to R41 whose resistance value is smaller than the voltage-sensitive resistors connected when the detection is turned off.

The basic function of each control signal is the same as each control signal of the control circuit 110 in the protection semiconductor device in the second embodiment shown in FIG. However, one of the terminals CB1 to CB4 (eg, the terminal CBx) outputs a "high level" before the disconnection test signal LTEST becomes "high level", and thus one of the NMOS transistors connected to the resistor Rcbx is turned on. In this case, the control circuit 210 switches the control signal CBCTL from "high level" to "low level" before the time period tpw, wherein the time period tpw is the time when the disconnection test signal LTEST becomes "high level". In response to this, the battery discharge control circuit 220 forces their output to become "low level" regardless of the state of the terminals CB1 to CB4. After this moment, when the operation of disconnection detection is performed after the disconnection test signal LTEST becomes "high level", the protective semiconductor device according to the third embodiment becomes the protective semiconductor device of the first embodiment. The same state in which the circuit for obtaining the above-described additional functions is not provided in the first embodiment. It is noted that the timing tcb of the control resistor is controlled before the detection of the disconnection operation, and the timing tcb is a timing sufficient for the secondary battery and the overall circuit to return to normal operation.

3.3 Operation of protective semiconductor devices

The operation of the protective semiconductor device according to the third embodiment of the present invention will be described with reference to Figs. 12, 9 and 10. Fig. 12 is a timing chart showing the operation of the protective semiconductor device of the third embodiment of the present invention. In the timing diagram, only the signals that need to be described are displayed. The operation of detecting disconnection is basically the same as that shown in Fig. 8. Also shown in Fig. 12, an example is shown to illustrate that the protective semiconductor device and the secondary battery are first "connected", second "disconnected", and then "connected" again at the end. After that, the operations will be described in chronological order.

[Sequence T1]: This timing is a timing for explaining disconnection of the secondary battery and the battery connection terminal VC2.

[Sequence T2]: The control signal CBCTL output from the control circuit 10 is changed from "high level" to "low level" Quasi, the output of the battery discharge control circuit 220 is forced to become "low level", and the "low level" is output to the NMOS transistors Mcb1 to Mcb4 regardless of the states of the voltage detecting circuits 201 to 204.

[Sequence T3]: The disconnection test signal LTEST outputted by the control circuit 210 is changed from the "low level" output to the "high level" output, and the judgment circuit 120 is informed that the disconnection test is in progress. At the same time, the control signal VG1 has changed from "high level" to "low level" and the PMOS transistor M1 is turned on. Furthermore, the outputs of the control signals Rsw1 to Rsw4 are changed from "low level" to "high level" and all of the PMOS transistors M11 to M14 are turned off. Therefore, the resistor Rs13 is connected in series with resistors Rs11 and Rs12, and the resistor R11 is connected in parallel. The resistor Rs23 is connected in series with resistors Rs21 and Rs22.

The voltage of the battery connection terminal VC2 is pulled up close to the voltage of the battery connection terminal VC1, wherein the battery connection terminal VC1 is the positive terminal of the secondary battery BAT1. Further, the voltage between the battery terminals VC2 and VC3 increases, and therefore, the output of the comparator 12 becomes "low level" indicating the detection state. Therefore, the detection signal VHS outputted by the failure detecting circuit 10 is changed from "low level" to "high level". Since the disconnection test is being performed (ie, the output of the disconnection test signal LTEST is "high level"), even if the detection signal VHS changes from "low level" to "high level", the AND circuit 124 in the decision circuit 120 will still be high voltage. The detection operation signal VHDet is kept at "low level" (ie, high voltage detection is not performed at this time). The AND circuit 125 in the judging circuit 120 changes the disconnection detecting operation signal LTDet from "low level" to "high level" as the detection signal VHS changes from "low level" to "high level".

[Sequence T4]: Since the detection signal VHS will maintain the "high level" until the end of the predetermined period, the delay circuit 123 in the decision circuit 120 delays the high level-pulse output output DLY2. The high level-pulse of the delayed output DLY2 from the delay circuit 123 is outputted while the test signal VHS outputting the test signal LTEST is "high level" and the fault detecting circuit 10 is "high level", the logic circuit B 122 judges the occurrence of the disconnection, and changes the disconnection detection signal LCout to "high level" to indicate the disconnection detection state.

[Sequence T5]: The disconnection test signal LTEST becomes "low level", the output of the control signal VG1 changes from "low level" to "high level", and thus the PMOS transistor M1 returns to the off state, and the control signals Rsw1 to Rsw3 The output changes from "high level" to "low level", and thus the PMOS transistors M11 to M14 return to the on state. Thus, the voltage between the battery terminals VC2 and VC3 returns. Therefore, the detection signal VHS outputted by the fault detecting circuit 10 changes from "high level" to "low level", but the off detection signal LCout outputted by the logic circuit B 122 remains at "high level". And since the disconnection test signal LTEST is "low level", it remains unchanged. The control circuit 210 is being input with a "high level" signal that turns off the detection signal LCout and maintains a "low level" state of the control signal CBCTL. Thus, the battery discharge control circuit 220 continues to output the signal "low level" to the NMOS transistors Mcb1 to Mcb4 regardless of the states of the voltage detecting circuits 201 to 204.

[Sequence T6]: The disconnection test signal LTEST outputted by the control circuit 110 is changed from "low level" to "high level", and the judgment circuit 120 is informed that the disconnection test is being executed. At the same time, the control signal VG2 output changes from "high level" to "low level", and thus the PMOS transistor M2 is turned on. Furthermore, the outputs of the control signals Rsw1 to Rsw4 are changed from "low level" to "high level" and all of the PMOS transistors M11 to M12 are turned off. Therefore, the resistor Rs13 is connected in series to Rs11 and Rs12. Since the resistor Rs23 is connected in series with the resistors Rs21 and Rs22, and the resistor Rs21 is connected in parallel, the voltage of the battery connection terminal VC2 is pulled down to the voltage of the battery connection terminal VC3, wherein the battery connection terminal VC is the negative terminal of the secondary battery BAT2. Further, when the voltage between the battery terminals VC2 and VC3 is lowered, the voltage V1A between the battery terminals VC1 and VC2 is increased. Therefore, the detection signal VHS outputted by the failure detecting circuit 10 is changed from "low level" to "high level".

Further, when the test operation is turned off (that is, when the disconnection test signal LTEST is "high level"), the detection signal VHS outputted by the fault detecting circuit 10 is changed from "low level" to "high level", but the logic circuit B The off-detection signal LCout of the output of 122 is already "high level" and remains unchanged.

[Sequence T7]: In the same manner as [Time Series T5], the disconnection test signal LTEST becomes "low level", and the output of the control signal VG1 changes from "low level" to "high level", and thus the PMOS transistor M1 returns The state is turned off, and the outputs of the control signals Rsw1 to Rsw4 are changed from "high level" to "low level", and thus the PMOS transistors M11 to M14 are returned to the on state. The voltage between the battery terminals VC2 and VC3 returns. Thus, the detection signal VHS outputted by the failure detecting circuit 10 changes from "high level" to "low level", but the off detection signal LCout output from the logic circuit B 122 remains at "high level" and is disconnected due to the disconnection test. The signal LTEST is "low level" and remains unchanged. Since the disconnection detection signal LCout is "high level", the control signal CBCTL remains "low level" and the output of the battery discharge control circuit 220 is also forced to remain "low level".

[Sequence T8]: Now, assume that the point of disconnection is fixed.

[Sequence T9]: The disconnection test signal LTEST outputted by the control circuit 210 changes from "low level" to "high level", and informs the logic circuit B 122 that the disconnection test is being executed. At the same time, the control signal VG1 changes from "high level" to "low level" and the PMOS transistor M1 is turned on. Furthermore, the control signal Rsw1 The output to Rsw4 changes from "low level" to "high level" and all PMOS transistors M11 to M14 are turned off. Therefore, the resistor Rs13 is connected in series with the resistors Rs11 and Rs12, and the resistor R11 is connected in parallel. Furthermore, the resistor Rs23 is connected in series with resistors Rs21 and Rs22. However, unlike [Timing T2] to [Timing T3], or [Timing T4] to [Timing T5], since the battery connection terminal VC2 is connected to the secondary battery, the voltage between the battery terminals VC2 and VC3 does not change from the voltage. VBAT2. Thus, the output of the fault detection circuit VHS is fixed.

[Sequence T10]: When the detection signal VHS is maintained at the "low level", the delay circuit 123 in the judgment circuit 120 delays the high level-pulse output output DLY2 until the end of the predetermined period. When the disconnection test signal LTEST is "high level" and the detection signal VHS output from the fault detecting circuit 10 is "low level", the high level-pulse is output from the delayed output DLY2 of the delay circuit 123. Thus, the logic circuit B 122 determines that the protective semiconductor device has returned from the off and turns the off detection signal LCout to "low level" to indicate returning from the off detection state.

[Sequence T11]: The disconnection test signal LTEST outputted by the control circuit 210 is changed from "high level" to "low level" to inform the logic circuit B 122 of the end of the test. At the same time, the output of the control signal VG1 changes from "low level" to "high level", so the PMOS transistor M1 returns to the off state, and the outputs of the control signals Rsw1 to Rsw4 change from "high level" to "low level", thus the PMOS The transistors M11 to M14 are returned to the on state. As with [Time Series T9], since the battery connection terminal VC2 is connected to the secondary battery, the voltage between the battery connection terminals VC2 and VC3 is not changed to the voltage VBAT2. Thus, the output of the fault detection circuit VHS is fixed.

Furthermore, since the disconnection detection signal LCout outputted by the determination circuit 120 becomes "low level" and the disconnection test signal LTEST becomes "low level", the control circuit 210 switches from "low level" to "high level" control. The signal CBCTL is output to the battery discharge control circuit 220. In response to this, if the voltage detecting circuits 201 to 204 and the protective semiconductor device 1 are in a state in which it is possible to output "high level" to the NMOS transistors Mcb1 to Mcb4, the battery discharge control circuit 220 changes to a state of outputting "high level". in.

This is an example of the operation of the protective semiconductor device when a disconnection occurs between the secondary battery and the battery connection terminal VC2. For the disconnection of other battery terminals (e.g., VC3 or VC4) and the secondary battery, the operation is the same as the above-described exemplary principle, and thus the description is omitted.

3.4 Summary of the third embodiment

As described above, in the third embodiment, in the protective semiconductor device of the secondary battery, The comparator for detecting voltage fluctuations is mounted in a series connected secondary battery, and the other resistors are sequentially and temporarily connected to the resistance of the comparator forming each secondary battery, and at this time, the comparator detects two The voltage on each end between the secondary battery and the protective semiconductor device fluctuates. When the above resistors are connected in parallel, and at the same time other resistors are connected in series to each of the resistors of the comparators forming all of the respective secondary batteries, the opposite phase of the comparator becomes high. At this time, the resistance connected in parallel to each secondary battery was disabled. Therefore, the protective semiconductor device enables the disconnection detection between the secondary battery and each of the battery terminals to operate normally, and also relates to each of the secondary batteries in series having resistance between the positive and negative terminals.

<Fourth embodiment>

The protective semiconductor device in the first to third embodiments performs detection of high voltage and disconnection. The disconnection detection is performed when the protective semiconductor device is in the high voltage protection detection mode, and this state is no longer effectively maintained, and the determination circuit 120 is controlled during the detection of the high voltage protection, making it impossible to perform the operation of the disconnection detection.

However, at least one secondary battery enters an overcharged state due to the occurrence of disconnection, which sometimes causes the protective semiconductor device to become a high voltage protection detection mode. In this case, the test disconnection test (disconnection test operation) cannot be performed despite the disconnection, and thus the disconnection is not detected.

Therefore, according to the protective semiconductor device in the fourth embodiment, a trailing selector circuit is added. The trailing selector circuit does not input the signal of the fault detecting circuit into the circuit that maintains the overcharge detection mode (high voltage protection detection mode), but instead represents the internal signal (disconnecting the test signal) that is performing the probe disconnection test. When LTEST) is turned on, the state held in the overcharge detection mode (high voltage protection detection mode) circuit is recursively input. Therefore, the overcharge detection mode (high voltage protection detection mode) can be maintained regardless of whether the detection of the disconnection test is performed, and the disconnection detection can be performed in the overcharge detection mode (high voltage protection detection mode).

4.1 Structure and operation of a part of the judgment circuit in the first to third embodiments

Before describing the fourth embodiment, the configuration of the input and output portions of the partial circuit of the judging circuit 120 in the protective semiconductor device of the first to third embodiments will be described. Fig. 13 is a view showing the circuit configuration of the input and output portions of the judging circuit 120 of the protective semiconductor device according to the first to third embodiments of the present invention.

The circuit shown in FIG. 13 includes: a NAND circuit 15 included in the fault detecting circuit 10; an XOR circuit 140; a NAND circuit 145; a NOR circuit 146; a flip-flop 150; 142, 144, 148. The XOR circuit 140 sends a signal to the circuit that generates the delay timing to return from the high voltage detection to the delay circuit 123 to set the delay timing returned from the high voltage detection, while at the same time, the output signal of the NAND circuit 15 and the flip-flop 150 The high voltage detection signal VHout of the output signal is input. The input signals of the NAND circuit 145 are the two output signals of the delay circuit 123 and the inverted output signals of the NAND circuit 145. The input signal of the NOR circuit 146 is one of the output signal of the NAND circuit 15, one of the output signals of the delay circuit 123, and the inverted phase signal VHoutb of the high voltage detection signal VHout of the output signal of the flip-flop 150. The input signal of the flip-flop 150 is the output signal of the NAND circuit 145, the inverted signal of the output signal of the NAND circuit 145, and the output signal of the NOR circuit 146, and the output signal of the flip-flop 150 is the high-voltage detection signal VHout and its opposite phase. Signal VHoutb.

Hereinafter, the operation of the circuit shown in Fig. 13 will be described. First, a case is assumed that the judging circuit 120 does not remain in the high voltage protection detecting mode. In this case, in addition to the high voltage protection detection mode (i.e., VHout = "low level"), a high voltage detection signal representing the state of the determination circuit 120 is input to one of the inputs of the XOR circuit 140. The NAND circuit 15 outputs the NAND signals of the comparators 11, 12, 13, 14 for high voltage detection. If the output of at least one of the comparators becomes a probing state ("low level" state), the "high level" signal output by the NAND circuit 15 is input to the other input of the XOR circuit 140. Thus, based on the output of NAND circuit 15, XOR circuit 140 sends a "high level" signal to the circuit that produces the delay timing to return from the high voltage detection. After the end of the reservation (delay) timing, if the NAND circuit 15 outputs a "high level" signal, the high voltage detection signal VHout becomes "high level" and the protective semiconductor device enters the high voltage protection detection mode.

Second, assume that the decision circuit 120 remains in the high voltage protection detection mode. In this case, in addition to the high voltage protection detection mode (i.e., VHout = "low level"), a high voltage detection signal representing the state of the determination circuit 120 is input to one of the inputs of the XOR circuit 140. If the output from all the comparators becomes a normal state ("high level" state), the "low level" signal output by the NAND circuit 15 is input to the other input of the XOR circuit 140. Thus, XOR circuit 140 issues a "high level" signal to the circuit that produces the delay timing to return from the high voltage detection based on the two inputs. After the end of the reservation (delay) timing, if the NAND circuit 15 still outputs the "low level" signal, the high voltage detection signal VHout output from the determination circuit 120 becomes "low level", and the protective semiconductor device returns to the high voltage protection detection mode. status.

It is noted that when the judging circuit 120 maintains the high voltage protection detection mode (ie, VHout = "high level"), the control circuit 110 shown in FIGS. 1 , 5 and 9 keeps the disconnection test signal LTEST at the "low level". quasi". Further, in this state, the disconnection test is not performed.

4.2 Structure of protective semiconductor device

Next, the protective semiconductor device 1 of the fourth embodiment will be described. Fig. 14 is a schematic view showing a protective semiconductor device 1 and a secondary battery according to a fourth embodiment of the present invention. The protective semiconductor device according to the fourth embodiment has a structure similar to that of the second embodiment. Therefore only the difference between the two is described.

The fault detecting circuit 10 of the protective semiconductor device 1 according to the fourth embodiment of the present invention includes: comparators 11, 12, 13, 14; reference voltages Vr11, Vr21, Vr31, Vr41; local resistors Rs11, Rs12, Rs21, Rs22, Rs31, Rs32, Rs41, Rs42; NAND circuit 15; voltage change changing circuits 101, 102, 103, 104; and hysteresis forming circuits 351, 352, 353, 354.

As shown in Fig. 14, the hysteresis forming circuit 351 is constituted by a parallel connection of the resistor Rs14 and the NMOS transistor M31. The other hysteresis forming circuits 352, 353, and 354 are the same.

In the failure detecting circuit 10 of the protective semiconductor device of the fourth embodiment shown in Fig. 14, the circuit for detecting the high voltage and the disconnection of the secondary battery BAT1 is formed by the comparator 11, the resistors Rs11, Rs12, and Rs14, forming hysteresis. The NMOS transistor M31, the reference voltage Vr11, and the pressure sensitive change circuit 101 are constructed. The resistors Rs11, Rs12, Rs14 and the pressure sensitive changing circuit 101 are connected in series and further connected between the battery terminals VC1 and VC2. The connection point of the resistors Rs11 and Rs12 is connected to the inverting input of the comparator 11. The reference voltage Vr11 is connected between the non-inverting input of the comparator 11 and the battery connection terminal VC2. Note that the resistors Rs11 and Rs12 are the voltage sensitive resistors of the first secondary battery BAT1.

When the high voltage and the disconnected circuit of the secondary battery BAT1 are detected without detecting the high voltage, the resistor Rs14 is shunted by turning on the NMOS transistor M31 in the hysteresis forming circuit 351. On the other hand, when the high voltage is detected, the NMOS transistor M31 is turned off by the signal of the high voltage hysteresis VHhys (described below). Therefore, the resistor Rs14 is inserted between the resistor Rs12 and the battery connection terminal VC2. As a result, in the circuit for detecting high voltage and disconnection, the voltage returned from the high voltage protection detection mode is smaller than the voltage that becomes the high voltage protection detection mode. This means that the circuit that detects high voltage and disconnect has a hysteresis relative to the high voltage protection detection mode.

The pressure sensitive changing circuit 101 in this embodiment has a structure similar to that of the pressure changing circuit in the second embodiment. The failure detecting circuits of the second secondary battery BAT2 to the fourth secondary battery BAT4 have the same structure as the failure detecting circuit of the first secondary battery BAT1.

The control circuit 410 is input to the off detection signal LCout, and outputs the control signals VG1, VG2, VG3, VG4 to the PMOS transistors M1 to M4 of the internal resistance change circuit 300 and the output off test signal LTEST to the decision circuit 320. Furthermore, the control circuit 410 outputs the control signals Rsw1, Rsw2, Rsw3, and Rsw4 to the gates of the PMOS transistors M11 to M14 of the voltage sensitive changing circuits 101 to 104, respectively. Further, a clock, an external trigger, or the like, which is not shown in the figure, is connected as its input, thereby generating control signals VG1 to VG4 and a disconnection test signal LTEST, and control signals Rsw1, Rsw2, Rsw3, and Rsw4.

The judging circuit 320 is a circuit for judging whether the fault detecting circuit 10 has detected a high voltage or a disconnection. The judging circuit 320 includes a selection circuit 327, an AND circuit 324, an AND circuit 325, a logic circuit A 121, a logic circuit B 121, a NOR circuit 322, a delay circuit 123, and an inverting circuit 326.

The judging circuit 320 is input to the detecting signal VHS outputted by the fault detecting circuit 10 and the disconnection test signal LTEST, and outputs a high voltage detecting signal VHout, a signal of a high voltage hysteresis VHhys, and a disconnection detecting signal LCout. The internal structure of the judgment circuit 320 will be described in detail below.

The selection circuit 327 located at the input portion of the decision circuit 320 is input with the high voltage detection signal VHout and the detection signal VHS, wherein the detection signal VHS is the output of the fault detection circuit 10 (of the NAND circuit 15), and the selection circuit 327 is based on the disconnection test signal LTEST The state selection outputs at least one signal.

The AND circuit 324 is input with the high voltage detection signal VHout and the inverted output signal of the selection circuit 327, and outputs the high voltage detection operation signal VHDet. The AND circuit 325 is input with the detection signal VHS and the disconnection test signal LTEST from the output of the NAND circuit 15 of the fault detecting circuit 10, and outputs the disconnection detecting operation signal LTDet.

The logic circuit A 121 is input with the high voltage detection operation signal VHDet and the delay output DLY1 from the delay circuit 123, and outputs the high voltage detection signal VHout.

The logic circuit B 122 is input with the off detection operation signal LTDet and the delay output DLY2 from the delay circuit 123, and outputs the off detection signal LCout.

The NOR circuit 322 is input with the high voltage detection signal VHout and the disconnection test signal LTEST, and The signal of the high voltage hysteresis VHhys is output.

The delay circuit 123 is input with the high voltage detection operation signal VHDet, the detection operation signal LTDet, the high voltage detection signal VHout, and the disconnection detection signal LCout. Further, the delay circuit 123 outputs the delayed output DLY1 to the logic circuit A 121, and delays the output DLY2 to the logic circuit B 122 as its input.

The delay circuit 123 is a circuit that sets a delay time of detection/return to prevent noise or the like from causing false detection. When the fault detecting circuit 10 detects a high voltage, once the signal VHDet output from the AND circuit 124 changes from "low level" to "high level", the delay circuit 123 starts execution, and then if the signal VHDet continues to be "high level", the output high level Quasi-pulse to output DLY1 until the end of the predetermined period. In order to return from the high voltage detection mode, once the signal VHDet output from the AND circuit 124 changes from "high level" to "low level", the delay circuit 123 starts execution, and if the signal VHDet is "low level", the high level-pulse is output until The scheduled period ends. The detection/return determination is performed based on the high voltage detection signal VHout. For example, the high-voltage detection signal VHout "high level" is judged as "probe" and the "low level" is judged as "return".

When the fault detecting circuit 10 has detected the disconnection, once the disconnection detecting operation signal LTDet output from the AND circuit 125 changes from "low level" to "high level", the delay circuit 123 starts execution if the signal LTDet is "high level" ", output high level - pulse to delay output DLY2 until the end of the predetermined period. In order to return to the disconnection detection mode, once the signal LTDet output from the AND circuit 125 changes from "high level" to "low level", the delay circuit 123 starts execution, and if the signal LTDet is "low level", the output high level-pulse Until the end of the scheduled period. The judgment of the detection/return is performed based on the disconnection detection signal LCout. For example, the disconnection detection signal LCout "high level" is judged as "probe" and the "low level" is judged as "return".

It is noted that the predetermined period of these high-voltage detection times, the predetermined period from the high-voltage return, the predetermined period of the disconnection detection, and the predetermined period of returning from the disconnection need not be the same, and may be different from each other. Further, if the circuit operates in the same manner, the delay circuit 123 can have any structure such as a counter and a capacitor charged with a fixed current.

4.3 Part of the judgment circuit structure and performance

Next, specifically, the structure of the input and output portions of the judging circuit 320 in the protective semiconductor device of the fourth embodiment will be described. Fig. 15 is a view showing the circuit configuration of the input and output portions of the judging circuit of the protective semiconductor device of the fourth embodiment of the present invention.

The circuit shown in Fig. 15 includes: a NAND circuit 15 included in the fault detecting circuit 10; a selecting circuit 327; an XOR circuit 140; a NAND circuit 145; a NOR circuit 146; a flip-flop 150; a NOR circuit 322; 148, 355, 356.

The selection circuit 327 is added to the circuit shown in Fig. 15 as compared with the input and output portions of the judging circuit 20 of the protective semiconductor device of the first to third embodiments shown in Fig. 13. The selector circuit 327 is input with the high voltage detection signal VHout as the first input, and the output signal of the NAND circuit 15 input to the failure detecting circuit 10 as the second input. Furthermore, the disconnection test signal LTEST is input to the selection terminal of the selector circuit 327. When the "high level" signal is input to the selection terminal, the selector circuit 327 outputs a signal input to the first input (terminal A shown in FIG. 15), and when the "low level" signal is input to the selection terminal, the selector The circuit 327 outputs a signal input to the second input (terminal B shown in Fig. 15). That is, when the disconnection test signal LTEST is "high level" (under the disconnection test), the selector circuit 327 outputs the high voltage detection signal VHout, and when the disconnection test signal LTEST is "low level" (not disconnected) When tested, the selector circuit 327 outputs an output signal from the NANd circuit 15 of the fault detecting circuit 10.

When the output signal of the selection circuit 327 and the high voltage detection signal VHout as the output signal of the flip-flop 150 are input, the XOR circuit 140 sends a signal to the circuit that generates the delay timing to return to the high voltage detection, wherein the circuit is included in the setting from the high voltage detection. The delay timing of the returned delay circuit 123. The NAND circuit 145 is input to the two output signals of the delay circuit 123 and the output signal of the selection circuit 327. The NOR circuit 146 is input to the output signal of the NAND circuit 15, the output signal of the delay circuit 123, and the inverted phase signal VHoutb of the high voltage detection signal VHout which is the output signal of the flip-flop 150. The flip-flop 150 is input to the output signal of the NAND circuit 145, the inverted output signal of the NAND circuit 145, and the output signal of the NOR circuit 146, and outputs the high-voltage detection signal VHout and its inverted phase signal, the high-voltage detection signal VHoutb.

Hereinafter, the operation of the circuit shown in Fig. 15 will be described. First, when the disconnection test is not performed (ie, the test signal LTEST = "low level" is turned off), the "low level" signal is input to the selection terminal of the selector circuit 327, and is input to the B terminal of the selector circuit 327. The output signal of the NAND circuit 15 of the fault detecting circuit 10 (second input) is output from the selector circuit 327. Therefore, when the disconnection test is not performed, the protective semiconductor device in the fourth embodiment cannot enter the high voltage protection detecting mode and return from the high voltage protection detecting mode, like the protective semiconductor devices in the first to third embodiments.

When the disconnection test is performed (ie, the test signal LTEST = "high level" is turned off), the "high level" signal is input to the selection terminal of the selector circuit 327 and is input to the A terminal of the selector circuit 327 (first The input high voltage detection signal VHout is output from the selection circuit 327. At this time, an in-phase signal is input to both ends of the XOR circuit 140 located after the selector circuit 327. That is, when the high voltage detection signal is in the high voltage protection detection mode (VHout = "high level"), the "high level" signal is input to both ends of the XOR circuit 140, and when the high voltage detection signal is not in the high voltage protection detection mode ( When VHout = "low level", the "low level" signal is input to both ends. Since the XOR circuit 140 outputs a "low level" signal at this time, the circuit which generates the delay timing which is set later cannot perform the return from the high voltage detection. Since the circuit that generates the delay timing cannot perform the return of the high voltage detection, the high voltage detection signal VHout does not change.

This means that even if the disconnection detection is performed and thus the output of the fault detecting circuit 10 is changed, since the circuit that generates the delay timing to return from the high voltage detection is not performed, the high voltage detection signal VHout does not change. Therefore, even when the disconnection detection test is performed while the protective semiconductor device is in the high voltage protection detection mode, the high voltage protection detection mode of the flip flop 150 is maintained. Therefore, it is not necessary for the control judging circuit 320 to perform the operation of the disconnection detection during the high voltage detection and protection process.

Table 1 below illustrates the relationship between the high voltage detection signal VHout, the disconnection test signal LTEST, and the output of the selection circuit 327 (vdlq). Note that "VHS" represents the output signal of the NAND circuit 15.

Further, a circuit is connected after the flip-flop 150 in the circuit shown in Fig. 15, wherein the circuit is constituted by inverters 355 and 356 and forms a hysteresis (VHhys) of the high voltage detection signal VHout. Just before this circuit, the NOR circuit 322 is set. The high voltage detection signal VHout and the disconnection test signal LTEST are input to the NOR circuit 322. During the disconnection probing test (i.e., LTEST = "high level"), the high voltage hysteresis signal is fixed to "low level" by the NOR circuit 322 regardless of the state of the high voltage detection signal VHout. As a result, the hysteresis forming circuits 351, 352, 353, 354 The NMOS transistors M31, M32, M33, and M34 are turned on, and then the hysteresis forming circuits 351, 352, 353, and 354 are shunted. That is, the NOR circuit 322 controls the threshold voltage not to decrease due to the hysteresis of the high voltage detection signal, and its threshold voltage represents whether or not the disconnection has occurred (specifically, the voltage returned from the detected off state). As a result, the threshold voltage representing whether or not the disconnection has occurred remains unchanged, regardless of the state of the high voltage detection signal just before the detection of the disconnection test, and the erroneous detection of the disconnected state is prevented.

Table 2 below describes the high voltage detection signal VHout, the disconnection test signal LTEST, and the high voltage hysteresis VHhys signal.

4.4 Summary of the fourth embodiment

As described above, in the fourth embodiment, in the protective semiconductor device of the secondary battery, the comparator in which the voltage fluctuation is detected is disposed in the secondary battery in series, and the resistors are sequentially and temporarily connected to form each The resistance of the comparator of the secondary battery. Further, the comparator detects voltage fluctuations at each of the battery terminals between each of the secondary batteries and the protective semiconductor device. The protective semiconductor device includes circuitry that maintains the signal in a state prior to the disconnection detection between the secondary battery and the protective semiconductor device during the detecting operation. The state of the signal indicates whether at least one secondary battery is at a high voltage. In this way, the high voltage protection detection mode is maintained even when the protective semiconductor device performs the detection disconnection test in the high voltage protection detection mode.

As described above, by applying the present invention, if a part of the connection between the secondary battery and the protective semiconductor device is broken when the secondary battery is used, the occurrence of this disconnection can be reliably detected.

Although the invention has been described in terms of specific embodiments, the invention is not limited thereto. It will be apparent that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention. Therefore, it is to be understood that the invention is intended to cover the modifications and

1‧‧‧Protective semiconductor device

10‧‧‧Fault detection circuit

11, 12, 13, 14‧‧ ‧ comparator

15‧‧‧NAND circuit

100‧‧‧Internal resistance change circuit

110‧‧‧Control circuit

120‧‧‧Judgement circuit

121‧‧‧Logic Circuit A

122‧‧‧Logic Circuit B

123‧‧‧Delay circuit

124, 125‧‧‧AND circuit

126, 127‧‧‧ inverter circuit

BAT1, BAT2, BAT3, BAT4‧‧‧ secondary batteries

DLY1, DLY2‧‧‧ delayed output

LCout‧‧‧ disconnected detection signal

LTDet‧‧‧Disconnect detection operation signal

LTEST‧‧‧ disconnect test signal

M1, M2, M3, M4‧‧‧ PMOS transistors

R11, R21, R31, R41‧‧‧ resistance

Rs11, Rs12, Rs21, Rs22, Rs31, Rs32, Rs41, Rs42‧‧‧ local resistance

VC1, VC2, VC3, VC4‧‧‧ battery connection

VDD‧‧‧ power supply terminal

VHDet‧‧‧High-voltage detection operation signal

VHout‧‧‧High voltage detection signal

VHS‧‧‧ detection signal

VG1, VG2, VG3, VG4‧‧‧ control signals

Vr11, Vr21, Vr31, Vr41‧‧‧ reference voltage

VSS‧‧‧ grounding terminal

Claims (11)

A protective semiconductor device capable of detecting a voltage state of a plurality of secondary batteries connected in series, the protective semiconductor device comprising: a plurality of connection terminals connectable to an electrode of each secondary battery; a plurality of first a resistor, which detects the voltage of each secondary battery, is disposed to correspond to each secondary battery, and is connected between a high voltage side and a low voltage side terminal corresponding to each electrode; a plurality of comparators, etc. Whether the voltage of each of the secondary batteries is within a reference voltage range can be detected by a voltage corresponding to each of the secondary batteries and obtained according to the first resistances; a plurality of series circuits each of which is composed of a second resistor and a first switching element configured to correspond to each of the secondary batteries and connected between the terminals; and a control circuit that controls on/off of each of the first switching elements, the first switching element Connecting the second resistor between the terminals by opening, the first switching element is disconnected from the terminals by being turned off, and the control circuit While maintaining an open state of a disconnection test signal, the first switching elements are sequentially turned on, and the control circuit detects the signals according to an output signal of the comparator from the first switching element corresponding to the opening Disconnection between the secondary battery and the terminals. The protective semiconductor device of claim 1, further comprising: a plurality of third resistors corresponding to each of the first resistors; and a plurality of second switching elements that switch each of the terminals and a connection/disconnection of a third resistor between the first resistors, wherein the control circuit changes the detection criteria of the comparator by transmitting a signal while the off test signal remains in the on state The reference voltage level is used to control the second switching element to connect the third resistor. The protective semiconductor device according to claim 2, wherein the comparators detect whether the voltage of each of the secondary batteries is greater than the reference voltage. The protective semiconductor device according to claim 2, wherein the comparators detect whether the voltage of each of the secondary batteries is less than the reference voltage. The protective semiconductor device according to claim 2, wherein the disconnection detection between the secondary battery and the terminals is performed only when the control circuit maintains the open state of the disconnection test signal . The protective semiconductor device of claim 2, wherein when the control circuit maintains the off state of the off test signal, if the comparator detects that a corresponding secondary battery voltage exceeds a reference voltage The range, as long as the detection continues, the control circuit continues to maintain the off state of the disconnect test signal. The protective semiconductor device according to claim 2, further comprising: a plurality of fourth resistors connected between a high voltage side and a low voltage side terminal of each secondary battery; and a plurality of a three-switching element that switches the connection/disconnection of each of the fourth resistors, wherein the control circuit transmits a control section from a predetermined period to the on state of the off-test signal before the disconnection test signal is turned on The signal of the three switching elements is to the third switching element to turn off the fourth resistance. The protective semiconductor device of claim 1, further comprising maintaining the signal before the disconnection test signal enters the on state At the moment of the circuit, the signal represents whether the voltage of each of the secondary batteries detected by the corresponding comparator exceeds the reference voltage range. The protective semiconductor device according to claim 8, wherein the comparators detect whether the voltage of each of the secondary batteries is greater than the reference voltage. The protective semiconductor device according to claim 8, wherein the comparators detect whether the voltage of each of the secondary batteries is less than the reference voltage. The protective semiconductor device of claim 8, further comprising a hysteresis forming circuit corresponding to whether the voltage of each of the secondary batteries detected by the corresponding comparator exceeds a reference voltage range to form a A hysteresis signal, wherein the output of the hysteresis forming circuit remains in the off state when the off test signal is in the on state.