TWI472221B - Image sensor circuit and method in the same, pixel circuit and image processing system - Google Patents

Description

Image sensor circuit and method for image sensor circuit, pixel circuit and image processing system Cross-reference to related patent applications

The present application claims the benefit of U.S. Patent Application Serial No. 12/184,160, entitled "Circuits and Methods Allowing for Pixel Array Exposure Pattern Control", filed on July 31, 2008, the entire contents of which are incorporated by reference. Incorporated herein. The present application claims the benefit of the U.S. Provisional Application Serial No. 60/953, 905, entitled " CMOS Image", filed on Aug. 3, 2007, the entire disclosure of which is incorporated herein by reference. The present application claims the benefit of U.S. Provisional Application Serial No. 61/020, 560, entitled " CMOS Image Sensor for Machine Vision, filed on Jan. 11, 2008, the entire disclosure of which is incorporated herein by reference. U.S. Patent Application Ser.

Field of invention

Embodiments of the present invention generally relate to image processing systems, image sensor circuits, pixel circuits, image capture methods, and image processing methods, and, in particular embodiments, to a pixel array and for control One or more image sensor circuits of the pixel array of the pixel array.

Background of the invention

Image sensor circuits are widely used to obtain images of solid scenes and objects. In many cases, image sensor circuits are used to obtain humans. An image that is seen and observed. In other cases, image sensor circuits are used to obtain images that are used in machine vision and other automated pattern recognition programs. Conventional image sensor circuits that emphasize the actual description of human observed scenes may present some problems when used in pattern recognition applications.

The image sensor circuit typically includes a pixel array having a plurality of pixel circuits arranged in columns and rows. Each of the pixel circuits typically includes a light sensing element, such as a light diode or the like, for sampling the light intensity of a corresponding portion of an imaged scene. During image capture, the accumulated charge from the photosensitive elements within the pixel circuit of the pixel array is typically controlled in accordance with a predetermined period of time assigned to a shutter operation. The two shutter operations used in the image sensor circuits of various related art are: (i) a global shutter operation; and (ii) a rolling shutter operation.

In a typical global shutter operation, all of the pixel circuits within a pixel array are reset and simultaneously exposed for a specified period of time to capture an image. With these global shutters, all of the pixel circuits within the pixel array begin to accumulate or accumulate charge from light at a same first time point, and then stop accumulating charge at a second, identical point in time. Thus, with these global shutters, all of the pixel circuits within the pixel array have an identical settling time during which charge is accumulated from light for an imaged scene.

In a typical rolling shutter operation, all of the pixel circuits in the same column of one pixel array are reset and then simultaneously exposed for a specified period of time. With these rolling shutters, all of the pixel circuits in the same column of the pixel array accumulate from the light at the same first time point The charge then stops accumulating charge at a second, identical point in time. Once one of the pixel circuits has been exposed during this rolling shutter operation for a specified gathering time period, the program continues to the next column within the pixel array, where all of the pixel circuits in the next column are then simultaneously exposed. The specified aggregation time period. The program continues column by column between the pixel arrays until all columns of the pixel circuit have been exposed for the specified gather time to capture an image.

The global shutter and rolling shutter operation seeks to maintain a relative relationship between the points of light intensity within a scene such that if one point in a physical scene is illuminated than the other, then the pixel circuits are not fully saturated. Within the scope, the situation within the captured image of the physical scene is the same. This is desirable when the captured image is for viewing to humans because the captured image is captured in order to maintain a true appearance of the physical scene. However, when one image of a high dynamic range scene is captured for pattern recognition purposes, attempts to maintain the relative relationship between the points of light intensity within a scene may cause problems because the variation in light intensity within the physical scene may exceed One of the dynamic ranges of the pixel circuits.

For example, consider a physical scene with a brighter central portion and dark edges, such as when looking out from inside a dark tunnel on a sunny afternoon. In this case, if a gather time for accumulating charges in a global shutter or rolling shutter operation is set to a long time to accumulate a sufficient amount of charge for a dark region, a pixel for accumulating charges for a bright region is obtained. The circuit may be saturated with charge. This saturation of charge may result in the inability to see objects in the bright areas of the image. On the other hand, if you are here In the case of a domain shutter or rolling shutter operation, the accumulation time of the accumulated charges is set to a short time to saturate the pixel circuits of the accumulated charge for the bright regions, and the pixel circuits that accumulate charges for the dark regions may not accumulate. Enough charge to allow to see objects in dark areas.

The problem of accumulating too much charge or accumulating too little charge as described above can be very severe under the context of automatic pattern recognition because it is difficult and generally impossible to identify an object that cannot be seen within an image. For example, in the example provided above, if the captured image is being used to automatically control a car traveling in the tunnel, saturating an image in the exit area of the tunnel may prevent the ability to recognize the object when leaving the tunnel. This may adversely affect the ability of the car to avoid such objects. Thus, in the case of capturing images of high dynamic range scenes having large differences in light intensity between different regions of the scenes, such global shutter and rolling shutter operations may create problems.

FIG. 1 depicts a block diagram of a conventional image sensor circuit 100. The image sensor circuit 100 includes a pixel array 101, a type of analog-to-digital converter (ADC) block 102, a digital image processor 103, a column of addressing circuits 104, a control processor 105, and an image memory buffer. 106. The pixel array 101 includes a plurality of pixel circuits 112 arranged in columns and rows. Each pixel circuit 112 includes a light sensing element, such as a light diode or the like, to sample the light intensity of a corresponding portion of an imaged scene, and each pixel circuit 112 is assembled to be sampled based on The light intensity produces an analog pixel signal.

The pixel array 101 includes column control lines 107 ₁ , 107 ₂ , . . . , 107 _n (each may include a plurality of control lines (not shown in FIG. 1)), and the pixel array 101 also includes an analog output. Lines 108 ₁ , 108 ₂ ,...,108 _m . The column addressing circuit 104 provides control signals to the pixel circuits 112 within the pixel array 101 via the column control lines 107 ₁ , 107 ₂ , ..., 107 _n to control operation of one of the pixel circuits 112. In the same column (e.g., i-th column of the pixel array 101) of the pixel array 101 pixel circuit 112 in the control line 107 _i share a common column via a column from the column addressing circuit 104 common control signal. The pixel circuits in the same row (e.g., j-th row of the pixel array 101) of the array 101 of pixel 112 share a common analog output line 108 to provide an output _j. The column addressing circuit 104 controls the pixel circuits 112 to perform column-by-column processing on a rolling shutter operation.

The analog pixel signals output from the pixel array 101 are input to the ADC block 102 through the analog output lines 108 ₁ , 108 ₂ , ..., 108 _m . The ADC block 102 generally includes a row ADC circuit 114 for each row of the pixel circuits 112 within the pixel array 101. The row ADC circuits 114 are configured to convert analog pixel signals received from the pixel array 101 through individual output lines 108 ₁ , 108 ₂ , ..., 108 _m to corresponding ones. A digital signal output on the digital output lines 109 ₁ , 109 ₂ , . . . , 109 _m . The control processor 105 is configured to control the operation of one of the ADC blocks 102 and is also configured to control the operation of one of the column addressing circuits 104. The digital pixel signals outputted from the digital output lines 109 ₁ , 109 ₂ , . . . , 109 _m from the ADC block 102 are input to the digital image processor 103. The digital image processor 103 cooperates with the image memory buffer 106 and the control processor 105 to process the input digital pixel signals to generate a digital output signal on an output line.

Figure 2 depicts a conventional design of the pixel circuit 112. The pixel circuit 112 includes a photodiode 121, a transmission gate transistor 122, a sensing node 131, a reset transistor 124, a driving transistor 125, and a read selection transistor 126. The transfer gate transistor 122, the reset transistor 124, the drive transistor 125, and the read select transistor 126 each comprise an N-channel metal oxide semiconductor (NMOS) field effect transistor. The same line in the column control lines 107 ₁ , 107 ₂ , . . . , 107 _n (see FIG. 1) is shown in FIG. 2 as a column of control lines 107, and the analog output lines 108 ₁ , A common line in 108 ₂ , ..., 108 _m (see Figure 1) is shown in Figure 2 as an analog output line 108. The column control line 107 includes a column of read signal lines 127, a transmission signal line 129, and a reset signal line 130. The pixel circuit 112 receives the column read signal line 127, the transmission signal line 129, and an input signal on the reset signal line 130. The pixel circuit 112 provides an output signal on the analog output line 108.

As described in FIG. 2, the photodiode 121 is connected between the ground terminal 133 and one of the first terminals of the transmission gate transistor 122. A second terminal of the transmission gate transistor 122 is connected to the sensing node 131, and one of the gates of the transmission gate transistor 122 is connected to the transmission signal line 129. One of the resetting transistors 124 is connected to a voltage source 132. One of the second terminals of the resetting transistor 124 is connected to the sensing node 131, and one of the resetting transistors 124 is connected to the gate. This resets the signal line 130. A first terminal of the driving transistor 125 is connected to the voltage source 132, and a second terminal of the driving transistor 125 is connected to one of the first terminals of the read selection transistor 126, and one of the driving transistors 125 A gate is connected to the sensing node 131. A second terminal of the read selection transistor 126 is coupled to the analog output line 108, and the A gate of the read transistor 126 is connected to the column read signal line 127.

Figure 3 depicts a conventional design of one of the rows of ADC circuits 114. The row of ADC circuits 114 includes a source transistor 140, a dual sampling amplifier 142, and a type of analog to digital converter (ADC) circuit 144. The double sampling amplifier 142 is controlled by a control signal provided from the control processor 105 (see FIG. 1), and the control signals are received by the double sampling amplifier 142 through an amplifier control signal line 146. The ADC circuit 144 is controlled by a control signal provided by the control processor 105 (see FIG. 1), which is received by the ADC circuit 144 via a converter control signal line 148. The same line in the analog output lines 108 ₁ , 108 ₂ , . . . , 108 _m (see FIG. 1) is shown in FIG. 3 as an analog output line 108, and the digital output lines 109 ₁ , A homologous line of 109 ₂ , ..., 109 _m (see Fig. 1) is shown as a digital output line 109 in Fig. 3. A first terminal of the source transistor 140 is coupled to the digital output line 108, and a second terminal of the source transistor 140 is coupled to the ground terminal 133. An input of the dual sampling amplifier 142 is coupled to the analog output line 108, and an output of the dual sampling amplifier 142 is coupled to an input of the ADC circuit 144. An output of one of the ADC circuits 144 is coupled to the digital output line 109.

Figure 4 depicts a conventional image sensor circuit 100 of Figure 1, wherein the pixel circuit 112 of Figure 2 and the ADC circuit 114 of Figure 3 are depicted. One of the operations of the image sensor circuit 100 is now described with reference to Figures 1, 2, 3 and 4. When an image capturing operation is initialized, the photodiode 121 turns on the transmission gate transistor 122 and provides a signal on the reset signal line 130 by providing a HIGH signal on the transmission signal line 129. HIGH signal It is reset by turning on the reset transistor 124. A LOW signal is then provided on the reset signal line 130 to turn off the reset transistor 124 while the transfer gate transistor 122 remains turned on to allow the charge generated in the photodiode 121 to be sensed. It is accumulated in the measurement node 131. At the end of an exposure time interval, a LOW signal is provided on the transmission signal line 129 to turn off the transmission gate transistor 122.

Once the transfer gate transistor 122 is turned off, a HIGH signal is provided on the column read signal line 127 to turn on the read select transistor 126, and the double sample amplifier 142 is on the analog output line 108. The pixel output voltage is sampled. Next, a LOW signal is provided on the column read signal line 127 to turn off the read select transistor 126, and a HIGH signal is provided on the reset signal line 130 and the transfer signal line 129 to turn on the The transistor 124 and the transfer gate transistor 122 are reset to reset the sensing node 131. When the sensing node 131 is in a reset state, a HIGH signal is provided on the column read signal line 127 to turn on the read select transistor 126, and the double sample amplifier 142 is on the analog output line 108. The one pixel circuit resets the voltage sampling. The double sampling amplifier 142 then calculates a difference between the pixel circuit output voltage and the pixel circuit reset voltage to achieve a corrected pixel circuit output voltage. The corrected pixel circuit output voltage is supplied from the double sampling amplifier 142 to the ADC circuit 144, and the ADC circuit 144 converts the corrected pixel circuit output voltage into a digital signal, and supplies the digital signal to the The digital image processor 103.

In the image sensor circuit 100, all of the pixel circuits 112 in a given column of the pixel array 101 accumulate charge for an equal amount of time. therefore, When one of the high dynamic range scene images is captured for pattern recognition purposes, the image sensor circuit 100 has the problem discussed above because the change in light intensity within the physical scene may exceed one of the pixel circuits 112 Dynamic Range. Such problems may prevent an object or pattern from being recognized from the image captured by the image sensor circuit 100.

Summary of invention

Various embodiments of the present invention allow one of the pixel arrays to be exposed over time during an image capture operation such that the pixel circuits within the pixel array can be exposed differently during the image capture operation The amount of time. In various embodiments, the exposure pattern of the pixel array is controlled based at least in part on signals output from the pixel array, the signals representing charges accumulated in at least a portion of the pixel array. In some embodiments, the exposure pattern of the pixel array is iteratively updated during an image capture operation based on the accumulated charge within the pixel array during the image capture operation.

An image sensor circuit in accordance with an embodiment of the invention includes a pixel array and one or more circuits. The pixel array contains a plurality of pixel circuits. The one or more circuits are configured to update exposure information based at least in part on the one or more signals output from the pixel array, and are configured to control an exposure pattern of the pixel array based on the exposure information. In various embodiments, the one or more circuits are configured to, when an image is being captured by the pixel array, based at least in part on the one or more signals output from the pixel array and at least one expansion criterion Update the exposure information in an iterative manner. In some embodiments, the at least one expansion criterion is specified by at least one structural element.

In various embodiments, the pixel circuits can be controlled such that at least one pixel circuit in one of the pixel arrays can collect charge at one of the pixel sensing nodes, while at least one of the columns The two pixel circuit is prevented from accumulating charge at one of the sensing nodes of the second pixel circuit during at least a portion of the image capturing operation. In some embodiments, the one or more circuits are configured to iteratively update the exposure information based at least in part on a value of the one or more signals output from the pixel array, wherein the one or more signals The equivalent value represents the charge accumulated in at least a portion of the pixel array.

In various embodiments, the one or more circuits are configured to individually control exposure states of the pixel circuits based on the exposure information to control the exposure pattern of the pixel array. Moreover, in various embodiments, the exposure state of each pixel circuit in the pixel circuits includes an on state and a off state in which the pixel circuit is allowed to be in the pixel circuit. A sense node aggregates charge, in which the pixel circuit is prevented from accumulating additional charge at the sense node.

In some embodiments, the image sensor circuit further includes one or more memory devices to store the exposure information as exposure pattern data, the exposure pattern data including an exposure state to be used to control the pixel circuit. At least one bit of each pixel circuit in the pixel circuits. In a further embodiment, the one or more circuits are configured to reset the exposure pattern data stored in the one or more memory devices to an initial pattern prior to an image capture operation. In some embodiments, the one or more circuits are configured to change the exposure pattern of the pixel array a plurality of times based on the exposure information when an image is captured by the pixel array.

In various embodiments, at least one of the pixel circuits of the pixel circuits includes a photosensitive element, a first transistor, and a second transistor. The first transistor has a terminal connected to the photosensitive element. The second transistor is connected between an exposure control signal line and one of the gates of the first transistor. In various embodiments, the one or more circuits are configured to control a signal on the exposure control signal line based on the exposure information. In some embodiments, the at least one pixel circuit further includes a third transistor and a fourth transistor. The third transistor is connected to the photosensitive element. The fourth transistor is coupled between an anti-scattering control signal and one of the gates of the third transistor. The one or more circuits are configured to control an anti-emitter signal on the anti-dispersion control signal line based on the exposure information.

In various embodiments, the one or more circuits are configured to control an anti-emitter signal on the anti-dispersion control signal line to be one of the exposure control signals on the exposure control signal line during an image capture operation Value. Moreover, in various embodiments, the photosensitive element has a first portion that extends below the exposure signal line and a second portion that extends below the anti-dispersion control signal line. In some embodiments, the at least one pixel circuit further includes one or more virtual diffusions that are coupled to a constant voltage during an image capture operation.

In some embodiments, the at least one pixel circuit further comprises a reset transistor. The reset transistor is coupled between a fixed voltage and a sense node, wherein a voltage on the sense node controls an output signal. In various embodiments, the one or more circuits are configured to control a reset signal that is applied to one of the gates of the reset transistor, Causing the reset transistor to remain off during at least two readouts of the output signal during an image capture operation such that the at least two readouts of the output signal are accumulated with respect to the sense node The charge is non-destructive.

In various embodiments, the pixel array further includes a plurality of row readout lines to provide the one or more signals, and the one or more signals are configured to selectively control the control on the row readout lines The signal is a voltage signal or a current signal. In some embodiments, the one or more signals are analog current signals for at least a portion of the time during an image capture operation. In various embodiments, the image sensor circuit further includes a row of digital-to-analog converter circuits that are configured to receive the analog converter circuits from the same row of one of the pixel circuits One of the pixel arrays of the two or more pixel circuits in the pixel circuit outputs an analog signal outputted on the line and is configured to convert the analog signals into corresponding digital signals.

In various embodiments, the pixel circuits are arranged in a plurality of columns and a plurality of rows. In some embodiments, the one or more circuits are configured to selectively control the pixel array to provide output from pixel circuits in two or more columns and two or more rows at the same time The outputs from the two or more columns are combined in analogy on the row readout lines of the pixel array.

In some embodiments, the image sensor circuit further includes a resistor grid. In various embodiments, the resistor grid includes a plurality of switchable resistors and a plurality of capacitors. In some embodiments, the capacitors are connected to receive with the one or more signals based on the output from the pixel array Signals of values, and the switchable resistors are configured to selectively connect the capacitors in accordance with the command signals. In various embodiments, the one or more circuits are configured to pair at least one of the capacitors when the switchable resistors have been controlled to connect the capacitors for a period of time A voltage is sampled inside. Moreover, in various embodiments, the one or more circuits are configured to update the exposure information based on the voltage.

In some embodiments, the pixel circuits are arranged in a plurality of columns and a plurality of rows, wherein each of the columns further includes a critical current generator. In various embodiments, the one or more circuits are configured to compare a voltage of a reference signal derived from an output of a particular threshold current generator in a particular one of the columns to and from the particular column One of the specific pixel circuits in the pixel circuits outputs one of the derived signals and is configured to update the exposure information based on the result of the comparison. In some embodiments, the one or more circuits are configured to terminate an image capture operation within the pixel array based on a comparison between a threshold number and a number calculated from the exposure information. Moreover, in some embodiments, the one or more circuits comprise a digital signal processor. In various embodiments, the image sensor circuit further includes an infrared filter disposed on at least a portion of the at least one pixel circuit in the pixel circuits. In some embodiments, the image sensor circuit further includes a color filter disposed on at least a portion of the at least one pixel circuit in the pixel circuits.

A method for an image sensor circuit according to an embodiment of the invention, comprising the steps of: (a) storing information related to an exposure pattern of a pixel array of the image sensor circuit; and b) based at least in part on (i) information that has been stored; and (ii) one or more signals output from the pixel array, the exposure pattern of the pixel array being changed.

A method for an image sensor circuit in accordance with an embodiment of the present invention includes the steps of: (a) starting each of a plurality of pixel circuits of a pixel array of the image sensor circuit (b) preventing accumulation of charges in at least one particular pixel circuit in the pixel circuits selected based at least in part on the one or more signal outputs from the pixel array; and (c) at least a portion Aggregation of charge within at least one of the pixel circuits in the pixel circuits adjacent to the particular pixel circuit within the pixel array is blocked based on an expansion criterion.

A pixel circuit in accordance with an embodiment of the present invention includes a photosensitive element, a first transistor, and a second transistor. In various embodiments, the photosensitive element comprises a photodiode or the like. The first transistor is coupled between the photosensitive element and a sensing node. The second transistor is connected between an exposure control signal line and a gate of the first transistor, and the second transistor has a gate connected to a transmission signal line.

An image processing system in accordance with an embodiment of the present invention includes an image sensor circuit and a processor. The image sensor circuit includes a pixel array and is configured to obtain an image by using a shutter operation, wherein an exposure pattern of the pixel array is set according to exposure information, the exposure information being based at least in part on the pixel array The charge accumulated in at least a portion varies with time. The processor is configured to detect one or more objects within the image. In various embodiments, the exposure information is further varied over time based on an expansion criterion specified by a structural element. In various embodiments, The image sensor circuit and the processor are all disposed on a single wafer.

Embodiments of the present invention allow control of a pixel array using feedback such that the pixel array is controlled based at least in part on signals output from the pixel array, the signals representing the pixel array during an image capture operation The charge accumulated in at least a portion of it. Moreover, various embodiments of the present invention allow pixel circuits in an identical column of the pixel array to be each during an image capture operation during one of the other pixel circuit level control aggregation times The charge is accumulated in different amounts of time. In various embodiments, a particular shutter operation allows for a pixel circuit that accumulates charge for a bright region of the physical scene, as compared to a darker region of a solid scene, in contrast to the aggregation time of the pixel-charging circuit. A short gathering time gathers the charge. Accordingly, various embodiments of the present invention provide for controlling an individual pixel circuit to be allowed to accumulate charge during an image capture operation for an amount of time, based at least in part on the charge that has been accumulated by the pixel circuit during the image capture operation.

Simple illustration

Figure 1 depicts a conventional image sensor circuit; Figure 2 depicts a conventional pixel circuit; Figure 3 depicts a conventional row analog-to-digital converter (ADC) circuit; The figure depicts a conventional image sensor circuit; FIG. 5 depicts an image processing system in accordance with an embodiment of the present invention; and FIG. 6 depicts an image sensor circuit in accordance with an embodiment of the present invention. Figure 7 depicts a pixel circuit in accordance with an embodiment of the present invention; Figure 8 depicts a critical current generator in accordance with an embodiment of the present invention; Figure 9 depicts a row of ADC circuits in accordance with one embodiment of the present invention; and Figure 10 depicts an embodiment in accordance with an embodiment of the present invention. Reference signal converter; FIG. 11 depicts an image sensor circuit in accordance with an embodiment of the present invention; FIG. 12 depicts a row of ADC circuits in accordance with an embodiment of the present invention; and FIG. 13 depicts An image sensor circuit of one embodiment; FIG. 14 depicts a layout of a pixel circuit in accordance with an embodiment of the present invention; and FIG. 15 depicts an image for use in accordance with an embodiment of the present invention A flowchart of a method of a sensor circuit; FIG. 16 depicts a flow chart of a method for an image sensor circuit in accordance with an embodiment of the present invention; and FIG. 17 depicts a method for use in accordance with the present invention A flowchart of one of the methods of an image sensor circuit of one embodiment; FIG. 18A depicts an expansion criterion specified by a structural element in accordance with an embodiment of the present invention; and FIG. 18B depicts a method according to the present invention One of the embodiments An expandable structural element specified criteria; FIG. 18C describes a second criterion specified by the expansion of a structural element according to one embodiment of the present invention; Figure 18D depicts an expansion criterion specified by a structural element in accordance with an embodiment of the present invention; Figure 19A depicts an example of the content of an exposure pattern buffer in accordance with an embodiment of the present invention; An example of an exposure pattern of a pixel array set in accordance with the content of the exposure pattern buffer of FIG. 19A is described in accordance with an embodiment of the present invention; FIG. 19C depicts an exposure in accordance with an embodiment of the present invention. An example of the contents of the pattern buffer; FIG. 19D depicts an example of the contents of an exposure pattern buffer in accordance with an embodiment of the present invention; and FIG. 19E depicts a 19D pattern according to an embodiment of the present invention. An example of an exposure pattern of a pixel array set by the content of the exposure pattern buffer; FIG. 19F depicts an example of the contents of an exposure pattern buffer in accordance with an embodiment of the present invention; FIG. 19G depicts An example of the contents of an exposure pattern buffer in accordance with an embodiment of the present invention; FIG. 19H depicts an exposure pattern buffer in accordance with the 19Gth image in accordance with an embodiment of the present invention. An example of an exposure pattern of a set of one pixel arrays; FIG. 19I depicts an example of the contents of an exposure pattern buffer in accordance with an embodiment of the present invention; and FIG. 19J depicts an embodiment in accordance with the present invention. One exposure pattern An example of the contents of the buffer; FIG. 19K depicts an example of an exposure pattern of a pixel array set according to the content of the exposure pattern buffer of FIG. 19J according to an embodiment of the present invention; FIG. 20 depicts An image sensor circuit in accordance with an embodiment of the present invention; FIG. 21 depicts an image sensor circuit in accordance with an embodiment of the present invention; and FIG. 22 depicts an implementation in accordance with the present invention A layout of the example.

Detailed description of the preferred embodiment

Figure 5 depicts a block diagram of an image processing system 700 in accordance with one embodiment of the present invention. The image processing system 700 includes an image sensor circuit 200 and a processor 800. The image sensor circuit 200 includes a pixel array 240 and one or more circuits 290. In various embodiments, the image sensor circuit 200 and the processor 800 are both disposed on a single wafer. In various embodiments, the image sensor circuit 200 allows for capturing images of a physical scene, and the processor 800 is configured to process images captured by the image sensor circuit 200. In some embodiments, the processor 800 is configured to receive data from an image sensor circuit 200 and is configured to process the data to detect one or more objects within the image. In various embodiments, the image processing system 700 can be used in machine vision or other automated pattern recognition applications. In some embodiments, the image processing system 700 can be used to obtain images for human viewing.

In some embodiments, the processor 800 can include circuitry for performing pattern matching to detect one or more objects, such as the US Provisional Patent Application Serial No. 60/991,545 (named "Vision System on a Chip", The circuit disclosed in the application filed on November 30, 2007, the entire contents of which is incorporated herein by reference. In some embodiments, the processor 800 is configured to search for an image representing one or more features of an object using one of the one or more features. Moreover, in some such embodiments, the processor 800 can be configured to perform a method of detecting an object by searching for features within an image, such as the US Provisional Patent Application Serial No. 60/991,545. The method of steps 802-810 within the flowchart of Figure 8.

Figure 6 depicts an image sensor circuit 200 in accordance with an embodiment of the present invention. The image sensor circuit 200 includes the pixel array 240, a type of analog-to-digital converter (ADC) block 249, a pixel control signal generator 213, a control processor 212, a digital image processor 210, and an image. Memory buffer 211. In some embodiments, the image sensor circuit 200 further includes an exposure pattern buffer 295. The pixel array 240 includes a plurality of pixel circuits 250 arranged in columns and rows. For example, in various embodiments, the pixel array 240 can include pixel circuits 250 of "n" columns and "m" rows, where n and m are integer values. Each pixel circuit 250 includes a light sensing element, such as a light diode or the like, to sample the light intensity of a corresponding portion of an imaged scene. In various embodiments, the pixel array 240 further includes a plurality of critical current generators 260 arranged in a row. Each critical current generator 260 can be coupled to a corresponding column of one of the pixel circuits 250 within the pixel array 240 and can be configured to provide the corresponding correspondence that needs to be used for signal comparison. One of the columns is a reference signal.

The pixel array 240 includes column control lines 223 ₁ , 223 ₂ , . . . , 223 _n , which may each include a plurality of control lines (not shown in FIG. 6), and the pixel array 240 also includes rows. Read lines 231 ₁ , 231 ₂ , ..., 231 _m . The pixel control signal generator 213 is configured to provide control signals to the pixel circuits 250 in the pixel array 240 through the column control lines 223 ₁ , 223 ₂ , ..., 223 _n to control the The operation of the pixel circuit 250. In various embodiments, the pixel circuits 250 in the same column of one of the pixel arrays 240 (e.g., the i-th column of the pixel array 240) are controlled by a common column from the pixel control signal generator 213. 223 _i-line share a common column control signal. Further, in various embodiments, the pixel circuits 250 share the same row (e.g., the pixel array 240 of the j-th row) of the pixel array of a total of 240 one peer _j readout line 231 to provide an output. In various embodiments, the pixel array 240 further includes a reference signal line 232, each of which can provide an output through the reference signal line 232.

Analog signals output from the pixel array 240 through the row readout lines 231 ₁ , 231 ₂ , ..., 231 _m are input to the ADC block 249. In various embodiments, the ADC block 249 includes one or more row ADC circuits 220 for each of the pixel circuits 250 within the pixel array 240. In various embodiments, the row ADC circuits 220 are configured to receive an analogy from the pixel arrays 240 through the individual read lines of the row readout lines 231 ₁ , 231 ₂ , . . . , 231 _m . The signals are converted to digital signals output on corresponding digital output lines 246 ₁ , 246 ₂ , ..., 246 _m . In various embodiments, the ADC block 249 further includes a reference signal converter 221 for receiving signals from the reference signal line 232 of the pixel array 240 and for using a reference A reference signal on voltage line 243 is provided to each of the row of ADC circuits 220 of ADC block 249. In various embodiments, the ADC block 249 includes one or more control lines 241 that provide control signals through the one or more control lines 241 to control the operation of the reference signal converter 221. Moreover, in various embodiments, the ADC block 249 includes one or more control lines 242 that provide control signals through the one or more control lines 242 to control the operation of the row ADC circuits 220.

In various embodiments, the control processor 212 is configured to control the operation of the ADC block 249 and is also configured to control the operation of the pixel control signal generator 213. In various embodiments, the control processor 212 provides control signals to the pixel control signal generator 213 via one or more control lines 244. The digit signals output on the digital output lines 246 ₁ , 246 ₂ , ..., 246 _m from the ADC block 249 are input to the digital image processor 210. The image sensor circuit 200 further includes pixel control signal lines 226 ₁ , 226 ₂ , . . . , 226 _m , and the pixel control signal lines 226 ₁ , 226 ₂ , . . . , 226 _m may each include a majority Control lines (not shown in Figure 6). The digital image processor 210 is coupled with a control group of signal lines _{2261, 2262} through such pixels, ... 226 _m provides control signals to the pixel circuit 250 such that the pixel within the array 240. In various embodiments the pixel circuit embodiment, located in the same row (e.g., one of the pixel array 240 j-th row) of the pixel array 240 within one of the pixels 250 share a common control signal line 226 _j, a control signal The common pixel control signal line 226 _j is transmitted from the digital image processor 210.

In various embodiments, the digital image processor 210 communicates with the control processor 212 via one or more communication lines 245. Moreover, in various embodiments, the digital image processor 210 reads data from the image memory buffer 211 through a read/write bus 248 and writes the data to the image memory buffer 211. In some embodiments, a separate write bus 247 allows data to be transferred from the digital image processor 210 to the image memory buffer 211. In various embodiments, the digital image processor 210 is configured to process digital signals received from the ADC block 249 through the digital output lines 246 ₁ , 246 ₂ , . . . , 246 _m and one or more An output signal is produced on output line 219. In various embodiments, the image memory buffer 211 includes a random access memory (RAM) or the like to store and retrieve data. In some embodiments, the image sensor circuit 200 includes the exposure pattern buffer 295, and the digital image processor 210 can read from the exposure pattern buffer 295 and write to the exposure pattern buffer 295. In various embodiments, the exposure pattern buffer 295 includes a RAM or the like.

Various embodiments of the image sensor circuit 200 allow for selection between: (i) a current-to-analog mode on which the row readout lines 231 ₁ , 231 ₂ , ..., 231 _m The output signal is an analog current signal; and (ii) a voltage-analog mode in which a signal output on the read lines 231 ₁ , 231 ₂ , ..., 231 _m on the line is an analog voltage signal. In various embodiments, the image sensor circuit 200 further includes a voltage source 230, a plurality of bias sources 234 ₁ , 234 ₂ , . . . , 234 _m and a plurality of voltage source switches 217 ₁ , 217 ₂ . ..,217 _m (for example, an analog switch or the like). Moreover, in various embodiments, the pixel array 240 further includes a plurality of voltage source lines 235 ₁ , 235 ₂ , . . . , 235 _m . In each pixel circuit embodiments, one located in the same row of the pixel array 240 (e.g., one of the pixel array 240 j-th row) in 250 share a common voltage source line 235 _j, and the line of voltage source line 235 _j is connected to a voltage source such switches _{217 1, 217 2, ...,} 217 m of a switch corresponding to the voltage source 217 _j. In various embodiments, the control processor 212 is configured to control each of the voltage source switches 217 ₁ , 217 ₂ , . . . , 217 _m to be controllably at one of the voltage sources 230 Switching between a first terminal of a corresponding one of the bias sources 234 ₁ , 234 ₂ , ..., 234 _m . In various embodiments, one of each of the bias sources 234 ₁ , 234 ₂ , . . . , 234 _m is connected to the ground terminal 233.

In various embodiments, the pixel array 240 further includes a voltage source line 238 coupled to each of the critical current generators 260. Moreover, in various embodiments, the image sensor circuit 200 further includes a bias source 281 and a switch 239 coupled to the voltage source line 238. In various embodiments, the control processor 212 is configured to control the switch 239 to controllably switch between a first terminal and an open state of the bias source 281. Moreover, in various embodiments, one of the bias sources 281 is connected to the ground terminal 233. In various embodiments, the pixel array 240 further includes a threshold voltage line 268 coupled to each of the critical current generators 260. Moreover, in various embodiments, the image sensor 200 further includes a threshold voltage source 267 having a first terminal coupled to the threshold voltage line 268 and a second terminal coupled to the ground terminal.

Referring to Figures 5 and 6, in various embodiments, the one or more circuits 290 include the digital image processor 210. In some embodiments, the digital image processor 210 includes a programmable digital signal processor or the like. In some embodiments, the one or more circuits 290 further include the pixel signal generator 213. In some embodiments, the one or more circuits 290 further include the control processor 212. In various embodiments, the one or more circuits 290 further include the ADC block 249. Moreover, in various embodiments, the one or more circuits 290 further include the bias sources 234 ₁ , 234 ₂ , . . . , 234 _m , the voltage source switches 217 ₁ , 217 ₂ , . 217 _m , the bias source 281, the switch 239, and the threshold voltage source 267.

Figure 7 depicts a pixel circuit 250 in accordance with an embodiment of the present invention. The pixel circuit 250 includes a photodetector or photosensitive element, such as a photodiode 201 or the like. The pixel circuit 250 further includes a transmission gate transistor 202, a sensing node 203 (eg, a floating diffusion node), a resetting transistor 204, a driving transistor 205, a read selection transistor 206, and a primary antibody. A glow gate transistor 216, a first write select transistor 214, and a second write select transistor 215. In various embodiments, the transfer gate transistor 202, the reset transistor 204, the drive transistor 205, the read select transistor 206, the anti-glow gate transistor 216, and the first write select transistor Crystal 214 and second write select transistor 215 may each comprise an N-channel metal oxide semiconductor (NMOS) field effect transistor or the like. The sense node 203 has a specific capacitance and is capable of storing some charge.

An exemplary one of the column control lines 223 ₁ , 223 ₂ , . . . , 223 _n (see FIG. 6) is shown in FIG. 7 as a column of control lines 223. In various embodiments, the column control line 223 includes a column of read signal lines 254, a transmit signal line 253, and a reset signal line 252. In various embodiments, the pixel circuit 250 receives the column read signal line 254, the transmit signal line 253, and the input signal on the reset signal line 252. An exemplary one of the pixel control signal lines 226 ₁ , 226 ₂ , ..., 226 _m (see Fig. 6) is shown in Fig. 7 as a pixel control signal line 226. In various embodiments, the pixel control signal line 226 includes an exposure control signal line 255 and an anti-dispersion control signal line 256. In various embodiments, the pixel circuit 250 receives the exposure control signal line 255 and the input signal on the anti-dispersion control signal line 256. An exemplary one of the voltage source lines 235 ₁ , 235 ₂ , ..., 235 _m (see Figure 6) is shown in Figure 7 as a voltage source line 235. In various embodiments, the pixel circuit 250 receives an input voltage signal through the voltage source line 235. An exemplary one of the row readout lines 231 ₁ , 231 ₂ , ..., 231 _m (see Fig. 6) is shown in Fig. 7 as a row of readout lines 231. In various embodiments, the pixel circuit 250 provides an output signal on the row readout line 231.

As described in an embodiment of the pixel circuit 250 in FIG. 7, one of the photodiodes 201 is anode-connected to the ground terminal 233, and one of the photodiodes 201 is cathode-connected to the transmission gate transistor 202. One of the first terminals and one of the first terminals of the anti-diffusion gate transistor 216. A second terminal of the transmission gate transistor 202 is connected to the sensing node 203, and one of the gates of the transmission gate transistor 202 is connected to one of the first terminals of the second write selection transistor 215. One of the first terminals of the reset transistor 204 is connected to a voltage source 251, one of the second terminals of the reset transistor 204 is connected to the sensing node 203, and one of the gates of the reset transistor 204 is connected to This resets the signal line 252. The A first terminal of the driving transistor 205 is connected to the voltage source line 235, and a second terminal of the driving transistor 205 is connected to one of the first terminals of the read selection transistor 206, and one of the driving transistors 205 A gate is connected to the sensing node 203. A second terminal of the read select transistor 206 is coupled to the row readout line 231, and a gate of the read select transistor 206 is coupled to the column readout signal line 254.

A second terminal of the anti-glow gate transistor 216 is coupled to the voltage source 251, and a gate of the anti-glow gate transistor 216 is coupled to a first terminal of the first write select transistor 214. A second terminal of the first write selection transistor 214 is connected to the anti-dispersion control signal line 256, and one of the gates of the first write selection transistor 214 is connected to the transmission signal line 253. A second terminal of the second write selection transistor 215 is connected to the exposure control signal line 255, and one of the gates of the second write selection transistor 215 is connected to the transmission signal line 253.

Figure 8 depicts a critical current generator 260 in accordance with an embodiment of the present invention. The critical current generator 260 includes a current control transistor 265 and a selection transistor 266. In various embodiments, the current control transistor 265 and the select transistor 266 each comprise an NMOS field effect transistor or the like. An exemplary one of the column control lines 223 ₁ , 223 ₂ , . . . , 223 _n (see FIG. 6) read signal line 254 is shown in FIG. 8 as being connected to the threshold. Current generator 260. As described in one embodiment of the critical current generator 260 of FIG. 8, one of the first terminals of the current control transistor 265 is coupled to the voltage source line 238. A gate of the current control transistor 265 is coupled to the threshold voltage line 268, and a second terminal of the current control transistor 265 is coupled to a first terminal of the selection transistor 266. A gate of the select transistor 266 is coupled to the column read signal line 254, and a second terminal of the select transistor 266 is coupled to the reference signal line 232.

Figure 9 depicts the row of ADC circuits 220 in accordance with an embodiment of the present invention. The row ADC circuit 220 includes an output mode switch 227, a dual sampling amplifier 207, a source transistor 208, an ADC circuit 209, a current to voltage converter 222, a difference comparator 225, and a digital multiplexer 228. . An exemplary one of the row readout lines 231 ₁ , 231 ₂ , ..., 231 _m (see Fig. 6) is shown as a row readout line 231 in Fig. 9. An exemplary one of the digital output lines 246 ₁ , 246 ₂ , . . . , 246 _m (see FIG. 6) is shown in FIG. 9 as a digital output line 246. One or more control lines 242 from the control processor 212 (see FIG. 6) are input to the row ADC circuit 220. In various embodiments, the control processor 212 (see FIG. 6) is configured to provide control signals at the one or more control lines 242 to control the output mode switch 227, the dual sampling amplifier 207, the source The crystal 208, the current to voltage converter 222, the ADC circuit 209, the difference comparator 225, and the digital multiplexer 228 operate. In various embodiments, the one or more control lines 242 include a select signal line 274 to provide a select signal from the control processor 212 (see FIG. 6) to the digital multiplexer 228.

As described in one embodiment of the row of ADC circuits 220 in FIG. 9, the output mode switch 227 can be controlled to connect the row sense line 231 to one of the current-to-voltage converters 222, Or connected to one of the input terminals of the double sampling amplifier 207 and the first terminal of the source transistor 208. In various embodiments, the output mode switch 227 can be processed by the control The 212 (see Figure 6) is controlled by a control signal provided through the one or more control lines 242. In various embodiments, the current to voltage converter 222 is configured to receive an analog current signal, convert the analog current signal to a voltage signal, and output the voltage signal. The output of one of the current to voltage converters 222 is coupled to a first input of the difference comparator 225. A second input of the difference comparator 225 is coupled to the reference voltage line 243 to receive a reference voltage signal from the reference signal converter 221 (see FIG. 6). In various embodiments, the difference comparator 225 is configured to amplify a difference between a voltage signal output from the current to voltage converter 222 and a reference voltage signal received on the reference voltage line 243, and A digital output is generated based on the difference. In various embodiments, the output of the difference comparator 225 is provided to a first input of the digital multiplexer 228.

In various embodiments, the first terminal of the source transistor 208 is coupled to the input of the double sampling amplifier 207. Moreover, in various embodiments, one of the source transistors 208 has a second terminal connected to ground terminal 233 and one of the source transistors 208 is coupled to a voltage supply source 273. In various embodiments, the double sampling amplifier 207 is configured to sample a pixel output voltage on the row readout line 231 and also sample a reset voltage on the row readout line 231 at a different time. And calculating a difference between the pixel output voltage and the reset voltage to obtain a corrected pixel output voltage. In various embodiments, the ADC circuit 209 is coupled to an output of the dual sampling amplifier 207 to receive the corrected pixel output voltage from the double sampling amplifier 207. In various embodiments, the ADC circuit 209 is configured to digitize the corrected pixel output voltage and output the digitized corrected pixel output. The voltage is supplied to a second input of one of the digital multiplexers 228. In various embodiments, the digital multiplexer 228 is configured to provide an output of the difference comparator 225 or the ADC circuit 209 on the digital output line 246 based on a control signal provided on the select signal line 274. The output.

Figure 10 depicts a reference signal converter 221 in accordance with an embodiment of the present invention. In various embodiments, the reference signal converter 221 includes a switch 281, a current to voltage converter 224, and a voltage driver 229. In various embodiments, the switch 281 is controllable to connect or disconnect the reference signal line 232 to one of the current to voltage converters 224. In various embodiments, the switch 281 is controlled by a control signal provided on one or more control lines 241 from the control processor 212 (see Figure 6). In various embodiments, the current to voltage converter 224 is configured to convert a reference analog current signal provided on the reference signal line 232 to a corresponding voltage signal and output the corresponding voltage signal. In various embodiments, the voltage signal output from the current to voltage converter 224 is provided to a first input of the voltage driver 229. In various embodiments, one of the voltage drivers 229 outputs a feedback that is provided as a second input to the voltage driver 229, and the voltage driver 229 is configured to drive a reference voltage signal on the reference voltage line 243, The reference voltage signal is based at least in part on the output of the current to voltage converter 224.

Figure 11 depicts an image sensor circuit 200 of Figure 6 in accordance with an embodiment of the present invention, wherein the pixel circuit of Figure 7, the critical current generator 260 of Figure 8, and the ADC of Figure 9 The circuit 220 and the reference signal generator 221 of FIG. 10 are described. An exemplary one of the voltage source switches 217 ₁ , 217 ₂ , ..., 217 _m (see Fig. 6) is shown in Fig. 11 as a voltage source switch 217. An exemplary one of the bias sources 234 ₁ , 234 ₂ , . . . , 234 _m (see FIG. 6) is shown in FIG. 11 as a bias source 234. In various embodiments, the image sensor circuit 200 can be controlled to operate in a voltage-to-analog mode or a current-to-analog mode. In various embodiments, the control processor 212 is configured to set a voltage-analog mode for the output from the pixel circuit 250 by controlling the voltage source switch 217, the output mode switch 227, and the digital multiplexer 228. Or current-analog mode.

In order to set the voltage-to-analog mode, in various embodiments, the control processor 212 controls (i) the voltage source switch 217 such that the first terminal of the drive transistor 205 is coupled to the voltage source 230 through the switch 217; Ii) the output mode switch 227 such that the second terminal of the read select transistor 206 is coupled to the first terminal of the source transistor 208 and the input of the dual sample amplifier 207; and (iii) the digital multiplexer 228, causing the digital multiplexer 228 to provide the output of the ADC circuit 209 as an output. In embodiments of such voltage-to-analog modes, the pixel circuit 250 can provide a voltage signal to the row of ADC circuits 220, which are sampled by the double sampling amplifier 207.

In order to set the current-to-analog mode, the control processor 212 controls (i) the voltage source switch 217 such that the first terminal of the driving transistor 205 is connected to the bias source 234 through the switch 217; (ii) the output mode switch 227 causes the second terminal of the read select transistor 206 to be coupled to the input of the current to voltage converter 222; (iii) the switch 239 causes the first terminal of the current control transistor 265 Connected to the bias source 281 through the switch 239; and (iv) the digital multiplexer 228 causes the digital multiplexer 228 to The output of the difference comparator 225 is provided as an output. In embodiments of the current-to-analog mode, the pixel circuit 250 can provide one or more current signals to the row of ADC circuits 220, the one or more current signals being converted by the current to voltage converter 222 into one Corresponding one or more voltage signals.

One of the operations of image sensor circuit 200 in accordance with an embodiment of the present invention is now described with reference to Figures 6, 7, 8, 9, 10 and 11. The photodiode 201 and the sensing node 203 provide a HIGH signal on the reset signal line 252 and on the transmission signal line 253 by causing the pixel control signal generator 213 to perform a video capture operation. A HIGH signal is provided, and is reset by causing the digital image processor 210 to provide a HIGH signal on the exposure control signal line 255 and a LOW signal on the anti-dispersion control signal line 256. The combination of this signal causes both the reset transistor 204 and the transfer gate transistor 202 to be turned "on" and the anti-dispersion control signal line 216 to be turned off.

In various embodiments, each of the anti-diffusion gate transistor 216 and the transmission gate transistor 202 has an individual parasitic capacitance such that it is written into the anti-glow gate transistor 216 and the transmission gate transistor 202. The values of individual gates can last (for example) until they are rewritten to new values. Moreover, the anti-diffusion gate transistor 216 and the gate of the transmission gate transistor 202 can be isolated by the first write selection transistor 214 and the second write selection transistor 215, respectively. Therefore, once the value has been supplied to the respective second terminals of the first write selection transistor 214 and the second write selection transistor 215 for the reset operation, and the HIGH signal has been supplied to the transmission signal line 253 Above, the signal on the transmission signal line 253 can be changed to LOW, and due to parasitic capacitance, The anti-diffusion gate transistor 216 and the transfer gate transistor 202 will maintain the provided value (for example) until a new value is written.

In various embodiments, when an image capture operation is initiated, a LOW signal is provided on the reset signal line 252 to turn off the reset transistor 204 while the transfer gate transistor 202 remains on to allow The charge generated in the photodiode is accumulated in the sensing node 203. During this state, charge from the photodiode 201 is concentrated into the sensing node 203. Once the charge begins to accumulate in the sensing node 203, an analog current readout can be set by setting the voltage source switch 217, the output mode switch 227, the switch 239, and the digital multiplexer according to the current-to-analog mode settings. 228, and then the pixel control signal generator 213 is provided with a HIGH signal on the column read signal line 254 to turn on the read select transistor 206. The control signal generator 213 can provide a LOW signal on the column read signal line 254 after the analog current sense has been performed.

When the HIGH signal is provided on the column read signal line 254 to turn on the read select transistor 206 in a current-to-analog mode, a current proportional to the voltage level of one of the sense nodes 203 is This row is generated within the readout line 231. The current to voltage converter 222 converts the current on the row sense line 231 to a pixel output voltage. A reference current is generated within the critical current generator 260 in accordance with a threshold voltage provided by the threshold voltage source 267. The current to voltage converter 224 converts the reference current into a reference voltage that is driven by the voltage driver 229 on the reference voltage line 243. The difference comparator 225 amplifies a difference between the pixel output voltage and the reference voltage to provide a digital output. The digital image processor 210 transmits the multiplex The 228 reads the digital output of the difference comparator 225.

Reading current from the row sense line 231 on the pixel circuit 250 is non-destructive such that after the current is read on the row sense line 231, the charge accumulated at the sense node 203 remains there. Node 203 is measured. Thus, in various embodiments, the read current from the pixel circuit 250 can be performed multiple times during the image capture operation without erasing the charge accumulated within the sense node 203 during the image capture operation. One or more additional analog current readouts may be set by the current-to-analog mode setting during the image capture operation, the output mode switch 227, the switch 239, and the digital multiplexer 228. And then the pixel control signal generator 213 is supplied with a HIGH signal on the column read signal line 254 to turn on the read selection transistor 206. The control signal generator 213 can provide a LOW signal on the column read signal line 254 after the analog current sense has been performed. Thus, the charge accumulated in the sense node 203 can be monitored during the image capture operation by performing a plurality of analog current readouts at different times during the image capture operation, wherein each analog current read Taking charge about the charge accumulated in the sensing node 203 is non-destructive.

In various embodiments, accumulating charge at the sense node 203 may be stopped during the image capture operation while maintaining accumulated charge within the sense node 203. In order to stop the charge from accumulating at the sensing node 203, the digital image processor 210 can provide a LOW signal on the exposure control signal line 255 and a HIGH signal on the anti-dispersion control signal line 256, and the pixel The control signal generator 213 can provide a HIGH signal on the transmission signal line 253. a combination of one of the signals causes the transmission gate transistor 202 to be turned off, and the The anti-diffusion gate transistor 216 is turned "on". Since the anti-glow gate transistor 216 and the transfer gate transistor 202 have some parasitic gate capacitance that allows the transistor to store values, the pixel control signal generator 213 can then provide a signal on the transmission signal line 253. The LOW signal, and the anti-glow gate transistor 216 and the transfer gate transistor 202 will maintain their values until a new value is written. When the anti-glow gate transistor 216 is turned on, the photodiode 201 is depleted.

A type of voltage readout can be set according to the voltage-to-analog mode setting, the output mode switch 227, and the digital multiplexer 228, and then the pixel control signal generator 213 is in the column. A HIGH signal is provided on the read signal line 254 to turn on the read select transistor 206 to be performed. When the HIGH signal is provided on the column read signal line 254 to turn on the read select transistor 206 and read in the voltage-to-analog mode, a pixel output voltage is first in the source transistor 208. A terminal is provided on the row readout line 231, the pixel output voltage being proportional to a voltage level of one of the sense nodes 203. The dual sampling amplifier 207 samples the pixel output voltage at a first terminal of the source transistor 208 during a voltage read from the pixel circuit 250. The control signal generator 213 can provide a LOW signal on the column read signal line 254 after the analog voltage readout has been performed. When the sensing node 203 is in a reset state, the double sampling amplifier 207 also samples a reset voltage at the first terminal of the source transistor 208. The double sampling amplifier 207 calculates a difference between the pixel output voltage and the reset voltage to achieve a corrected pixel output voltage that is digitized by the ADC circuit 209. For the analog voltage reading, the digital image processor 210 reads the ADC circuit through the multiplexer 209 digital output.

By providing the digital image processor 210 with a HIGH signal on the exposure control line 255 and a LOW signal on the anti-dispersion control signal line 256, and by causing the pixel control signal generator 213 to A HIGH signal is provided on the transmission signal line 253 and a HIGH signal is provided on the reset signal line 252. The pixel circuit 250 can be reset to set the sensing node 203 in a reset state. One combination of this signal causes both the reset transistor 204 and the transfer gate transistor 202 to be turned "on" and the anti-glow gate transistor 216 to be turned off. When the sensing node 203 is in the reset state and a HIGH signal is provided by the pixel control signal generator 213 on the column read signal line 254 to turn on the read selection transistor 206, and the sensing A reset voltage in which one of the nodes 203 is reset to a voltage level is provided at a first terminal of the source transistor 208. The double sampling amplifier 207 can sample the reset voltage at a first terminal of the source transistor 208 to be used for reading from a voltage analog of the pixel circuit 250.

One advantage of allowing analog current readout and analog voltage readout from the pixel circuit 250 is that each read type has a desired quality. The analog current sense can provide high speed readout from the pixel array 240 because the high capacitance of the row sense line 231 (which may be present for large pixel arrays) does not prevent the analog current output from rapidly developing. The analog voltage readout provides low noise signal readout from the pixel array 240. Thus, in various embodiments, the analog current sense can be used to quickly obtain values from the pixel array multiple times during an image capture operation, while the analog voltage read can be used in an image. At the end of the fetch operation, the last value with low noise is obtained.

Another advantage of analog current sensing is that it allows multiple columns of pixel circuits 250 within the pixel array 240 to be simultaneously selected to produce an output current for each row of the pixel array 240, the output current and the pixel. The sum of the output currents of the pixel circuits 250 of the selected columns of array 240 is proportional. This multi-column readout allows spatial averaging or smoothing of an output image in a vertical direction. In some image capture methods, the local image is averaged for filtering certain noises (eg, noise typically generated by pixel circuit defects and fixed patterns generated by differential crystals between different pixel circuits). Noise may be advantageous because when an image is sampled column by column, the local image provides low pass filtering and anti-aliasing filtering in one of the vertical directions of the image.

Figure 12 depicts another embodiment of a row ADC circuit 220 in accordance with an embodiment of the present invention. Elements of the embodiment of the ADC circuit 220 of the same row as the embodiment of the ADC circuit 220 of FIG. 9 are labeled with the same reference symbols. The embodiment of the ADC circuit 220 of FIG. 12 differs from the embodiment of the ADC circuit 220 of FIG. 9 in that the current-to-voltage converter 222 and the difference comparator 225 are replaced by a current comparator 222b. The current comparator 222b is configured to detect whether a current input to the current comparator 222b is positive or negative and provides a binary output indicative of one of the results of the detection. In the event that the switch 227 is controlled to connect the row sense line 231 to the input of the current comparator 222b, the input of the current comparator 222b is coupled to the row sense line 231. The output of the current comparator 222b is provided to a first input of the multiplexer 228.

Figure 13 depicts an image sensor in accordance with an embodiment of the present invention. Another embodiment of the road 200. The embodiment of the image sensor circuit 200 of FIG. 13 is different from the embodiment of the image sensor circuit 200 of FIG. 11 because the embodiment of the image sensor circuit 200 of FIG. 13 includes the line of the ADC of FIG. An embodiment of circuit 220, rather than an embodiment of ADC row circuit 220 of FIG. Moreover, the embodiment of the image sensor circuit 200 of Fig. 13 does not include the reference signal converter 221 (see Fig. 6). In addition, the embodiment of image sensor circuit 200 of FIG. 13 further includes a current source for each row of the pixel circuit, an exemplary one of which is shown as current source 218, and Further included is a current source switch for each row of the pixel circuit, an exemplary one of which is shown as current source switch 283. Other elements of the embodiment of the image sensor circuit 200 of Fig. 13 which are identical to the elements of the embodiment of the image sensor circuit 200 of Fig. 11 are designated by the same reference numerals.

In the embodiment of image sensor circuit 200 of FIG. 13, each current source (e.g., current source 218) for each row of the pixel circuit is coupled to the reference signal line 232. The current source 218 provides a bias current that is set by mapping a current generated by the threshold current generator 260 when the threshold current generator 260 is activated with a bias voltage from the threshold voltage source 267. . In various embodiments, the current source switch 283 can be controlled by the control processor 212 to be in an open state or to connect the current source 218 to the row readout line 231. In a voltage-to-analog mode of an embodiment of the image sensor circuit 200 of FIG. 13, the control processor 212 controls the current source switch 283 to be in an off state.

In the current-analog mode of the embodiment of the image sensor circuit 200 of FIG. 13, the control processor 212 controls the current source switch 283 to Stream source 218 is coupled to the row readout line 231. In this state, when a current is generated by the pixel circuit 250, a total current reaching the input of the current comparator 222b is equal to the current generated by the pixel circuit 250 minus the bias current generated by the current source 218. . The current comparator 222b determines whether the arriving current is positive or negative, and for the current analog mode in these embodiments, provides binary information as the output of the digital multiplexer 228 based on the decision. In various embodiments, the one or more circuits 290 (see FIG. 5) further include 24 lines of current sources (eg, current source 218) and current source switches (eg, current sources) of the pixel circuits of the pixel array 240. Switch 283).

Figure 14 depicts an exemplary layout of a pixel circuit 250 of Figure 7 in accordance with an embodiment of the present invention. Elements within the exemplary layout of the pixel circuit 250 of FIG. 14 that are identical to elements within the pixel circuit 250 of FIG. 7 are labeled with the same reference symbols. In various embodiments, the transmission gate transistor 202 and the anti-glow gate transistor 216 can be disposed on opposite sides of the photodiode 201. In some embodiments, the transfer gate transistor 202, the sense node 203, the reset transistor 204, the drive transistor 205, the read select transistor 206, the first write select transistor 214, and The second write selection transistors 215 are each disposed on the same side of the photodiode 201.

Figure 15 depicts a flow chart of a method in accordance with an embodiment of the present invention. The method of Fig. 15 will be explained with reference to the image sensor circuit 200 of Fig. 6 and the pixel circuit 250 of Fig. 7. Moreover, an exemplary operation of one of the methods in accordance with an embodiment of the present invention is provided in Figures 19A-19K. An example provided in Figures 19A-19K is an embodiment of the pixel array 240 having 7 columns and 8 rows of pixel circuits. It should be understood that this pixel array 240 is one of Embodiments are merely provided as an example, and in various other embodiments, the pixel array 240 may have more or fewer columns and more or fewer rows of pixel circuits. For example, some embodiments of the pixel array 240 can include more than 7 columns and more than 8 rows of pixel circuits.

Some of the steps in Figure 15 relate to an exposure pattern buffer. In various embodiments, a portion of the image memory buffer 211 is used as the exposure pattern buffer. In various other embodiments, the image sensor circuit 200 can include an exposure pattern buffer 295 as a memory separate from the image memory buffer 211. In the example of Figures 19A-19K, some of the figures of the example describe exemplary aspects of one embodiment of the exposure pattern buffer 295. It should be understood that the size of the embodiment of the exposure pattern buffer 295 in this example is merely provided as an example, and in various other embodiments, the exposure pattern buffer 295 has a larger capacity than that described in this example. Or smaller capacity.

In the method of FIG. 15, in S301, the exposure pattern buffer 295 is cleared by the digital image processor 210, and the pixel array 240 is reset by the pixel control signal generator 213 and the digital image processor 210. . In various embodiments, the exposure pattern buffer 295 stores exposure information, such as exposure pattern data including one or more bits of each pixel circuit 250 within the pixel array 240. Moreover, in various embodiments, the exposure pattern buffer 295 is emptied by setting each of the stored bits within the exposure pattern buffer 295 to an initial state. Figure 19A depicts an exemplary content of the exposure pattern buffer 295 in accordance with an embodiment of the present invention after the exposure pattern buffer 295 has been emptied. In Figure 19A In the example, the exposure pattern buffer 295 includes one bit of each pixel circuit in one embodiment of the pixel array 240 (see FIG. 19B), and the exposure pattern buffer 295 in this example is used by All bits are set to a "0" value and are emptied so that the memory is zeroed.

In various embodiments of the image sensor circuit 200, the pixel array 240 is caused by the pixel control signal generator 213 in the column control lines 223 ₁ , 223 ₂ , ..., 223 _n each of the weight setting on the signal line 252 and the transmission signal line 253 and by providing a HIGH signal so that the digital image processor 210 in the pixel control signal line _{226 1, 226 2, ...,} 226 m in Each of the exposure control signal lines 255 provides a HIGH signal and a LOW signal is provided on the anti-dispersion control signal line 256 to be reset. With this combination of signals, the resetting transistor 204 and the transfer gate transistor 202 of the pixel circuits 250 are turned "on", and the anti-diffusion gate transistor 216 of each of the pixel circuits 250 is shut down. Once the anti-glow gate transistor 216 and the transfer gate transistor 202 receive the supplied signals on their respective gates, the parasitic capacitances on their respective gates are charged or discharged (depending on the written a value such that when the first write selection transistor 214 and the second write selection transistor 215 of each of the pixel circuits are turned off by a LOW signal on the corresponding transmission signal line 253, the resistance The state of the glow gate transistor 216 and the transfer gate transistor 202 can be maintained. In practice, this means that only two bits written to the digital memory maintain the state of the anti-glow gate transistor 216 and the transfer gate transistor 202. The method then proceeds to S302.

In S302, an image capture operation is initialized such that image capture is initialized within the pixel array 240. In various embodiments, a LOW signal is provided on the reset signal line 252 of each of the column control lines 223 ₁ , 223 ₂ , . . . , 223 _n by the pixel control signal generator 213. The transistor 204 is turned off by turning off each of the pixel circuits 250, and image capture is initialized in the pixel array 240. In various embodiments, each of the photodiodes 201 of the pixel circuits 250 is controlled to a voltage that causes the transfer gate 202 of each of the pixel circuits 250 to be turned on from the pixel circuit 250. The charge of the photodiode 201 spontaneously migrates to the sensing node 203. In various embodiments of the pixel circuit 250, when the reset transistor 204 is turned on, the reset transistor 204 is used to maintain the sense node 203 at a reset voltage level, thereby substantially preventing charge. Accumulating within the sense node 203, but when the reset transistor 204 is turned off and the transfer gate transistor 202 is turned on, the charge will be at a rate proportional to the amount of light energy that is incident on the photodiode 201. Accumulated within the sensing node 203.

Figure 19B depicts an example of an exposure pattern of one embodiment of the pixel array 240 in which image capture has been initialized. For illustrative purposes, the pixel circuits of pixel array 240 in the example of Figure 19B, which is enabled to accumulate charge in their sensing nodes, are shown as white squares. In Fig. 19B, since the image capture has been initialized, all of the pixel circuits in the pixel array 240 are displayed as white squares because all of the pixel circuits in the pixel array 240 of the embodiment of Fig. 19B are shown. It is enabled to accumulate charge at its sensing nodes at the beginning of an image capture operation. Once the image capture has been initialized within the pixel array 240, the method continues to S303.

In S303, a binary image is read from the pixel array 240. In various embodiments, the reading from the pixel array 240 in S303 is performed in a current-to-analog mode such that the row readout lines 231 ₁ , 231 ₂ , . . . , 231 _m are from the pixel array. The signal output by 240 is the current signal. In the case of the embodiment using the image sensor circuit 200 of FIG. 11, the voltage source switch 217, the output mode switch 227, and the digital multiplexer 228 and the switch 239 for each row of the pixel circuit 250 are discussed above. The current-analog mode is set. In the case where the embodiment of the image sensor circuit 200 of Fig. 13 is used, the current source switch 283 of each row of the pixel circuit 250 is further set in accordance with the current analog mode discussed above.

In various embodiments, in the current-to-analog mode, each of the pixel circuits 250 is sampled and their current-to-analog output levels (representing their photodiode 201 from the end of the reset) The number of absorbed photons is compared to a reference level to produce a binary representation of an image that is currently captured and stored in the pixel circuits 250 of the pixel array 240. In various embodiments, the resetting transistor 204 of each pixel circuit 250 remains off during the pixel circuit readout in S303, thereby causing the pixel circuit readout process to sense each pixel circuit 250. The charge accumulated in node 203 is non-destructive.

In various embodiments, the readout process in S303 is performed on a column by column basis. For example, in various embodiments, one column of pixel circuits 250 within the pixel array 240 is read, and then another column of the pixel circuit 250 within the pixel array 240 is read, etc., until all columns Has been read. For example, when each column needs to be read, a HIGH signal is provided on the column read signal line 254 of the column control line 223 of the column by the pixel control signal generator, and then the column has been After reading, the control signal line 223 is read in the column. A LOW signal is provided on the outgoing signal line 254, and each column can be read. In some embodiments, more than one column of the pixel array 240 may be sampled and/or selected at a time. In the current-to-analog mode, when more than one column of selected pixels are selected for reading at the same time, the row readout line 231 of any given row of the pixel array 240 provides the selected pixel circuits 250 of the selection. A sum of the outputs to provide the output of the line. This technique can be used, for example, to implement a vertical image smoothing operation, completely within the current-to-analog domain of one of the image sensor circuits 200, and such filtering has generally associated benefits associated with reduced spatial noise, among which Some specific uses include anti-aliasing and mitigating the effects of pixel circuit manufacturing defects. Once the binary image has been read from the pixel array 240, the method continues to S304.

In S304, the binary image data obtained in S303 is processed. For example, the binary image data can be spatially filtered to eliminate noise. Some methods for filtering the binary image data include median filtering or morphological closure to eliminate features that are too small to be considered important for the method of Figure 15. In the case where the smoothing in the vertical direction has been applied as part of the current analog reading process of S303, the processing in S304 in the respective embodiments can be simplified by limiting the processing of the binary image data in a horizontal direction. In some embodiments of the method of Figure 15, the step S304 is optional and may be skipped altogether. In some embodiments, following the noise filtering described above in S304, the step S304 can also include the expansion of the image produced by a structural element to accelerate an exposure control signal pattern near the initial point provided by the binary image data. Spread. In various embodiments, the processing within S304 is performed by the digital image processor 210. The process continues to S305.

In S305, in the case where the step S304 has been performed, the filtered binary image data from S304 is combined with the exposure pattern data stored in the exposure pattern buffer 295. In the case where the step S304 has been skipped, the binary image material from S303 is combined with the exposure pattern data stored in the exposure pattern buffer 295. In various embodiments, the logical "OR" of the filtered binary image material and the exposure pattern data stored in the exposure pattern buffer 295 is performed, for example, and the result is then stored back The exposure pattern buffer 295 combines the filtered binary image data with the exposure pattern data stored in the exposure pattern buffer 295.

Figure 19C depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 of Figure 19A has been updated by combining with the exemplary filtered binary image data. In this example, the filtered binary image data and the 19A map are in addition to a "1" bit having an output corresponding to one of the pixel circuits in column 5 and row 3 of the pixel array 240. The exposure pattern data in the exposure pattern buffer 295 is the same, so the exposure pattern data in FIG. 19A is logically "OR" with the filtered binary image data, and then the exposure pattern buffer 295 generated in the 19Cth image is generated. There is a "1" bit for column 5 and row 3. The "1" bit of the pixel circuit in column 5 and row 3 of the corresponding pixel array 240 in the example of Fig. 19C may represent, for example, when the current signal is read out in S303, from the pixel. An output current signal of the circuit exceeds a threshold. In this example, the pixel circuits of columns 5 and 3 can be the brightest from one of the scenes being imaged. The portion of the sampled light is such that the charge accumulated in one of the sensing nodes of the pixel circuit may have exceeded a certain value, and the accumulated charge in the other pixel circuits may not have reached this value.

In various embodiments, once the exposure pattern buffer 295 has been updated within S305, the method continues to S306. Within S306, the contents of the exposure pattern buffer 295 are updated to provide expansion in accordance with an expansion criterion. In various embodiments, the expansion criterion is specified by one or more structural elements. A structural element can specify, for example, how to expand the content of the exposure pattern buffer 295. In some embodiments, a structural element can specify how to extend a logic value "1" within the exposure buffer 295 by some unit in one or more directions within the exposure pattern buffer 295. Various examples of the expansion criteria specified by the structural elements in accordance with embodiments of the present invention are described in Figures 18A-18D. It should be understood that the exemplary structural elements provided in Figures 18A-18D are merely examples, and that any desired structural elements can be used in the method of Figure 15.

Figure 18A depicts an example of an expansion criterion specified by a structural element in accordance with an embodiment of the present invention. In Fig. 18A, a black square indicates that an item in an exposure pattern buffer has a logical value of "1". An item having a logical value of "1" is associated with a particular pixel circuit within a pixel array. A square having an "x" indicates that an item in the exposure pattern buffer associated with a pixel circuit in the pixel array immediately to the right of the particular pixel circuit also needs to be set to a logical value of "1". Therefore, if the expansion criterion specified by the structural element of Fig. 18A is used for expansion, each logical value "1" in the exposure pattern buffer will be expanded to an item on the right.

Figure 18B depicts an example of an expansion criterion specified by a structural element in which a logical value of a "1" in an exposure pattern buffer extends two items above the item having a logical value of "1", Make the two items above the item set to the logical value of "1". Figure 18C depicts an example of an expansion criterion specified by a structural element having a logical value of "1" in an exposure pattern buffer associated with two adjacent pixel circuits of a pixel array. Two adjacent projects are each expanded one project above the project. In this example, a single item having a logical value of "1" (with no adjacent items having a logical value of "1") is not extended to other items. Figure 18D depicts an example of an expansion criterion specified by a structural element in which a logical value of a "1" in an item of an exposure pattern buffer is expanded in all directions within the exposure pattern buffer. project.

Figure 19D depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 of Figure 19C has been expanded in accordance with the exemplary expansion criteria specified by the structural elements of Figure 18D. In the example of Fig. 19D, the logical value of "1" in column 5 and row 3 of the exposure pattern buffer 295 is expanded in all directions according to the expansion criterion of Fig. 18D, so that the columns 5 and 3 are surrounded. All items of the project are set to have a logical value of "1". Thus, in various embodiments, step S306 allows the exposure pattern data within the exposure pattern buffer 295 to be morphologically enlarged such that the feature adds some pixels to one or more directions within the exposure pattern buffer 295. unit. The rate at which the exposure pattern data propagates relative to the read rate of one of the pixel arrays can be controlled by modifying the size and shape of one or more structural elements defining an expanded pattern. Once the content of the exposure pattern buffer 295 The method of Fig. 15 continues to S307 after one or more structural elements have been updated by expansion.

Referring to Figures 6, 7 and 15, in step S307, the updated exposure pattern data from the exposure pattern buffer 295 is written to the pixel array 240 to change the exposure pattern of the pixel array 240. In various embodiments, the exposure pattern of the pixel array 240 is defined, and the pixel circuits 250 within the pixel array 240 are enabled to accumulate additional charges within their respective sensing nodes, and the painting The pixel circuits 250 within the prime array 240 are thereby being prevented or stopped accumulating additional charges within their respective sensing nodes. In various embodiments, by exposing the exposure pattern data from the exposure pattern buffer 295 to the pixel array 240, the exposure pattern of the pixel array 240 is resynchronized with the contents of the exposure pattern buffer 295. Within the exposure pattern buffer 295 of various embodiments, a logical value of a "0" indicates that the corresponding pixel circuit 250 within the pixel array 240 is allowed to be at its respective sensing node 203 during the image capturing operation. The charge continues to accumulate or accumulate, and a logical value of a "1" indicates that the corresponding pixel circuit 250 within the pixel array 240 needs to be blocked or stopped accumulating additional charge within its individual sense node 203, but The accumulated charge in its individual sensing node 203 is maintained.

Although there are other possibilities, in various embodiments of the method as in FIG. 15, it is assumed that one of the states of the anti-diffusion gate transistor 216 of each pixel circuit 250 is always the same as the pixel circuit 250. One of the transfer gate transistors 202 is in the opposite state. In other words, in these embodiments, when the transfer gate transistor 202 of the pixel circuit 250 is controlled to turn "on", the anti-diffusion gate transistor 216 of the same pixel circuit 250 is controlled to be turned off, and when Pixel circuit When the transfer gate transistor 202 of 250 is controlled to turn off, the anti-glow gate 216 of the same pixel circuit 250 is controlled to turn "on".

In various embodiments, when the contents of the exposure pattern buffer 295 are written to the pixel array 240, the transmission gate transistor 202 within each pixel circuit 250 is turned off and the anti-glow gate 216 is turned off. Turned on, an item corresponding to the logical value of "1" specified in the pattern buffer 295 is exposed. In such pixel circuits 250, when the transfer gate transistor 202 is turned off and the anti-bright gate transistor 216 is turned on, the accumulation of additional light generated charges within the corresponding sense node 203 is blocked or Prohibited or stopped, and any charge subsequently generated by the corresponding photodiode 201 is substantially discharged through the anti-glow gate transistor 216. Moreover, in various embodiments, when the contents of the exposure pattern buffer 295 are written to the pixel array 240, the transfer gate transistor 202 within each pixel circuit 250 is turned "on" and the anti-diffusion gate transistor 216 is turned "on". Keep off, corresponding to an item in the pattern buffer 295 that has been assigned a logical value of "0". In the pixel circuits 250, when the transfer gate transistor 202 is turned on and the anti-glow gate transistor 216 is turned off, the charge generated by the light from the corresponding photodiode 201 is allowed to continue in the corresponding sense. Cumulative within node 203.

In various embodiments, the contents of the exposure pattern buffer 295 are written to the pixel array 240 one column at a time. In various embodiments, each bit in the exposure pattern buffer 295 corresponding to a pixel circuit 250 in a selected column to be written is interpreted as a corresponding picture connected to the pixel circuit 250. The signal on the control signal line 226. In various embodiments, when an item in the exposure pattern buffer 295 corresponding to a pixel circuit 250 has a logic value of "0", the digital image processor 210 is connected to the pixel circuit 250. The exposure control signal line 255 of the pixel control signal line 226 provides a HIGH signal and a LOW signal is provided on the anti-scattering control signal line 256. Moreover, in various embodiments, when an item in the exposure pattern buffer 295 corresponding to a pixel circuit 250 has a logic value of "1", the digital image processor 210 is connected to the pixel circuit 250. A LOW signal is provided on the exposure control signal line 255 of the pixel control signal line 226 and a HIGH signal is provided on the anti-dispersion control signal line 256.

Thus, in various embodiments, the digital image processor 210 based on the contents of the exposure pattern buffer 295 provides a signal to the pixels of such control signal lines _{226 1, 226 2, ...,} 226 m each to A pixel circuit 250 within a particular column is controlled. Thus, in such embodiments, the pixel control signal generator 213 can provide a HIGH signal on the control signal line 223 of the particular column such that the transmission gate of each pixel circuit 250 within the particular column Crystal 202 and anti-glow gate transistor 216 are written in accordance with the signals that are correspondingly provided. The pixel control signal generator 213 can then provide a LOW signal on the control column 223 of the particular column, and the gate transistor 202 and the anti-bright gate of each pixel circuit 250 in the particular column. Crystal 216 will maintain its value due to the parasitic gate capacitance of the transistors. In various embodiments, the process of writing the pixel array 240 in accordance with the contents of the exposure pattern buffer 295 may continue to the next column or the like within the pixel array 240 until all columns have been written. In some embodiments, steps S303 through S307 can be operated in a pipelined manner such that the exposure pattern data of the first column of one of the pixel arrays 240 can be used whenever, for example, a small number of columns have been read. The state of one of the pixel circuits 250 of the first column is updated, thus allowing readout and status updates to be performed in less time.

Fig. 19E depicts an example of an exposure pattern of the pixel array 240 set in accordance with the exposure pattern data in the exposure pattern buffer 295 of Fig. 19D. According to the exposure pattern of the pixel array 240 in FIG. 19E, the pixel circuits in one of the columns 4-6 of the pixel array 240 and one of the rows 2-4 have been controlled to stop at Additional charge is accumulated within the respective sensing nodes and is controlled to maintain any charge that has accumulated within its respective sensing node. The pixel circuits correspond to items having a logical value of "1" in the exposure pattern buffer 295 of Fig. 19D. The other pixel circuits within the pixel array 240 of Figure 19E are controlled to continue to accumulate or accumulate charge within their respective sensing nodes. The pixel circuits correspond to an item having a logical value of "0" in the exposure pattern buffer 295 of Fig. 19D. Referring again to Figures 6 and 15, once the updated exposure pattern data from the exposure pattern buffer 295 has been written to the pixel array 240 in S307 to change the exposure pattern of the pixel array 240, the method continues. Go to S308.

At S308, a total number of pixel circuits 250 for which further exposure has been stopped for the image capture operation is tested relative to a predetermined threshold, the total number being equal to one of the exposure pattern buffers 295 has been designated. The sum of the bits of the logical value of 1". In the case where the sum of the bits in the exposure pattern buffer 295 is not greater than the critical value, the method returns to S303. On the other hand, in the case where the sum of the bits in the exposure pattern buffer 295 is larger than the critical value, the method proceeds to S309. The sum of the bits of the exposure pattern buffer 295 is an example of one of many possible image features that can be used to make a decision in step S308. An item in the exposure pattern buffer 295 In the embodiment where the logical value of a "1" corresponds to the stop or block or inhibit of the accumulation of further charge in the sensing node of one of the pixel circuits (corresponding to the item), once all bits in the exposure pattern buffer 295 are present The element has been set to a logical value of "1", and returning to step S303 is not advantageous. In some embodiments, a maximum time limit value can also be set to the image capture operation.

In the example of Figs. 19A-19K, it is assumed that the critical value used in step S308 of Fig. 15 is 45. Of course, this threshold is only provided to the example, and other thresholds can be used for other embodiments. Since the sum of the bits in the exposure pattern buffer 295 of Fig. 19D is 9 (not greater than 45), this example will result in returning to step S303. Figure 19F depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 in Figure 19D has been updated by combining with the exemplary filtered binary data. In this example, the filtered binary image data includes a "1" bit corresponding to one of the pixel circuits in column 2 and row 7 of the pixel array 240 of Figure 19E. It should be noted that for each output of the pixel array 240, there may be multiple "1" bits within the filtered image material. Figure 19G depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 in Figure 19F has been expanded in accordance with the exemplary expansion criteria specified by the structural elements of Figure 18D.

Figure 19H depicts an example of an exposure pattern of the pixel array 240 set in accordance with the contents of the exposure pattern buffer 295 of Figure 19G. According to the exposure pattern of the exposure array 240 of FIG. 19H, one of the columns 3-7 of the pixel array 240 and one of the rows 1-5, or one of the columns 1-3 and the row 6 The pixel circuit in one of -8 has been controlled to stop at it, etc. Additional charge is accumulated within the individual sensing nodes and is controlled to maintain any charge that has accumulated within its respective sensing node. The pixel circuits correspond to items having a logical value of "1" in the exposure pattern buffer 295 of Fig. 19G. The other pixel circuits within the pixel array 240 of Figure 19H are controlled to continue to accumulate or accumulate charge within their respective sensing nodes. The pixel circuits correspond to items having a logical value of "0" in the exposure pattern buffer 295 of Fig. 19G. Since the sum of the bits in the exposure pattern buffer 295 of Fig. 19G is 34 (which is not greater than the exemplary threshold 45), this example will result in returning to step S303 in Fig. 15.

Figure 19I depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 of Figure 19G has been updated by combining with the exemplary filtered binary image data. In this example, the filtered binary image data includes "1" bits corresponding to the pixel circuits in column 1 and row 1-2 of pixel array 240 of Figure 19H. Figure 19J depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 of Figure 19I has been expanded in accordance with the exemplary expansion criteria specified by the structural elements of Figure 18D. Fig. 19K depicts an example of an exposure pattern of the pixel array 240 set in accordance with the contents of the exposure pattern buffer 295 of Fig. 19J. Since the sum of the bits in the exposure pattern buffer 295 of Fig. 19J is 49 (which is an exemplary threshold greater than 45), the example will proceed to step S309 in Fig. 15.

Referring again to Figures 6, 7 and 15, in step S309, image capture within the pixel array 240 is terminated. In various embodiments, image capture within the pixel array 240 is terminated by stopping any remaining pixel circuits 250 that are still accumulating charge from their individual sensing nodes 203 from their individual photodiodes 201. Exposure. In various embodiments, the stopping of the exposure can be performed by forcing the transfer gate transistor 202 of each of the pixel circuits 250 to a closed state and resisting each of the pixel circuits 250. The gate transistor 216 is forced to an on state to be executed. For example, the digital image processor 210 can provide a LOW signal on the exposure control signal line 255 of each of the pixel control signal lines 226 ₁ , 226 ₂ , . . . , 226 _m and A HIGH signal is provided on the control signal line 256, and the pixel control signal generator 213 can provide a signal on the transmission signal line 253 of each of the column control lines 223 ₁ , 223 ₂ , ..., 223 _n HIGH signal. In various embodiments, when the image capture of the pixel array 240 in step S309 is terminated, the accumulated charge in each of the sensing nodes 203 of each pixel circuit 250 is within the pixel circuit 250. maintain. The method then proceeds to S310.

In S310, an image captured in the pixel array 240 is read from the pixel array 240. In various embodiments, the reading of the image in step S310 is performed using a voltage analog mode. If the embodiment of the image sensor circuit 200 of FIG. 11 or the image sensor circuit 200 of FIG. 13 is used, the voltage source switch 217 and the output mode switch 227 of each row of the pixel array 240 are used. And the digital multiplexer 228 is controlled in accordance with the voltage-to-analog mode discussed above. In various embodiments, a voltage-to-analog readout from the pixel array 240 may be slower than a current-to-analog read from the pixel array 240, but the voltage-to-analog read ratio from the pixel array 240 This current-to-analog readout has a higher signal-to-noise performance. Thus, in various embodiments, an image capture operation is performed such that the last read from the pixel array 240 is an electrical Press analog reading is advantageous to obtain the best quality signal from the pixel array 240 to define the captured image. In various embodiments, the voltage-to-analog readout in step S310 is performed using the double sample amplifier 207 of each of the row ADC circuits 220, so the corrected pixel output voltage is based on the pixel output voltage and reset. The difference between the voltages is calculated. The method ends at S311. Some electronic shutter operations consistent with the method of Figure 15 are referred to herein as "wave shutter" operations.

In various embodiments, a pixel array can be initialized, image capture within the pixel array can be initialized, and concentrated in a pixel circuit near a space where the image intensity derivation metric exceeds a critical level. The exposure to the pixel circuit of a signal propagating from the pixel circuit whose exposure has been stopped can be stopped. Moreover, in various embodiments, image capture within a pixel array may be complete when exposure within some of the pixel circuits of the pixel array has been stopped during an image capture operation. In various embodiments, a spatially filtered analog image suitable for machine vision processing is captured according to one of the following methods: wherein one of the pixel arrays is exposed by a multidimensional control pattern and a structural element, the multidimensional control The pattern develops intermittently with a non-linear function of the analog data content when the pixel array is partially exposed.

Figure 16 depicts a flow chart of a method in accordance with an embodiment of the present invention. In S601, exposure information associated with an exposure pattern of one pixel array is stored. In various embodiments, the exposure information can include one or more bits of each pixel circuit within the pixel array. In various other embodiments, the exposure information can include a smaller number of bits than the total number of one of the pixel circuits of the pixel array. In some embodiments, the exposure information may refer to A number or other indicator associated with the exposure pattern of the pixel array. Moreover, in some embodiments, the exposure information can include one or more combinations of bits associated with the exposure pattern of the pixel array. After the exposure information has been stored, the method continues to S602.

In S602, the exposure pattern of the pixel array is changed based, at least in part, on: (i) exposure information that has been stored; and (ii) one or more signals output from the pixel array. In various embodiments, the stored exposure information is changed based on the one or more signals output from the pixel array, and the changed exposure information is used to control one of the exposure patterns of the pixel array. Variety. In some embodiments, the stored exposure information is changed in accordance with an expansion criterion, and the changed exposure information is used to control a change in the exposure pattern of the pixel array. In various embodiments, the possible exposure states of each of the pixel circuits within the pixel array include (i) an on state, wherein the pixel circuit is allowed to accumulate charge at one of the pixel nodes of the pixel circuit; And (ii) a closed state in which the pixel circuit is blocked or stopped from accumulating additional charges at the sensing node. Moreover, in various embodiments, the exposure pattern of the pixel array is defined, and the pixel circuits within the pixel array are in an on state such that they are still accumulating charges at their sensing nodes, and within the pixel array. The pixel circuits are thus turned off so that they do not accumulate additional charge within their sensing nodes. Once the exposure pattern of the pixel array has been changed in S602, the method ends in S603.

Figure 17 depicts a flow chart of a method in accordance with an embodiment of the present invention. In S651, one of the charges accumulates in the majority of the picture in a pixel array. Each of the prime circuits begins within the process and the method continues to S652. In S652, the accumulation of charge is blocked within at least one particular pixel circuit of the pixel circuits selected based at least in part on the one or more signals output from the pixel array. The method continues to S653. In S653, based at least in part on an expansion criterion, accumulation of charge in at least one of the pixel circuits of the pixel circuits adjacent to the particular pixel circuit within the pixel array is blocked. In various embodiments, the expansion criterion is specified by a structural element. The method ends in S654.

Figure 20 depicts another embodiment of an image sensor circuit 200 in accordance with an embodiment of the present invention. The embodiment of image sensor circuit 200 of FIG. 20 differs from the embodiment of image sensor circuit 200 of FIG. 11 in that the embodiment of image sensor circuit 200 of FIG. 20 includes a resistor grid 400. Elements of an embodiment of image sensor circuit 200 of Fig. 20 that is identical to elements of an embodiment of image sensor circuit 200 of Fig. 11 are labeled with the same reference symbols. In various embodiments, the resistor grid 400 includes a plurality of programmable or switchable resistors 401 and a plurality of capacitors 402. In various embodiments, the resistor grid 400 includes a switchable resistor 401 and a capacitor 402 for each row of the pixel circuit 250. In various embodiments, each switchable resistor 401 is coupled to one of a corresponding current to voltage converter 222 output and to one or more adjacent switchable resistors 401. Moreover, in various embodiments, each capacitor 402 is coupled between an output of one of the corresponding current-to-voltage converters 222 and the ground.

In various embodiments, the resistive grid 400 can be used to perform a spatial filtering that can be used, for example, in step S304 of the method of FIG. Performing spatial filtering in a analog domain using the resistor grid 400 in various embodiments One of the spatial filtering speeds can be improved as compared to other embodiments in which spatial filtering is performed by, for example, the digital image processor 210 in a digital domain. In some embodiments, the resistor grid 400 is used to perform horizontal filtering of signals for an image. In various embodiments, each of the switchable resistors 401 is controlled by the control processor 212. In various embodiments, the image sensor circuit 200 of FIG. 20 can be used to perform the method described in FIG. 15, and the spatial filtering of step S304 can be performed using the resistance gate 400.

In various embodiments, an operational mode in which the resistor grid 400 is used includes three functional steps. In a first step, each current of each row in the pixel circuit 250 loads a corresponding capacitor 402 to the voltage converter 222 while each of the switchable resistors 401 is turned off. In a second step, each current to one of the voltage converters 222 is set to a high impedance and the switchable resistors 401 are connected. In this state, the voltage value on each capacitor 402 is spatially low pass filtered, wherein the spatial filtering bandwidth and the time of the filtering process and the value of one of each switchable resistor 401 and each capacitor The value of one of the 402 capacitors is related. In a third step, the corresponding difference comparator 225 compares a voltage value stored in each capacitor 402 with a threshold to provide filtered binary image data.

Figure 21 depicts another embodiment of an image sensor circuit 200 in accordance with an embodiment of the present invention. The embodiment of image sensor circuit 200 of FIG. 21 differs from the embodiment of image sensor circuit 200 of FIG. 13 in that the embodiment of image sensor circuit 200 of FIG. 21 includes a resistor grid 400. Other elements of the embodiment of the image sensor circuit 200 of Fig. 21 that are identical to the elements of the embodiment of the image sensor circuit 200 of Fig. 13 are provided with the same reference. Symbol mark. In various embodiments, the resistor grid 400 includes a plurality of programmable or switchable resistors 401, a plurality of capacitors 402, and a plurality of voltage comparators 403.

In various embodiments, the resistive gate 400 includes a switchable resistor 401, a capacitor 402, and a voltage comparator 403 for each of the rows in the pixel circuit 250. In various embodiments, each switchable resistor 401 is coupled to one of a corresponding current comparator 222b output and to one or more adjacent switchable resistors 401. Moreover, in various embodiments, each capacitor 402 is coupled between an output of one of the corresponding current comparators 222b and the ground. In various embodiments, one of each voltage comparator 403 input is coupled to a corresponding capacitor 402, and one of each voltage comparator 403 output is coupled to a corresponding digital multiplexer 228.

In various embodiments, the resistive grid 400 can be used to perform a spatial filtering used in, for example, step S304 of the method of FIG. Compared to other embodiments in which spatial filtering is performed in a digital domain by, for example, the digital image processor 210, performing spatial filtering in a analog domain using the resistive gate 400 in various embodiments may improve one of spatial filtering. speed. In some embodiments, the resistor grid 400 is used to perform horizontal filtering of signals for an image. In various embodiments, each of the switchable resistors 401 is controlled by the control processor 212. In various embodiments, the image sensor circuit 200 of FIG. 21 can be used to perform the method described in FIG. 15, and the spatial filtering of step S304 can be performed using the resistance gate 400.

In various embodiments, an operational mode using the resistor grid 400 of FIG. 21 includes three functional steps. In a first step, the pixel circuit 250 Each of the current comparators 222b of each of the rows is loaded with a corresponding capacitor 402 when each of the switchable resistors 401 is turned off. In a second step, one of the outputs of each of the current comparators 222b is set to a high impedance, and the switchable resistors 401 are connected. In this state, the voltage value on each capacitor 402 is spatially low pass filtered, wherein the spatial filter bandwidth is a function of the filter program and the on-resistance of each switchable resistor 401 and each The value of one of the capacitors 402 is related. In a third step, a voltage value stored in each capacitor 402 is digitized by a corresponding voltage comparator 403 to provide filtered binary image data.

Referring again to FIGS. 6 and 7, in various embodiments, the image sensor circuit 200 is configured to obtain an image using an electronic shutter operation, wherein an exposure pattern of the pixel array 240 is dependent on time. The exposure information is set based, at least in part, on the charge accumulated in at least a portion of the pixel array 240. When a shutter operation conforming to, for example, the method of FIG. 15 is used, a maximum allowable time for performing an image capturing operation can be limited by the shutter efficiency of the pixel circuit 250. Shutter efficiency may represent the ability of each of the pixel circuits 250 to accurately maintain their charge within the sense node 203 during an image capture operation that is inhibited or prevented from additional charge during the image capture operation Or stop the time accumulated in the sensing node 203 until the last image is read out to capture the time of the pixel array 240. During this time, the charge stored or maintained within the sense node 203 may be degraded due to the charge generated by the light that accidentally reaches the sense node 203. One of the degradations can be compared to the light illuminating the pixel circuit 250 The intensity is proportional to the amount of time that the stored charge must be maintained until it is finally read from the pixel array 240.

In various embodiments, an automatic shutter mechanism allows for the use of light intensity to control the exposure time of one of the individual pixel circuits or pixel circuits within an image sensor circuit. In some such embodiments, the exposure of the pixel circuit receiving the bright light may be stopped earlier than the exposure of the pixel circuit receiving the lower intensity during an image capture operation. In various embodiments, when the exposure ends within a pixel circuit of a pixel array, the sensed value within one of the pixel circuits of the pixel circuit must be maintained within the sensing node until the painting The exposure in the remaining pixel circuits within the prime array ends and the last signal of an image is read from the pixel array. Shutter efficiency may represent the maximum amount of time that analog information may be stored in a sensing node (eg, a floating diffusion node) of one of the pixel circuits of the pixel array without significant degradation.

Referring to Fig. 22, various techniques that allow for improved shutter efficiency are described herein. Figure 22 depicts a layout 900 in accordance with an embodiment of the present invention. The layout 900 includes the pixel circuit 250. Elements of the embodiment of the pixel circuit 250 in Fig. 22, which are similar to the elements of the embodiment of the pixel circuit 250 in Fig. 14, are designated by the same reference numerals.

In various embodiments, the pixel circuit 250 includes the anti-glow gate transistor 216. Incorporating the anti-diffusion gate transistor 216 into the pixel circuit 250 can provide a means for blocking the photodiode 201 after the exposure of the pixel circuit 250 has stopped reaching the sensing node 203 of the pixel circuit 250. The mechanism of light generated by the light. This use of a primary anti-gap gate transistor can be used differently from one of the anti-gap gate transistors to avoid a pixel near a saturated pixel circuit. The photodiode of the circuit draws an excess of charge from the pixel circuit.

In various embodiments, a light sensor (eg, photodiode 201) is extended. For example, one of the regions of the photodiode 201 can be added to one or more extended regions 501. In some embodiments, the photodiode 201 is a pin-type photodiode. Moreover, in some embodiments, one of the regions of the photodiode 201 is extended or increased as much as possible. In some embodiments, the one or more extension regions 501 may even extend under one or more lines, such as exposure control line 255, anti-dispersion control signal line 256, voltage source line 235, row readout line 231, or Similar. In various embodiments, the one or more lines are metal lines. In some embodiments, although the one or more extended regions 501 may not improve one of the response of the pixel circuit 250, the one or more extended regions 501 may increase the area in which the charge generated by the light is absorbed, thus reducing The possibility of this charge accidentally reaching the sensing node 203. Thus, in various embodiments, the one or more extended regions 501 may allow for improved shutter efficiency.

In various embodiments, the layout 900 further includes one or more virtual diffusions 502. In some embodiments, the one or more virtual diffusions 502 can be located in other empty regions of the pixel circuit 250 that do not belong to the photodiode 201 or the transistors 214, 215, 205, 205, and 206. Without the one or more virtual diffusions 502, some of the light generated by the light reaching the space may be diffused to the sensing node 203 and reduce a shutter efficiency. In various embodiments, to prevent this from occurring, the equal-space region covers one or more virtual diffusions 502. In various embodiments, the one or more virtual diffusions 502 are coupled to a constant voltage source (not shown in FIG. 22), such as a voltage supply or the like, thereby passing through the one or more virtual diffusions The charge generated by any light of 502 is Absorbed to the voltage supply source.

In various embodiments, short wavelength illumination is used to help improve shutter efficiency. In various embodiments, the use of short wavelength light can help improve shutter efficiency because short wavelength photons can be absorbed near a surface and can therefore be captured by the photodiode 201. Longer wavelength photons can reach deeper into a substrate and may fall out of one of the active regions of the photodiode 201, thus increasing their likelihood of reaching the sensing node 203 and reducing shutter efficiency.

In various embodiments, the layout 900 further includes an infrared (IR) filter 503 on the pixel circuit 250. By penetrating into a very deep substrate of one of the pixel circuits 250 where no electric field is present, infrared photons may cause problems, and electrons from the photons may randomly diffuse and reach the sensing node 203, thereby degrading The data stored in the sensing node 203. In various embodiments, by using the IR filter 503 on the pixel circuit 250, the amount of charge generated by light within a deep substrate of the pixel circuit 250 may be reduced, thereby allowing for improved shutter efficiency. In some embodiments, the layout 900 can include a color filter (not shown in FIG. 22) on the pixel circuit 250. The behavior of long wavelength photons in the visible spectrum may be similar to IR photons and may cause problems due to penetration into a very deep place within one of the pixel circuits 250. In various embodiments, a color filter can be used to inhibit such photons from reaching a substrate of the pixel circuit 250. In some embodiments, the pixel circuit 250 can be configured to sense light within the visible light spectrum. In some embodiments, the pixel circuit 250 can be configured to sense light outside of the visible spectrum.

In various embodiments, the layout 900 further includes a metal protection Sign 504. In various embodiments, the metal protection feature 504 can cover at least a portion of the sensing node 203. In some embodiments, protecting the sense node 203 with a metal protection may allow for a reduction in the degradation of charge stored within the sense node 203 due to light generation.

Referring again to FIG. 6, in various embodiments, the image sensor circuit 200 can be configured to allow receipt of an instruction that specifies a shutter mode to be used for one or more particular image capture operations. Types of. For example, in various embodiments, the image sensor circuit 200 can be configured to receive an instruction that selects (i) a global shutter operation to be used for an image capture operation; (ii) a scroll a shutter operation; and (iii) one of a wave of shutter operations. In such embodiments, the image sensor circuit 200 can capture an image using a global shutter operation in the event that the command specifies a global shutter operation. Moreover, in such embodiments, in the event that the command specifies a rolling shutter operation, the image sensor circuit 200 can utilize an scrolling shutter operation to capture an image. Moreover, in such embodiments, in the event that the command specifies a shutter operation, the image sensor circuit 200 can capture an image using a wave shutter operation in accordance with the method of FIG. In various embodiments, where the image sensor circuit 200 is used to perform a wave of shutter operation, the image capture sensor circuit 200 can receive a signal that specifies that the wave is to be used for the wave. One or more structural elements of the shutter operation. In some embodiments, the image capture sensor circuit 200 can be configured to automatically select one of a type of shutter operation based on the sensed light condition.

Exemplary applications of image sensor circuits (eg, image sensor circuit 200) include, for example, manufacturing automation, product components, identification (ID) reading Use in vehicle, vehicle control, gesture recognition, video surveillance, three-dimensional (3D) modeling, motion analysis, medical devices, military devices, mapping systems, or the like.

The embodiments disclosed herein are considered to be illustrative and not limiting of the invention in all aspects. The invention is not limited to the embodiments described above. Various modifications and changes may be made to the invention without departing from the spirit and scope of the invention. Various modifications and variations are intended to be included within the scope of the invention.

100‧‧‧Image sensor circuit

101‧‧‧ pixel array

102‧‧‧ Analog-to-digital converter (ADC) block

103‧‧‧Digital Image Processor

104‧‧‧ column addressing circuit

105‧‧‧Control processor

106‧‧‧Image Memory Buffer

107 ₁ , 107 ₂ ,...,107 _n ‧‧‧ column control line

108 ₁ , 108 ₂ ,...,108 _m ... analog output line

109 ₁ , 109 ₂ ,...,109 _m ...digital output line

112‧‧‧pixel circuit

114‧‧‧ line ADC circuit

121‧‧‧Light diode

122‧‧‧Transmission gate transistor

131‧‧‧Sensor node

124‧‧‧Resetting the transistor

125‧‧‧Drive transistor

126‧‧‧Read selection transistor

127‧‧‧ column readout signal line

129‧‧‧Transmission signal line

130‧‧‧Reset signal line

131‧‧‧Sensor node

132‧‧‧voltage source

133‧‧‧The end

140‧‧‧Source transistor

142‧‧‧Double Sampling Amplifier

144‧‧‧ Analog-to-digital converter (ADC) circuits

146‧‧‧Amplifier control signal line

148‧‧‧Converter control signal line

200‧‧‧Image sensor circuit

201‧‧‧Light diode

202‧‧‧Transmission gate transistor

203‧‧‧Sensor node

204‧‧‧Resetting the transistor

205‧‧‧Drive transistor

206‧‧‧Read selection transistor

207‧‧‧Double-sampling amplifier

208‧‧‧ source transistor

209‧‧‧ADC circuit

210‧‧‧Digital Image Processor

211‧‧‧Image Memory Buffer

212‧‧‧Control processor

213‧‧‧ pixel control signal generator

214‧‧‧First write selection transistor

215‧‧‧Second write selection transistor

216‧‧‧Anti-glow gate transistor

217‧‧‧Voltage source switch

217 ₁ ~217 _m ‧‧‧voltage source switch

218‧‧‧current source

219‧‧‧Output line

220‧‧‧ line ADC circuit

221‧‧‧Reference signal converter

222‧‧‧current to voltage converter

222b‧‧‧current comparator

223‧‧‧ column control line

223 ₁ ~ 223 _n ‧‧‧ column control line

224‧‧‧current to voltage converter

225‧‧‧Difference comparator

226‧‧‧ pixel control signal line

226 ₁ ~ 226 _m ‧‧‧ pixel control signal line

227‧‧‧Output mode switch

228‧‧‧Digital multiplexers

229‧‧‧Voltage Driver

230‧‧‧voltage source

231‧‧‧ line readout line

231 ₁ ~ 231 _m ‧‧‧ line readout line

232‧‧‧reference signal line

233‧‧‧The end

234‧‧‧ bias source

234 ₁ ~ 234 _m ‧‧‧ bias source

235‧‧‧voltage source line

235 ₁ ~ 235 _m ‧‧‧voltage source line

238‧‧‧Voltage source line

239‧‧‧Switch

240‧‧‧ pixel array

241‧‧‧Control line

242‧‧‧Control line

243‧‧‧reference voltage line

245‧‧‧Communication line

246‧‧‧Digital output line

246 ₁ ~ 246 _m ‧‧‧ digital output line

247‧‧‧Write bus

248‧‧‧Read/Write Busbar

249‧‧‧ADC block

250‧‧‧ pixel circuit

251‧‧‧voltage source

252‧‧‧Reset signal line

253‧‧‧Transmission signal line

254‧‧‧ column readout signal line

255‧‧‧Exposure control signal line

256‧‧‧anti-radiation control signal line

260‧‧‧critical current generator

265‧‧‧current control transistor

266‧‧‧Selecting a crystal

267‧‧‧critical voltage source

268‧‧‧critical voltage line

273‧‧‧Voltage supply

274‧‧‧Select signal line

281‧‧‧ bias source

283‧‧‧current source switch

290‧‧‧One or more circuits

295‧‧‧Exposure pattern buffer

400‧‧‧resistance grid

401‧‧‧Switchable Resistors

402‧‧‧ capacitor

403‧‧‧Voltage comparator

501‧‧‧Extended area

502‧‧‧Virtual Diffusion

503‧‧‧Infrared filter

504‧‧‧Metal protection features

700‧‧‧Image Processing System

800‧‧‧ processor

900‧‧‧ layout

S301~S311‧‧‧Steps

S601~S654‧‧‧Steps

Figure 1 depicts a conventional image sensor circuit; Figure 2 depicts a conventional pixel circuit; Figure 3 depicts a conventional row analog-to-digital converter (ADC) circuit; The figure depicts a conventional image sensor circuit; FIG. 5 depicts an image processing system in accordance with an embodiment of the present invention; and FIG. 6 depicts an image sensor circuit in accordance with an embodiment of the present invention. Figure 7 depicts a pixel circuit in accordance with an embodiment of the present invention; Figure 8 depicts a critical current generator in accordance with an embodiment of the present invention; and Figure 9 depicts an embodiment in accordance with the present invention. a row of ADC circuits; FIG. 10 depicts a reference signal converter in accordance with an embodiment of the present invention; FIG. 11 depicts an image sensor circuit in accordance with an embodiment of the present invention; and FIG. 12 depicts the basis A row of ADC circuits in accordance with an embodiment of the present invention; Figure 13 depicts an image sensor circuit in accordance with an embodiment of the present invention; Figure 14 depicts a layout of a pixel circuit in accordance with an embodiment of the present invention; Figure 15 depicts A flowchart of a method of an image sensor circuit of an embodiment of the invention; FIG. 16 depicts a flow chart of a method for an image sensor circuit in accordance with an embodiment of the present invention; The figure depicts a flow chart of a method for an image sensor circuit in accordance with an embodiment of the present invention; FIG. 18A depicts an expansion criterion specified by a structural element in accordance with an embodiment of the present invention; Figure 18B depicts an expansion criterion specified by a structural element in accordance with an embodiment of the present invention; Figure 18C depicts an expansion criterion specified by a structural element in accordance with an embodiment of the present invention; Figure 18D depicts An expansion criterion specified by a structural element in accordance with an embodiment of the present invention; FIG. 19A depicts an example of the contents of an exposure pattern buffer in accordance with an embodiment of the present invention; and FIG. 19B depicts invention An example of an exposure pattern of a pixel array set according to the content of the exposure pattern buffer of FIG. 19A; and FIG. 19C depicts an exposure pattern according to an embodiment of the present invention. An example of the contents of the buffer; FIG. 19D depicts an example of the contents of an exposure pattern buffer in accordance with an embodiment of the present invention; and FIG. 19E depicts an arrangement according to the 19D according to an embodiment of the present invention. An example of an exposure pattern of a pixel array set by the content of the exposure pattern buffer; FIG. 19F depicts an example of the contents of an exposure pattern buffer according to an embodiment of the present invention; and FIG. 19G depicts the basis An example of the content of an exposure pattern buffer of an embodiment of the present invention; FIG. 19H depicts one of the pixel arrays set according to the content of the exposure pattern buffer of FIG. 19G according to an embodiment of the present invention. An example of an exposure pattern; FIG. 19I depicts an example of the contents of an exposure pattern buffer in accordance with an embodiment of the present invention; and FIG. 19J depicts the contents of an exposure pattern buffer in accordance with an embodiment of the present invention. An example of FIG. 19K depicts an example of an exposure pattern of a pixel array set according to the content of the exposure pattern buffer of FIG. 19J according to an embodiment of the present invention; 0 depicts an image sensor circuit in accordance with an embodiment of the present invention; and FIG. 21 depicts an image sensor circuit in accordance with an embodiment of the present invention; Figure 22 depicts a layout depicting an embodiment in accordance with the present invention.

200‧‧‧Image sensor circuit

240‧‧‧ pixel array

290‧‧‧One or more circuits

700‧‧‧Image Processing System

800‧‧‧ processor

Claims (30)

An image sensor circuit comprising: a pixel array comprising a plurality of pixel circuits, wherein at least one of the plurality of pixel circuits includes a sensing node, and a voltage control output on the sensing node a signal; and one or more circuits configured to update exposure information based at least in part on one or more signals output from the pixel array, and configured to control an exposure pattern of the pixel array based on the exposure information And wherein the one or more circuits are assembled such that readout of the output signal is non-destructive with respect to charge accumulated on the sensing node. The image sensor circuit of claim 1, wherein the one or more circuits are configured to update the exposure information in an iterative manner when an image is being captured by the pixel array, based at least in part on The one or more signals and at least one expansion criterion output from the pixel array. The image sensor circuit of claim 2, wherein the at least one expansion criterion is specified by at least one structural element. The image sensor circuit of claim 1, wherein the pixel circuits are controllable such that at least one pixel circuit in one of the pixel arrays can be aggregated at one of the pixel nodes of the pixel circuit The charge, while at least one second pixel circuit in the column is prevented from accumulating charge at one of the sensing nodes of the second pixel circuit during at least a portion of the image capture operation. The image sensor circuit of claim 1, wherein the one or more circuits are assembled to be based at least in part on the pixel The value of the one or more signals output by the array alternately updates the exposure information, the equivalent of the one or more signals representing the accumulated charge in at least a portion of the pixel array. The image sensor circuit of claim 1, wherein the one or more circuits are configured to individually control an exposure state of the pixel circuits based on the exposure information to control the exposure of the pixel array. pattern. The image sensor circuit of claim 6, wherein the exposure states of each pixel circuit of the pixel circuits include an on state and a off state, wherein the pixel is in the on state. The circuit is allowed to accumulate charge at one of the sensing nodes of the pixel circuit, in which the pixel circuit is prevented from accumulating additional charge at the sensing node. The image sensor circuit of claim 1, further comprising: one or more memory devices for storing the exposure information as exposure pattern data, including to be used to control the pixel circuit At least one bit of each pixel circuit in the pixel circuits of one of the exposed states. The image sensor circuit of claim 8, wherein the one or more circuits are configured to store the exposure pattern data stored in the one or more memory devices prior to an image capture operation. Reset to an initial pattern. The image sensor circuit of claim 1, wherein the one or more circuits are combined to form an image by the pixel array When capturing, the exposure pattern of the pixel array is changed multiple times based on the exposure information. The image sensor circuit of claim 1, wherein at least one pixel circuit of the pixel circuit comprises: a photosensitive element; a first transistor having a terminal connected to the photosensitive element; And a second transistor connected between an exposure control signal line and one of the gates of the first transistor; the one or more circuits being configured to control a signal on the exposure control signal line based on the exposure information . The image sensor circuit of claim 11, wherein the at least one pixel circuit further comprises: a third transistor connected to the photosensitive element; and a fourth transistor connected to an anti-glow The control signal line is coupled to one of the gates of the third transistor; the one or more circuits are configured to control an anti-fuzzescent signal on the anti-dispersion control signal line based on the exposure information. The image sensor circuit of claim 12, wherein the one or more circuits are configured to control the anti-glow signal on the anti-dispersion control signal line for the exposure during an image capturing operation The opposite value of one of the exposure control signals on the control signal line. The image sensor circuit of claim 12, wherein the photosensitive element has a length extending below the exposure control signal line a first portion and a second portion extending below the anti-dispersion control signal line. The image sensor circuit of claim 11, wherein the at least one pixel circuit further comprises: one or more virtual diffusions connected to a constant voltage during an image capturing operation. The image sensor circuit of claim 11, wherein the at least one pixel circuit further comprises: a reset transistor coupled between a fixed voltage and the sensing node, and one of the sensing nodes The voltage control is an output signal; the one or more circuits are configured to control a reset signal, the reset signal being applied to one of the gates of the reset transistor, such that the reset transistor is in an image capture operation The period remains off during and between at least two readouts of the output signal such that the at least two out of the output signal is non-destructive with respect to the charge accumulated on the sense node. The image sensor circuit of claim 1, wherein the pixel circuit array further comprises a plurality of row readout lines to provide the one or more signals; and the one or more circuits are configured to select The signals on the read signal lines of the lines are controlled to be voltage signals or current signals. The image sensor circuit of claim 1, wherein the one or more signals are analog current signals. For example, the image sensor circuit described in claim 1 of the patent scope is further The step includes: a row of analog-to-digital converter circuits, configured to receive the pixel array of two or more pixel circuits in the pixel circuits in the same row as one of the pixel arrays An analog signal outputted on the line is read out and matched to convert the analog signals into corresponding digital signals. The image sensor circuit of claim 1, wherein the pixel circuits are arranged in a plurality of columns and a plurality of rows; the one or more circuits are configured to selectively control the pixel array to Providing output from two or more columns and two or more rows of pixel circuits at the same time such that the outputs from the two or more columns are analogized on the row readout line of the pixel array Form combination. The image sensor circuit of claim 1, further comprising: a resistor grid comprising a plurality of switchable resistors and a plurality of capacitors connected to receive the pixel based array a signal outputting the value of the one or more signals, the switchable resistors being configured to selectively connect the capacitors in accordance with the command signal; the switchable resistors have been controlled to connect the capacitors and In the event that a period of time has elapsed, the one or more circuits are configured to sample a voltage stored in at least one of the capacitors; and the one or more circuits are configured to be based on the voltage Update the exposure information. The image sensor circuit of claim 1, wherein the pixel circuits are arranged in a plurality of columns and a plurality of rows, each of the columns further comprising a threshold current generator; the one or more Circuitry is configured to specify a voltage of a reference signal derived from one of a particular threshold current generator in a particular column of the columns and one of the pixel circuits from the particular column A voltage of one of the signals derived from the output of the pixel circuit is compared and combined to update the exposure information based on the result of the comparison. The image sensor circuit of claim 1, wherein the one or more circuits are configured to terminate the pixel array based on a comparison between a critical number and a number calculated from the exposure information. An image capture operation within. The image sensor circuit of claim 1, wherein the one or more circuits comprise a digital signal processor. The image sensor circuit of claim 1, further comprising: an infrared filter disposed on at least a portion of the at least one pixel circuit in the pixel circuits. The image sensor circuit of claim 1, further comprising: a color filter disposed on at least a portion of the at least one pixel circuit in the pixel circuits. A method for an image sensor circuit, the image sensor circuit comprising a pixel array having a plurality of pixel circuits, the method comprising The following steps: storing information related to an exposure pattern of the pixel array; and changing the picture based at least in part on (i) the stored information; and (ii) one or more signals output from the pixel array The exposure pattern of the array of pixels, wherein the one or more signals output from the pixel array are non-destructive with respect to charge accumulated on a sensing node of at least one of the plurality of pixel circuits. A method for an image sensor circuit, the image sensor circuit comprising a pixel array having a plurality of pixel circuits, the method comprising the steps of: starting a charge in each of the pixel circuits Converging; preventing aggregation of charges in at least one particular pixel circuit in the pixel circuits selected based at least in part on one or more signals output from the pixel array, wherein the pixel array is Outputting the one or more signals is non-destructive with respect to charge accumulated on a sensing node of at least one of the plurality of pixel circuits; and blocking the pixel array based at least in part on an expansion criterion An accumulation of charges within at least one of the pixel circuits in the pixel circuits adjacent to the particular pixel circuit. A pixel circuit comprising: a photodiode; a first transistor coupled between the photodiode and a sensing node, wherein the voltage of the sensing node controls an output signal having a The charge accumulated on the sensing node is non-destructive readout; And a second transistor connected between an exposure control signal line and a gate of the first transistor, the second transistor having a gate connected to a transmission signal line. An image processing system comprising: an image sensor circuit comprising a pixel array and being configured to obtain an image by using a shutter mode, wherein an exposure pattern of the pixel array is set according to exposure information, the exposure information At least in part based on the charge accumulated in at least a portion of the pixel array as a function of time, wherein reading of at least a portion of the pixel array is dependent on a charge accumulated in the at least one portion of the pixel array Destructive; and a processor configured to detect one or more objects within the image.