TW200917827A - Circuits and methods allowing for pixel array exposure pattern control - Google Patents

Abstract

An image processing system includes an image sensor circuit. The image sensor circuit is configured to obtain an image using a type of shutter operation in which an exposure pattern of a pixel array is set according to exposure information that changes over time based at least partially on charge accumulated in at least a portion of the pixel array. An image sensor circuit includes a pixel array and one or more circuits. The one or more circuits are configured to update exposure information based at least partially on one or more signals output from the pixel array, and to control an exposure pattern of the pixel array based on the exposure information. A pixel circuit includes a first transistor connected between a photodiode and a sense node, and a second transistor connected between an exposure control signal line and a gate of the first transistor.

Description

200917827 IX. INSTRUCTIONS: [Improvement of the related patent application of the singularity of the singularity of the present invention is based on the benefit of US Patent Application Serial No. 12/184,160, entitled "Circuits and Methods Allowing for Pixel Array Exposure Pattern Control". The application is filed on July 31, 2008, the entire contents of which are incorporated herein by reference. The present application claims the benefit of the U.S. Provisional Application Serial No. 60/953,905, entitled " CMOS Image", filed on Aug. 3, 2007, the entire content of which is incorporated herein by reference. This application claims the benefit of the US Provisional Application No. 61/020,560, entitled "CMOS Image Sensor for Machine Vision", filed on January 11, 2008, the entire contents of which are incorporated by reference. Incorporated herein. U.S. Patent Application Serial No. 12/184,160, the entire disclosure of which is hereby incorporated by reference in its entirety in its entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all FIELD OF THE INVENTION Embodiments of the present invention generally relate to image processing systems, image sensor circuits, pixel circuits, image capture methods, and image processing methods, and in particular embodiments, An image sensor circuit for controlling 20 or a plurality of circuits of the pixel array of the pixel array. [Prior Art 3 BACKGROUND OF THE INVENTION Image sensor circuits are widely used to obtain images of solid scenes and objects. In many cases, the image sensor circuit is used to obtain images that are seen and observed by humans 5 200917827. In other cases image sensor circuits are used to obtain images that are used for camera vision and other automatic pattern rhythm programs. Conventional image sensor circuits that emphasize the actual description of human observed scenes may present problems when used in pattern recognition applications. The image sensor circuit generally includes a pixel array having a plurality of pixel circuits arranged in columns and rows. Each of the pixel circuits generally includes a germanium, an optical element such as a photodiode or the like for use in imaging an image. The light intensity of the split is sampled. The accumulated charge of the photosensitive elements in the pixel circuit from the 5 voltaic array during image manipulation is generally controlled in accordance with a predetermined period of time assigned to a shutter operation. Two shutter operations for image sensor circuits of various related art 疋·(1)-wide shutter operation; and (9) a rolling shutter operation. 15 In "Typical Global Shutter Operation" - all the paintings in the pixel array are weighted q and are simultaneously exposed - referring to the period between (4) to capture one: as in the use of such a global shutter, the painting The same first-time point in the prime array accumulates or accumulates charge from the light, and then in the shutter, talks about how to accumulate the electric charge. Therefore, all the pixel circuits that use these global gates/deniers and 歹1m are used. When there is - the same aggregation, S accumulates during this aggregation time. The field of the job 'charges from the light is in the typical rolling pure door operation, all the pixel circuits in the column are _1 == - the same time period. Simultaneously exposing all the pixel circuits within a specified number - the same column - the same column, the same time point _1 « since 4 200917827, then stop accumulating charges at the same second time point. Once the = circuit is listed in this _ rolling shutter operation has been exposed - during the specified "day" period, then the program continues to the pixel array (10) under the column - Β #Ρ1# (four) of all the pixel circuits Next (4), the specified aggregation is exposed. The program is between the pixel arrays (four)_, and all columns of the straight_draw four-way have been exposed to the scene during the specified aggregation time. In the global fast and rolling shutter operation, it is sought to maintain the relative relationship between the light intensity in the scene 10 15 = point ^, so that the point in the county_physical scene is affected by the time, then the pixel circuits are not fully saturated. Within the range, the situation within the image of the spine of the body scene is the same. This is expected when it is manipulated to look at humans, because the images that were taken are taken for the sake of the physical body. : And Tian draws for the purpose of pattern recognition - one of the high dynamic range scenes: when 'try to maintain the relative relationship between the points of light intensity within a scene, can generate $] title 'because of the light intensity in the physical scene The change may exceed the dynamic range of one of the pixel circuits. An apricot, for example, considers a physical scene with a brighter central portion and a darker edge, such as when viewed from a dark-light afternoon. In this case, if the accumulation time of the accumulated charge in the - global shutter or rolling shutter operation is set to - a long time to accumulate a sufficient amount of charge for the dark area, the pixel circuit for accumulating charge for the bright area Possible charge saturation. This fresh charge may result in the inability to see objects in the bright areas of the image. On the other hand, if the accumulation time of the accumulated electric charge is set to a short time in the case of the full 20 200917827 domain shutter or rolling shutter operation to saturate the pixel circuits of the accumulated electric charge for the bright areas, A pixel circuit that accumulates charge in dark areas may not accumulate enough charge to allow viewing of objects in dark areas. 5 The problem of accumulating too much charge or accumulating too little charge as described above can be very severe under the context of automatic pattern recognition because it is difficult and generally impossible to identify an object that cannot be seen within an image. For example, in the example provided above, if the captured image is being used to automatically control a car traveling in the tunnel, saturating a 10 image in the exit area of the tunnel may prevent the object from being recognized when leaving the tunnel. Ability, which may adversely affect the ability of the car to avoid such objects. Thus, in the case of capturing images of high dynamic range scenes having large differences in light intensity between different regions of the scenes, such global shutter and rolling shutter operations may cause problems. 15 Figure 1 depicts a block diagram of a conventional image sensor circuit 100. The image sensor circuit 100 includes a pixel array 101, a type of analog-to-digital converter (ADC) block 102, a digital image processor 103, a column of addressing circuits 104, a control processor 105, and an image memory buffer. 106. The pixel array 101 includes a plurality of pixel circuits 20 112 arranged in columns and rows. Each of the pixel circuits 112 includes a light sensing element, such as a light diode or the like, to sample the light intensity of a corresponding portion of an imaged scene, and each pixel circuit 112 is assembled to be sampled based on The light intensity produces a class of ubiquitin signals. The pixel array 101 includes column control lines 107, 1072, ..., 107n (each 200917827 may include a plurality of control lines (not shown in the mth)), and the pixel array ι〇ι also includes an analog output line 108l , K..., milk. The column addressing circuit has just passed through the column control lines 1071, 1〇72, . . . , W to provide control signals to the pixel circuits 112 in the pixel array ιοί to control the operations of the pixel circuits ι2. The pixel circuits 112 in the same column of the pixel barrier 101 (e.g., the i-th column of the pixel array) are shared by a common column control line i〇7i from the column addressing circuit ι4 Column control signal. The pixel circuits U2 in the same row of the pixel array ι〇ι (e.g., the row of the pixel array 1〇1) share a common analog output line 108_i to provide an output. The column addressing circuit 104 10 controls the pixel circuits 112 to perform column-by-column processing on a rolling shutter operation. The analog pixel signals output from the S-cell array 101 are input to the ADC block 102 through the analog output lines 108A, 1B, 82, ..., l8m. The ADC block 102 generally includes a row ADC circuit 114 for each row of the pixel circuits 12 within the pixel array 101. The row ADC circuits 114 are configured to convert the analog pixel signals received from the pixel array 101 through the individual output lines of the analog wheel outputs 108, 108, ..., l8m to the corresponding digits. The digital signal output on the output line 109!, 1 Oh, ..., 1 〇 9m. The control processor 105 is configured to control the operation of one of the ADC blocks 102 and is also configured to control the operation of one of the column addressing circuits 104. The digital pixel signals that are rounded up from the two digit output lines 109P 1092, ..., 109' from the ADc block 1〇2 are input to the digital image processor 103. The digital image processor 1〇3 and The image memory buffer 106 and the control processor 〇5 cooperatively process the input digital pixel signals to produce a digital output signal on an output line. Figure 2 depicts a conventional design of the pixel circuit 112. The pixel circuit 200917827 includes a photodiode 121, a transmission gate transistor 122, a sensing node 13 and a resetting transistor 124, a driving transistor 125, and a read selection transistor 126. The transmission gate The transistor 122, the reset transistor 12 4, the drive transistor 125 and the read select transistor 12 each comprise a 5-N channel metal oxide semiconductor (NMOS) field effect transistor. The column control lines 107 The same line in !, 1072, ..., 107n (see Fig. 1) is shown in Fig. 2 as a column of control lines 107, and the analog output lines 108, 1〇82,, l〇8m (see The same line in Figure 1 is shown as an analogy in Figure 2. The output line 108. The column control line 1 〇 7 includes a column of read signal lines 127, a pass signal line 129, and a reset signal line 13. The pixel circuit 112 receives the column read signal line 127, the transmission a signal line 129 and an input signal on the reset signal line 130. The pixel circuit 112 provides an output signal on the analog output line 1 。 8. As described in Fig. 2, the photodiode 121 is connected to ground. The terminal 133 15 is between the first terminal of the transmission gate transistor 12. The second terminal of the transmission gate transistor 122 is connected to the sensing node 131, and one of the gates of the transmission gate transistor 122 Connected to the transmission signal line 129. One of the first terminals of the resetting transistor 124 is connected to a voltage source 132, and one of the second terminals of the resetting transistor DA is connected to the sensing node 131, and the resetting is performed. A gate of the crystal 20 I24 is connected to the reset signal line 130. One of the first terminals of the driving transistor 125 is connected to the voltage source 132, and one of the second terminals of the driving transistor 125 is connected to the read selection One of the first terminals of the crystal 126, and the driving transistor 12 One of the gates is connected to the sense node 1M. The second terminal of the read select transistor 126 is connected to the analog output line 1〇8, and the gate of the 10 200917827 read transistor 126 is connected to The column reads signal line 127. Figure 3 depicts a conventional design of the row of ADC circuits 114. The row of ADC circuits 114 includes a source transistor 140, a dual sampling amplifier 142, and a type of comparison digital converter (ADC). The circuit 144. The double sampling amplifier 142 5 is controlled by a control signal provided from the control processor 1 〇 5 (see FIG. 1), and the control signals are received by the double sampling amplifier 142 through an amplifier control signal line 146. . The ADC circuit 144 is controlled by a control signal provided from the control processor 1〇5 (see Figure 1), which is received by the ADC circuit 144 via a converter control signal line 148. The same line in the analog output lines 10 1 〇 8 ι, 1 〇 82, ..., 108 m (see Fig. 1) is shown in Fig. 3 as an analog output line 108, and the digital output lines 丨ο, A common line of 1, 92, ..., 109m (see Fig. 1) is shown as a digital output line 109 in Fig. 3. A first terminal of the source transistor 140 is coupled to the digital output line 108, and a second terminal of the remote source transistor 140 is coupled to the ground terminal 15 I33. One of the double sampling amplifiers 142 is coupled to the analog output line 108, and one of the dual sampling amplifiers 142 is coupled to one of the input terminals of the ADC circuit 144. An output of one of the ADC circuits 144 is coupled to the digital output line 109. Fig. 4 depicts a conventional image sensor circuit 1 of Fig. 1, wherein the pixel circuit 112 of Fig. 2 and the ADC circuit 114 of Fig. 3 are described. One of the operations of the image sensor circuit 100 is now described with reference to Figures 2, 3 and 4. When an image capturing operation is initialized, the photodiode 丨21 turns on the transmission gate transistor 12 2 and the reset signal line 藉3 by providing a high (HIGH) signal on the transmission signal line 129. A η GH signal 200917827 is provided on the 以 to turn the reset transistor 124 on and reset. A LOW signal is then provided on the reset signal line 130 to turn off the reset transistor 124 while the transfer gate transistor 122 remains turned on to allow charge generated in the photodiode 121 to be The sensing node 131 accumulates. At the end of an exposure time 5 interval, a LOW signal is supplied to the transmission signal line 129 to turn off the transmission gate transistor 122. Once the transfer gate transistor 122 is turned off, a HIGH signal is provided on the column read signal line 127 to turn on the read select transistor 126, and the double sample amplifier 142 is on the analog output line 108. A halogen circuit outputs 10 voltage samples. Next, a LOW signal is provided on the column read signal line 127 to turn off the read select transistor 126' and a HIGH signal is provided on the reset signal line 130 and the transfer signal line 129 to turn on the The germanium transistor 124 and the s-transfer gate transistor 122 are reset to reset the sensing node 131. When the sensing node 131 is in a reset state, a high signal 15 is provided on the column read signal line 127 to turn on the read select transistor 126, and the double sample amplifier 142 pairs the analog output line 108. The upper pixel circuit resets the voltage sampling. The double sampling amplifier 142 then calculates a difference between the pixel circuit turn-off voltage and the pixel circuit reset voltage to achieve the corrected pixel circuit output voltage. The corrected pixel circuit wheel 2 output voltage is supplied from the double sampling amplifier 142 to the ADC circuit 144, and the ADC circuit 144 converts the corrected pixel circuit output voltage into a digital position, and A digital signal is supplied to the digital image processor 1〇3. In the n-shirt-like sensor circuit 1 所有, all of the pixel circuits 112 in the one of the pixel arrays 1 & 1 accumulate charge-equal amount of time. Therefore, 12 200917827 image captures a high dynamic range for pattern recognition purposes, > thick a loss, the image sensor circuit 100 has the above discussed problem, because the light intensity in the real gamma The change may exceed the enthalpy of thunder 攸 110 , 冲 — cell 112 — dynamic range 5 15 20 . This specific problem may prevent an object or pattern from being recognized from the image captured by the image sensor. c SUMMARY OF THE INVENTION: SUMMARY OF THE INVENTION Various embodiments of the present invention allow for control over time during a capture operation, such as during a capture operation, such that within a pixel array during a money image manipulation operation The pixel circuit can be exposed for different amounts of time. In various embodiments, the exposure pattern of the pixel array is controlled based at least in part on signals from the pixel array, the signals representing charges accumulated in at least a portion of the pixel array. In some embodiments, the exposure of the pixel array is iteratively updated during the video recording operation based on the accumulated charge in the pixel array during the image capture operation. An image sensor circuit in accordance with an embodiment of the present invention includes a pixel array and/or a plurality of circuits. The pixel array contains a plurality of pixel circuits. The one or more circuits are configured to control the exposure information based on the plurality of signals from the pixel array and are configured to control the pixel array based on the exposure. In various embodiments, one or more circuits are configured to - when the image is being captured by the pixel array 'to the knife based on the one or more signals that are rotated from the pixel array and at least one expansion criterion Update the exposure information in an iterative manner. In this embodiment, the at least-expansion is specified by at least the _ structural element. 13 200917827 In various embodiments, the pixel circuits can be controlled such that at least a halogen circuit within the column of the pixel array can collect charge at one of the sensing nodes of the pixel circuit while At least the second pixel circuit is prevented from accumulating charge at the sensing node of the second pixel circuit during at least a portion of the image capturing operation. In some embodiments, the one or more lightning traces are configured to iteratively update the exposure information based at least in part on the value of the one or more signals that are rotated from the pixel array, wherein the one or more The equivalent of the signal represents the charge accumulated in at least a portion of the pixel array. In various embodiments, the one or more circuits are configured to individually control the exposure state of the f-circuits based on the exposure information to convert the exposure pattern of the pixel array. Moreover, in various embodiments, the exposure state of each pixel circuit in the pixel circuits includes an on state and a off state in which the pixel circuit is allowed to be in the pixel circuit One of the sensing nodes accumulates a charge, and in the off state, the pixel 15 is prevented from accumulating additional charges at the sensing node. In some embodiments, the image sensor circuit further includes one or more memory devices to store the exposure information as exposure pattern data, the exposure pattern data including an exposure to be used to control the pixel circuit At least _ bits of each of the pixel circuits in the state of the pixel circuits. In the embodiment of step 20, the one or more circuits are configured to reset the exposure pattern data stored in the one or more memory devices to an initial pattern prior to an image manipulation operation. In some embodiments, the one or more circuits are configured to change the exposure pattern of the pixel array a plurality of times based on the exposure information when the image is captured by the pixel array. 14 200917827 In various embodiments, the pixel charges comprise a salt-out-synchronization circuit 70-transistor and a second transistor.兮 The terminal connected to the photosensitive element. The second and second exposure-exposure control signal lines and the first crystal-gate 2 are in each embodiment 'the one or more circuits are configured to control the exposure control signal line based on the warm gamma a signal. In some embodiments, the = 少 - 昼 电路 circuit includes - the third transistor and - the fourth electric celestial body. The third transistor is connected to the photosensitive element. The fourth electric day is connected between the anti-dispersion control signal and one of the third transistors. The gas 10: or a plurality of circuits are combined to generate an anti-glow signal on the anti-glow (four) signal line based on the exposure information. In various embodiments, the one or more circuits are configured to control an anti-emitter signal on the anti-dispersion control signal line during an image manipulation operation as one of the exposure control signals on the exposure control signal line Value. Further, in various embodiments, the photosensitive element has a first portion extending below the exposure signal line and a second portion extending below the anti-dispersion control signal line. In some embodiments, the at least-halogen circuit further includes one or more virtual spreads that are coupled to a constant voltage during an image capture operation. In some embodiments, the at least one halogen circuit further comprises - resetting the transistor. The reset transistor is coupled between a fixed voltage and a sense node, wherein a voltage on the sense node controls an output signal. In various embodiments, the one or more circuits are configured to control a reset ##, the reset signal is applied to one of the reset transistors 15 200917827 such that the reset transistor is in an image The output signal during the fetch operation is held off during at least two readout periods and so that the u-edge of the output signal is at least twice read out with respect to the charge accumulated at the sense node being non-destructive. In various embodiments, the pixel array further includes a plurality of row readout lines to provide the one or more signals, and the one or more signals are combined to selectively control the row readouts The control signal on the line is a voltage signal or a current signal. In some embodiments, the one or more signals are analog current signals for at least a portion of the time during an image manipulation operation. In each of the implementations, the image sensor circuit further includes a row of digital-to-analog converter circuits that are configured to receive from the same row of the pixel circuit One of the pixel arrays of the two or more pixel circuits in the pixel circuits has an analog signal output on the line readout line, and is configured to convert the analog signals into corresponding digital signals. In each of the embodiments, the pixel circuits are arranged in a plurality of columns and a plurality of rows. In some embodiments, the one or more circuits are configured to selectively control the pixel array to provide output from two or more columns and two or more rows of pixel circuits at the same time The outputs from the two or more columns are combined in analogy 20 on the row readout line of the pixel array. In some embodiments, the image sensor circuit further includes a resistor grid. In various embodiments, the resistor grid includes a plurality of switchable resistors and a plurality of capacitors. In some embodiments, the capacitors are coupled to receive signals having 16 200917827 values based on the one or more signals output from the pixel array, and the switchable resistors are configured to select according to the command signals These capacitors are connected in a sexual manner. In various embodiments, after the switchable resistors have been controlled to connect the capacitors and have passed a period of time, the circuit or the circuit is assembled to be within 5 V of the capacitors. The voltage is sampled and, in various embodiments, the one or more circuits are configured to update the exposure information based on the voltage. In some embodiments, the pixel circuits are arranged in a plurality of columns and a plurality of rows, wherein each of the far columns further includes a threshold current generated in each of the real details, the one or more The circuit is configured to compare a voltage of a reference signal derived from an output of one of a particular threshold current generator in a particular one of the 10 columns to a voltage from the pixel circuit in the particular column One of the specific pixel circuits outputs a voltage of one of the derived signals and is configured to update the exposure information based on the result of the comparison. In some embodiments, the one or more circuits are configured to terminate an image capture operation within the pixel array based on a comparison between a threshold number and a number calculated from the U exposure information. Moreover, in some embodiments, the one or more circuit packs § a number ## processor. In various embodiments, the image sensor circuit further includes an infrared filter disposed on at least a portion of the at least one pixel circuit in the pixel circuits. In some embodiments, the image sensor circuit further includes a color filter disposed on at least a portion of the at least one pixel circuit of the pixel circuits. A method for an image sensor circuit in accordance with an embodiment of the present invention includes the steps of: (tapping information relating to an exposure pattern of an array of pixels of the image sensor circuit; and (b) At least in part based on 17 200917827 (1) stored H and (9) from the pixel signal, changing the exposure pattern of the pixel array. - or a plurality of 5 10 in accordance with the embodiment of the present invention - image The sensing method includes the following steps: (4) starting one of the image sensor circuits: aggregation of charges in each of the paths; (b) blocking one or more of the output from the pixel array The sum of the signal selections: the accumulation of charges in the at least one particular pixel circuit of the circuit, to partially block the pixel circuits adjacent to the special pixel circuit in the pixel array, based in part on the -expansion criterion In the at least one pixel circuit, a pixel circuit according to the present invention includes a photosensitive element: a first-electrode and a second transistor. In various embodiments, the photosensitive element includes a photodiode Body or similar. The first crystal Connected between the photosensitive element and the sensing node. The second transistor is connected between a 15 exposure control signal line and one of the first transistor, and the second transistor has a connection to the transmission An image processing system in accordance with an embodiment of the present invention includes an image sensor circuit and a processor. The image sensor circuit includes a pixel array and is configured to utilize a shutter The operation obtains an image, wherein an exposure pattern of the 20 pixel array is set according to exposure information, the exposure information being changed based at least in part on the accumulated charge in at least a portion of the pixel array as a function of %. Detecting one or more objects within the image. In various embodiments, the exposure information is further varied over time based on an expansion criterion indexed by a structural element. In various embodiments, 18 200917827 the image sense The detector circuit and the processor are all disposed on a single wafer. Various embodiments of the present invention allow control of a pixel array using feedback, such that the pixel array is Partially based on signals output from the pixel array, the signals represent charges accumulated in at least a portion of the pixel array 5 during an image capture operation. Moreover, various embodiments of the present invention allow for one The pixel circuit level controls one of the aggregation times such that the pixel circuits in the same column of the pixel array can each collect charge for different amounts of time during an image capture operation. In various embodiments In contrast to the aggregation time of the charge-distributing pixel circuit 10 for a darker region of a solid scene, a particular shutter operation allows for a shorter aggregation time for the pixel circuit that collects charge for the bright region of the solid scene. Accumulating charge. Accordingly, various embodiments of the present invention provide for controlling an amount of time that an individual pixel circuit is allowed to accumulate charge during an image capture operation, based at least in part on the accumulation of pixels by the pixel circuit during the image capture operation. Electricity 15 load. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 depicts a conventional image sensor circuit; Figure 2 depicts a conventional pixel circuit; Figure 3 depicts a conventional row analog-to-digital converter (ADC) Circuitry; 20 FIG. 4 depicts a conventional image sensor circuit; FIG. 5 depicts an image processing system in accordance with an embodiment of the present invention; FIG. 6 depicts an embodiment in accordance with an embodiment of the present invention Image sensor circuit; Figure 7 depicts a pixel circuit in accordance with an embodiment of the present invention; 19 200917827 Figure 8 depicts a critical current generator in accordance with an embodiment of the present invention; Figure 9 depicts A row of ADC circuits in accordance with an embodiment of the present invention; FIG. 10 depicts a reference signal to converter in accordance with an embodiment of the present invention; and FIG. 11 depicts an image sensing in accordance with an embodiment of the present invention Figure 12 depicts a row of ADC circuits in accordance with an embodiment of the present invention; Figure 13 depicts an image sensor 10 circuit in accordance with one embodiment of the present invention; Figure 14 depicts a circuit in accordance with the present invention a pixel of an embodiment One of the circuits; Figure 15 depicts a flow chart of a method for an image sensor circuit in accordance with an embodiment of the present invention; 15 Figure 16 depicts a method for use in accordance with an embodiment of the present invention A flowchart of one of the methods of the image sensor circuit; FIG. 17 depicts a flow chart of a method for an image sensor circuit in accordance with an embodiment of the present invention; FIG. 18A depicts a method in accordance with the present invention An expansion criterion specified by a structural element 20 of one embodiment; Figure 18B depicts an expansion criterion specified by a structural element in accordance with an embodiment of the present invention; Figure 18C depicts an in accordance with the present invention An expansion criterion specified by a structural element of an embodiment; 20 200917827 Figure 18D depicts an expansion criterion specified by a structural element in accordance with an embodiment of the present invention; Figure 19A depicts one of the aspects of the present invention An example of the content of an exposure pattern buffer of an embodiment; * 5 FIG. 19B depicts a pixel set according to the content of the exposure pattern buffer of the first embodiment according to an embodiment of the present invention. An example of an exposure pattern of a column; 〆 19 (: an example of the contents of an exposure pattern buffer in accordance with an embodiment of the present invention; 1 〇 19D depicts an embodiment in accordance with the present invention An example of the content of an exposure pattern buffer; FIG. 19E depicts an example of an exposure pattern of a pixel array set according to the content of the exposure pattern buffer of FIG. 19D according to an embodiment of the present invention; 15 Figure 19F depicts an exposure pattern (an example of the contents of a buffer; '19G depicting the contents of an exposure pattern_buffer according to an embodiment of the present invention. An example;

FIG. 19H depicts an example of an exposure pattern of a pixel array set according to the content of the exposure pattern buffer of the 19th G 2 sigma diagram according to an embodiment of the present invention; FIG. 191 depicts the basis An example of the contents of an exposure pattern buffer of an embodiment of the invention; FIG. 19J depicts an example of the contents of an exposure pattern 21 200917827 buffer in accordance with an embodiment of the present invention; An example of an exposure pattern of a pixel array set in accordance with the content of the exposure pattern buffer of FIG. 19J in one embodiment of the invention; FIG. 20 depicts an image sensor in accordance with an embodiment of the present invention. Circuitry; Figure 21 depicts an image sensor circuit in accordance with an embodiment of the present invention; and Figure 2 depicts a layout in accordance with an embodiment of the present invention. [Embodiment] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 5 depicts a block diagram of an image processing system 700 in accordance with an embodiment of the present invention. The image processing system 700 includes an image sensor circuit 200 and a processor 800. The image sensor circuit 200 includes a pixel 15 array 240 and one or more circuits 290. In various embodiments, the image sensor circuit 200 and the processor 800 are both disposed on a single wafer. In various embodiments, the image sensor circuit 200 allows for capturing images of a physical scene, and the processor 800 is configured to process images captured by the image sensor circuit 200. In some embodiments, the processor 800 is configured to receive data from an image sensor circuit 200 and is configured to process the data to detect one or more objects within the image. In various embodiments, the image processing system 700 can be used in machine vision or other automated pattern recognition applications. In some embodiments, the image processing system 700 can be used to obtain images for human viewing. 22 200917827 In some embodiments, the processor 800 can include circuitry for performing pattern matching to detect one or more objects, such as the US ππ Β patent application file numbered 6〇/991,545 (named The circuit disclosed in "Vision System on a Chip", filed on November 30, 2007, the entire contents of which is incorporated herein by reference. In some embodiments, the processor 800 is configured to search for an image representing one or more features of an object using one of the one or more features. Moreover, in some such embodiments, the processor 8 can be configured to perform a method of detecting an object by searching for features within an image, for example, including a US Provisional Patent Application Serial No. 60/991,545 The method of steps 802-810 in the flowchart of Figure 8 of the 10th. Figure 6 depicts an image sensor circuit 200 in accordance with an embodiment of the present invention. The image sensor circuit 2 includes the pixel array 240, a type of analog-to-digital converter (ADC) block 249, a pixel control signal generator 213, a control processor 212, a digital image processor 210, and An image memory 15 body buffer 211. In some embodiments, the image sensor circuit 200 further includes an exposure pattern buffer 295. The pixel array 240 includes a plurality of pixel circuits 250 arranged in columns and rows. For example, in various embodiments, the pixel array 240 can include pixel circuits 250 of "n" columns and "m" rows, where n and m are integer values. Each pixel circuit 250 includes a photosensitive element, such as a 20-diode or the like, to sample the light intensity of a corresponding portion of an imaged scene. In various embodiments, the pixel array 240 further includes a plurality of critical current generators 260 arranged in a row. Each of the critical current generators 260 can be associated with one of the pixel circuits 250 within the pixel array 240 and can be configured to provide a reference signal for the corresponding 23 200917827 column to be used for signal comparison. The pixel array 240 includes column control lines 223!, 2232, ..., 223n, which may each include a plurality of control lines (not shown in FIG. 6), and the pixel array 240 also includes a row read line 231. ,, 2312,...,231m. The pixel control 5 signal generator 213 is configured to provide control signals to the pixel circuits 25 in the pixel array 24 through the column control lines 223!, 2232, ..., 223n to control the The operation of the pixel circuit 250. In various embodiments, the pixel circuits 250 in the same column of the pixel array 240 (e.g., the third column of the pixel array 24) pass through a common 10 from the pixel control signal generator 213. Column control lines 223i share a common column control signal. Moreover, in various embodiments, the same row of one of the singular pixel arrays 240 (e.g., the pixel circuit 250 in the jth row of the pixel array 240) shares a common row readout line 231" to provide an output. . In various embodiments, the pixel array 240 further includes a reference signal line 232, each of which can provide an output through the reference signal 15 line 232. Analog signals output from the pixel array 240 through the row readout lines 23h, 2312, ..., 231m are input to the ADC block 249. In various embodiments, the ADC block 249 includes one or more row ADC circuits 220 for each of the pixel circuits 250 within the pixel array 240. In each of the 20 implementations, the row ADC circuits 220 are configured to convert the analog signals received from the pixel array 240 through the individual read lines of the row readout lines 231!, 2312, ..., 231m into A digital signal output on the corresponding digital output lines 246, 2462, ..., 246m. In various embodiments, the ADC block 249 further includes a reference signal converter 221 for receiving signals from the reference signal line 232 of the pixel array 240 at 24 200917827, and for A reference signal on a reference voltage line 243 is provided to each of the ADC blocks 249 of the ADC block 249. In various embodiments, the ADC block 249 includes one or more control lines 241 that provide control signals through the one or more control lines 241 to control the operation of the reference signal. Moreover, in various embodiments, the ADC block 249 includes one or more control lines 242 that provide control signals through the one or more control lines 242 to control the operation of the row ADC circuits 22A. In various embodiments, the control processor 212 is configured to control the operation of the ADC block 249 and is also configured to control the operation of the pixel control signal generator 213. In various embodiments, the control processor 212 provides control signals to the pixel control signal generation state 213 via one or more control lines 244. The digit signals outputted from the digital output lines 246, 2462, ..., 15 246m from the ADC block 249 are input to the digital image processor 210. The image sensing profit circuit 200 further includes pixel control signal lines 226ι, 2262, ..., 226m, and the pixel control signal lines 226], 2262, . . . , 22 cores each include a plurality of control lines (in Figure 6 _ not shown). The digital image processor 210 is configured to provide control signals to the pixel circuits 250 within the pixel array 240 via the pixel control signal lines 226i, 2262, ..., 20 226m. In various embodiments, the pixel circuits 250 located in the same row of one of the pixel arrays 240 (eg, the jth row of one of the pixel arrays 240) share a common pixel control signal line 226, the control signal The common pixel control signal line 226 is transmitted from the digital image processor 210. 25 200917827 In various embodiments, the digital image processor 2 communicates with the control processor 212 via one or more communication lines 245. Moreover, in various embodiments, the digital image processor 210 reads data from the image memory buffer 211 through a read/write bus 248 and writes the data into the image 5 memory buffer 21 In some embodiments, an individual write bus 247 allows data to be transferred from the digital image processor 2i to the image memory buffer 211. In various embodiments, the digital image processor 21A is configured to process digital signals received from the adc block 249 through the digital output lines 246i, 2462, Mb and one or more output lines 2丨9 The output is #1. In various embodiments, the image memory buffer 211 includes a k-machine access suffix (RAM) or the like to store and retrieve data. In some embodiments, the image sensor circuit 200 includes the exposure pattern buffer 295' and the digital image processor 21 can be fetched from the exposure pattern buffer and written to the exposure pattern buffer 295. In various embodiments, the exposure 15 pattern buffer 295 includes a RAM or the like. The various embodiments of the 3H image sensor circuit 200 allow for selection between (i) a current-to-analog mode in which the output lines 23^1, 2312, ..., 231m are output. The signal is an analog current signal; and (丨丨) a voltage _ analog mode in which the signal output on the read lines 231l, 23l2, . . . , 23^ on the line is an analog voltage signal. In various embodiments, the image sensor circuit 200 further includes a voltage source 23A, a plurality of bias sources 234ι, 2342, ..., 234, and a plurality of voltage source switches 217ι, 2172, . . . , 217m ( For example, an analog switch or the like. Moreover, in various embodiments, the 4-pixel array 240 further includes a plurality of voltage source lines 235ι, 2352, . . . , 26 200917827 235m. In various embodiments, located in the The pixel circuits 25 in the same row (for example, the jth row of one of the pixel arrays 240) share a common voltage source line 235 』, and the voltage source line 235 』 of the row is connected to the A corresponding voltage source switch 217j of the isoelectric waste source switches 217, 2172, ..., 217m. 5 In various embodiments, the control processor 212 is configured to control the voltage source switches 217^2171 Each of ..., 217m is switchably switchable between a terminal of one of the voltage sources 230 and a first terminal of one of the bias sources 234, 23, ..., 234m. In various embodiments, each of the bias sources 234ρ2342, ..., 234m The two terminals are connected to ground terminal 10 233. In various embodiments, the pixel array 240 further includes a voltage source line 238 coupled to each of the critical current generators 260. Moreover, in various embodiments, The image sensor circuit 200 further includes a bias source 281 and a switch 239 coupled to the voltage source line 238. In each of the embodiments, the control processor 212 is configured to control the switch 239 to Controllably switching between a first terminal of the bias source 281 and an open state. Also, in various embodiments, one of the bias terminals 281 is connected to the ground terminal 233. In the example, the pixel array 240 further includes a threshold voltage line 268 coupled to each of the critical power 20 stream generators 26. Moreover, in various embodiments, the image sensing The device 200 further includes a threshold voltage source 267 having a first terminal coupled to the threshold voltage line 268 and a second terminal coupled to the ground terminal. Referring to Figures 5 and 6, in various embodiments One or more Road 290 27 200917827 includes a digital image processor 21 〇. In some embodiments, the digital image processor 210 includes a programmable digital signal processor or the like. In some embodiments, the one or more Circuitry 290 further includes the pixel signal generator 213. In some embodiments, the one or more circuits 290 further include a control processor 212. In various embodiments, the one or more circuits The UI block 249 is further included. Moreover, in various embodiments, the one or more circuits 290 further include the bias sources 234, 2342, ..., 234, the voltage source switches 217l, 2172, ..., 217m, the bias Source 28i, the switch 239, and the threshold voltage source 267. The Figure 10 depicts a pixel circuit mo in accordance with an embodiment of the present invention. The pixel circuit 250 includes a photodetector or photosensitive element, such as a photodiode The pixel circuit 250 further includes a transmission gate transistor 202, a sensing node 2〇3 (eg, a floating diffusion node), a resetting transistor 204, a driving transistor 205, and a read. The selection transistor 206, a 15 anti-glow gate transistor 216, a first write selection transistor 214, and a second write selection transistor 215. In various embodiments, the transmission gate transistor 202, the Resetting the transistor 2〇4, the driving transistor 2〇5, the read selection transistor 206, the anti-glow gate transistor 216, the first write selection transistor 214, and the second write selection The crystals 215 can each comprise an n-channel 20 metal oxide semiconductor (NMOS) An effect transistor or the like. The sensing node 203 has a specific capacitance and is capable of storing some charge. An exemplary one of the column control lines 223, 2232, ..., 223n (see Fig. 6) is A row of control lines 223 is shown in Figure 7. In various embodiments, the column control line 223 includes a column of read signal lines 254, a transmission 28 200917827 signal line 253, and a reset signal line 252. In various embodiments, The pixel circuit 2 mixes the column readout packet 254, the transmission (four) line tap and the input signal on the reset signal line 252. The pixel control signal lines 226], 2262, ..., 226m (see An exemplary one of FIG. 6 is shown as a pixel control signal line 226 in FIG. 75. In various embodiments, the pixel control signal line 226 includes an exposure control signal line 255 and a Anti-dispersion control signal line 256. In various embodiments, the pixel circuit 25 receives the exposure control signal line 255 and the input signal on the anti-dispersion control signal line 256. The voltage source lines 235!, 2352 ,..., 235m (see Figure 6) One of the features is shown as a voltage source line 235 in Figure 7. In each of the real % examples, the s-pixel pixel circuit 250 receives an input voltage signal through the voltage source line 235. The row readout lines 231 An exemplary one of , , 23h, ..., 231m (see Figure 6) is shown in Figure 7 as a row of readout lines 231. In various embodiments, the pixel circuit 250 is read in the row. The output signal is provided on the outgoing line 231. As described in one embodiment of the pixel circuit 250 in Fig. 7, one of the photodiodes 201 is anode connected to the ground end 233, and the photodiode 2〇1 One of the cathodes is coupled to a first terminal of the transfer gate transistor 202 and a first terminal of the anti-glow gate transistor 216. a second terminal 20 of the transmission gate transistor 2〇2 is connected to the sensing node 203, and one of the gates of the transmission gate transistor 2〇2 is connected to one of the second write selection transistors 215. terminal. One of the first terminals of the resetting transistor 204 is connected to a voltage source 251, one of the second terminals of the resetting transistor 204 is connected to the sensing node 2〇3, and one gate of the resetting transistor 204 is Connected to the reset signal line 252. A first terminal of the 29 200917827 driving transistor 205 is connected to the voltage source line 235, and a second terminal of the driving transistor 205 is connected to a first terminal of the read selection transistor 206, and the driving A gate of the transistor 205 is connected to the sensing node 203. A second terminal of the read select transistor 206 is coupled to the row read 5 output line 231, and a gate of the read select transistor 206 is coupled to the column read signal line 254. A second terminal of the anti-diffusion gate transistor 216 is coupled to the voltage source 251, and a gate of the anti-glow gate transistor 216 is coupled to a first terminal of the first write select transistor 214. A second terminal of the first write selection transistor 214 10 is coupled to the anti-dispersion control signal line 256, and a gate of the first write selection transistor 214 is coupled to the transmission signal line 253. A second terminal of the second write selection transistor 215 is connected to the exposure control signal line 255, and a gate of the second write selection transistor 215 is connected to the transmission signal line 253. Figure 8 depicts a critical current generator 260 in accordance with an embodiment of the present invention. The critical current generator 260 includes a current control transistor 265 and a selection transistor 266. In various embodiments, the current control transistor 265 and the select transistor 266 each comprise an NMOS field effect transistor or the like. An exemplary one of the column control lines 223i, 2232, ..., 223n (see FIG. 6) 20 of the read signal lines 254 is shown in FIG. 8 as being coupled to the critical current generator 260. . One of the first terminals of the current control transistor 265 is coupled to the voltage source line 238 as described in one embodiment of the threshold current generator 260 of FIG. A gate of the current control transistor 265 is coupled to the threshold voltage line 268, and a second terminal of the current control transistor 265 30 200917827 is coupled to a first terminal of the selection transistor 266. A gate of the select transistor 266 is coupled to the column read signal line 254, and a second terminal of the select transistor 266 is coupled to the reference signal line 232. Figure 9 depicts the row a DC circuit 5220 in accordance with an embodiment of the present invention. The row ADC circuit 220 includes an output mode switch 227, a dual sampling amplifier 207, a source transistor 208, an ADC circuit 209, a current to voltage converter 222, a difference comparator 225, and a digital multiplexer 228. . An exemplary one of the line readout lines 231!, 2312, ..., 231m (see the figure) is shown as a line readout line 231 in Fig. 9. An exemplary one of the digital output lines 10 246!, 2462, ..., 246m (see Figure 6) is shown in Figure 9 as a digital output line 246. One or more control lines 242 from the control processor 212 (see Figure 6) are input to the row of ADC circuits 220. In various embodiments, the control processor 212 (see FIG. 6) is configured to provide control signals at the one or more control lines 242 to control the output 15 mode switch 227, the dual sampling amplifier 207, the source The transistor 208, the current to voltage converter 222, the ADC circuit 209, the difference comparator 225, and the digital multiplexer 228 operate. In various embodiments, the one or more control lines 242 include a select signal line 274 to provide a select signal from the control processor 212 (see FIG. 6) to the digital multiplexer 228. 20 The output mode switch 227 can be controlled to connect the row sense line 231 to one of the current-to-voltage converters 222 as described in one embodiment of the row of ADC circuits 220 in FIG. Or connected to one of the input terminals of the double sampling amplifier 207 and the first terminal of the source transistor 208. In various embodiments, the output mode switch 227 can be controlled by the control process 31 200917827 212 (see Figure 6) by a control signal provided through the one or more control lines 242. In various embodiments, the current to voltage converter 222 is configured to receive an analog current signal, convert the analog current signal to a voltage signal, and output the voltage signal. The output of the current to voltage converter 222 is coupled to a first input of the difference comparator 225. A second input of the difference comparator 225 is coupled to the reference voltage line 243 to receive a reference voltage signal from the reference signal converter 221 (see Figure 6). In various embodiments, the difference comparator 225 is configured to amplify a difference between a voltage signal output from the current to voltage converter 222 and a reference voltage signal received on the reference voltage line 243. And generating a digital output based on the difference. In various embodiments, the output of the difference comparator 225 is provided to a first input of the digital multiplexer 228. In various embodiments, the first terminal of the source transistor 208 is coupled to the input of the double sampling amplifier 207. Moreover, in various embodiments, one of the source 15 transistors 208 has a second terminal connected to ground terminal 233 and one of the source transistors 208 is coupled to a voltage supply source 273. In various embodiments, the double sampling amplifier 207 is configured to sample a pixel output voltage on the row sense line 2 31 and also to a reset voltage on the row sense line 231 at a different time. Sampling, and calculating a difference between the pixel output voltage and 20 of the reset voltage to obtain a corrected pixel output voltage. In various embodiments, the ADC circuit 209 is coupled to an output of the dual sampling amplifier 207 to receive the corrected pixel output voltage from the double sampling amplifier 207. In various embodiments, the ADC circuit 209 is configured to digitize the corrected pixel output voltage and provide the digitally corrected pixel output power 32 200917827 to one of the digital multiplexers 228 The second input. In various embodiments, the digital multiplexer 228 is configured to provide an output of the difference comparator 225 or the ADC circuit 209 on the digital output line 246 based on a control signal provided on the select signal line 274. The output. 5 The figure depicts a reference signal converter 221 in accordance with an embodiment of the present invention. In various embodiments, the reference signal converter 221 includes a switch 28, a current to voltage converter 224, and a voltage driver 229. In various embodiments, the switch 281 is controllable to connect or disconnect the reference signal line 232 to one of the current to voltage converters 224. In the various embodiments, the switch 281 is controlled by a control signal provided on one or more control lines 241 from the control processor 212 (see Figure 6). In various embodiments, the current to voltage converter 224 is configured to convert a reference analog current signal provided on the reference signal line 232 to a corresponding voltage signal and output the corresponding voltage signal. The voltage signal output from the current to voltage converter 224 is supplied to one of the first inputs of the voltage driver 229 in each of the 15 examples. In various embodiments, one of the voltage drivers 229 outputs a feedback that is provided as a second input to the voltage driver 229, and the voltage driver 229 is configured to drive a reference voltage signal on the reference voltage line 243, The reference voltage signal is at least partially 20 based on the output of the current to voltage converter 224. 11 is a diagram showing the image sensor circuit 200 of FIG. 6 in which the pixel circuit 25 of FIG. 7, the threshold current generator 260 of FIG. 8, and the line of FIG. 9 are performed according to an embodiment of the present invention. The ADC circuit 220 and the reference signal generator 221 of Fig. 10 are described. An exemplary one of the voltage source switches 217!, 2172, ..., 33 200917827 217m (see Fig. 6) is shown as a voltage source switch 217 in Fig. u. An exemplary one of the bias sources 234, 2342, ..., 234m (see Figure 6) is shown as a bias source 234 in the second diagram. In various embodiments, the image sensor circuit 2 can be controlled to operate in a voltage/analog mode or a current-to-analog mode. In various embodiments, the control processor 212 is configured to set a voltage-to-analog ratio of the output from the pixel circuit 250 by controlling the voltage source switch 217, the s-ary output mode switch 227, and the digital multiplexer 228. Mode or current_ analog mode. In order to set the voltage-to-analog mode, in various embodiments, the control 10 processor 212 controls (1) the voltage source switch 217 such that the first terminal of the drive transistor 205 is coupled to the voltage source 230 through the switch 217; The output mode switch 227 is such that a second terminal of the read select transistor 2〇6 is coupled to a first terminal of the source transistor 208 and an input of the double sampling amplifier 2〇7; and (iii) the digit The multiplexer 228 causes the digital multiplexer 228 15 to provide the output of the ADC circuit 209 as an output. In the embodiment of the voltage-to-analog mode, the pixel circuit 250 can provide a voltage signal to the row of ADC circuits 220, which are sampled by the double sampling amplifier 207. In order to set the current-to-analog mode, in various embodiments, the control processor 212 controls (1) the voltage source switch 217 such that the first terminal of the drive transistor 205 20 is coupled to the bias source 234 through the switch 217; Ii) the output mode switch 227 is such that the second terminal of the read select transistor 206 is coupled to the input of the current to voltage converter 222; (iii) the switch 239 causes the first terminal of the current control transistor 265 to pass through The switch 239 is coupled to the bias source 281; and (iv) the digital multiplexer 228 causes the digital multiplexer 228 to provide 34 200917827 the output of the difference comparator 225 as an output. In an embodiment of the current-to-analog mode, the pixel circuit 250 can provide one or more current signals to the row of ADC circuits 220. The one or more current signals are converted to a voltage by the current-to-voltage conversion to 222. Corresponding one or more voltages. 5 Operation of an image sensor circuit 2 in accordance with an embodiment of the present invention is now described with reference to Figures 6, 7, 8, 9, 10 and 11. After an image capturing operation, the photodiode 201 and the sensing node 2〇3 provide a two high signal on the reset signal line 2 by causing the pixel control signal generator 213 to be in the transmission. The signal line 253 provides a number and 10 is reset by causing the digital image processor 210 to provide a HIGH signal on the exposure control signal line condition and provide a l〇w signal on the anti-dispersion control signal line 256. . The combination of this-signal causes both the reset transistor 2 〇 4 and the transfer gate transistor 202 to be turned on, and the anti-dispersion control signal line 216 is turned off. In each of the embodiments, the anti-glow gate transistor 216 and the transfer gate transistor 202 each have an individual parasitic capacitance such that the anti-glow gate transistor 216 and the transfer gate transistor 2 are written. The values of the individual gates of 〇2 can be continued (for example) until they are rewritten to new values. Moreover, the anti-diffusion idler transistor 216 and the gate of the transfer gate transistor 2〇2 can be isolated by the first write select transistor 214 and the second write select transistor 215, respectively. Therefore, once the value has been supplied to the first write select transistor 214 and the individual second terminal of the second write select transistor 215 for the reset operation, the HIGH signal has been provided on the transfer signal line 253. Above, the signal on the transmission semaphore line 253 can be changed to L 〇 w, and due to the parasitic capacitance, the 35 200917827 anti-Glory gate transistor 216 and the transmission gate transistor 2 〇 2 will be the value of the dimension (for example) until The new value is written. In each of the embodiments, when an image capturing operation is initialized, a LOW signal is provided on the button (252) line 252, and the 5 transistor 204' is reset. Miscellaneous to allow charge generated in the photo-pole to accumulate within the sensing node 2 G 3 . The charge from the photodiode 201 is concentrated in the sensing node 2〇3 during this state. Once the charge begins to accumulate in the sensing node 2〇3, an analog current readout can be set by setting the voltage source switch 10 217 according to the current-analog mode setting, the output mode switch 2 27, the switch 2 3 9 and the digital multiplexer 228, and then the pixel control signal generator 213 is provided with an HIGi^f number on the column read signal line 254 to turn on the read select transistor 2〇6 to be executed. . The control signal generator 213 can provide an L〇w signal on the column read signal line 254 after the analog current readout has been performed. 15 when the high signal is provided on the column read signal line 254 to turn on the read select transistor 206 in a current-to-analog mode, a current proportional to a voltage level of one of the sense nodes 203 Generated in the row readout line 231. The current to voltage converter 222 converts the current on the row sense line 231 to a pixel output voltage. A threshold voltage supplied by the reference current source 267 is generated within the threshold current generator 260. The current-to-voltage converter 224 converts the reference current into a reference voltage that is driven by the voltage driver 229 on the reference voltage line 243. The difference comparator 225 amplifies a difference between the pixel output voltage and the reference voltage to provide a digital output. The digital image processor 21 transmits the multiplex 36 200917827 Μ

10 15

The 228 reads the digital output of the difference comparator 225. ▲ Reading current from the row read line 2 3 i is non-destructive on the pixel circuit 2 5 , so that after the current is read on the row read line 231, the accumulated money is accumulated in the sense. The charge remains at the sensing node 203. Thus, in various embodiments, the read current from the pixel circuit 250 can be asserted multiple times during the image capture operation without being accumulated in the sense node 2〇3 during the image capture operation. The charge. One or more additional analog current readouts 2 may be set by the current/analog mode setting during the shadow capture operation, the output mode switch milk, the switch 239, and the digital multiplexer 228 And then the pixel control signal generator 213 is supplied with the -HIG number on the column read signal line 254 to turn on the read selection transistor 206. The control signal generator 213 can provide a l〇w signal on the chirp read signal line 254 after the analog current sense has been performed. Thus, the charge accumulated in the sensing node 2〇3 can be monitored during the image capturing operation by performing a plurality of analog current readings at different times during the image capturing operation, wherein each analogy The current reading is non-destructive with respect to the charge accumulated within the 4 sense node 203. In various embodiments, accumulating charge at the sense node 2〇3 may be stopped during the image capture operation while maintaining a charge of 20 accumulated in the sense node 203. In order to stop the charge from accumulating at the sensing node 2〇3, the digital image processor 210 can provide a -L〇W signal on the exposure control signal line 255 and a mGH signal on the anti-dispersion control signal line 256. And the pixel control signal generator 213 can provide a -mGH signal on the transmission signal line 253. A combination of this signal causes the transmission gate transistor 2〇2 to be turned off, and the 37 200917827 anti-gate gate transistor 216 is turned "on". Since the anti-glow gate transistor 216 and the transfer gate transistor 2〇2 have some parasitic gate capacitances that allow the transistors to store values, the pixel control signal generator 213 can then provide - L on the transmission line 253. 〇 w signal, and the anti-diffusion gate transistor 216 is 5 and. The relay gate transistors 2〇2 will maintain their values until a new value is written. When the Tianhui anti-diffusion gate transistor 216 is turned on, the photodiode 201 is depleted. A type of voltage readout can be set according to the voltage-to-analog mode setting, the output mode switch 227, and the digital multiplexer 228, and then the pixel control signal generator 213 is in the column. Reading a 10 仏 line 254 provides a HIGH signal to turn the read select transistor 206 on. When the number is supplied on the column read signal line 254 to turn on the read select transistor 20 6 and read in the voltage-to-analog mode, a pixel pull-out voltage is at the source transistor 2〇8. The first terminal is provided on the row readout line 231, and the pixel output voltage is proportional to the voltage level of one of the sense nodes 2〇3. The dual sampling amplifier 207 samples the pixel output voltage at a first terminal of the source transistor 208 during a voltage read from the pixel circuit 250. The control signal generator 213 can provide a LOW signal on the column read signal line 254 after the analog voltage readout has been performed. When the sensing node 203 is in a reset state, the double sampling amplifier 2〇72 2 also samples a reset voltage at the first terminal of the source transistor 208. The dual sampling amplifier 207 calculates a difference between the pixel output voltage and the reset voltage to achieve a corrected pixel output voltage that is digitized by the ADC circuit 209. For the analog voltage reading, the digital image processor 210 reads the digital output of the ADc circuit 38 200917827 209 through the multiplexer. By providing the digital image processor 21 to provide an Η Η signal on the exposure control line 255 and providing a LOW signal on the anti-dispersion control signal line 256 and by controlling the ellipses The signal generator 213 provides a HIGH signal on the transmission signal line 253 and a HIGH signal on the reset signal line 252. The pixel circuit 25A can be reset to set the sensing node 203 to Reset the status. A combination of this signal causes both the reset transistor 204 and the transfer gate transistor 2〇2 to be turned on and the anti-glow gate transistor 216 to be turned off. When the sensing node 2〇3 is in the reset state and the signal is provided by the pixel control signal generator 213 on the column read signal line 254 to turn on the read selection transistor, A reset voltage proportional to the voltage level of one of the sensing nodes is provided at the first, the winter of the source. The double sampling amplifier 207 can sample the reset voltage at the first terminal of the source transistor 208 to be used for reading from a voltage analog of the halogen battery 150. One of the advantages of reading is that each read type has a desired quality. The analog current readout can provide high speed readout from the pixel array because the row read line 231 is @电谷 (for large The pixel array may be present) not | blocking analog to allow analog current readout and analog voltage from the pixel circuit 250. The analog voltage readout may be provided from the pixel array

Current output develops rapidly. The low noise signal readout current readout of column 240 can be used to obtain values quickly, Another advantage of analog current sensing is that it allows multiple columns of the pixel circuit 250 within the pixel array 240 to be simultaneously selected to produce an output current for each of the pixel arrays 24, The round current is positively proportional to the sum of the output currents of the pixel circuits 250 of the selected columns of the halogen array 240. This multi-column readout allows spatial averaging or smoothing of an output image in a vertical direction. In some image manipulation methods, This partial image averaging may be advantageous for filtering certain noises (e.g., noise typically generated by pixel circuit defects and fixed pattern noise caused by differences between the driving transistors of different pixel circuits). Because when an image is sampled column by column,  The 10 partial images provide low pass filtering and anti-aliasing filtering in one of the vertical directions of the image.  Figure 12 depicts another embodiment of a row ADC circuit 220 in accordance with an embodiment of the present invention. Elements of the embodiment of the ADC circuit 220 of the same row as the embodiment of the embodiment of the ADC circuit 220 of Fig. 9 are labeled with the same reference numerals. The embodiment of the ADC circuit 220 of the row of Fig. 12 differs from the embodiment of the ADC circuit 220 of the row of Fig. 9, Because the current to voltage converter 222 and the difference comparator 225 are replaced by a current comparator 222b. The current comparator 222b is configured to detect whether a current input to the current comparator 222b is positive or negative, A 20 binary output representing one of the results of the test is provided. In the case where the switch 227 is controlled to connect the row sense line 231 to the input of the current comparator 222b, The input of the current comparator 222b is coupled to the row readout line 231. The output of the current comparator 222b is provided to a first input of the multiplexer 228.  FIG. 13 illustrates another embodiment of an image sensor circuit 40 according to an embodiment of the present invention. The embodiment of the image sensor circuit 2 is different from the image of FIG. An embodiment of the sensor circuit 2, Because the embodiment of image sensor circuit 200 of Figure 13 includes an embodiment of row ADC circuit 220 of Figure 12, Rather than the embodiment of ADC row circuit 220 of Figure 9.  5 and, The embodiment of the image sensor circuit 200 of Fig. 13 does not include the reference signal converter 221 (see Fig. 6). Other than that, The embodiment of image sensor circuit 200 of Figure 3 further includes a current source for each row of the pixel circuit, An exemplary one of them is shown as current source 218, And further including a current source switch for each row of the pixel circuit, One of the exemplary ones of which is shown as current source switch 283. Other elements of the embodiment of the image sensor circuit 200 of Fig. 13 which are identical to the elements of the embodiment of the image sensor circuit 200 of Fig. 11 are designated by the same reference numerals.  In the embodiment of the image sensor circuit 200 of FIG. 13, Each current source (e.g., current source 218) for each row of the pixel circuit is coupled to the reference 15 signal line 232. The current source 218 provides a bias current, When the critical current generator 260 is activated with a bias voltage from the threshold voltage source 267,  The bias current is set by mapping a current generated by the critical current generator 260. In various embodiments, The current source switch 283 can be controlled by the control processor 212 to be in an open state or to connect the current source 218 to the row readout line 231. In a voltage-to-analog mode of an embodiment of the image sensor circuit 200 of Figure 13, The control processor 212 controls the current source switch 283 to be in an open state.  In the current-analog mode of the embodiment of the image sensor circuit 200 of Figure 13, The control processor 212 controls the current source switch 283 to connect the electrical source 41 200917827 μ source 218 to the row readout line 23i. In this state, When a current is generated by the pixel circuit 250, The input terminal @ ― reaching the current comparator 22 等于 is equal to the current generated by the pixel circuit 25G minus the bias current generated by the current source 218. The current comparator 222b determines whether the current arriving 5 疋 is positive or ’' and for the current analog pattern of the shots,  The binary information is provided based on the output of the digital multiplexer 228. In each case, The one or more circuits 29 (see Figure 5) further comprise . Each row of current sources (e.g., current source 218) and current source switches (e.g., current source switch 283) of the pixel circuit of the Hierarchy array 240.  . Figure 14 depicts an exemplary layout of a pixel % road 250 of Figure 7 in accordance with an embodiment of the present invention. The elements in the exemplary layout of the pixel circuit 25A of Fig. 14 which are the same as those in the pixel circuit of Fig. 7 are designated by the same reference numerals. In various embodiments, The transmission transistor 1 202 and the anti-glow gate transistor 216 can be disposed on opposite sides of the photodiode 201. In some embodiments, The transmission transistor 2〇2 The sense point 203, Reset the transistor 2〇4, The driving transistor (10), The read selects the transistor 206, The first write select transistor 214 and the second write select transistor 215 are each disposed on the same side of the photodiode 2 ()1.  Figure 15 depicts a flow diagram 20 of a method in accordance with an embodiment of the present invention. The method of Fig. 15 will be explained with reference to the image sensor circuit 2A of Fig. 6 and the pixel circuit 250 of Fig. 7. and, An exemplary operation of one of the methods in accordance with an embodiment of the present invention is provided in the 19th-19th. The example provided in Figures 19A-19K is an embodiment in which the pixel array 24 has 7 columns and 8 rows of pixel circuits. It should be understood that The pixel array 24 is a 42 200917827 embodiment which is merely provided as an example. And in various other embodiments, The pixel array 240 can have more or fewer columns and more or fewer rows of pixel circuits. For example, some embodiments of the pixel array 24 can include more than 7 columns and more than 8 rows of pixel circuits.  5 Some of the steps in Figure 15 relate to an exposure pattern buffer. In various embodiments, A portion of the image memory buffer 211 is used as the exposure pattern buffer. In various other embodiments, the image sensor circuit 200 can include an exposure pattern buffer 295 as a memory. It is separated from the image memory buffer 211. In the example of Figure 19A-19K, Some of the drawings of this example describe exemplary aspects of one embodiment of the exposure pattern buffer 295. It should be understood that The size of the embodiment of the exposure pattern buffer 295 in this example is merely provided as an example. And in various other embodiments, The exposure pattern buffer 295 has a larger or smaller capacity than that described in this example.  15 In the method of Figure 15, In S301, The exposure pattern buffer 295 is emptied by the digital image processor 210. The pixel array 240 is reset by the pixel control signal generator 213 and the digital image processor 21. In various embodiments, The exposure pattern buffer 295 stores exposure information. For example, exposure pattern data for one or more of the bits 20 of each pixel circuit 250 within the pixel array 240 is included. and, In various embodiments, The exposure pattern buffer 295 is emptied by setting each of the stored bits in the exposure pattern buffer 295 to an initial state. Figure 19A depicts an exemplary content of the exposure pattern buffer 295 in accordance with an embodiment of the present invention after the exposure pattern buffer 295 has been emptied. In the example of 43A, 200917827, Figure 19A, The exposure pattern buffer 295 includes one bit of each of the pixel circuits in one embodiment of the pixel array 24 (see FIG. 19B). And the exposure pattern buffer 295 in this example sets all bits to a ‘‘〇, ,  Value is emptied, The memory is zeroed.  5 In various embodiments of the image sensor circuit 200, The pixel array 240 is caused by the pixel control signal generator 213 on the column control lines 2231 2232, ..., a reset signal line 252 and a transfer signal line 253 for each of the 223n are provided with a HIGH signal and by causing the digital image processor 210 to be on the pixel control signal line 2261, 2262,  , A HIGH signal is provided on the 10 exposure control signal line 255 of each of 226m and a LOW signal is provided on the anti-radiation control ## line 256 to be reset. Using this combination of signals, The resetting transistor 204 of the halogen circuit 250 and the transmission gate transistor 202 are turned on. At the same time, the anti-glow gate transistor 216 of each of the pixel circuits 25A is turned off. Once the anti-glow gate transistors 216 and 15 receive the supplied signals on their respective gates, The parasitic capacitances on their respective gates are charged or discharged (depending on the value being written), When the _ write flex transistor 214 and the second write select transistor 215 of each of the pixel circuits are turned off by a LOW signal on the corresponding transfer signal line 253, The state of the anti-glow gate transistor 20 and the transmission gate transistor 202 can be maintained. Actually, , It is stated that only two bits written to the digital memory maintain the state of the anti-glow gate transistor and the transfer gate transistor 202. The method then proceeds to the illusion 2 in S302, an image capture operation is initialized, The image pusher is initialized within the pixel array 240. In various embodiments,  4' straw Yujun 44 200917827 The pixel control signal generator 213 is in the column control line 223, , 2232,  A LOW signal is provided on each of the reset signal lines 252 of 223n to turn off the reset transistor 204 of each of the pixel circuits 250 such as S The image capture is initialized within the pixel array 240. In various embodiments, The photodiode 201 of each of the NMOS circuits 250 is controlled to a voltage, Resulting that whenever the transfer gate 202 of the pixel circuit 250 is turned on, The charge from the photodiode 2〇丨 of the halogen circuit 250 spontaneously migrates to the sensing node 2〇3. In each of the embodiments of the «Hidan Suanzao Road 25, When the reset transistor is turned on, The resetting transistor 204 is configured to maintain the sensing node 2〇3 at a voltage level of 1 〇 and 疋, Thereby substantially preventing charge from accumulating within the sensing node 203, But when the reset transistor 2 〇 4 is turned off and the transfer gate transistor 202 is turned on, The charge will accumulate within the sensing node 203 at a rate proportional to the amount of light energy incident on the photodiode 2'''''''  Figure 19B depicts an example of an exposure pattern of one embodiment of the pixel array 24〇, The image capture has been initialized. For illustrative purposes,  The pixel circuits of the pixel array 240 in the example of Fig. 19b, which is enabled to accumulate #charges in their sensing nodes, are shown as white squares. In the 19th figure, 'because the image capture has been initialized, Therefore, all the pixel circuits in the pixel array 24 are displayed as white squares. Because all of the pixel circuits within the pixel array 240 of the embodiment of Figure 19B are enabled to accumulate charge at their sensing nodes at the beginning of an image capture operation. Once the image manipulation has been initialized in the pixel array 240, Then the method continues to S3〇3.  In S303, A binary image is read from the pixel array 24〇. In each implementation, The reading from the pixel array in S303 is performed in the current class 45 200917827 ratio mode to make the row readout lines 231ι, 23l2,  , The signal output from the pixel array 240 at 231 m is a current signal. In the case of an embodiment using the image sensor circuit 200 of Fig. u, a voltage source switch 217 for each row of the pixel circuit 25A, The output mode switch 227 and the digital multiplexer 5 228 and the switch 239 are set in accordance with the current_analog mode discussed above. In the case where the embodiment of the image sensor circuit 2 of Fig. 13 is used, The current source switch 283 of each row of the pixel circuit 250 is further set in accordance with the current analog mode discussed above.  In various embodiments, in the current-analog mode, Each of the halogen batteries 10 is sampled, And their current_ analog output levels (representing the number of photons absorbed by their photodiodes 2〇1 from the end of the reset) are compared to a reference level to produce a binary of the currently captured image. Represented and stored in the pixel circuits 250 of the pixel array 240. In various embodiments, The resetting transistor 204 15 of each of the pixel circuits 250 remains off during the pixel circuit readout in the phantom 03. Thereby, the pixel circuit readout process is non-destructive with respect to the charge accumulated in the sensing node 203 of each pixel circuit 250.  The readout process in 'S303' in various embodiments is performed on a column by column basis. For example, 'in various embodiments, One column of the pixel circuits 2〇 250 in the pixel array 240 is read out, Then another column of pixel circuits 250 within the pixel array 240 is read and so on until all columns have been read. E.g, When each column needs to be read, By providing the halogen control signal generator with a HIGH signal on the column read signal line 254 of the column of control lines 223 of the column, And then after the column has been read, a L〇w signal is provided on line k 254 of the read control line 223 of the column of the control signal line 223. Each column can be read. In the case of some real details, Readout may be performed by sampling the columns and/or selecting more than one column of the pixel array 240 at a time. The row continuation line 231 of any given row 5 of the pixel array 240 provides the selected pixel circuits 250 in a row in a current-analog mode at a same time in a row. Take out ~ and to & For the output of the side line. This technique can be used, for example, to implement a vertical image smoothing operation. Completely within the analog domain of one of the image sensor circuits 200, And such a wave has the general benefits associated with reduced spatial noise, Some of these specific uses include anti-aliasing and mitigating the effects of pixel circuit fabrication. Once the ternary image has been read from the pixel array, The method continues to S3〇4.  In S304, The binary image data obtained in S303 is processed. For example, the binary image data can be spatially filtered to eliminate noise. Some methods for filtering the gamma image include median filtering or morphologically closing 15 to eliminate too small a feature that is considered important for the method of Figure 15. In the case where the smoothing in the vertical direction has been applied as part of the current analog reading process of S303, The processing in S3〇4 in the various embodiments can be simplified by limiting the processing of the binary image data in a horizontal direction. In some embodiments of the method of Figure 15, This step S304 is optional and can be completely skipped. In some embodiments, Following the noise filtering described above in S304, This step of illusion 4 may also include the expansion of the shirt image produced by a structural element, Thereby accelerating an exposure control signal pattern in the image by the binary shirt > , Propagation near the initial point provided by the material. In various embodiments, The processing in s3〇4 is performed by the digital image processor 21〇. The process then proceeds to 47 200917827 S305.  In S305, In the case where this step S304 has been performed, The filtered binary image data from S304 is combined with the exposure pattern data stored in the exposure pattern buffer 295. In the case 5 which has been skipped in this step S304, The binary image data from S303 is combined with the exposure pattern data stored in the exposure pattern buffer 295. In various embodiments, Performing a logical "OR" of, for example, one of the filtered binary image data and the exposure pattern data stored in the exposure pattern buffer 295, And then storing the result back to the exposure pattern buffer 295, The digital image processor 10 21 combines the filtered binary image data with the exposure pattern data stored in the exposure pattern buffer 295.  Figure 19C depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 of Figure 19A has been updated by combining with the exemplary filtered binary image data. In the example 5, In addition to having a "spot" output corresponding to one of the pixel circuits in column 5 and row 3 of the pixel array 240, The filtered binary image data is the same as the exposure pattern data in the exposure pattern buffer 295 of Fig. 19A. Therefore, after the exposure pattern data of Fig. 19A and the filtered binary image data are logically ORed, The exposure pattern buffer 295 generated in Fig. 19C has a "1" bit for column 5 and row 3. The "1" rice element corresponding to the pixel circuit in column 5 and row 3 of the pixel array 240 in the example of Fig. 19C can indicate, for example, when the current signal is read out in S303, An output current signal from the pixel circuit exceeds a threshold. In this example,  The pixel circuits of columns 5 and 3 can sample light from a portion of one of the scenes being imaged 48 200917827, Causing that the charge accumulated in one of the sensing nodes of the pixel circuit may have exceeded a certain value, The accumulated charge in other halogen circuits may not have reached this value.  In various embodiments, Once the exposure pattern buffer 295 has been updated in S305 5, The method then continues to S306. In S306, The contents of the exposure pattern buffer 295 are updated to provide expansion in accordance with an expansion criterion. In various embodiments, The expansion criterion is specified by one or more structural elements. A structural component can specify, for example, how to expand the content of the exposure pattern buffer 295. In some embodiments, A structural component can specify how to extend a logic value "1" within the 10 exposure buffer 295 by some unit in one or more directions within the exposure pattern buffer 295. Various examples of the expansion criteria specified by the structural elements in accordance with embodiments of the present invention are described in Figures 18A-18D. It should be understood that Exemplary structural elements provided in Figures 18A-18D are merely examples. And any desired structural element can be used in the method of Figure 15.  Figure 18A depicts an example of an expansion criterion specified by a structural element in accordance with an embodiment of the present invention. In Figure 18A, The black square indicates that an item in an exposure pattern buffer has a logical value of "1". An item having a logical value of "1" is associated with a particular pixel circuit 20 within a pixel array. A square having an "X" indicates that an item in the exposure pattern buffer associated with a pixel circuit in the pixel array immediately to the right of the particular pixel circuit also needs to be set to a logical value of "1". therefore, If the expansion criteria specified by the structural elements of Figure 18A are used for expansion, Then each logical value "1" in the exposure pattern buffer will be expanded to an item on the right.  49 200917827 Figure 18B depicts an example of an expansion criterion specified by a structural element, A logical value of "1" in one of the exposure pattern buffers expands two items above the item having a logical value of "1". Make the two items above the item set to the logical value of "1". Figure 18C depicts an example of an expansion criterion specified by a structure 5 component. Two adjacent items having a logical value of "1" in an exposure pattern buffer associated with two adjacent pixel circuits of a pixel array are each expanded by an item above the item. In this example, A single item with a logical value of "1" (with no adjacent items with a logical value of "1") will not be extended to other items. Figure 10 18D depicts an example of an expansion criterion specified by a structural element, A logical value of a "1" in one of the items of the exposure pattern buffer needs to be expanded by one item in all directions within the exposure pattern buffer.  Figure 19D depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 of Figure 19C has been expanded 15 according to the exemplary expansion criteria specified by the structural elements of Figure 18D. In the example of Figure 19D, The logic values of "1" in column 5 and row 3 of the exposure pattern buffer 295 are expanded in all directions according to the expansion criterion of Fig. 18D. All items surrounding the items of column 5 and line 3 are set to have a logical value of "1". therefore, In various embodiments, Step S306 allows the exposure pattern data in the exposure pattern buffer 295 to be enlarged in form. Thus, the feature adds some pixel units in one or more directions within the exposure pattern buffer 295. The rate at which the exposure pattern data is propagated relative to the read rate of one of the pixel arrays can be controlled by modifying the size and shape of one or more structural elements defining an expanded pattern. Once the content of the exposure pattern buffer 295 50 200917827 has been updated by expansion using one or more structural elements, Then the method of Fig. 15 continues to S307.  See section 6, Figures 7 and 15, In step S307, The updated exposure pattern data from the exposure pattern buffer 295 is written to the pixel array 240 5 to change the exposure pattern of the pixel array 240. In various embodiments, The exposure pattern of the pixel array 240 is defined, The pixel circuits 250 within the pixel array 24 are enabled to accumulate additional charges within their respective sensing nodes, And the pixel circuits 250 within the pixel array 240 are being blocked or stopped accumulating additional charges within their respective sensing nodes. In each of the 10 implementations, By writing the exposure pattern data from the exposure pattern buffer 295 to the pixel array 240, The exposure pattern of the pixel array 240 is resynchronized with the contents of the exposure pattern buffer 295. In the exposure pattern buffer 295 of the various embodiments, One item of a project, , The logical value indicates that the corresponding pixel circuit 250 in the pixel array 24 is allowed to continue to accumulate or accumulate charge in each of its 15 self-sensing nodes 2〇3 during the image capturing operation. And - a "Γ" of the project,  The logical value indicates that the corresponding pixel circuit 25 within the pixel array 240 is not required to be blocked or stopped accumulating additional charges in its individual sensing node 203, However, it is necessary to maintain the accumulated charge in its individual sensing node 2〇3.  Although there are other possibilities, but in each of the 20 embodiments in the method of Figure 15, It is assumed that one of the states of the anti-diffusion gate transistor 216 of each pixel circuit 250 is always opposite to the state of one of the transfer gate transistors 2〇2 of the same pixel circuit 25〇. In other words, In these embodiments, When the transfer gate transistor 202 of the pixel circuit 250 is controlled to be turned on, The anti-glow gate transistor 216 of the same halogen circuit 250 is controlled to be turned off, And when the pass gate transistor 2〇2 of the pixel circuit 51 200917827 250 is controlled to be turned off, The anti-diffusion gate transistor 216 of the same halogen circuit 250 is controlled to be turned "on".  In various embodiments, When the content of the exposure pattern buffer 295 is written into the pixel array 24, The pass gate transistor body 202 in each of the pixel circuits 25A is turned off and the anti-glow gate transistor 216 is turned on. An item in the pattern buffer 295 that has been assigned a logical value of "1" is correspondingly exposed. In the pixel circuit 250, When the transfer gate transistor 2〇2 is turned off and the anti-glow gate transistor 216 is turned on, The accumulation of additional light-generating charges within the corresponding sense node 203 is prevented or inhibited or stopped, Any charge subsequently generated by the corresponding light 10 diode 201 is substantially discharged through the anti-bright gate transistor 216. and, In various embodiments, When the content of the exposure pattern buffer 295 is written to the pixel array 24, The transfer gate transistor 202 in each of the pixel circuits 25A is turned "on" and the anti-glow gate transistor 216 remains "off" an item corresponding to a specified logic value 15 in the sigma exposure pattern buffer 295. In these pixel circuits 250, When the transfer gate transistor 202 is turned on and the anti-glow gate transistor 216 is turned off, The charge generated by the light from the corresponding photodiode 2〇1 is allowed to continue to accumulate in the corresponding sensing node 2〇3.  The contents of the exposure pattern buffer 295 are written to the pixel array 240 one column at a time in various embodiments. In various embodiments, Each bit in the exposure pattern buffer 295 corresponding to a pixel unit 250 in a selected column to be written is interpreted as a corresponding pixel control signal line connected to the pixel circuit 250. Signal on 226. In various embodiments, When an item in the exposure pattern buffer 295 corresponding to the pixel circuit 250 has a "〇, , Logic value, The digital image processor 21 is connected to the pixel circuit 250 52 200917827 " The -HIGHk number is provided on the exposure control signal line 255 of the HI line 226 and a LOW signal is provided on the anti-dispersion control signal line 256. and, In various embodiments, When the - item in the exposure pattern buffer 295 of the corresponding-pixel circuit 250 has _ "Γ, Logic value, The 5-digit shirt image processor 210 provides an L〇w signal on the exposure control signal line 255 connected to the pixel control signal line 226 of the pixel circuit 25 and is on the anti-scatter control signal line 256. A mGH signal is provided on it.  therefore, In various embodiments, The digital image processor 21 提供 provides a signal to the pixel control signal 1 220 line 2201 based on the content of the exposure pattern buffer 295. 2262, ..., Each of 226m controls a pixel circuit 250 within a particular column. therefore, In these embodiments, The pixel control signal generator 3 can provide a HIGH signal on the control signal line 223 of the specific column. The transmission gate transistor 2A2 and the anti-glow gate transistor 216 of each of the pixel circuits 250 in the particular column are written in accordance with the corresponding supplied signals. The 15-cell control signal generator 213 can then provide a LOWt on the control signal line 223 of the particular column. And the transmission gate transistor 202 and the anti-glow gate transistor 216 of each of the pixel circuits 250 in the particular column will maintain their values, Due to the parasitic gate capacitance of the transistors. In various embodiments,  The flow of writing to the pixel array 240 according to the content of the § 曝光 exposure pattern buffer 295 can continue to the next column in the pixel array 240, etc. Until all columns have been written. In some embodiments, Steps S303 to S307 can be operated in a pipelined manner. So that whenever, for example, a small number of columns have been read, The exposure pattern data of the first column of the pixel array 歹1J 24〇 can be used to update one of the states of the first column of the pixel circuit 250. This allows readouts 53 200917827 and status updates to be performed in less time.  Fig. 19E depicts an example of an exposure pattern of the pixel array 24 〇 set in accordance with the exposure pattern data in the exposure pattern buffer 295 of Fig. 19D. According to the exposure pattern of the halogen array 24〇 in Fig. 19E, The pixel circuits located in one of columns 4-6 of the five-element array 240 and one of rows 2-4 have been controlled to stop accumulating additional charges in their respective sensing nodes' and are Control to maintain any charge that has accumulated within its respective sensing node. The pixel circuits correspond to items having a logical value of 1" in the exposure pattern buffer 295 of Fig. 19D. The other pixel circuits in the pixel array 1 〇 240 of Fig. 19E are controlled to continue in their respective sensing nodes? κ set or accumulated charge. The pixel circuits correspond to an item having a logical value of "〇" in the exposure pattern buffer 295 of Fig. 19D. Referring again to Figures 6 and 15, The updated exposure pattern data from the exposure pattern buffer 295 has been written to the pixel array in S307. To change the exposure pattern of the image 15 array, then the method continues to the eighth.  At S308, The total number of pixel circuits 250 for which the exposure of the image capture operation has been stopped is tested relative to a predetermined threshold value, The total number is equal to the sum of the bits in the exposure pattern buffer 295 that have been assigned a logical value of "". In the case where the total 20 of the bits in the violation pattern buffer 295 is not greater than the threshold, The method returns to (4). on the other hand, In the case where the sum of the bits in the exposure pattern buffer 295 is greater than the threshold, The method continues to S3Q9. The sum of bits 2 of the exposure pattern buffer 295 is an example of many of the possible image features that can be used to make the decision at step S3. In the s-illumination pattern buffer 295, a project of 54 200917827 a "1" logic value corresponds to the stop or block or prohibition of the accumulation of further charge in the sensing node of one of the pixel circuits (corresponding to the item) In an embodiment,  Once all the bits in the exposure pattern buffer 295 have been set to a logical value of "1", Returning to step S303 is not advantageous. In some embodiment 5, A maximum time limit value can also be set for the image capture operation.  In the example of Figure 19A-19K, It is assumed that the critical value used in step S308 of Fig. 15 is 45. of course, This threshold is only provided to the example.  And other threshold values can be used in other embodiments. Since the sum of the bits in the exposure pattern buffer 295 of Fig. 19D is 9 (not greater than 45), So this example 10 will result in a return to step S303. Figure 19F depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 in Figure 19D has been updated by combining with the exemplary filtered binary data. In this example, The filtered binary image data includes a "1" bit, One of the pixel circuits of column 2 and row 7 of the pixel array 240 corresponding to Fig. 19E is output. It should be noted that For each output of the pixel array 240, There may be multiple "1" bits within the filtered image material. Figure 19G depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 in Figure 19F has been expanded in accordance with the exemplary expansion criteria specified by the structural elements of Figure 18D.  2〇 Figure 19H depicts an example of an exposure pattern of the pixel array 240 set in accordance with the contents of the exposure pattern buffer 295 of Fig. 19G. According to the exposure pattern of the exposure array 240 in Fig. 19H, One of the columns 3-7 of the halogen array 240 and one of the rows 1-5, Or one of the columns 1-3 and the pixel circuit in one of the rows 6-8 have been controlled to stop accumulating additional charges in their respective sense nodes. And being controlled to maintain any charge that has accumulated in the respective sensing nodes. These pairs are in the exposure pattern buffer 295 of Fig. 19G ": :  The item ''n旳畀 has a logical value of -1'). Beans in the pixel array 240 of Figure 19H,  197/, His pixel circuits are controlled to continue to accumulate or accumulate charge in their respective nodes. The pixel circuits correspond to items having a logical value of "〇" in the exposure pattern buffer 295 of the 19th G1I. Because the sum of the bits in the exposure pattern buffer 295 of the 19Gth image is 34 (which is not greater than the exemplary threshold 45), This example will result in returning to step S303 in Fig. 15.  Figure 191 depicts an example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 of Figure 19G has been updated by combining with the exemplary filtered binary image data. In this example, the filtered binary image data includes "1" bits corresponding to the pixel circuits in column 1 and row 1-2 of pixel array 240 of Figure 19H. An example of the content of the exposure pattern buffer 295 after the content of the exposure pattern buffer 295 in FIG. 191 has been expanded according to the exemplary expansion criteria specified by the structural elements of FIG. 18D is described in FIG. . Fig. 19K depicts an example of an exposure pattern of the pixel array 240 set in accordance with the contents of the exposure pattern buffer 295 of Fig. 19J. Because the sum of the bits in the exposure pattern buffer 20 295 of Figure 19J is 49 (which is an exemplary threshold greater than 45), This example will proceed to step S309 in Fig. 15.  See page 6, again. Figures 7 and 15, In step S309, Image capture within the pixel array 240 is terminated. In various embodiments, image capture within the pixel array 240 is terminated. By exposing any remaining book circuit 250 that is still accumulating charge from its individual photodiode 56 200917827 body 201 at its individual sensing node 2_. In various embodiments, The stopping of the exposure can be performed by forcing the transfer gate transistor 202 of each of the pixel circuits 25A to a closed state and anti-radio discharge of each of the pixel circuits 25 5 The crystal 5 216 is forced to an on state to be executed. E.g, The digital image processor 210 can control the signal line η%, An L 〇 w signal is provided on each of the exposure control signal lines 2 5 5 of 22 to 22, and a HIGH signal is provided on the anti-bright emission control signal line 256. And the halogen (four) signal generator 213 can be in the column control line 223], 223h..., A HIGH signal is provided on each of the 203n transmission lines 253. In various embodiments, When the image capture of the pixel array 24 in step S309 is terminated, The accumulated charge in each of the sensing nodes 2〇3 of each pixel circuit 250 is maintained within the pixel circuit 250. The method then proceeds to S310.  In S310, An image captured within the pixel array 24 is read from the pixel 15 array 240. In various embodiments, The reading of the image in step S310 is performed using the voltage analog mode. If the embodiment of the image sensor circuit 200 of Fig. 11 or the image sensor circuit 200 of Fig. 13 is used, Then, the voltage source switch 217 of each row of the pixel array 240, Output mode switch 227 and digital multiplexer 228 are controlled in accordance with the voltage-to-class ratio 20 mode discussed above. In various embodiments, A voltage-to-analog readout from the pixel array 240 may be slower than a current-to-analog read from the pixel array 240.  However, the voltage-to-analog readout from the pixel array 240 has a higher signal-to-noise performance than the current-to-analog readout. therefore, In various embodiments, For an image capture operation, The final read from the pixel array 240 is an electrical 57 200917827. Analogue readout is advantageous 'to obtain an optimal quality signal from the pixel array 24' to define the captured image. In various embodiments, The voltage-to-analog readout in step S31 is performed using the double sampling amplifier 207 of each of the row ADC circuits 220. Thus, the corrected pixel output voltage is based on the between the book 5 output voltage and the reset voltage. The difference is calculated. The method ends at S311. Some electronic shutter operations that conform to the method of Figure 15 are referred to herein as "wave shutter" operations.  In various embodiments, A pixel array can be initialized, The image capture in the pixel array can be initialized and concentrated in a pixel circuit near the space where the image intensity is derived by more than a critical level and is encountered by a pixel circuit that has been stopped from exposure. The exposure within the pixel circuit of a signal can be stopped. and, In various embodiments, During an image capture operation, When the exposure in some of the pixel circuits of the pixel array has been stopped,  Image capture within a pixel array can be complete. In each of the embodiments 15, A spatially filtered analog image suitable for machine vision processing is captured according to one of the following methods: One of the pixel arrays is exposed by a multidimensional control pattern and a structural component. The multi-dimensional control pattern develops intermittently with a non-linear function of the analog data content when the pixel array is partially exposed.  Figure 16 depicts a flow diagram of a method in accordance with an embodiment of the present invention. In S601, Exposure information associated with an exposure pattern of a pixel array is stored. In various embodiments, The exposure information can include one or more bits of each pixel circuit within the pixel array. In various other embodiments, The exposure information can include a smaller number of bits than the total number of one of the pixel circuits of the pixel array. In some embodiments, The exposure information may refer to a number or other indicator associated with the exposure pattern of the pixel array at 58 200917827.  And in some embodiments, The exposure information can include one or more combinations of bits associated with the exposure pattern of the pixel array. After the exposure information has been stored, the method continues to S6〇2.  5 Within %02, the exposure pattern of the pixel array is changed based at least in part on the following. (1) exposure information that has been stored; and (丨丨) one or more signals output from the pixel array. In various embodiments, the stored exposure information is changed based on the one or more signals output from the pixel array, and the changed exposure information is used to control 10 of the exposure patterns of the pixel array. A change. In some embodiments, the stored exposure information is changed in accordance with an expansion criterion, and the changed exposure information is used to control a change in the exposure pattern of the pixel array. In various embodiments, the possible exposure states of each of the pixel circuits within the pixel array include (1) an on state, wherein the pixel circuit is allowed to collect 15 sets of charge at one of the sensing nodes of the pixel circuit, And (11) a closed state in which the pixel circuit is blocked or stopped from accumulating additional charges at the sensing node. Moreover, in various embodiments, the exposure pattern of the pixel array is defined, and the pixel circuits within the pixel array are in an on state such that they are still accumulating charges at their sensing nodes, and within the pixel array. The pixel circuits are thus turned off so that they do not accumulate additional charge in their sensing nodes. The exposure pattern of the _ 画 pixel array has been changed in S602, and the method ends in S6 〇 3. Figure 17 depicts a process diagram of a method in accordance with an embodiment of the present invention. In S651, one of the charges is accumulated starting in each of a plurality of pixel circuits of a pixel array, and the method continues to S652. In S652, the accumulation of charge is blocked in at least one particular pixel circuit of the pixel circuits selected based at least in part on the one or more signals output from the pixel array. The method continues to S653. In S653, based at least in part on an expansion 5 criterion, accumulation of charge in at least one of the pixel circuits of the pixel circuits adjacent to a particular pixel circuit within the pixel array is blocked. In various embodiments, the expansion criterion is specified by a structural element. The method ends in S654. Figure 20 depicts another embodiment of an image sensor circuit 200 in accordance with an embodiment of the present invention. The image sensor circuit 2 of FIG. 2 is implemented in an embodiment different from the image sensor circuit 200 of FIG. 11, because the embodiment of the shirt image sensing circuit 200 of FIG. 20 includes · A resistance thumb 400. Elements of an embodiment of the image sensor circuit 200 of Fig. 20, which is identical to the elements of the embodiment of the image sensor circuit 200 of Fig. 11, are designated by the same reference numerals. In various embodiments, the resistor grid 4 includes a plurality of programmable or 15 switchable resistors 401 and a plurality of capacitors 402. In various embodiments, the resistor grid 400 includes a switchable resistor 401 and a capacitor 402 for each row of the pixel circuit 250. In various embodiments, each switchable resistor 401 is coupled to one of a corresponding current to voltage converter 222 and is coupled to one or more adjacent switchable resistors 4〇1. Moreover, in each of the twenty embodiments, each capacitor 402 is coupled between a corresponding current-to-voltage conversion 222 output terminal and ground. In various embodiments, the resistive grid 4 can be used to perform a spatial filtering that can be used, for example, in step S304 of the method of Figure 15. Performing spatial filtering 60 in a class-like domain using the resistive gate 400 in various fine-grained examples can improve one of the spatial filtering speeds, as compared to spatial filtering in a digital domain by, for example, the digital image processor 210. Other embodiments. In some embodiments, the resistor grid 400 is used to perform horizontal filtering of signals for an image. In various embodiments, each of the switchable resistors 4〇1 is controlled by the 5 control processor 212. In various embodiments, the image sensor circuit 200 of Figure 2 can be used to perform the method described in Figure 15, and the spatial filtering of step S304 can be performed using the resistance gate 4〇〇. In the various examples, an operation mode using the resistor housing 40 包含 includes two functional steps. In a first step, the parent current of each row 10 of the pixel circuit 25A loads a corresponding capacitor 402 to the voltage converter 222, and each of the switchable resistors 4〇1 is broken. open. In a second step, each current to one of the voltage converters 222 is set to a high impedance, and the switchable resistors 401 are connected. In this state, the voltage value on each capacitor 402 is spatially low pass filtered, wherein the spatial filtering bandwidth is a function of 15 filtering effects and the value of one of each switchable resistor 4〇1 and The value of one of the capacitances of each capacitor 402 is related. In a third step, the corresponding difference comparator 225 compares the voltage value and the -th threshold stored in each capacitor 4〇2 to provide filtered binary image data. Figure 21 depicts another embodiment of an image sensor electrical circuit 200 in accordance with an embodiment of the present invention. The embodiment of the image sensor circuit 2 of FIG. 21 is different from the embodiment of the image sensor circuit 200 of FIG. 13 because the embodiment of the image sensor circuit 200 of FIG. 21 includes a resistor grid 4. Hey. Other elements of the embodiment of the image sensor circuit 2 of Fig. 21 which are identical to the elements of the embodiment of the image sensor circuit 200 of Fig. 13 are designated by the same reference numeral 61 200917827. In various embodiments, the resistor grid 400 includes a plurality of programmable or switchable resistors 401, a plurality of capacitors 402, and a plurality of voltage comparators 403. In various embodiments, the resistor grid 4 includes a switchable resistor 401, a capacitor 402, and a voltage comparator 403 for each of the rows of the pixel circuits 25A. In various embodiments, each switchable resistor 4〇1 is coupled to one of a corresponding current comparator 222b output and to one or more adjacent switchable resistors 401. Moreover, in various embodiments, each capacitor 402 is coupled between an output of one of the corresponding current comparators 222b and the ground 10 end. In various embodiments, one of each voltage comparator 403 input is coupled to a corresponding capacitor 402, and one of each voltage comparator 4〇3 output is coupled to a corresponding digital multiplexer 228. In each implementation, the resistive grid can be used to perform the steps (4) of the method of (e), for example, 15 20, FIG. 15 for fear of (four) - seeding (four) waves. In contrast to the other embodiments in which the spatial chopping is performed in the digital domain by, for example, the digital image processor 210, the resistive gate copper is used in various embodiments to perform "chopping in the analog domain. Wave - speed. In some embodiments, the resistor grid is used to perform horizontal signaling of the signal. In various embodiments, each of the switchable devices is operated by the control processor. In various embodiments, the image sensor circuit 200 of Fig. 21 can be used to perform the method described in Fig. 15, and the spatial filtering of step S304 can be performed using the resistance gate 400. In various embodiments, an operational core using the resistor grid 400 of Figure 21 includes three functional steps. In a first step, each current comparator 222b of each row of 62 200917827 in pixel circuit 250 loads a corresponding capacitor 402 when each of the switchable resistors 401 is turned off. In a second step, one of the outputs of each of the current comparators 222b is set to a high impedance, and the switchable resistors 401 are connected. In this/state, the voltage value on each of the 5 capacitors 402 is spatially low pass filtered, wherein the spatial filtering bandwidth is a function of the filter program and a value of the on-resistance of each of the switchable resistors 401 and each The value of one of the capacitors 402 is related to the capacitance. In a third step, a voltage value stored in each capacitor 402 is digitized by a corresponding voltage comparator 403 to provide filtered binary image data. Two more people refer to brothers 6 and 7 in various embodiments.

20 circuit 200 is configured to obtain an image using an electronic shutter operation, wherein the exposure pattern of the pixel array 2 4 G is set based on exposure information that changes over time, based at least in part on the fineness of the pixel array - the charge accumulated in the part. When a shutter operation conforming to, for example, the method of Fig. 15 is used, the maximum allowable time for performing an image capturing operation can be limited by the efficiency of the pixel circuit 250. The ability of the shutter to accurately reproduce the charge of the ^^ point 2_ during the image capture operation is 'the ability of the image to be prohibited or blocked or Stop the money in the sense of loss = time to - the last image is read out of the book of the operation of the film. During this time, the section is degraded. The amount of this degradation can be proportional to the amount of charge generated by the singulation, the intensity of the light 63 200917827 on the 4 pixel circuit 250, and the amount of time the stored charge must be maintained 'until it is finally from the 昼The matrix array 240 is read. In various embodiments, an automatic shutter mechanism allows for the use of light intensity to control one of the individual pixel circuits or pixel circuits within an image sensor circuit. In some such embodiments, during an image capture operation, the exposure of the pixel circuit receiving the bright light may be stopped earlier than the exposure of the pixel device receiving the lower intensity light. In various embodiments, when exposed in a pixel circuit of a pixel array, the sensed value within one of the pixel circuits must be maintained within the sensing node until the drawing The exposure in the remaining pixel circuits within the array of primes 10 ends and the last signal of an image is read from the pixel array. Shutter efficiency may indicate that analog information may be stored in one of the sensing nodes (e.g., - floating diffusion nodes) of one of the pixel arrays of the pixel array for a maximum amount of time without significant degradation. Referring to Fig. 22, various techniques that allow for improved shutter efficiency are described herein. Figure 22 depicts a layout 90 in accordance with an embodiment of the present invention. The layout 900 includes the pixel circuit 25A. The elements of the embodiment of the pixel circuit 250 in Fig. 22 which are similar to the elements of the embodiment of the pixel circuit 25A in Fig. 14 are denoted by the same reference symbols. In various embodiments, the pixel circuit 25A includes the anti-glow gate transistor 20 body 216. Incorporating the anti-diffusion gate transistor 216 into the pixel circuit 250 can provide a way to block the photodiode 201 after the exposure of the pixel circuit 250 has stopped reaching the sensing node 203 of the pixel circuit 250. The mechanism of the charge generated by the light inside. The use of a primary anti-gap gate transistor can be used differently from one of the anti-gluence gate transistors to avoid a pixel of the pixel near the pixel of a saturating pixel circuit. The photodiode of the 200917827 circuit draws an excess of the pixel circuit. The charge. In various embodiments, a light sensor (e.g., photodiode 201) is extended. For example, one of the regions of the photodiode 2〇1 can be added to one or more of the extended regions 501. In some embodiments, the photodiode 2〇1 is a pin-type light 5 diode. Moreover, in some embodiments, a region of the photodiode 201 can be extended or increased as much as possible. In some embodiments, the one or more extension regions 501 may even extend under one or more lines, such as exposure control line 255, anti-dispersion control signal line 256, voltage source line 235, row readout line 231, or Similar. In various embodiments, the one or more lines are metal wires. In some embodiments, although the one or more extended regions may not improve one of the response of the pixel circuit 250, the one or more extended regions 〇1 may increase the area in which the charge generated by the light is absorbed, thus reducing The possibility of this charge accidentally reaching the sensing node 203. Thus, the one or more extended regions 5〇1 in various embodiments may allow for improved shutter efficiency. In various embodiments, the layout 9 further includes one or more virtual diffusions 502. In some embodiments, the one or more virtual diffusions 5〇2 may be located in other empty regions of the pixel circuit 250 that do not belong to the photodiode 201 or the transistors 214, 215, 205, 205, and 206. If some of the light generated by the one or more virtual diffusions 502' arrives at the vacant space, it may diffuse to the sensing node 203 and reduce the shutter efficiency. In various embodiments, to prevent this from happening, the equal-space region covers one or more virtual diffusions 〇2. In various embodiments, the one or more virtual diffusions 〇2 are connected to a constant voltage source (not shown in FIG. 22), such as a voltage supply or the like, thereby passing through the one or more The charge generated by any light of the virtual diffusion 502 is absorbed by the voltage supply source 65 200917827. Rate Because in various embodiments, short wavelength illumination is used to help improve shutter efficiency. In various embodiments, the use of short wavelength light can help improve the shutter to short wavelength photons that can be absorbed near the -11 surface, and thus can be Light = 2: Capture. Longer wavelength photons can reach the deeper part of the material, and the photodiode-action area' thus increases the probability of reaching the sensing point 203 and reduces the shutter ratio. 10 15 20 In various embodiments, the layout 9〇〇 further includes an infrared ray on the painting (by 穿透·波 please. By penetrating to the non-occlusion of the electric field, the prime circuit 2 Huan-based (four) is deep _ square, infrared photons may cause problems' and electrons from the photons may randomly diffuse and reach the sensing node 203, thereby degrading the data stored in the sensing node 2〇3. (4) The money wave (4) 3 of the money road 25, the number of charges generated by the light in the deep substrate of the pixel circuit 25Q may be reduced, thereby allowing the shutter efficiency to be improved. In some embodiments, the layout 9GG may A color filter (not shown in Fig. 22) is included on the pixel circuit 25(). The behavior of long wavelength photons in the visible spectrum may be similar to the claw photons and may be due to the penetration of the pixel into the pixel circuit 25 A problem occurs in a very deep area of the substrate. In various embodiments, a color filter can be used to prevent such photons from reaching one of the substrate of the pixel circuit 25. In some embodiments, The pixel circuit 250 can be matched to sense the visible light spectrum In some embodiments, the halogen circuit 25 can be configured to sense light outside the visible spectrum. In various embodiments, the layout 9 further includes a metal protection feature 66 200917827 sign 504. In various embodiments, the metal protection feature 504 can cover at least a portion of the sensing node 203. In some embodiments, protecting the sensing node 203 with a metal protection can allow for reduced storage due to light generation. The degradation of the charge within node 203 is measured. 5 Referring again to Figure 6, in various embodiments, image sensor circuit 200 can be configured to allow receipt of an instruction that specifies that it needs to be used for one or more The type of shutter mode for a particular image capture operation. For example, in various embodiments, the image sensor circuit 200 can be configured to receive an instruction that is selected for use in an image capture operation (1) a global shutter 10 operation; (ii) a rolling shutter operation; and (iii) one of a wave shutter operation. In such embodiments, in the case where the command specifies a global shutter operation, the image The sensor circuit 200 can capture an image using a global shutter operation. Moreover, in such embodiments, the image sensor circuit 200 can utilize a rolling shutter operation in the event that the command specifies a rolling shutter operation. 15 is to capture an image. Further, in such embodiments, in the case where the command specifies a shutter operation, the image sensor circuit 200 can utilize a wave shutter operation in accordance with the method of FIG. In various embodiments, in the case where the image sensor circuit 200 is used to perform a wave shutter operation, the image capture sensor circuit 200 can receive a signal that is determined by the signal 20 One or more structural elements that are used for the shutter operation of the wave. In some embodiments, the image capture sensor circuit 200 can be configured to automatically select one of a type of shutter operation based on the sensed light condition. Exemplary applications for image sensor circuits (eg, image sensor circuit 200) include, for example, manufacturing automation, product components, identification (ID) reading 67 200917827, vehicle control, gesture recognition, video surveillance, three-dimensional ( 3D) Use in modeling, mobile analysis, medical devices, military devices, mapping systems, or the like. The embodiments disclosed herein are considered to be illustrative and not limiting of the invention in all aspects. The present invention is not limited to the embodiment described above. Various modifications and changes may be made to the invention without departing from the spirit and scope of the invention. Various modifications and variations are intended to be included within the scope of the invention. t-Simple Description 3 Figure 1 depicts a conventional image sensor circuit; 10 Figure 2 depicts a conventional pixel circuit; Figure 3 depicts a conventional row analog-to-digital converter (ADC) circuit; FIG. 4 depicts a conventional image sensor circuit; FIG. 5 depicts an image processing system in accordance with an embodiment of the present invention; FIG. 6 depicts an embodiment in accordance with the present invention An image sensor 15 circuit; FIG. 7 depicts a pixel circuit in accordance with an embodiment of the present invention; FIG. 8 depicts a threshold current generator in accordance with an embodiment of the present invention; A row of ADC circuits in accordance with an embodiment of the present invention; 20 FIG. 10 depicts a reference signal converter in accordance with an embodiment of the present invention; FIG. 11 depicts an image sensing in accordance with an embodiment of the present invention Figure 12 depicts a row of ADC circuits in accordance with an embodiment of the present invention; 68 200917827 Figure 13 depicts an image sensor circuit in accordance with an embodiment of the present invention; Figure 14 depicts in accordance with the present invention a glimpse of the embodiment One of the circuits; FIG. 15 is a flow chart depicting a method for an image sensor circuit in accordance with an embodiment of the present invention; FIG. 16 depicts a method for use in accordance with an embodiment of the present invention. A flowchart of one of the methods of the image sensor circuit; FIG. 17 depicts a flow chart of a method for an image sensor circuit in accordance with an embodiment of the present invention; Inventive - an expansion criterion specified by a structural element of the embodiment; Figure 18B depicts an expansion criterion specified by a structural element in accordance with an embodiment of the present invention; 15 帛 18C depicts a method in accordance with the present invention - An expansion criterion specified by the structural element of the embodiment; FIG. 18D depicts an expansion criterion specified by a structural element in accordance with an embodiment of the present invention; FIG. 19A depicts an embodiment in accordance with an embodiment of the present invention An example of the content of the exposure pattern 20 buffer;

Figure 19B depicts an example of an exposure pattern of a pixel array set in accordance with the contents of the exposure pattern buffer of Figure 19A in accordance with an embodiment of the present invention; Figure 19C depicts an embodiment in accordance with the present invention. An exposure pattern 69 200917827 An example of the contents of the buffer; Figure 19D depicts an example of the contents of an exposure pattern buffer in accordance with an embodiment of the present invention; Figure 19E depicts an implementation in accordance with one embodiment of the present invention An example of an exposure pattern of a pixel array set according to the content of the exposure pattern buffer of FIG. 5; FIG. 19F depicts a content of an exposure pattern buffer according to an embodiment of the present invention. Example; Figure 19G depicts an example of the contents of an exposure pattern 10 buffer in accordance with an embodiment of the present invention; Figure 19H depicts an exposure pattern buffer in accordance with Figure 19G in accordance with an embodiment of the present invention. An example of an exposure pattern of a pixel array of content settings; FIG. 191 depicts an example of the contents of an exposure pattern 15 buffer in accordance with an embodiment of the present invention; Figure 19J depicts an example of the contents of an exposure pattern buffer in accordance with an embodiment of the present invention; Figure 19K depicts the content setting of the exposure pattern buffer in accordance with Figure 19J, in accordance with an embodiment of the present invention. An example of an exposure pattern 20 of one of the pixel arrays; FIG. 20 depicts an image sensor circuit in accordance with an embodiment of the present invention; and FIG. 21 depicts an image sense in accordance with an embodiment of the present invention. Detector circuit; and 70 200917827 FIG. 2 2 depicts a layout according to an embodiment of the present invention [main component symbol description] 129...transmission signal line 130···reset signal line 131...sensing node 132 ···Voltage source 133... Ground terminal 140···Source transistor 142...Double sampling amplifier 144... Analog-to-digital converter (ADC) circuit 146···Amplifier control signal line 148... Converter control signal line 200...Image Sensor circuit 201...photodiode 202···transmission gate transistor 203···sensing node 204···resetting transistor 205...driving transistor 206...reading selection transistor 207...double sampling amplifier 2 08···Source transistor 209...ADC circuit 210.············································· 104...column addressing circuit 105...control processor 106...image memory buffer 107^1072, ..., 107 wide. column control lines 108!, 1082, ..., 108^... analog output lines 109丨, 1092 ,...,109m...digital output line 112···昼 电路 circuit 114...row ADC circuit 121...photodiode 122···transmission gate transistor 131...sensing node 124···resetting the transistor 125··· Driving transistor 126···Reading selection transistor 127··· Column reading signal line 71 200917827 211···Image memory buffer 212··. Control processor 213··· pixel control signal generator 214 ···First write selection transistor 215···Second write selection transistor 216···Anti-glow gate transistor 217···Voltage source switch 217^217^··Voltage source switch 218·· Current source 219...output line 220···row ADC circuit 221···reference signal converter 222···current to voltage converter 222b...electric Comparator 223...column control line 223^223^4] control line 224...current to voltage converter 225···difference comparator 226... elementary control signal line 2261~226m... 昼 control signal line 227... output mode Switch 228···Digital multiplexer 229···Voltage driver 230···voltage source 231···row readout line 231^231...row readout line 232···reference signal line 233···ground end 234...bias source 234丨~234m···bias source 235··voltage source line 2351~235m...voltage source line 238···voltage source line 239...switch 240...morphe array 241...control line 242· ··Control line 243···Reference voltage line 245...Communication line 246···Digital output line 246,~246m··•Digital output line 247...Write bus 248...Read/write bus 249...ADC Block 250... 昼 电路 circuit 251 ···voltage source 252···reset signal line 253...transmission signal line 72 200917827 254··· column readout signal line 400...resistance gate 255···exposure control signal line 401· ··Switchable resistor 256...anti-dispersion control signal line 402...capacitor 260···critical current generator 403...voltage ratio Comparator 265···current control transistor 501...extension region 266...selection transistor 502...virtual diffusion 267···threshold voltage source 503...infrared filter 268···threshold voltage line 504...metal protection feature 273·· Voltage supply source 700...image processing system 274...selection signal line 800...processor 281...bias source 900...layout 283··current source switch S301~S311...step 290...one or more circuits 295...exposure pattern buffer S601~S654...Step 1/73

Claims (1)

200917827 X. Patent application scope: h - an image sensor circuit comprising: - a pixel array comprising a plurality of pixel circuits; and one or more circuits arranged to be based at least in part on the pixel array wheel The one or more signals are updated to update exposure information and are configured to control an exposure pattern of the pixel array based on the exposure information. 2. The image sensor circuit of claim 1, wherein the one or more circuits are configured to update the exposure information in an iterative manner when an image is being captured by the pixel array. Based in part on the one or more signals and at least one expansion criterion that are rotated from the pixel array. • The image sensor circuit of claim 2, wherein the at least one expansion criterion is specified by at least one structural element. 4. The image sensor circuit of claim 1, wherein the pixel circuits are controllable such that at least one of the pixel circuits in the column of pixels is senseable in one of the pixel circuits The node collects charge while at least one second pixel circuit in the column is prevented from accumulating charge at one of the sensing nodes of the second pixel circuit during at least a portion of the image capture operation. 5' The image sensor circuit of claim 1, wherein the one or more circuits are configured to be iteratively updated based at least in part on values of the one or more signals output from the pixel array The exposure information 'the equivalent of the one or more signals represents the charge accumulated in at least a portion of the pixel array. /r • The image sensor circuit of claim 1, 74 200917827 The one or more circuits are configured to individually control the exposure state of the pixel circuits based on the exposure information to control the picture The exposure pattern of the prime array. 7. The image sensor circuit of claim 6, wherein the exposure states of each of the pixel circuits of the pixel circuits include an on state and a off state, wherein in the on state, the The pixel circuit is allowed to accumulate charge at one of the sensing nodes of the pixel circuit, and in the off state, the pixel circuit is prevented from accumulating additional charges at the sensing node. 8. The image sensor circuit of claim 1, further comprising: one or more memory devices for storing the exposure information as exposure pattern data' including the need to be used to control the painting At least one bit of each of the pixel circuits in the one of the pixel circuits in an exposed state. 9. The image sensor circuit of claim 8, wherein the or more circuits are configured to store the exposure in the one or more memory devices prior to an image capture operation The pattern data is reset to an initial pattern. 10. The image sensor circuit of claim 1, wherein the one or more circuits are configured to change the pixel multiple times based on the exposure information when an image is captured by the pixel array The exposure pattern of the array. U. The image sensor circuit of claim 1, wherein at least one of the pixel circuits comprises: 75 200917827 a photosensitive element; a first transistor having a connection to the photosensitive element And a second transistor connected between an exposure control signal line and one of the gates of the first transistor; the one or more circuits being configured to control the exposure control signal based on the exposure information A signal on the line. 12. The image sensor circuit of claim 11, wherein the at least one pixel circuit further comprises: a third transistor coupled to the photosensitive element; and a fourth transistor coupled to the primary antibody Between the divergence control signal line and one of the gates of the second transistor, the one or more circuits are configured to control an anti-glow signal on the anti-dispersion control signal line based on the exposure information. 13. The image sensor circuit of claim 12, wherein the one or more circuits are configured to control the anti-glow signal on the anti-dispersion control signal line during an image capture operation An opposite value of one of the exposure control signals on the exposure control signal line. 14. The image sensor circuit of claim 12, wherein the photosensitive element has a first portion extending below the exposure control signal line and a portion extending below the anti-dispersion control signal line the second part. 15. The image sensor circuit of claim 11, wherein the at least one pixel circuit further comprises: 76 200917827 one or more virtual diffusions coupled to a constant voltage during an image capture operation. 16. The image sensor circuit of claim 11, wherein the at least one pixel circuit further comprises: a reset transistor coupled between a fixed voltage and a sensing node, the sensing node One of the voltages controls an output signal; the one or more circuits are configured to control a reset signal that is applied to one of the gates of the reset transistor such that the reset transistor is in an image The off operation remains off during and between at least two readouts of the output signal such that the at least two out of the output signal is non-destructive with respect to the charge accumulated on the sense node. 17. The image sensor circuit of claim 1, wherein the pixel circuit array further comprises a plurality of row readout lines to provide the one or more signals; and the one or more circuits are combined The signal on the line of the readout signal is selectively controlled to be a voltage signal or a current signal. 18. The image sensor circuit of claim 1, wherein the one or more signals are analog current signals. 19. The image sensor circuit of claim 1, further comprising: a line of analog-to-digital converter circuits configured to receive the same in a row that is identical to one of the pixel arrays One of the pixel arrays of the two or more pixel circuits in the prime circuit outputs a class 77 200917827 ratio signal output on the line and is configured to convert the analog signals into corresponding digital signals. 20. The image sensor circuit of claim 2, wherein the pixel circuits are arranged in a plurality of columns and a plurality of rows; the one or more circuits are configured to selectively control the pixels Arrays provide outputs from two or more columns and two or more rows of pixel circuits at the same time such that the two or more columns are in the row readout line of the pixel array Combine in analogy. The image sensor circuit of claim 1, further comprising: a resistance gate comprising a plurality of switchable resistors and a plurality of electric 4 equal power grids connected to receive having a signal of a value of a Hz signal or a signal of a circumscribing signal, the switchable resistors being configured to selectively connect the capacitors according to the command signal; and in the case of a period of time-lapse, the pair is The storage left A sub-worker, the switch resistors at 5 hai, etc. have been controlled to connect the capacitors to at least one of the capacitors stored in the capacitors. The one or more circuits are combined to generate a new blue light based on the voltage f The circuit is configured to output a voltage of a reference f: number derived from one of a particular critical current generator in a particular 78 of the columns of the 2009 17827 column and the pixel circuits from the particular column The second specific pixel circuit - the output - the signal - voltage is compared to & and the group (4) is updated based on the result - the exposure information is updated. The image sensor circuit of claim 1, wherein the one or more circuits are configured to terminate the comparison based on a comparison between a critical number and a number calculated from the exposure information. An image capture operation in the column of f arrays. 24. The image sensor circuit of claim 1, wherein the one or more circuits comprise a digital signal processor. 25. The image sensor circuit of claim 2, further comprising: an infrared wave modulator disposed on at least a portion of the at least one pixel circuit in the pixel circuits. 26. The image sensor circuit of claim 1, wherein the image sensor circuit comprises: 'a color filter' disposed on at least a portion of the at least one pixel circuit of the pixel circuits. 27 - A method for an image sensor circuit, the image sensor circuit comprising a pixel array having a plurality of pixel circuits, the method comprising the steps of: storing an exposure pattern with the pixel array Relevant information; and based at least in part on (i) information that has been stored; and (ii) one or more signals output from the pixel array, the exposure pattern of the pixel array is changed. 79 200917827 Beginning each of the four (4) charge-gatherings in the pixel circuits; in the sine-constant circuits of the books selected based at least in part from the output of the pixel array At least one of the plurality of pixel circuits in the particular pixel circuit; and a portion based on the -expansion criterion to prevent at least one of the pixel circuits adjacent to the °Hertz pixel circuit in the pixel array The accumulation of charge in the prime circuit. 29. A halogen circuit comprising: a photodiode; a first transistor coupled between the photodiode and a sensing node; and a second transistor coupled to an exposure control signal line Between one of the gates of the first transistor, the second transistor has a gate connected to a transmission signal line. 30. An image processing system comprising: an image sensor circuit comprising a pixel array and configured to obtain an image using a shutter mode, wherein an exposure pattern of the pixel array is set according to exposure information, The exposure information is based, at least in part, on the accumulation of charge over at least a portion of the pixel array over time; and a processor configured to detect one or more objects within the image. 80