TWI470956B - Digital satellite equipment control device - Google Patents

Description

Digital satellite equipment control device

The present invention relates to a digital satellite device control device, and more particularly to a digital satellite device control device having a noise reduction function and a short circuit protection function.

With the popularity of satellite signals, there are many products for receiving satellite signals, such as digital satellite equipment control (Diseqc) devices. Common digital satellite device control devices are used to issue commands to corresponding devices, such as switchers, switches, antenna drive devices, low noise block down converters (LNBs), and the like. However, the circuit of the prior art digital satellite device control device must be composed of various components, such as an integrated circuit (IC), a diode, a bipolar transistor, a resistor, a capacitor, etc., and thus in circuit design. More complicated and costly. In addition, the prior art digital satellite device control device lacks a mechanism for filtering noise, and does not provide a short circuit protection design, so that it is prone to malfunction or malfunction in operation.

One embodiment of the present invention relates to a digital satellite device control apparatus including an RF switch, a DC switch, a noise cancellation circuit, a decoder, and a power clock generator. The plurality of input ends of the RF switch are configured to receive an RF signal, and the output end of the RF switch is configured to output an RF signal input by the plurality of input terminals, and the control end of the RF switch is used according to a first The control signal couples the output end of the RF switch to one of the plurality of input terminals of the RF switch. The input end of the DC switch is coupled to a voltage source to receive an input voltage, and the plurality of output ends of the DC switch are used to output the input voltage, and the control end of the DC switch is The input end of the DC switch is coupled to one of the plurality of output ends of the DC switch according to a second control signal. The noise cancellation circuit is configured to cancel the noise of the input voltage (the signal of the non-Diseqc command), the input end of the noise cancellation circuit is coupled to the voltage source to receive the input voltage, and the noise cancellation circuit The output is used to output an AC component of the input voltage. The first input end of the decoder is coupled to the output end of the noise cancellation circuit to receive the AC component of the input voltage, and the first output end of the decoder is coupled to the control end of the RF switch to The AC component of the input voltage outputs the first control signal, and the second output of the decoder is coupled to the control terminal of the DC switch to output the second control signal according to the AC component of the input voltage. The power clock generator is configured to provide an operating voltage to the digital satellite device control device, the input end of the power clock generator is coupled to the voltage source to receive the input voltage, and the power clock generator The first output is coupled to the second input of the decoder to output a clock signal to the second input of the decoder according to the input voltage.

Another embodiment of the present invention is directed to a digital satellite device control apparatus including an RF switch, a DC switch, a decoder, a power clock generator, and a short circuit detection circuit. The plurality of input terminals of the RF switch are configured to receive an RF signal, the output end of the RF switch is configured to output an RF signal input by the plurality of input terminals, and the control end of the RF switch is used according to a first control The signal couples the output end of the RF switch to one of the plurality of input terminals of the RF switch. The input end of the DC switch is coupled to a voltage source to receive an input voltage, the plurality of output ends of the DC switch are used to output the input voltage, and the control end of the DC switch is used according to a second control The signal couples the input end of the DC switch to one of the plurality of output ends of the DC switch. The first input end of the decoder is coupled to the voltage source for receiving the input voltage, and the first output end is coupled to the control end of the RF switch for outputting the first control according to the AC component of the input voltage And a second output end of the decoder is coupled to the control end of the DC switch for outputting the second control signal according to the AC component of the input voltage. The power clock generator is configured to provide an operating voltage to the digital satellite device control device, the power clock The input end of the generator is coupled to the voltage source for receiving the input voltage, and the first output end of the power clock generator is coupled to the second input end of the decoder for output according to the input voltage A clock signal is sent to the second input of the decoder. The short circuit detecting circuit is coupled to the plurality of output ends of the DC switch and the decoder for controlling the decoder to turn off the DC switch when the current of the output of the DC switch is excessive.

Through the apparatus and method provided by the embodiments of the present invention, the digital satellite device control device can prevent the decoder from malfunctioning or inoperating due to excessive noise of the received output voltage, and can provide a short circuit protection function. In addition, the digital satellite device control device only needs to include integrated circuits and capacitors in the installation, and does not require components such as a diode, a bipolar transistor, and a resistor. Therefore, the digital satellite device control of the present invention is compared with the prior art. The device is relatively simple in circuit design.

20‧‧‧RF switch

22, 32‧‧‧ control end

24, DC1 to DC4, 44‧‧‧ output

30‧‧‧DC switch

40‧‧‧ Noise Elimination Circuit

47‧‧‧ analog bandpass filter

48‧‧‧Digital glitch interference canceller

50‧‧‧Decoder

51‧‧‧ first input

52‧‧‧second input

53‧‧‧ third input

54, 64‧‧‧ first output

56, 66‧‧‧ second output

60‧‧‧Power Clock Generator

67‧‧‧ Clock Generator

68‧‧‧clock tuner

70‧‧‧Short circuit detection circuit

80‧‧‧Set-top box

100, 400, 500‧‧‧ digital satellite equipment control devices

CON1‧‧‧ first control signal

CON2‧‧‧second control signal

CLK‧‧‧ clock signal

DCIN‧‧‧voltage source

RF1 to RF4, 31, 42, 62‧‧‧ inputs

S1‧‧‧ analog signal

V1‧‧‧ input voltage

Fig. 1 is a schematic view showing a digital satellite device control device according to a first embodiment of the present invention.

Fig. 2A is a schematic diagram of the noise canceling circuit of Fig. 1.

Figure 2B is a schematic diagram of the power clock generator of Figure 1.

Figure 2C is another schematic diagram of the power clock generator of Figure 1.

3 is a schematic diagram of a digital satellite device control device coupled to a set-top box according to a second embodiment of the present invention.

Figure 4 is a schematic diagram of a digital satellite device control apparatus according to a third embodiment of the present invention.

Figure 5 is a schematic diagram of a digital satellite device control apparatus according to a fourth embodiment of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the differences in the functions of the elements as the basis for the distinction. The "contains" mentioned in the entire specification and subsequent claims are open-ended terms and should be explained. It is "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if the first device is described as being coupled to the second device, it is meant that the first device can be directly connected to the second device or indirectly connected to the second device through other devices or connection means.

The following is a detailed description of the present invention in accordance with the present invention, but the embodiments are not intended to limit the scope of the present invention, and the method flow number is not limited to the execution order. The order, any process that is recombined by method steps, produces a method with equal efficiency, which is within the scope of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a digital satellite device control apparatus 100 according to a first embodiment of the present invention. As shown in FIG. 1, the digital satellite device control apparatus 100 includes a radio frequency switch 20, a direct current switch 30, a noise canceling circuit 40, a decoder 50, and a power clock generator 60. The radio frequency switch 20 includes a plurality of input terminals RF1 to RF4, an output terminal 24, and a control terminal 22. The input terminals RF1 to RF4 are used to receive the RF signal, the output terminal 24 is used to output the RF signal input from the input terminals RF1 to RF4, and the control terminal 22 is configured to couple the output terminal 24 according to the first control signal CON1. One of the input terminals RF1 to RF4, that is, the digital satellite device control device 100 switches the received signal source according to the first control signal CON1. The DC switch 30 includes an input terminal 31, a plurality of output terminals DC1 to DC4, and a control terminal 32. The input terminal 31 is coupled to a voltage source DCIN for receiving an input voltage V1, the output terminals DC1 to DC4 for outputting the input voltage V1 received from the voltage source DCIN, and the control terminal 32 is configured to be used according to the second control signal CON2. The input terminal 31 is coupled to one of the output terminals DC1 to DC4. The noise cancellation circuit 40 is for eliminating the DC component of the input voltage V1 and includes an input terminal 42 and an output terminal 44. The input terminal 42 is coupled to the voltage source DCIN to receive the input voltage V1. The output 44 is used to output an AC component of the input voltage V1. The decoder 50 includes a first input terminal 51, a second input terminal 52, a first output terminal 54, and a second output terminal 56. First An input terminal 51 is coupled to the output 44 of the noise cancellation circuit 40 to receive an AC component of the input voltage V1. The first output terminal 54 is coupled to the control terminal 22 of the RF switch 20 to output the first control signal CON1 according to the AC component of the input voltage V1. The second output terminal 56 is coupled to the control terminal 32 of the DC switch 30 to output the second control signal CON2 according to the AC component of the input voltage V1. The power clock generator 60 is configured to provide an operating voltage to the digital satellite device control device 100 and includes an input terminal 62 and a first output terminal 64. The input terminal 62 is coupled to the voltage source DCIN to receive the input voltage V1. The first output end 64 is coupled to the second input end 52 of the decoder 50 to output the clock signal CLK to the second input end 52 of the decoder 50 according to the input voltage V1.

Please refer to FIG. 2A. FIG. 2A is a schematic diagram of the noise cancellation circuit 40 of FIG. As shown in FIG. 2A, the noise canceling circuit 40 includes an analog band pass filter 47 and a digital short time pulse waveform interference canceller 48. The analog bandpass filter 47 is coupled to the voltage source DCIN for canceling the DC component of the input voltage V1 to generate the analog signal S1. The digital glitch canceler 48 is coupled to the analog bandpass filter 47, the power clock generator 60 and the decoder 50 for synchronizing the signal according to the clock signal CLK transmitted from the power clock generator 60. S1 samples and filters the high frequency noise in the analog signal S1 to generate an alternating current component of the input voltage V1. Through the noise canceling circuit 40, it is possible to prevent the decoder 50 from malfunctioning or not operating due to excessive noise of the received output voltage V1.

Please refer to FIG. 2B, which is a schematic diagram of the power clock generator 60 of FIG. As shown in FIG. 2B, the power clock generator 60 includes a clock generator 67 and a clock tuner 68. The clock generator 67 is configured to generate the clock signal CLK, and the clock tuner 68 is coupled to the clock generator 67 for adjusting the clock signal CLK according to the input voltage V1.

Please refer to FIG. 2C, which is another schematic diagram of the power clock generator 60 of FIG. Different from FIG. 2B, the power clock generator 60 of FIG. 2C is set to be additionally included. A second output 66, and the decoder 50 further includes a third input 53. The power clock generator 60 is configured to output a reset signal S2 to the third input terminal 53 of the decoder 50 through the second output terminal 66 to reset the decoder 50 when the digital satellite device control device 100 is powered on.

Please refer to FIG. 3, which is a schematic diagram of a digital set of satellite device control device 100 coupled to a set-top box 80 according to a second embodiment of the present invention. As shown in FIG. 3, the set-top box 80 is coupled to the digital satellite device control device 100 to provide voltage to the satellite device control device 100, and the output terminal 24 of the radio frequency switch 20 of the digital satellite device control device 100 is coupled. The set-top box 80 outputs an RF signal to the set-top box 80. A digital choke 90 is provided between the digital satellite device control device 100 and the set-top box 80.

Please refer to FIG. 4, which is a schematic diagram of a digital satellite device control apparatus 400 according to a third embodiment of the present invention. As shown in FIG. 4, the digital satellite device control device 400 and 100 differ in that the digital satellite device control device 400 further includes a short circuit detecting circuit 70, but does not include the noise canceling circuit 40 in FIG. The first input end 51 of the decoder 50 is coupled to the voltage source DCIN for receiving the input voltage V1, and the first output end 54 is coupled to the control terminal 22 of the RF switch 20 for outputting the AC component according to the input voltage V1. A control signal CON1 is coupled to the control terminal 32 of the DC switch 30 for outputting the second control signal CON2 according to the AC component of the input voltage V1. The short circuit detection circuit 70 is coupled to the plurality of output terminals DC1 to DC4 and the decoder 50 of the DC switch for controlling the decoder 50 to turn off the DC switch 30 when the current of the DC terminals DC1 to DC4 of the DC switch 30 is excessive. Short circuit protection is available.

Please refer to FIG. 5, which is a schematic diagram of a digital satellite device control apparatus 500 according to a fourth embodiment of the present invention. As shown in FIG. 5, the digital satellite device control device 500 and 100 differ in that the digital satellite device control device 500 further includes a short circuit detecting circuit 70. In other words, the digital satellite device control device 500 includes both the short circuit detection circuit 70 and the noise cancellation circuit 40. Therefore, the digital satellite device control device 500 can eliminate the DC component of the input voltage V1 through the noise cancellation circuit 40 to generate the analog signal S1, and can also pass the short circuit detection when the current of the DC switch 30 output terminals DC1 to DC4 is excessive. Circuitry 70 controls decoder 50 to turn off DC switch 30. Therefore, the digital satellite device control device 500 can prevent the decoder 50 from malfunctioning or inoperating due to excessive noise of the received output voltage V1, and has a short circuit protection function.

In summary, the digital satellite device control apparatus 100, 500 can prevent the decoder 50 from malfunctioning or not operating due to excessive noise of the received output voltage V1. And the digital satellite device control devices 400, 500 can provide short circuit protection. In addition, the digital satellite device control devices 100, 400, and 500 need only include an integrated circuit and a capacitor, and do not require components such as a diode, a bipolar transistor, and a resistor. Therefore, compared with the prior art, the present invention The invention of the digital satellite device control device 100, 400, 500 is less complex in circuit design and can reduce cost.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

20‧‧‧RF switch

22, 32‧‧‧ control end

24, DC1 to DC4, 44‧‧‧ output

30‧‧‧DC switch

40‧‧‧ Noise Elimination Circuit

50‧‧‧Decoder

51‧‧‧ first input

52‧‧‧second input

54, 64‧‧‧ first output

56‧‧‧second output

60‧‧‧Power Clock Generator

100‧‧‧Digital satellite equipment control device

CON1‧‧‧ first control signal

CON2‧‧‧second control signal

CLK‧‧‧ clock signal

DCIN‧‧‧voltage source

RF1 to RF4, 31, 42, 62‧‧‧ inputs

S1‧‧‧ analog signal

V1‧‧‧ input voltage

Claims (8)

A digital satellite equipment control (Diseqc) device includes: a radio frequency (RF) switch, comprising: a plurality of inputs for receiving RF signals; and an output for outputting the plurality And the input end of the RF switch is coupled to one of the plurality of input ends of the RF switch according to a first control signal; the DC switch The method includes: an input end coupled to a voltage source for receiving an input voltage; a plurality of output terminals for outputting the input voltage; and a control end for the DC switch according to a second control signal The input end is coupled to one of the plurality of output ends of the DC switch; a noise canceling circuit for canceling the noise of the input voltage, comprising: an input end coupled to the voltage source, Receiving the input voltage; an output terminal for outputting an AC component of the input voltage; and an analog bandpass filter coupled to the voltage source for canceling the DC voltage of the input voltage And a digital short-time pulse waveform interference canceller; a decoder comprising: a first input coupled to an output of the noise cancellation circuit for receiving the input voltage An AC component; a first output end coupled to the control end of the RF switch for outputting the first control signal according to an AC component of the input voltage; and a second output terminal coupled to the DC switch control End, according to the input power The AC component of the voltage outputs the second control signal; and a power clock generator for providing the operating voltage and the working clock to the digital satellite device control device, comprising: an input terminal coupled to the voltage source, Receiving the input voltage; and a first output end coupled to the second input end of the decoder, for outputting a clock signal to the second input end of the decoder according to the input voltage; wherein the digit is short-lived a pulse waveform interference canceller coupled to the analog bandpass filter, the power clock generator, and the decoder for sampling and filtering the analog signal according to a clock signal transmitted by the power clock generator The analog high frequency noise in the signal produces an alternating component of the input voltage. The digital satellite device control device of claim 1, further comprising a short circuit detecting circuit coupled to the plurality of output ends of the DC switch and the decoder for controlling when the current of the output of the DC switch is excessive The decoder turns off the DC switch. A digital satellite device control device comprising: an RF switch comprising: a plurality of input terminals for receiving RF signals; an output terminal for outputting RF signals input by the plurality of input terminals; and a control terminal for The output end of the RF switch is coupled to one of the plurality of input terminals of the RF switch according to a first control signal; the DC switch includes: an input end coupled to a voltage source, Receiving an input voltage; a plurality of output terminals for outputting the input voltage; and a control terminal for coupling the input end of the DC switch to the plurality of output ends of the DC switch according to a second control signal One of the outputs; a decoder, comprising: a first input end coupled to the voltage source for receiving the input voltage; a first output end coupled to the control end of the RF switch for communicating according to the input voltage The component outputs the first control signal; and a second output terminal coupled to the control terminal of the DC switch for outputting the second control signal according to the AC component of the input voltage; a power clock generator for Providing an operating voltage to the digital satellite device control device, comprising: an input coupled to the voltage source for receiving the input voltage; and a first output coupled to the second input of the decoder for use And outputting a clock signal to the second input end of the decoder according to the input voltage; and a second output end coupled to the third input end of the decoder for outputting when the digital satellite device control device is turned on a reset signal to the third input of the decoder to reset the decoder; and a short circuit detection circuit coupled to the plurality of output terminals of the DC switch and the decoder for use as the DC switch Output The current through the control of the decoder closing the DC switch is large. The digital satellite device control device of claim 1 or 3, wherein the power clock generator further comprises: a clock generator for generating the clock signal; and a clock tuner coupled to the clock generation The device is configured to adjust the clock signal according to the input voltage. The digital satellite device control device of claim 1 or 3, wherein the digital satellite device control device is coupled to a set-top box. The digital satellite device control device of claim 5, wherein the digital satellite device control device and the set-top box have a choke. The digital satellite device control device of claim 1 or 3, wherein the output of the radio frequency switch is coupled to a set-top box. A digital satellite device control device comprising: an RF switch comprising: a plurality of input terminals for receiving RF signals; an output terminal for outputting RF signals input by the plurality of input terminals; and a control terminal for The output end of the RF switch is coupled to one of the plurality of input terminals of the RF switch according to a first control signal; the DC switch includes: an input end coupled to a voltage source, Receiving an input voltage; a plurality of output terminals for outputting the input voltage; and a control terminal for coupling the input end of the DC switch to the plurality of output ends of the DC switch according to a second control signal One of the output terminals; a noise cancellation circuit for canceling the noise of the input voltage, comprising: an input terminal coupled to the voltage source for receiving the input voltage; and an output terminal for outputting An AC component of the input voltage; a decoder comprising: a first input coupled to the output of the noise cancellation circuit for receiving an AC component of the input voltage; a first output , Coupled to the control terminal of the radio frequency switch of to the first control signal AC input voltage component of the output in accordance with; and a second output end coupled to the control end of the DC switch for outputting the second control signal according to an AC component of the input voltage; and a power clock generator for providing the digital satellite device control device The operating voltage and the operating clock include: an input coupled to the voltage source for receiving the input voltage; a first output coupled to the second input of the decoder for receiving the input The voltage output is a clock signal to the second input end of the decoder; and a second output end is coupled to the third input end of the decoder for outputting a reset signal when the digital satellite device control device is turned on To the third input of the decoder to reset the decoder.