TWI470796B - Power ldmos transistor - Google Patents

Description

Power lateral diffusion metal oxide semiconductor transistor

The present invention relates to semiconductor structures and more specifically to laterally diffused MOS transistors (LDMOS) and methods of fabricating the same.

Power MOSFETs (MOSFETs) are used, for example, as electrical switches for high frequency PWM (Pulse Width Modulation) applications such as voltage regulators and/or power applications. Load switcher in the middle. When used as a load switch, where the switching time is usually very long, the cost, size and on-resistance of the switches are primarily designed. When used in PWM applications, the transistors must exhibit low power losses during switching, which is accompanied by an additional requirement, namely small internal capacitance, which makes the MOSFET design challenging and often expensive. Special attention has been placed on gate-to-drain (Cgd) capacitors, so the capacitance determines the voltage transient time during switching and is the most important parameter affecting the switching power loss.

An example of a prior art laterally-dividing power MOSFET device is provided by U.S. Patent No. 5,949,104 to D'Anna et al., and U.S. Patent No. 6,831,332 to D. Both devices use a thick epitaxial layer to achieve the high breakdown voltage (>60 V) required for target RF applications. To minimize parasitic source inductance in the assembly, both devices are designed on the P+ substrate and cause the source electrode to appear on the back side of the die. The thick epitaxial layer and the P+ substrate cause the device to generate a high on-resistance (R _ds , _on ) that is not acceptable for power management applications.

Another prior art laterally diffused metal oxide semiconductor device is disclosed in U.S. Patent No. 6,600,182 to Rumennik, entitled "High Current Field-Effect Transistor". The Rumennik device includes a drain region having a first portion that extends through the epitaxial layer and extends perpendicularly to connect to the substrate and a second portion that extends laterally along a top surface of the device. The device has a low specific on-resistance and supports high current flow. However, the breakdown voltage of the device is highly dependent on the position of the first portion of the drain region, which narrows the manufacturing tolerance of the device.

There is still a need for a laterally diffused metal oxide semiconductor design that exhibits improved device performance (R _ds , _on and Cgd ) and improved manufacturability.

A laterally diffused metal oxide semiconductor device is provided comprising a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. The source and drain regions of the first conductivity type are formed in an epitaxial layer adjacent to the upper surface, and the source and drain regions are spaced apart from each other and have the epitaxial layer A channel region of a second conductivity type formed therebetween while the channel region extends below the source region. A conductive gate is formed over a gate dielectric layer formed over the channel region and partially overlaps the source and drain regions. A drain contact electrically connects the drain region to the substrate and is spaced apart from the channel region, and includes a first trench formed from an upper surface of the epitaxial layer to the substrate and having a A highly doped region of a first conductivity type formed along a sidewall of the epitaxial layer, a sidewall along the first trench sidewall, and a drain inserted in the first trench adjacent to the highly doped region. A source contact is electrically connected to the source region and provides an electrical short between the source region and the channel region. An insulating layer is formed between the conductive gate and the source contact.

In an alternative embodiment, the gate contact includes a highly doped gate contact region formed between the substrate and a drain extension region in the semiconductor layer, wherein the highly doped gate contact One of the topmost portions of the region is spaced apart from the upper surface of the semiconductor layer. A source contact electrically couples the source region to the body region.

The above and other features of the present invention will be more fully understood from the detailed description of the preferred embodiments of the invention.

As used herein, the following dopant concentrations are distinguished by the following notation: (a) N++ or P++: dopant concentration > 5x10 ¹⁹ atoms/cm ³ ; (b) N+ or P+: dopant concentration Approximately 1x10 ¹⁸ to 5x10 ¹⁹ atoms/cm ³ ; (c) N or P: a dopant concentration of about 5 x ^{10 16} to 1 x 10 ¹⁸ atoms/cm ³ ; (d) N- or P-: dopant concentration is about 1x10 ¹⁵ to 5x10 ¹⁶ atoms/cm ³ ; and (e) N-- or P--: a dopant concentration of about <1x10 ¹⁵ atoms/cm ³ .

In the following description, numerous specific details are set forth, such as material type, doping amount, structural features, processing steps, and the like, in order to provide a thorough understanding of the present invention. Those skilled in the art will appreciate that the invention described herein can be practiced without a substantial portion of the details. In other examples, well-known components, techniques, features, and processing steps are not described in detail to avoid The invention is difficult to understand.

It is also to be understood that the elements in the drawings are representative and are not intended to It will also be appreciated that the p-channel transistor can be realized by having all of the illustrated diffusion/doping regions utilize the opposite conductivity type.

1 illustrates a specific embodiment of an improved power transistor, more specifically an improved laterally diffused metal oxide semiconductor transistor 10. In an exemplary application, the transistor 10 is used as a switch in a power supply voltage regulator such as a server or desktop computer or in a commonly used DC/DC converter.

More specifically, Figure 1 shows an improved n-channel laterally diffused metal oxide semiconductor device. The transistor structure 10 includes a semiconductor substrate 12, which in the illustrated embodiment is preferably a highly doped (N+) germanium wafer doped with, for example, arsenic or phosphorous. The highly doped (N+) substrate has a lower electrical resistance than the P+ substrate, although in alternative embodiments the substrate 12 may be P+ doped. In some embodiments, a drain electrode 11 is formed along the bottom of the substrate 12 and electrically connected to the N+ substrate 12. Metallizing the bottom surface of the substrate 12 in this manner facilitates future connections to a packaged electrode (not shown). In an exemplary embodiment, the substrate 12 has a thickness of less than or equal to about 3 mils (76.2 μm) to provide a very low resistance contact to the gate electrode and to cause the substrate to be bonded to the transistor. The effect of on-resistance is minimized. The substrate can be ground and/or etched or otherwise formed to the desired thickness. These procedures will typically be completed near the end of the substrate wafer process.

A lightly doped germanium epitaxial layer 14 is formed on the substrate 12 and has An upper surface 15. In some embodiments, the epitaxial layer 14 can have a dopant of the N (arsenic or phosphorous) or P (boron) dopant type and an N-, N-, P- or P-- Dopant concentration. In a specific embodiment, the epitaxial layer has a thickness of between about 1.5 and 3.5 μm.

The doping of the epitaxial layer is typically lower than the doping concentration of the implanted source/drain regions. On the other hand, in the case of a device having a vertical current, the background doping of the epitaxial layer is preferably as high as possible in order to reduce the on-resistance (Rds, on) between the drain and the source. And just enough low to meet the target breakdown voltage of the transistor. However, with the present device, since current will flow through the vertical drain contact region 22, and the doping concentration can be maintained low, for example, less than 2x10 ¹⁶ atoms/cm ³ , and more preferably equal to or Below 8x10 ¹⁵ atoms/cm ³ , the original doping of the epitaxial layer has no effect on the resistance of the device.

A conductive gate 31 is overlaid on the upper surface 15 of the epitaxial layer 14. In the embodiment illustrated in FIG. 1, the conductive gate 31 includes a lower doped polysilicon layer 30 having a germanium formed thereon or thereon by a procedure well known to those skilled in the art. Object layer 32. The telluride layer 32 can comprise any transition metal halide, and in an exemplary embodiment is selected from the group consisting of Ti, W, and Co. The conductive gate preferably has a thickness of between about 0.3 and 0.6 μm, and a length defined by the technique for its manufacture, such as 0.8 μm, 0.5 μm, 0.35 μm or 0.25 μm. The conductive gate 31 is formed on a gate dielectric 36, which preferably includes forming a level of between about 150 and 500. The thickness of SiO ₂ .

The drain region 20 is completely formed in the epitaxial layer 14 and forms an enhanced Bungee drift area. The enhanced drain drift region 20 is formed against or at least adjacent to the upper surface 15 of the epitaxial layer 14, and has a dopant concentration N in the illustrated embodiment. The enhanced drain drift region 20 enhances the drain-to-source breakdown voltage of the laterally diffused metal oxide semiconductor structure 10. The drain drift region 20 has a lateral dimension between about 0.5 and 1.5 μm and a depth between about 0.2 and 0.4 μm. The region 20 preferably extends between the conductive gates (i.e., the conductive gates overlap) between about 0.05 and 0.15 μm, and is disclosed in the literature of U.S. Patent No. 5,907,173 to Kwon et al. Lightly doped drain (LDD) structures are known, all of which are incorporated herein by reference.

The laterally diffused metal oxide semiconductor structure 10 also includes a source implant region 18 having a conductivity N+ that is spaced apart from the enhanced drain drift region 20. The source region 18 extends laterally between about 0.5 and 0.8 μm, has a depth of between about 0.15 and 0.3 μm, and is also partially located between the conductive gates and between about 0.05 and 0.15 μm. A body region 16 having a P-type dopant and having a P concentration conductivity is formed in the epitaxial layer 14 and has a region between the source electrode 18 and the enhanced drain region 20 while Form a channel area. The body region 16 includes a body contact region 26. In an exemplary embodiment, the body region 16 is formed to a depth of between about 0.5 and 1.0 μm and a horizontal length of between about 0.8 and 1.5 μm.

The body contact region 26 has a dopant concentration P++ that is greater than the concentration of the body region 16. In a specific embodiment, the body contact region 26 is formed at the base of a shallow trench region 19 and has a lateral dimension. It is between about 0.1 and 0.3 μm and is formed to a depth of between about 0.1 and 0.3 μm. The body contact region 26 provides a low resistance contact between the source metal layer 28 (described in greater detail below) and the body region 16. In the case where a voltage is applied to the drain electrode to cause a reverse bias of the body to the drain PN- junction, the depletion layer or region is implanted at the junction 26 and doped from the substrate 12. The gradient is "squeezed" in the vertical direction. The reduction in the width of the depletion layer results in a lower source-drainage breakdown voltage that would be where the collapse occurred below the junction implant. Next, the above will define a path for the current generated during the sag situation, wherein the sag condition is that the electric field at the PN-junction of the body is extremely high, thereby causing a minority load to be generated by collision. Child time.

A deep trench region 25 (shown by a plug 24) is formed adjacent to the enhanced drain drift region 20 and spaced apart from the conductive gate 31. The trench 25 is formed from the upper surface 15 of the epitaxial layer 14 to the upper surface of the substrate 12. The trench 25 is formed such that the vertical drain contact region 22 can be adjacent to the sidewall of the trench region 25, which provides a low resistance path between the enhanced drain drift region 20 and the substrate 12, and the low resistance path thus reaches The drain electrode 11. In the n-channel embodiment shown in FIG. 1, the drain contact 22 has a dopant concentration N+ or higher and is formed by low angle implantation while the trench 25 is open. The trench 25 is then filled with a conductive material (e.g., tungsten or doped polysilicon) or an insulating material (e.g., Si _x O _y ) to form the plug 24. In one embodiment, the drain contact 22 enters the epitaxial layer 14 in a total size of about 0.4 to 0.8 μm. In other embodiments, the epitaxial layer is very thin (eg, 1.5 μm) and does not need to be etched to form the drain contact implant 22. In this particular embodiment, the drain contact 22 is created by a diffusion region (s) of a first conductivity type that is created by multiple implantations while extending from the surface to the substrate. In this embodiment, since no deep trenches 25 are formed, there is no need for a drain plug.

The device 10 also includes an insulating layer 34 formed over the upper surface 15 of the epitaxial layer, and thus over the source implant region 18, over the sidewalls of the conductive gate 31 and above its upper surface. And the enhanced drain drift region 20 and the contact plug 24. The insulating layer 34 preferably comprises SiO ₂ or SiO _x N _y . However, it should be understood that the insulating layer 34 can include a plurality of layers of insulating material that collectively form the insulating layer 34. The insulating layer 34 is preferably formed on the sidewall of the conductive gate 31 to a thickness of at least 0.03 μm, and a top surface of the conductive gate 31 is formed to a thickness of at least 0.05 μm. In an exemplary embodiment, the insulating layer 34 is formed on the drain region 20 to a thickness of between about 0.05 and 0.15 μm. The insulating layer insulates the drain regions 20 from the gate 31 and the source metal layer 28, as will be described below.

As shown in FIG. 1, device 10 also includes a source metal layer 28, which preferably includes a group selected from the group consisting of Al, Ti/Al, Ti/TiN/Al, or W by, for example, CVD (Chemical Vapor Phase) Depositing or sputtering to blanket the conductive material deposited on the device. The deposited source metal layer 28 is intended to fill the shallow trench 19, thereby providing a contact between a source electrode and the source implant 18, and providing a source between the source region 18 and the body region 16. Short circuit. The source metal layer 28 extends over the insulating layer 34, the conductive gate 31, and the drain implant region 20 and the drain plug 24. In a specific embodiment, the source The metal layer 28 has a thickness defined between the upper surface 15 of the epitaxial layer 14 and its upper surface 29, which is between about 1.0 and 5.0 μm.

When the laterally diffused metal oxide semiconductor transistor device 10 is "on", the conductive current flows through the source metal 28 and laterally penetrates the channel below the gate 31 to the drain region 20, The gate electrode 12 is then vertically and highly doped, and the substrate 12 is vertically penetrated to the gate electrode 11 on the bottom side of the device 10.

The source metal structure 28 of Figure 1 provides a number of advantages. First, a single metal layer can serve as a source contact and a shield electrode that shields the conductive gate from the drain contact 22 and reduces the capacitance between the gate and the drain ( Cgd). It is not necessary to form a separate shielding gate, and it is not necessary to separately connect the shielding gate to the source. Thereby the manufacturability of the device is greatly improved.

In addition, the drain-source resistance (Rsd) is optimized by using an N+ substrate. As will be appreciated by those skilled in the art, n-channel devices designed for RF applications are typically formed on a P+ substrate because of the importance of having a source electrode system at ground potential at the bottom of the die. While n-channel devices may be preferred due to their lower channel resistance compared to p-channel devices, prior art P-doped substrates provide much higher resistance than n-substrate, typically 2 to 3 times higher. However, the device 10 provides an n-channel device on a low resistance n-doped substrate.

An exemplary method of forming device 10 will now be described. Certain details that are apparent to those skilled in the art will be eliminated so as not to obscure the invention. Substrate 12 has a predefined N+ dopant concentration. have An epitaxial layer 14 of N- or P-dopant concentration is then formed on the upper surface of the substrate 12. A first trench is etched through the epitaxial layer after depositing and patterning a thin oxide layer for use as a dedicated drain contact mask. The sidewalls of the trench are N+ doped with a suitable implant of 7 degrees to form the drain contact regions, wherein the dopant is preferably phosphorus or arsenic. The first trench is filled with a material to form a drain plug. In one embodiment, the trench is filled with N+ doped polysilicon. Next, the polysilicon is etched back to a level slightly below the surface of the epitaxial layer, and the oxide mask is removed.

After the gate contact and the plug regions are formed in the epitaxial layer 14, a thin gate oxide layer is formed on the epitaxial layer upper surface 15. Next, a polysilicon layer is deposited and etched to form a polysilicon gate. The telluride layer 32 is then formed using a well-known self-aligned germanide process, or a germanide layer is deposited on the polysilicon layer and then etched to form the stacked polysilicon/germanide structure shown in FIG. Subsequent to the formation of the vaporized layer 32, the P-body or N-enhanced drift region is formed by a masked implantation and thermal diffusion step of individual dopants. The sidewall spacers adjacent the conductive gate can be formed separately using a known sidewall spacer procedure if desired. For example, an oxide layer can be deposited and then etched back by an anisotropic reactive ion etching (RIE). The N+ source region is formed by implanting arsenic as a mask using a patterned photoresist.

An oxide layer 34 is deposited over the upper surface 15 and the conductive gate 31 to a desired thickness. Next, the shallow trench 19 is patterned and etched to the desired depth, and then the implanted region 26 is formed. Finally, a metal layer is deposited over the monolithic structure to form the source metal layer 28. Thinning the original structure To a desired thickness, a backside metal layer 11 is deposited to form the drain electrode. Subsequently, the device was packaged and tested.

Figure 2 illustrates a second embodiment 10A of an improved laterally diffused metal oxide semiconductor device. The device 10A is identical in all respects to the device 10 of Figure 1, and similar features are indicated by similar reference codes, with the exception of the modified insulating layer 34A and the modified source metal layer 28A. It will be appreciated that the modification of source metal layer 28A is only limited to deposition on modified insulating layer 34A. In the region adjacent the drain implant region 20 and the drain plug 24, the modified insulating layer 34A has two thicknesses. More specifically, the modified insulating layer 34A has a thicker region, generally designated 35, formed over the drain plug 24 and a portion of the drain region 20, and a thinner portion 37 is formed over Above the drain region 20, between the thicker portion 35 and the gate 31. In one embodiment, the length of the thin oxide region 37 may be between the gate 31 and the drain plug 24. to . In an exemplary embodiment, the thinner portion 37 has a thickness between about 0.05 and 0.15 μm, and the thicker portion 35 has a thickness between about 0.2 and 0.5 μm. The improved insulating layer 34A can be formed by etching a thicker oxide layer deposited after forming the drain plug region. The thin oxide region 37 is deposited after the gate is formed and its thickness is added to the final thickness of the region 34A, which includes the portion 35.

In the embodiment of FIG. 2, the source metal layer 28A not only provides a pair of contacts between the source region 18 and the body region 16 and a shield between the gate 31 and the gate contact 22, It will also optimize the plate effect of the field. The thin oxide region 37 will be very effective at the gate corner by pushing the depletion layer away from the PN-junction between the body region 16 and the drain 20. If the thinner oxide extends laterally to cover all of the drain region 20 and the drain plug 24, a high electric field peak will be located at the corner of the N-N+ drain contact. Making the oxide thicker at 35 mitigates the electric field between the source metal and the drain contact region 22. The doping and length of the drain region under the field plate, the oxide step position between regions 37 and 35, and the oxide thickness can be optimized for a given breakdown voltage target. As an example, for a target breakdown voltage of 20 V, the design of this part of the transistor can be as follows: - total gate to drain plug distance is 0.8 to 1.2 μm; - thin oxide region length is 0.5 Up to 0.8 μm; - the thinner oxide region has a thickness of 0.06 to 0.1 μm; - the thicker oxide region has a thickness of 0.2 to 0.3 μm; and - the dose and energy of the LDD implant is 5x10 ¹² to 7x10 ¹² atoms/cm ² with 80 to 150 keV.

FIG. 3 illustrates another alternative embodiment 10B of the laterally diffused metal oxide semiconductor device of FIG. 1 or 2. The device 10B of Figure 3 is identical to the devices 10, 10A except for the following aspects: reducing the depth of the body implant region 16B and providing a first buffer region 38 between the body region 16B and the substrate 12. In an exemplary embodiment, the first buffer region 38 includes a germanium layer doped with a P-dopant to a concentration equal to or greater than the dopant concentration of the body region 16B. The buffer layer 38 will abut the side walls of the vertical drain contact 22 and is preferably formed to a thickness of between about 0.3 and 0.6 μm. In a specific embodiment, the buffer layer 38 is deepened by boron. The implant is formed by implanting the epitaxial layer 14. In the specific embodiment 10B from Figure 3, this deep implant is performed after patterning the thicker oxide 34A, but before forming the gate. The buffer layer 38 serves to suppress short-channel effects sufficiently described in the document by helping to confirm that the depletion region has not reached too far in the channel.

In the embodiment of FIG. 3, the location of the collapse is still based in part on the thickness of the epitaxial layer 14, and in part on the doping concentration of the substrate 12. Referring to the specific embodiment 10C of FIG. 4, the buffer layer 38 is replaced by a thinner p-buffer layer 38C and a second buffer layer 40 having a dopant concentration N. In the dual depth implant buffer structure, the collapse location is advantageously located at or around the P-N junction between the buffer layer 38C and the buffer layer 40, such that the collapse location is primarily associated with the epitaxial layer. The thickness is independent of the dopant concentration of the substrate 12. Deep implantation of an N dopant, preferably phosphorous, to form the second buffer layer 40 is performed at the beginning of the program flow, after deposition of the epitaxial layer 14.

Figure 5 illustrates the termination of the edge at the peripheral unit of the device of Figure 2, so that no gate is shown. The edge-terminated structure is important from a design perspective because it closes the P-N junction in a manner that confirms the target breakdown voltage. The illustrated edge termination region will surround the active region of the transistor produced by the P-well 16. It will be appreciated that a single die may have a plurality of equal transistor cells that are fabricated in parallel as explained above and that operate as a single transistor in, for example, a power switch. As explained above in connection with Figure 2, the source metal 28A extends beyond the P-well 16 and acts as a field plate (which affects the breakdown voltage in this region of the device). An insulating layer under the field plate portion of layer 28A (also described with reference to code 35) There is a thickness between about 0.2 and 0.5 μm, which is like the thicker oxide portion 35 of the insulating layer 34A shown in Figures 2 through 4. The drain plug 24 is formed at an edge of the cut crystal grain in which the transistor is formed, or adjacent to an edge of the cut crystal grain in which the transistor is formed, that is, the die is from the drain Adjacent grains on the plug 24 or on the wafer adjacent to the drain plug 24 are cut. The edge termination region ends with a drain plug 24 that separates the transistor from the edge of the dicing die. This structure illustrated forms the normal result of the structure of Figure 2.

In a preferred embodiment, the background layer of the epitaxial layer is 1×10 ¹⁶ atoms/cm ³ , and the P-well 16 is formed by implanting the body 16 with the overlap depth buffer 38 ( FIG. 3 ). The distance between the P-well and the bungee plug is 1.5 μm. This edge termination supports a breakdown voltage above 35 V.

In an exemplary application, the improved power laterally diffused metal oxide semiconductor device is fabricated in parallel with a plurality of other similar structural devices and packaged for use as a power transistor in, for example, a DC/DC voltage regulator. .

Figures 6 to 10 show the electrical characteristics of the 20 V device 10 of Figure 4 obtained by numerical simulation with a maximum breakdown voltage of 20 V and a maximum allowable source-to-gate voltage of 12 V of 1 mm ² active region. And has a gate thickness of 300 . Figure 6 shows the relationship between the drain current and the drain voltage as Vgs equals 2.0, 2.5, 3.0, 4.0, and 5.0 volts. The flat Ids curve in the saturated region (Vds > 1 V) shows that the electro-crystalline system is not affected by the short channel effect.

Figure 7 shows the resistance of a device with a 1 mm ² active region as a function of gate voltage when the drain voltage is 0.1 V. It can be seen that the expected resistance at a Vgs of 4.5 V is about 13 mΩ*mm ² , while the resistance of a similar device of the present technology is higher than 20 mΩ*mm ² .

Figure 8 shows the relationship between the drain current and the gate voltage as the drain voltage is 5 V. It can be seen that the threshold voltage of the transistor is kept below a low value of 1.5 V, which is advantageous for power applications. Conversely, modern power MOSFETs with short channel lengths typically produce a much higher threshold voltage, which is greater than 2.2 V to protect the device from short channel effects.

Figure 9 shows the capacitance Ciss, Coss, and Crss as a function of the drain voltage, where CiSS is the input capacitance (Cgs+Cgd), the Coss output capacitance (Cds+Cdg), and the Crss feedback capacitance (Cdg). The Cdg system is very close to Cgd, depending on the endpoint to which the source signal is applied, and at what endpoint the response signal is measured. In general, the proposed device will have a smaller capacitance than commercially available products. Specifically, the feedback capacitor Crss (approximately equal to Cgd) is less than five times the existing similar power MOSFETS.

Finally, Figure 10 shows a gate charge curve. It can be seen from this curve that a gate voltage of 5 V can be achieved by charging the gate only at 2.2 nC/mm ² . This is a very low charge, which provides an acceptance of the benefits of Rds (Vgs = 10 V) * Qg (VS = 5 V) of 22 mΩ * nC, while similar devices of the present technology produce above 50 mΩ * nC value.

As mentioned above, the improved power laterally diffused metal oxide semiconductor device is provided with an n-channel transistor formed on a low resistance N-substrate. The device exhibits a low on-resistance (R _ds-on ) by reducing the resistance of the substrate and exhibits a low Cgd capacitance by minimizing electrostatic coupling between the gate and the drain electrode. In a specific embodiment, the source contact extends over the gate and drain regions to provide a high current capability.

Figure 11 illustrates an alternative embodiment of an improved power transistor, more specifically an improved laterally diffused metal oxide semiconductor transistor 10D. In an exemplary application, the transistor 10D is used as a switch in a power supply voltage regulator such as a server or desktop computer or in a commonly used DC/DC converter.

More specifically, Figure 11 shows an improved n-channel laterally diffused metal oxide semiconductor device 10D. As noted above, the transistor structure 10D includes an N+ doped semiconductor substrate 12, although in alternative embodiments the substrate 12 can be P+ doped. In a specific embodiment, a drain electrode 11 is formed along the bottom of the substrate 12 and electrically connected to the N+ substrate 12.

As described above, a semiconductor layer is formed over the substrate 12. In a specific embodiment, the semiconductor layer is a lightly doped germanium epitaxial layer 14 formed on the upper surface of the substrate 12. The epitaxial layer 14 has an upper surface, which is referred to by reference numeral 15. The epitaxial layer is lightly doped at the time of manufacture based on reasons not related to this disclosure, and then doped to form the illustrated doping profile, as explained in more detail below. In one embodiment, the epitaxial layer 14 has a thickness of between about 1.5 and 3.5 μm. The thickness of the epitaxial layer is referred to as the metallurgical thickness of the grown layer.

The doping of the epitaxial layer 14 is typically much lower than the doping concentration of the implanted source/drain regions. Since current will flow through the vertical drain contact region 23 (described below), the original doping of the epitaxial layer has no effect on the resistance of the device. In a specific embodiment, the initial doping concentration can be kept low, for example, less than 2 x 10 ¹⁶ atoms/cm ³ , and more preferably equal to or lower than 8 x 10 ¹⁵ atoms/cm ³ . A conductive gate stack 31 (described above) is overlaid on the upper surface 15 of the epitaxial layer 14.

The drain implant region 20 is completely formed within the epitaxial layer 14 and forms an enhanced drain drift region (labeled LDD-N). As used herein, this region is also referred to as a bungee extension region. The drain extension region 20 is formed adjacent or at least adjacent to the upper surface 15 of the layer 14, and in the illustrated embodiment has a dopant concentration N that is less than the highly doped source region The dopant concentration of 18 (N+). As will be appreciated by those skilled in the art, this drain extension region 20 increases the drain-to-source breakdown voltage of the laterally diffused metal oxide semiconductor structure 10D. The LDD extension region 20 has a lateral dimension of between about 0.3 and 1.5 μm and a depth of between about 0.2 and 0.4 μm, although such dimensions will vary depending on the desired breakdown voltage rating of the device. The region 20 preferably extends below the conductive gate 31 (i.e., overlapped by the conductive gate 31) by between about 0.05 and 0.15 μm.

The laterally diffused metal oxide semiconductor structure 10D also includes a source implant region 18 having a conductivity N+ that is spaced apart from the enhanced drain drift region 20. The source region 18 extends laterally between about 0.3 and 0.8 μm, has a depth between about 0.15 and 0.3 μm, and is also partially located below the conductive gate 31 between about 0.05 and 0.15 μm. At the office. The gate 31 slightly overlaps the source region 18 and the drain region 20 to provide continuous conduction in the channel region of the device.

a body region 16 having a P-type dopant and having a P concentration conductivity It is formed in the epitaxial layer 14 and has a primary region between the source 18 and the enhanced drain region 20 while forming the channel region therebetween. The body region 16 includes a body contact region 26. In an exemplary embodiment, the body region 16 is formed to a depth of between about 0.5 and 1.0 μm and a horizontal length of between about 0.8 and 1.5 μm.

The body contact region 26 has a high dopant concentration (e.g., P++) that is greater than the dopant concentration of the body region 16. As described above, in one embodiment, the body contact region 26 is formed at a base of the shallow trench region 19 formed in the epitaxial layer 14 and has a half width transverse dimension of between about 0.1 and 0.3. Between μm (meaning the width of one of a pair of adjacent cells), and a depth between about 0.1 and 0.3 μm. The body contact region 26 provides a low resistance contact between the source metal layer 28 and the body region 16. In the case where a voltage is applied to the drain electrode to cause a reverse bias of the body to the drain PN-junction, the depletion layer or region is implanted at the junction 26 and from the N doping The doping gradient of the buffer layer 17 or the N+ doped substrate 12 is "squeezed" in the vertical direction (in the few embodiments there is no N-buffer 17). The reduction in the width of the depletion layer results in a lower source-drainage breakdown voltage, but where the collapse occurs below the junction implant region 26. Subsequently, the above will define the current path for the period of time during the sag, where the electric field at the PN- junction of the body is extremely high and the minority carrier is made by impact ionization. When it is produced.

While the collapse voltage below the implanted region 26 may be lower than the collapse voltage along the top surface of the drain extension region 20, offsetting the collapse location provides a number of benefits. First, the hot carrier that occurs when, for example, the transistor is turned off is generated away from the gate stack 31 and improves the reliability of the gate oxide 36. The electric field at the corner region of the gate oxide never reaches the threshold level. Second, in several embodiments, the doping concentration of the drain extension region can be increased (to a higher portion of the doping range of the "N" implant), thereby reducing its lateral resistance and reducing the device. Any associated effects of Rds, on. A peak concentration of 1 x 10 ¹⁷ atoms/cm ³ or more can be achieved when the observed charge balance design criteria are as described below.

The transistor device 10D also includes an insulating layer 34 as described above.

As briefly described above, the apparatus includes a highly conductive region 23 formed in the epitaxial layer 14 and electrically connecting the drain extension region 20 to the conductive substrate 12. In prior art laterally diffused metal oxide semiconductor transistor devices, the breakdown voltage of the transistor is highly sensitive to any change in the separation between the end edge of the gate contact and the gate 31. This distance defines the length of the drain extension region and may vary in the manufacturing process as it relates to the alignment tolerance of both the gate 31 and the gate contact. The change in length of the LDD extension region then optimizes device design difficulties and narrows the manufacturing window.

In a preferred embodiment of the apparatus of FIG. 11, the conductive region 23 is an N+ doped implant region 23 formed between the substrate 12 and the drain extension region 20. This doped region 23 is laterally and vertically spaced apart from the gate 31. The topmost portion of the doped region 23 is also vertically spaced from the upper surface 15 of the epitaxial layer 14 (i.e., recessed from the upper surface 15 of the epitaxial layer 14). In several embodiments, the doped region 23 is at least a portion of the drain extension region 20 It is spaced apart from the upper surface 15 of the epitaxial layer 14. In some embodiments, the highly doped implant region 23 can extend partially into the drain extension region 20, although in some preferred embodiments it is substantially limited to the drain extension region 20 and the substrate. 12 defined zones, and only electrical contacts are made to the bungee extension zone 20. The doped gate contact region 23 provides a low resistance path between the drain extension region 20 and the substrate 12 and thus reaches the drain electrode 11. In the n-channel embodiment shown in FIG. 11, the drain contact 23 has a dopant concentration of N+ or higher. In one embodiment, the drain contact 23 has a horizontal width in the epitaxial layer 14 of about 0.2 to 0.4 μm (half width).

The use of the N+ doped region 23 as a junction between the drain extension region 20 and the substrate 12 provides a number of manufacturing and operational benefits. This doping profile can be readily applied to a low voltage MOSFET where the doped flat portion of the epitaxial layer 14 is very short and typically is between about 0.5 and 2.5 μιη. For example, in the case of an n-channel MOSFET designed with Vds, max of 20 V, the drain plug region 23 can be formed by two consecutive phosphorous implants. In this particular embodiment, the first implant at 200 keV with a dose of 8e12 cm ^-2 at 800 keV and the second implant has a dose of 8e12 cm ^-2. A double layer formed by a photoresist having a thickness of about 1.3 μm covering a thickness of about 1.5 μm over the upper surface 15 of the epitaxial layer 14 shields the implants.

The doped gate contact region 23 produces a region of high conductivity that is interposed between the drain extension region 20 and the dopant profile produced by the substrate 12 of the epitaxial layer 14. The preferred doping concentration for this region is at least 1 x 10 ¹⁸ atoms/cm ³ . An important feature of the doped gate contact region 23 is that the region is substantially or completely confined below the drain extension region 20. This feature makes the breakdown voltage of the transistor 10D much less sensitive to changes in the distance between the drain contact and the conductive gate 31, thus improving the processing window of its fabrication. As also explained below, the modified structure allows the drain region 20 to be designed to have a shorter length (a level of 70% to 90% of the original LDD length) compared to a device having the same breakdown voltage. This, in turn, results in a smaller distance between the active cells, which in turn increases the channel density of the MOSFET per unit area, reducing the specific resistance of the device (Rds, on* area). In the absence of such a recessed design, the drain extension region must be relatively long such that the drain contact is laterally spaced from the conductive gate to reduce the high electric field along the surface of the epitaxial layer. If the gate contact is not recessed, the collapse occurs parallel to the surface of the epitaxial layer and the depletion region is squeezed to approach the surface of the epitaxial layer, and the long LDD extension region needs to be accommodated. This crash is such that a target crash voltage can be reached. In the case of the design of Figure 11, the high electric field deepens into the epitaxial layer and a gradient of the impact ionization intensity (e.g., about 45 angstroms) is observed. This high electric field occurs at the region where the conductivity is the highest (i.e., the depressed gate contact region 23 is not the gate region 20). This makes the design easier and the breakdown voltage higher (for example, 5 to 7 V or higher) compared to devices with the same pitch.

In a preferred embodiment, the epitaxial layer 14 of the laterally diffused metal oxide semiconductor device 10D is doped to include a thin N-doped buffer layer 17 directly formed on the substrate 12 (calibrated to N) -buffer). In several embodiments, the doping concentration of the buffer layer 17 is comparable to or less than the doping concentration of the body region 16 (ie, the N doping concentration). high. The buffer region 17 is used to suppress the dielectric breakdown voltage under the source contact region (i.e., under the implant region 26), thereby suppressing the effect of variations in the thickness of the epitaxial layer on the performance of the device.

A P-doped buffer layer 21 is formed on the N-doped buffer 17 under the LDD extension region 20 and laterally interposed between the p-body 16 and the N+ doped gate contact region 23. The buffer layer 21 and the body region 16 are doped separately, and the sheet charge (concentration multiplied by the thickness) in the layer is comparable to the sheet charge in the LDD layer 20. This buffer layer 21 will be discussed in more detail below.

The drain extension region 20 and the buffer region 21 conform to the design criteria for charge balancing as discussed in, for example, U.S. Patent Nos. 4,754,310 and 5,216,275, the entireties of each of each of This charge balancing technique (also known as charge coupling) replaces a single high-resistance portion of a conventional transistor's drain region with a staggered structure of the first and second regions of an alternating conductivity type (generally considered to be in one The high repression voltage of the device is absorbed in the depletion layer). In the case of a breakdown voltage increase, the drift region of the conventional drain must be made longer and doped less to increase the Rds. To achieve a desired breakdown voltage in the device structure, the charge in those regions should be balanced and optimized to maximize the breakdown voltage and minimize Rds-on. The thickness of the doping concentration of each of the first and second regions is such that, once depleted, the space charge per unit area formed in each of the regions is balanced. In a preferred embodiment of the invention, a charge balance is provided between the drain region 20 and the P-buffer region 21. The depletion region will develop simultaneously in the two regions with compensated net charge, and the resulting electric field distribution is also very uniform. This technique maintains the target rejection voltage of the device The required distance becomes shorter and the doping amount in the drain region 20 becomes higher (i.e., the conductivity is higher). In several embodiments, the amount of doping is increased by about 10 to 30 times, and from N- to an amount of N doping. This reduces the electrical resistance of the region 20.

The N-doped buffer region 17 has a dopant concentration N and the P-doped buffer region 21 has a dopant concentration P. The deep implantation of an N dopant, preferably phosphorous, to form the buffer layer 17 can be performed after deposition of the epitaxial layer 14 at the beginning of the program flow. The buffer layer 21 may be formed after the implant layer 17 or after the formation of the drain plug 23.

The source metal layer or electrode 28 of device 10D preferably comprises a blanket deposited on the device, such as by Al, Ti/Al, Ti/TiN/Al, or by sputtering by CVD (Chemical Vapor Deposition) or sputtering. A conductive material of the group consisting of W. The metal layer 28 can comprise a plurality of metal or metal alloy layers. In several embodiments, the source electrode 28 can be wire bonded or soldered directly to an external package electrode. The source electrode 28 is deposited to fill the shallow trench 19, thereby providing electrical contact with the source implant 18 and creating a short between the source 18 and the body region 16. The source electrode 28 extends over the insulating layer 34 and covers the entire surface area of the wafer, including the gate structure 31 and the drain extension region 20 (except for the cell adjacent to the gate contact). In one embodiment, the source metal layer 28 has a thickness defined between the upper surface 15 of the epitaxial layer 14 and its upper surface 29, which is between about 1.0 and 5.0 μm.

When the device 10D is "on", a conductive current will flow through the source metal 28, through the source region 18, through the channel below the gate 31, and laterally to the drain extension region 20, through Through the drain extension region 20 to the vertical height The gate contact 23 is further doped to the substrate 12 and penetrates the substrate 12 to flow to the drain electrode 11 which is electrically coupled to the bottom side of the device 10D.

The source metal structure 28 of Figure 11 provides a number of advantages. First, a single conductive layer can serve as both a source contact and a shield electrode, which shields the conductive gate 31 from the drain contact 23 and reduces the gate and the drain. Capacitance (Cgd). Due to the depression of the drain contact region 23 below the surface 15, the insulating layer 34 may now have a single uniform thickness approximately equal to the thickness of the thinner portion 37 of Figures 3 through 4. There is no need to form a single shield gate or any separate connection of the shield gate to the source 18. Thereby, the manufacturability of the device is greatly improved.

In addition, the drain-source resistance (Rds) is optimized by using an N+ substrate 12. Even prior art P-doped substrates provide much higher resistance (often 2 to 3 times higher) than n-substrate, however, those skilled in the art will appreciate that n-channel devices designed for RF applications are typically formed. On the P+ substrate, it is important to have a source electrode system with a ground potential at the bottom of the die. However, the present crystal device 10D provides an n-channel device on a low resistance n-doped substrate 12.

In one embodiment, the source metal 28 is overlapped with the drain extension region 20 and the two regions are separated by a predetermined thickness of insulating layer 34 to induce additional charge coupling. In some embodiments, the insulating layer 34 has a thickness in this region of between about 0.05 and 0.15 μm. The electric field distribution can be numerically simulated and optimized to determine the optimum thickness. This charge coupling effect causes the doping concentration of the drain extension region 20 to increase again, thereby lowering the Rds.

An exemplary method of forming device 10D will now be described. Certain details that are apparent to those skilled in the art will be eliminated so as not to obscure the invention. Substrate 12 has a predefined N+ dopant concentration. Next, an epitaxial layer 14 is formed on the upper surface of the substrate 12. The N-buffer layer 17 is formed by deeply implanting an N dopant, preferably phosphorus, after depositing the epitaxial layer 14 as needed. An oxide layer serving as a drain contact mask is formed and patterned on the epitaxial layer 14. The implanted region 23 is formed using the dual implant procedure described above. A portion of the oxide layer is removed using an etch process to expose the active region of the transistor as defined by a dedicated photoresist mask. The P-buffer layer 21 is implanted in the active region of the transistor. The photoresist mask is removed and the remaining oxide layer is used as a so-called surrounding active transistor region to cover the field oxide of the die.

After the gate contact 23 is formed, a thin gate oxide layer 36 is formed on the upper surface 15 of the epitaxial layer 14. Next, a polysilicon layer is deposited and etched to form a polysilicon gate layer 30. The telluride layer 32 is then formed using a well-known self-aligned germanide process, or a germanide layer is deposited over the polysilicon layer 30 and then etched to form the stacked polysilicon/germanide structure 31 shown in FIG. . Subsequent to the formation of the vaporized layer 32, the P-body 16 and the drain extension region 20 are formed by a masked implantation and thermal diffusion step of individual dopants. The sidewall spacers adjacent to the conductive gate 31 can be individually formed using a known sidewall spacer procedure if desired. For example, an oxide layer can be deposited and then etched back by an anisotropic reactive ion etching (RIE) to form an insulating spacer. The N+ source region 18 is formed by implanting arsenic as a mask using a patterned photoresist.

An oxide layer 34 is deposited over the upper surface 15 and the conductive gate 31 to a desired thickness. The shallow trench 19 is patterned and etched to the desired depth, and then the implanted region 26 is formed. Finally, a metal layer is deposited over the monolithic structure and patterned to form the source metal 28. The original structure is then thinned to a desired thickness and a backside metal 11 is deposited to form the drain electrode. Subsequently, the device was packaged and tested.

Various other specific embodiments of the crystal device 10D will be described below. Such devices may be formed using the above-described procedures and modifications to the program that are not apparent to those skilled in the art.

Figure 12 illustrates a specific embodiment of an improved laterally diffused metal oxide semiconductor transistor 10E. The transistor 10E is identical to the transistor 10D described above (except as explained below), and similar reference codes indicate similar features. In the embodiment of FIG. 12, the epitaxial layer 14 includes a second trench 46 filled with doped polysilicon. A highly conductive (N+) doped implant region 23A surrounds the doped polysilicon. After the polycrystalline germanium is deposited, the polycrystalline germanium filled trench 46 is recessed from the top surface 15 of the epitaxial layer 14 in an etch back step. In a preferred embodiment, the polysilicon is doped in situ. This recess is filled with a dielectric material from insulating layer 34B. The polysilicon plug 46 is adjacent to the drain extension region 20A. In this embodiment, the conductive region 23A is formed by diffusing dopants from the doped polysilicon material into the surrounding portion of the epitaxial layer 14 to electrically contact the drain extension region 20A and the substrate 12. Both. Diffusion occurs during the fabrication of the laterally diffused metal oxide semiconductor transistor 10E and is experienced during high temperature annealing which will be familiar to those skilled in the art. The annealing step is typically used during gate oxide formation and/or Implant dopants in the body or source/drain regions 16, 18, 20A are activated. The N+ well 23A created around the polysilicon fill 46 forms a highly conductive drain plug that connects the drain extension region 20A to the substrate 12. Since the conductive gate contact plug 23 is provided, the highly doped region 23A is spaced apart from the top surface 15 of the epitaxial layer 14 by at least a portion of the lightly doped region 20A and the insulating layer 34B. open.

Figure 13 illustrates another embodiment of an improved laterally diffused metal oxide semiconductor transistor 10F. The transistor 10F is identical to the transistor 10E of Fig. 12 described above (except as explained below), and similar reference codes indicate similar features. In this embodiment, the source metal layer 28A that provides an electrical short between the N+ source 18A and the lower P-body region 16 penetrates the N+ from the top surface 15 of the epitaxial layer 14 with a metal fill. The source region 18A is formed by etching one of the shallow trenches 19A. In this embodiment, the source contact trench 19A is self-aligned to the conductive gate stack 31. This self-aligned approach reduces the layout pitch and increases the density per channel area of the MOSFET channel, thereby reducing the specific resistance (Rds, on* area) of the device. In the self-aligned process, the source contact mask has a contact opening extending at least partially over the conductive gate 31. The conductive gate 31 has previously covered a dielectric layer, and the dielectric layer is The lead of the electrical layer 34C has a thickness on top of the gate 31 that is different from the thickness of the tantalum surface 15 of the epitaxial layer 14 in the contact region. Two deposits can be used to create regions of different thicknesses. The thickness of the dielectric layer on top of the gate structure 31 is significantly greater than the thickness of the dielectric layer in the contact region, such as greater than about 0.3 to 0.5 μm, so that the contact etch stops before reaching the top surface of the gate stack 31. On the upper surface 15 of the epitaxial layer or attached near. In a subsequent step, the epitaxial layer 14 is etched through the N+ source region 18A in the contact region and reaches a depth lower than the N+ source region 18A, thereby contacting the body region 16. The second etch step uses an etchant that is more selective to the epitaxial layer 14 than to the dielectric layer 34C. Subsequently, a metal layer forming the source electrode 28A is deposited on the substrate as a continuous layer, wherein the metal fills the source contact trench 19A and overlaps the gate 31 and the drain extension region 20A. In this embodiment, the source contact opening is the same size as the opening used to form the device of Figures 11 through 12, but the separation between the contact window and the gate stack 31 is reduced by the overlap. Then, the distance between the devices 10F is reduced as compared to the devices 10 to 10E.

In some embodiments, the source contact mask is also used to perform a shielded P+ implant in the P-body region 16. The first implant is performed after the oxide etch and produces a P+ region 48 just below the N+ source region 18A. The implant 48 reduces the sheet resistance of the P-body 16A below the N+ source region 18A so as to completely avoid triggering bipolar transistor action during a collapse. The second P++ implant 26 is performed after etching the epitaxial layer 14 to form the trench 19A. The implant is used to increase the doping concentration of the source contact 28A at the interface of the P-body region 16A, thereby improving the contact between the source metal layer 28A and the P-body 16A. In the absence of the N+ buffer layer 17, the location of the collapse is fixed between the implanted region 48 and the N+ contact 23 or 23A, rather than just below the source contact implant region 26.

As discussed, the P+/P++ implants 26, 48 are used to secure the electrical breakdown of the transistor to the PN junction. The crash can be designed to occur in the The PN junction below the source-body junction or between the source-body junction and the drain plugs 23, 23A at a plurality of lateral distances from the source contact. The second case of collapse between the source-body contact 26 and the drain plug 23A was confirmed by numerical simulation. The simulation shows the impact ionization distribution at the collapse in the cross section of the transistor. The highest rate at which minority carriers are generated is distributed between the P-body 16 beside the source-body junction 26 and the drain plug 23 of the laterally diffused metal oxide semiconductor transistor. The primary effect of these embodiments is that the thermal carriers are generated away from the gate stack 31, for example, when the transistor is turned off, thereby improving the reliability of the gate oxide 36.

In another alternative embodiment, the collapse location is fixed between the P-buffer region 21A of FIG. 13 or the p-buffer region 21 of FIGS. 11 and 12 and the drain plug 23A, wherein the collapse The plug structure 23A is adjacent to the doped polysilicon fill trench 46 and is formed of dopants from the doped polysilicon fill trench 46, as shown in Figures 12 and 13. This is mainly determined by the amount of doping concentration at the PN junction; if the concentration is high on both sides of the junction, the breakdown voltage is low. In this embodiment, the dopant concentration in the P-buffer region 21A is increased beyond the proposed optimal value of the charge-coupling design criteria as discussed above, and in the P-buffer 21A and the drain- A lower collapse occurs at the interface between the plug regions 23, 23A. Deliberately violate the charge-coupling design guidelines discussed above to be able to fix the breakdown voltage at this location. The concentration of the P-buffer layer 21 is just increased to the maximum concentration required to fix the collapse. In a specific embodiment, the concentration is increased by about 30 to 50%. No N-buffer layer is used in the specific embodiment of Figure 13, because the N- An increase in the concentration of the buffer will fix the breakdown voltage below the P+ contact implant 26. The N-buffering does not need to be as described above in the specific embodiment of FIG.

Figure 14 is a partial cross-sectional view of a macro-cell device 100 (sometimes referred to herein as a "quasi-lateral laterally diffused metal-oxide-semiconductor device") that includes a plurality of parallel diffusions of lateral diffusion. Metal oxide semiconductor transistor device (as described above in connection with Figures 11, 12 or 13). Those skilled in the art will appreciate that similar lateral unit arrangements can be formed using the laterally diffused metal oxide semiconductor transistors of Figures 1 through 5. The various connections and configurations of such macrocell devices are described in co-pending and commonly assigned U.S. Patent Application Serial No. 11/254,482, the entire disclosure of which is incorporated herein by reference. Although only two such laterally diffused metal oxide semiconductor transistors 10D, 10E or 10F are shown in device 100, it should be understood that hundreds of such devices can be electrically coupled in parallel to form a single functional macrocell device 100. The connections of groups of such units may be generated by busbar structures (not shown) formed on the devices. In one embodiment, each macrocell device 100 includes between about 50 and 200 (and preferably about 100) laterally diffused metal oxide semiconductor transistors 10D, each laterally diffused metal oxide semiconductor The crystal 10D has a pitch of about 2 μm or less. An exemplary wafer level or near wafer level power laterally diffused metal oxide semiconductor device includes a plurality of macro cell devices 100 through which the busbars are as described in the '482 application and described more fully below. The structures are coupled together to operate as a single power laterally diffused metal oxide semiconductor device.

Individual laterally diffused metal oxide semiconductor transistors shown in FIG. The details are described above in connection with Figures 11 to 13. The source contact electrode 28 is disposed on the top surface of the device 100 as explained in connection with FIGS. 11 through 13 and as shown in FIG. However, unlike the specific embodiment of Figures 11 through 13, the gate electrode 104 comprising the conductive material described above in connection with the source electrode 28 is also located on the top side of the device 100, rather than placing the gate electrode The bottom surface of the device 100 (i.e., the drain electrode 11 (Figs. 11 to 13) formed on the bottom surface of the substrate 12). This feature enables a power MOSFET design to have a high current density, as illustrated in the '482 application. The drain electrode 104 is isolated from the source electrode 28 by an insulating layer 108 formed on the top surface of the epitaxial layer 14. The drain electrode 104 is coupled to the substrate 12 via a high density implant region 102. Current first penetrates the substrate 12 from the implanted region 23 and then flows laterally into the conductive region 102 (which concentrates the current from the multi-cell group) and then flows vertically into the drain electrode 104. The same procedure can be used to form the implant region 23 to form the implant region 102, however, after the procedure, just below the upper surface 15 of the epitaxial layer 14 and just above the epitaxial layer 14 surface 15 is followed by a Additional contacts are implanted to ensure a high doping concentration and thus good electrical contact with the drain electrode 104.

Figure 15 illustrates an alternative embodiment of the macrocell device of Figure 15. The device 100A of FIG. 14 includes a P-doped substrate 12A instead of an N-doped substrate 12. The above-mentioned transistor 10D, 10E or 10F is formed on a buried layer 106 which is a highly doped N+ layer formed in the epitaxial layer 14A. The buried layer 106 laterally carries current from the transistors to the implant plug 102, which provides the current to the drain electrode 104. The buried layer 106 provides electrical isolation of the laterally diffused metal oxide semiconductor transistors from the substrate 12A and enables a plurality of independent laterally diffused metal oxide semiconductors (or other devices) to be integrated on a common substrate 12A. For example, device 100A can form a power management IC by multiple independent integrated power switches. Although not shown in FIG. 15, the lateral diffusion metal oxide semiconductor device spacing can also be reduced by self-aligning the source contact opening to the gate structure, as in the lateral diffusion metal oxidation in conjunction with FIG. The semiconductor device 10F is described.

As mentioned above, in several embodiments, the improved power laterally diffused metal oxide semiconductor device is provided with an n-channel transistor formed on a low resistance N-substrate. The device exhibits a low on-resistance (R _ds-on ) by reducing the resistance of the substrate and exhibits a low Cgd capacitance by minimizing electrostatic coupling between the gate electrodes and the drain electrodes. The length of the enhanced drain drift region can be reduced and the device can produce a smaller pitch while still having the same collapse voltage as prior art devices. As such, the device density and current capability can then be improved.

In several embodiments, the doping profile is selected and a drain connection is configured to optimize the collapse location. The device can be configured to collapse at a predefined location of the PN junction near the P+ junction of the P-body layer. The region of highest impact ionization rate may extend vertically from the P+ junction toward the substrate or laterally toward the drain plug region to cause the collapse to be fixed away from the gate stack and reduce the risk of triggering the bipolar transistor. The collapse location can also be between a P-buffer layer and the buried drain contact. The doped structure controls the high impact ionization rate to expand in a vertical or horizontal manner. Make the crash location the best This helps to avoid device crashes as explained in this article.

Using FIG. 11 as an illustrative example, the power laterally diffused metal oxide semiconductor described herein reflects an innovative method of designing an LDD region 20 that supports the LDD region 20 (FIG. 11) based on the voltage. The charge balance of the polar doped region (eg, P-buffer layer 21 of FIG. 11) is coupled to the tight capacitance charge control electrode between the source electrode 28 and the drain extension region 20 (ie, the source electrode 28 will be An electric field is induced in the extended region 20 because it overlaps as a dielectric for isolation). The combination of the opposite polarity and the electrode region maintains a high electric field inside the drift layer 20, thereby improving the voltage rating and increasing its doping energy and shortening its length, thereby reducing the size of the transistor unit and its Rds,on.

Once the three regions (the drain extension 20, the P-buffer 21 and the source electrode 28) are nearly charge balanced, the perfect design of the breakdown voltage and the minimum drift layer resistance can be achieved. The total net doping and dopant distribution in the drain extension region 20 is almost equal to the net doping and dopant in the opposite polarity doping region (ie, the P-buffer layer 21). Occurs when distributing. When the top source electrode 28 is to be charge-balanced with the LDD region 20, the dielectric layer thickness of the dielectric layer 34 is selected such that the LDD region 20 has an electric field inside, which is large enough to improve the collapse but not greater than the LDD region 20. The limited electric field in the middle will cause a lower premature burst.

Once the doping and oxide thickness are optimized (as guided by numerical simulation), a high electric field will be maintained in the LDD region 20 and cause a breakdown voltage to increase because the voltage is along the length of the LDD region 20. The integral of the area. Unlike traditional devices, an added benefit is that it can be used The higher doping of the LDD layer 20 is because the breakdown voltage is not limited to the LDD doping. Therefore, this higher doping can be used to maintain a high electric field throughout the LDD layer 20. The voltage rating of the charge balancing LDD layer 20 can be increased only by increasing the length of the LDD region 20, as opposed to conventional devices that must reduce the doping to increase the length of the LDD region.

In some embodiments, several imbalances in charge can occur in the laterally diffused metal oxide semiconductor transistor device by doping the P-buffer layer 21 beyond the optimum balance described above. It is believed that this doping profile is advantageous in terms of the ability to handle the collapse, as it would be used to confine most of the breakdown current in the buffer layer 21 while allowing other layers to release the breakdown current. The importance of this property is that the power devices are designed to have robust sag handling capabilities because such power devices are used in circuits that expose the device to sudden collapse due to failure or starting conditions. By confining this current to the P-buffer layer 21, the current will be drawn through the P++ layer 26. This current flow path produces the lowest current resistance to reduce heat generation and also protects the current from flowing under the source, thereby avoiding parasitic bipolar latching (on).

Although the present invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the scope of the invention is to be construed as being limited by the scope of the invention.

10‧‧‧LDMOS/device

10A‧‧‧LDMOS/device

10B‧‧‧LDMOS/device

10C‧‧‧LDMOS/device

10D‧‧‧LDMOS/device

10E‧‧‧LDMOS/device

10F‧‧‧LDMOS/device

11‧‧‧汲electrode/backside metal layer

12‧‧‧Substrate

12A‧‧‧Substrate

14‧‧‧ epitaxial layer

14A‧‧‧Elevation layer

15‧‧‧Upper surface/top surface

16‧‧‧Main Area/P Well

16A‧‧‧Main Area

16B‧‧‧Subject area

17‧‧‧ Buffer layer

18‧‧‧Source (region) / source implant

18A‧‧‧N+ source area

19‧‧‧Shallow Ditch

19A‧‧‧Shallow Ditch

20‧‧‧Bungee area

20A‧‧‧Bungee Extension Area

21‧‧‧P-buffer layer

21A‧‧‧P-buffer area

22‧‧‧汲 Contact area/dual contact implant

23‧‧‧汲 contact area/N+ doped area/bungee plug

23A‧‧‧汲pole plug

24‧‧‧ Plug

25‧‧‧Deep trench area

26‧‧‧Main contact area/implant area/P++ layer

28‧‧‧Source metal layer/electrode

28A‧‧‧Source metal layer/electrode

29‧‧‧Upper surface

30‧‧‧Polysilicon layer

31‧‧‧ Conductive gate/gate stack

32‧‧‧ Telluride layer

34‧‧‧Insulation/Oxide/Dielectric Layer

34A‧‧‧Insulation

34B‧‧‧Insulation

34C‧‧‧ dielectric layer

35‧‧‧ thicker part

36‧‧‧Gate dielectric/gate oxide

37‧‧‧ Thinner part

38‧‧‧First buffer zone

38C‧‧‧buffer layer

40‧‧‧buffer layer

46‧‧‧Polysilicon plug/polysilicon filled trench

48‧‧‧ implanted/P+ area

100‧‧‧ device

100A‧‧‧ device

102‧‧‧Conducting area/implantation area/implantation plug

104‧‧‧汲electrode

106‧‧‧buried layer

108‧‧‧Insulation

The drawings will illustrate preferred embodiments of the invention, as well as additional information related to the present disclosure, in which: 1 illustrates a laterally diffused metal oxide semiconductor transistor in accordance with the present invention; and FIG. 2 illustrates a specific embodiment of a laterally diffused metal oxide semiconductor transistor of the present invention having improved field plate effect; FIG. A specific embodiment of a laterally diffused metal oxide semiconductor transistor of the present invention having a buffer layer for suppressing short channel effects; and FIG. 4 illustrates a lateral diffusion metal oxide semiconductor transistor of FIG. a specific embodiment having a second buffer layer for improving the collapse characteristics of the improved transistor; FIG. 5 illustrates a region adjacent to a side edge of a semiconductor substrate on which the improved laterally diffused metal oxide is formed Semiconductor transistor; Figures 6 through 10 show electrical characteristics of the power laterally diffused metal oxide semiconductor device obtained by numerical simulation; Figure 11 illustrates lateral diffusion metal oxide in accordance with an alternative embodiment of the present invention Semiconductor semiconductor transistor; FIG. 12 illustrates an alternative embodiment of the laterally diffused metal oxide semiconductor transistor of FIG. 11; FIG. An alternative embodiment of the laterally diffused metal oxide semiconductor transistor of FIG. 12; FIG. 14 illustrates a semiconductor device including a plurality of laterally diffused metal oxide semiconductor transistors having source and drain electrodes oriented upward; 15 illustrates an alternative embodiment of the device configuration of FIG.

10D‧‧‧LDMOS/device

11‧‧‧汲electrode/backside metal layer

12‧‧‧Substrate

14‧‧‧ epitaxial layer

15‧‧‧Upper surface/top surface

16‧‧‧Main Area/P Well

17‧‧‧ Buffer layer

18‧‧‧Source (region) / source implant

19‧‧‧Shallow Ditch

20‧‧‧Bungee area

21‧‧‧p-buffer layer

23‧‧‧汲 contact area/N+ doped area/bungee plug

26‧‧‧Main contact area/implant area/P++ layer

28‧‧‧Source metal layer/electrode

29‧‧‧Upper surface

30‧‧‧Polysilicon layer

31‧‧‧ Conductive gate/gate stack

32‧‧‧ Telluride layer

34‧‧‧Insulation/Oxide/Dielectric Layer

36‧‧‧Gate dielectric/gate oxide

Claims (20)

A laterally diffused metal oxide semiconductor transistor device comprising: a substrate having a first conductivity type; a semiconductor layer formed over the substrate and having a lower and upper surface; the first conductivity type a source region and a lightly doped drain extension region of the first conductivity type formed in a semiconductor layer adjacent to the upper surface of the semiconductor layer, the source and the lightly doped The drain extension regions are spaced apart from each other; a body region of a second conductivity type formed in the semiconductor layer, the body region forming a channel between the source and the lightly doped drain extension region a region extending under the source region; a conductive gate formed on a gate dielectric layer formed over the channel region; a drain contact that extends the lightly doped drain a region electrically connected to the substrate and laterally spaced from the channel region, the gate contact comprising a highly doped gate contact region formed in the semiconductor layer and extending to the lightly doped drain Between regions, where Lightly doping at least a portion of the drain extension region and spacing a topmost portion of the highly doped gate contact region from the upper surface of the semiconductor layer; and a source contact that causes the source The area is electrically connected to the body area. The device of claim 1, further comprising forming a trench in the semiconductor layer adjacent to the source region and extending into the body region, The source contact includes a layer of conductive material deposited in the trench, wherein the source contact provides an electrical short between the source region and the body region. The device of claim 2, further comprising an insulating layer formed over the conductive gate and adjacent to the conductive gate, wherein the transistor device further comprises a source electrode layer forming the source A contact extends over the conductive gate, the insulating layer insulating the conductive gate from the source electrode layer. The device of claim 3, wherein the insulating layer and the source electrode layer extend over the drain extension region, the insulating layer insulating the drain extension region from the source electrode layer. The device of claim 2, further comprising a first highly doped region of the second conductivity type formed in the body region under the trench and coupling the body region to the source contact. The device of claim 5, further comprising a second highly doped region of the second conductivity type formed between the source region and the first highly doped region of the second conductivity type In the body area between. The device of claim 1, further comprising an implant buffer layer formed between the body region and the substrate, the buffer layer comprising the dopant of the first conductivity type. The device of claim 1, further comprising an implant buffer layer in the semiconductor layer, formed under the drain extension region and interposed between the body region and the drain contact, the implant buffer The layer includes the second conductive Rate type dopants. The device of claim 8, wherein the implant buffer layer is doped with a doping profile relative to the drain extension region to concentrate a breakdown current in the implant buffer layer in the event of a collapse. The device of claim 8, wherein the drain extension region and the implant buffer layer are doped with a doping profile to provide a charge balance between the implant buffer layer and the drain extension region. The device of claim 8, wherein the dopant extension region is doped with a dopant of the first conductivity type having a concentration of at least 1 x 10 ¹⁷ atoms/cm ³ . The device of claim 1, wherein the highly doped gate contact region surrounds one of the doped polysilicon plugs disposed in the semiconductor layer. The device of claim 12, wherein the doped polysilicon plug is used to form a source of dopants for the highly doped gate contact region. The device of claim 13, wherein the doped polysilicon plug is recessed from the upper surface of the semiconductor layer, wherein the recess is filled with an insulator material. The device of claim 1, wherein the first conductivity type is an N conductivity type and the substrate has a highly doped concentration. The device of claim 1, wherein the topmost portion of the highly doped gate contact region is spaced apart from the upper surface of the semiconductor layer by at least a portion of the drain extension region. The device of claim 16, wherein the highly doped gate contact region comprises one of the implant regions formed in the semiconductor layer. The device of claim 1, wherein the drain extension region has a dopant concentration of between about 5 x ^{10 16} and 1 x 10 ¹⁸ atoms/cm ³ . The device of claim 1, further comprising a top side source electrode disposed above the substrate and a top side drain electrode disposed under the substrate. The device of claim 1, wherein at least a portion of the highly doped gate contact region is located below the lightly doped drain extension region.