TWI469528B - Direct digital frequency synthesizer - Google Patents

Description

Direct frequency synthesizer

The invention relates to a direct frequency synthesizer, in particular to a direct frequency synthesizer which can effectively improve spectral resolution and operation speed.

The conventional direct frequency synthesizer 200, as shown in FIG. 4, includes a phase accumulator 210, a read-only memory 220 electrically connected to the phase accumulator 210, and an electrical connection. The digital analog converter 230 of the read-only memory 220, wherein the phase accumulator 210 can receive a phase accumulating unit, the read-only memory 220 has a memory 221, a digital operation unit 222, and an output stage 223. The direct frequency synthesizer 200 is configured to look up the sine wave value stored in the read-only memory 220. However, the direct frequency synthesizer 200 includes the read-only memory 220, so the circuit area is still In addition, the manner of the look-up table method will greatly reduce the operation speed of the direct frequency synthesizer 200.

The main object of the present invention is to provide a direct frequency synthesizer comprising a phase accumulator and a phase amplitude converter, the phase amplitude converter having a first complement unit and an electrical connection a first adder of the number unit, a second coefficient unit electrically connected to the first complement unit and the first adder, a squarer electrically connected to the first adder, and an electrical connection a complement unit and a first coefficient unit of the squarer, and a third coefficient electrically connected to the first complement unit And a second adder electrically connected to the first coefficient unit and the third coefficient unit and a second complement unit electrically connected to the second adder. According to the present invention, the coefficient unit, the first adder, the second adder, and the squarer are used, and an approximation method in a mathematical equation is used to obtain an output of an ideal sine wave, which is simulated by the present invention. The error between the sine wave and the ideal sine wave can be effectively reduced, so the present invention has the characteristics of high spectral purity, and in addition, when the present invention is applied to protein frequency shift detection, since the direct frequency synthesizer has high spectral purity, it can ensure The center frequency has the highest judging peak within the range of the sweep frequency. Moreover, the present invention does not need to check the table, so the operation speed can be effectively improved.

Referring to FIG. 1 , a direct frequency synthesizer 100 includes a phase accumulator 110 and a phase amplitude converter 120 electrically connected to the phase accumulator 110. The phase amplitude converter 120 has a first complement unit 121, a first adder 122 electrically connected to the first complement unit 121, a first connection to the first complement unit 121, and the first adder. a second coefficient unit 124 of 122, a squarer 125 electrically connected to the first adder 122, a first coefficient unit 123 electrically connected to the first complement unit 121 and the squarer 125, and an electrical connection a third coefficient unit 126 of the first complement unit 121, a second adder 127 electrically connected to the first coefficient unit 123 and the third coefficient unit 126, and a second electrically coupled to the second adder 127 The two-complement unit 128, the direct frequency synthesizer 100 adopts the above circuit architecture, and adopts a second-order non-uniform parabola sampling method applied to the direct frequency synthesizer 100 to achieve high spectral purity, and the sampling method The equation is y=a _i *(x+b _i ) ² +c _i (1≦i≦M), where y is the sine wave vibration, a _{i is} the first coefficient generated by the first coefficient unit 123, and is used to control the slope of the sine wave, and b _{i is} the second The second coefficient generated by the coefficient unit 124 is used to control the upper and lower movement of the sine wave, and c _{i is} the third coefficient generated by the third coefficient unit 126, which is used to control the left and right movement of the sine wave, and x is the first coefficient. The input signal generated by the complement unit 121, M is the number of cut line segments of the quarter-wave, and i is a non-equal segment.

Referring to FIG. 1 again, in the embodiment, the first complement unit 121 is electrically connected to the phase accumulator 110, and the phase accumulator 110 has a third adder 111 and a register 112. The register 112 is electrically connected to the third adder 111. The phase accumulator 110 is configured to provide a phase required by the phase amplitude converter 120. The second complement unit 128 is electrically connected to the phase accumulating. The first coefficient unit 123 has a plurality of selectors 123a, a plurality of first shift registers 123b and a plurality of first multiplexers 123c, each of which is selected. Each of the first shift register 123b is electrically connected to each of the first multiplexers 123c, and the selectors 123a are electrically connected to the first shift register 123b. The squarer 125 is electrically connected to the first complement unit 121 and the second adder 127. In addition, the second coefficient unit 124 has a second shift register 124a. And a second multiplexer 124b electrically connected to the second shift register 124a, the second multiplexer 124b is electrically connected The first complement unit 121 and the first adder 122, the third coefficient unit 126 has a third shift register 126a and a third electrically coupled register 126a. The third multiplexer 126b is electrically connected to the first complement unit 121 and the second adder 122. In this embodiment, the fourth multiplexer 126b further has a fourth adder 130 and a first Four coefficient unit The fourth adder 130 is electrically connected to the second complement unit 128. The fourth coefficient unit 140 is electrically connected to the fourth adder 130, and the fourth coefficient unit 140 is configured to generate a compensation trimming coefficient. As the final correction of the sine wave signal.

Referring to FIG. 1 again, the direct frequency synthesizer 100 is controlled as follows. A phase accumulating unit of a total of 32 bits is input to the phase accumulator 110. Next, the output of the phase accumulator 110 is phase truncated. Obtain 20 bits, and use the highest bit [19] as the control signal for controlling the upper and lower symmetry of the output sine wave, and the sub-high bit [18] as the control signal for controlling the left and right symmetry of the output sine wave. The remaining 18-bit input signal x is added to the second coefficient b _i generated by the second coefficient unit 124, and then squared by the squarer 125, and then the multiplication effect is achieved by the displacement function of the first coefficient unit 123. In this embodiment, the selectors 123a of the first coefficient unit 123 select the slope of the corresponding sine wave segment, and each of the selectors 123a can select one of the 16 segments of the non-average segment displacement amount. Adding the selected 12 sets of displacements is the slope of the corresponding sine wave segment, and finally, adding the shifted signal to the third coefficient c _i generated by the third coefficient unit 126, that is, completing the non-equalization Parabolic interpolation Count. Referring to Figures 2 and 3, the present invention simulates the split-score sampling method and the average-sampling method through software. From the simulation results, the spurious-free dynamic range of the non-uniform sampling method (Spurious- The free dynamic range (SFDR) is 68.67dB, the spurious-free dynamic range of the equal-sampling method is 64.72dB, and the spurious-free dynamic range of the non-averaged equal-sampling method is 3.95dB. The improvement is due to the sine wave. The more linear segments are shifted by the same slope, and the other sine wave segments with larger slope changes are divided into 15 equal parts, so the simulated sine wave is closer to ideal than the even sampling method. Sine wave.

The present invention utilizes the first adder 122, the second adder 127, the squarer 125, the first coefficient unit 123, the second coefficient unit 124, and the third coefficient unit 126, and utilizes mathematical equations. The approximation method is used to obtain the output of the ideal sine wave. Since the error of the sine wave and the ideal sine wave simulated by the present invention can be effectively reduced, the present invention has the characteristics of high spectral purity, and further, when the present invention is applied to proteins In the frequency shift detection, since the direct frequency synthesizer 100 has a high spectral purity characteristic, it is ensured that the center frequency has the highest judging peak in the range of the sweep frequency.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧Direct frequency synthesizer

110‧‧‧ phase accumulator

111‧‧‧ third adder

112‧‧‧ register

120‧‧‧Phase Amplitude Converter

121‧‧‧First complement unit

122‧‧‧First Adder

123‧‧‧First coefficient unit

123a‧‧‧Selector

123b‧‧‧First shift register

123c‧‧‧First multiplexer

124‧‧‧Second coefficient unit

124a‧‧‧Second shift register

124b‧‧‧Second multiplexer

125‧‧‧ square

126‧‧‧ third coefficient unit

126a‧‧‧ Third shift register

126b‧‧‧Second multiplexer

127‧‧‧second adder

128‧‧‧second complement unit

130‧‧‧fourth adder

140‧‧‧fourth coefficient unit

200‧‧‧Direct frequency synthesizer

210‧‧‧ phase accumulator

220‧‧‧Read-only memory

221‧‧‧ memory

222‧‧‧Digital unit

223‧‧‧Output level

230‧‧‧Digital Analog Converter

Figure 1 is a circuit diagram of a direct frequency synthesizer in accordance with a preferred embodiment of the present invention.

Figure 2: A simulation of the direct frequency synthesizer simulated by a non-uniform sampling method in accordance with a preferred embodiment of the present invention.

Figure 3: A simulation diagram of the direct frequency synthesizer simulated by a uniform sampling method in accordance with a preferred embodiment of the present invention.

Figure 4: Circuit block diagram of a conventional direct frequency synthesizer.

100‧‧‧Direct frequency synthesizer

110‧‧‧ phase accumulator

111‧‧‧ third adder

112‧‧‧ register

120‧‧‧Phase Amplitude Converter

121‧‧‧First complement unit

122‧‧‧First Adder

123‧‧‧First coefficient unit

123a‧‧‧Selector

123b‧‧‧First shift register

123c‧‧‧First multiplexer

124‧‧‧Second coefficient unit

124a‧‧‧Second shift register

124b‧‧‧Second multiplexer

125‧‧‧ square

126‧‧‧ third coefficient unit

126a‧‧‧ Third shift register

126b‧‧‧Second multiplexer

127‧‧‧second adder

128‧‧‧second complement unit

130‧‧‧fourth adder

140‧‧‧fourth coefficient unit

Claims (9)

A direct frequency synthesizer comprising: a phase accumulator; and a phase amplitude converter electrically coupled to the phase accumulator, the phase amplitude converter having: a first complement unit; a first An adder electrically connected to the first complement unit; a second coefficient unit electrically connected to the first complement unit and the first adder; a squarer electrically connected to the first An adder; a first coefficient unit electrically connected to the first complement unit and the squarer, the first coefficient unit having a plurality of selectors, a plurality of first shift registers, and a plurality of a first multiplexer, each of the selectors is electrically connected to each of the first shift registers, and each of the first shift registers is electrically connected to each of the first multiplexers, and the selectors are Electrically connecting the squarer, the first multiplexer is electrically connected to the first complement unit; a third coefficient unit electrically connected to the first complement unit; and a second adder Electrically connecting the first multiplexer and the third coefficient unit of the first coefficient unit And a second complement means, which is electrically connected to the second line adder. The direct frequency synthesizer of claim 1, wherein the phase accumulator has a third adder and a register electrically connected to the third adder. The direct frequency synthesizer of claim 1, wherein the first complement unit is electrically connected to the phase accumulator. The direct frequency synthesizer of claim 1, wherein the second coefficient unit has a second shift register and a second multiplexer electrically connected to the second shift register. The second multiplexer is electrically connected to the first complement unit and the first adder. The direct frequency synthesizer of claim 4, wherein the third coefficient unit has a third shift register and a third multiplexer electrically connected to the third shift register. The third multiplexer is electrically connected to the first complement unit and the second adder. The direct frequency synthesizer of claim 1, further comprising a fourth adder electrically connected to the second complement unit. The direct frequency synthesizer of claim 6, further comprising a fourth coefficient unit electrically connected to the fourth adder. The direct frequency synthesizer of claim 1, wherein the second complement unit is electrically connected to the phase accumulator and the first complement unit. The direct frequency synthesizer of claim 1, further comprising a second-order non-uniform parabolic sampling method applied to the direct frequency synthesizer, the equation of the sampling method being y=a _i *(x+ b _i ) ² + c _i (1≦i≦M), where a _i is the first coefficient, b _i is the second coefficient, c _i is the third coefficient, x is the input signal, and M is the quarter sine wave The number of cut line segments, i is a non-equal segment.