CN102006066A - ROM-less DDS circuit structure - Google Patents
ROM-less DDS circuit structure Download PDFInfo
- Publication number
- CN102006066A CN102006066A CN2009100919617A CN200910091961A CN102006066A CN 102006066 A CN102006066 A CN 102006066A CN 2009100919617 A CN2009100919617 A CN 2009100919617A CN 200910091961 A CN200910091961 A CN 200910091961A CN 102006066 A CN102006066 A CN 102006066A
- Authority
- CN
- China
- Prior art keywords
- rom
- bit
- less
- circuit structure
- dds circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 238000009825 accumulation Methods 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 238000000205 computational method Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000004422 calculation algorithm Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000013144 data compression Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Abstract
The invention discloses an ROM (read only memory)-less DDS (direct digital synthesizer) circuit structure, which comprises a pipelined accumulator, an exclusive OR unit, a thermometer coder, a sine weighting nonlinear DAC (digital to analog converter) and a Gilbert multiplier unit, wherein the pipelined accumulator is connected with the Gilbert multiplier unit. The structure eliminates the waveform storage ROM in the traditional DDS structure, so that the work frequency of the DDS circuit is improved and the power consumption of the DDS circuit is greatly reduced under the condition of the same output waveform performance.
Description
Technical field
The present invention relates to the semiconductor integrated circuit design field, relate in particular to a kind of (ROM-less) Direct Digital frequency synthesizer (DDS) circuit structure that does not need wave memorizer.
Background technology
Direct Digital Frequency Synthesizers (Direct Digital frequency Synthesizer, DDS) be a kind of frequency synthesizer, it directly adopts digital technology that sine-shaped phase information is converted to amplitude information, advantage such as have the frequency resolution height, the frequency switch speed is fast and maintenance output waveform phase place is continuous when frequency is switched.DDS is widely used in various military-civil purposes such as communication, radar, signal processing and electronic countermeasures.
Traditional DDS circuit structure block diagram is stored electronic circuits such as ROM 12, linear DAC 13, low pass filter 14 and clock distribution network 15 comprising N-bit accumulator 11, sinusoidal waveform as shown in Figure 1, and N is the natural number greater than 2.Phase accumulator 11 is at clock frequency f
cControl under make accumulating operation with the decimal number K of N-bit width frequency control word representative, output N-bit width binary format data are as the index address of waveform storage ROM 12; Waveform storage ROM 12 outputs to the linear Digital To Analog Convert of M-bit (DAC) 13 with the M-bit width sinusoidal waveform amplitude data of storing on the appropriate address; Linear DAC 13 is converted to staircase waveform with the Wave data of storage in the random asccess memory (ROM), and then the frequency that obtains synthesizing afterwards through low pass filter 14 is f
oSine wave-shaped signal.Output signal frequency f
oWith clock frequency f
cThe pass be: f
o=Kf
c/ 2
N
In traditional DDS structure, waveform storage ROM 12 is main bottlenecks of circuit power consumption, speed, and is the unit of area occupied maximum in the circuit.In order to reduce the circuit area of waveform storage ROM among the DDS, two kinds of ways are arranged usually: one for to block phase place, the low m-bit that is about to the N-bit width data (being the address of ROM) of N-bit accumulator output clips and keeps the address of height (N-m)-bit as ROM, like this can be with the address number of ROM from 2
NBe reduced to 2
N-m, simultaneously the output waveform quality is had only less deterioration; Two for compressing storage data among the ROM, is original 1/4th such as utilizing sine-shaped symmetry with the data compression among the ROM, perhaps other advanced compression algorithm, as Sunderland structure, Nicholas structure and Taylor series linear interpolation structure etc. commonly used, can effectively reduce the area of waveform storage ROM.But these all can not fundamentally solve waveform storage ROM brings in traditional DDS circuit power consumption, speed and area for cutting, only are the limited alleviations to original problem.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of ROM-less DDS circuit structure, with the restriction of thorough elimination waveform storage ROM to DDS circuit power consumption, speed and area.
(2) technical scheme
For achieving the above object, the present invention should become the circuit structure of traditional DDS, a kind of ROM-less DDS circuit structure is provided, comprise the streamline accumulator, XOR unit, thermometer encoder, sine weighting non-linear DAC and the Gilbert multiplier unit that connect successively, wherein, the streamline accumulator also is connected in the Gilbert multiplier unit.
In the such scheme, described streamline accumulator is a N-bit streamline accumulator, N is the natural number greater than 2, be used for will input the operation that adds up of N-bit frequency control word, in each clock cycle, export an accumulation result, and will export to described Gilbert multiplier unit through the N-bit result of time delay to described XOR unit.
In the such scheme, described XOR unit is (N-2)-bit width XOR computing array, N is the natural number greater than 2, be used for low (N-2)-bit data of the N-bit result of described streamline accumulator output are carried out the XOR operation with the second high position data 2nd-MSB respectively separately, and to described thermometer encoder output (N-2)-bit width result data.
In the such scheme, this XOR computing array has been realized the expansion of second quadrant of sinusoidal waveform from the monotonically increasing first quartile to monotone decreasing.
In the such scheme, described thermometer encoder, be used for the binary coded format digital coding of (N-2)-bit width of described XOR unit output thermometer coding formatted data, and export to described sine weighting non-linear DAC for [2^ (N-2)-1]-bit width.
In the such scheme, described sine weighting non-linear DAC comprises [2^ (N-2)-1] individual current source, the switch of each current source is controlled by the corresponding position in the thermometer coding formatted data of [2^ (N-2)-the 1]-bit width of described thermometer encoder output respectively, and the current value of current source is a sine weighting.
In the such scheme, logic " height " or " low " according to corresponding of the thermometer coding formatted data of [2^ (N-2)-1]-bit width, the corresponding current sources switch cuts out or opens in the described sine weighting non-linear DAC, the electric current of corresponding weighted value is joined on the output node of DAC, total current on the DAC output node is converted to voltage signal through a resistance, the range value of this voltage signal has been represented the range value of sinusoidal waveform at first, second quadrant, and this voltage signal is exported to described Gilbert multiplier unit.
In the such scheme, described Gilbert multiplier unit is used for and will carries out multiplication mutually with the voltage signal that described sine weighting non-linear DAC is exported through the N-bit result's of the streamline accumulator of time delay output the first high position data 1st-MSB, has realized that sinusoidal waveform is from first, second quadrant to the three, four-quadrant expansion.
In the such scheme, the output signal of described Gilbert multiplier unit is the output signal of whole ROM-lessDDS circuit.
In the such scheme, this structure further comprises a clock distribution network, and this clock distribution network is exported to streamline accumulator, XOR unit and thermometer encoder simultaneously with the clock signal that receives.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, ROM-less DDS circuit structure provided by the invention can adopt various semiconductor technologies to realize (as CMOS, GaAs HBT etc.), has eliminated waveform storage ROM in structure, makes speed, power consumption and the area of DDS circuit that very big performance boost all arranged.
2, ROM-less DDS circuit structure provided by the invention has been eliminated the waveform storage ROM in traditional DDS structure, thereby under the situation of identical output waveform performance, has been improved the DDS circuit work frequency, and reduced the power consumption of DDS circuit widely.
Description of drawings
Fig. 1 is traditional DDS structural system block diagram;
Fig. 2 is a ROM-less DDS structural system block diagram provided by the present invention;
Fig. 3 changes to the 7-bit thermometer coding for the 3-bit binary coding;
Fig. 4 is the computational methods and the DAC circuit form of sine weighting non-linear DAC current source weighted value;
Fig. 5 is a 8-bit 15GHz GaAs HBT ROM-less DDS Circuits System block diagram;
Fig. 6 is accumulator output result and sinusoidal waveform phase relation;
Fig. 7 is the logical operation of 3-bit thermometer encoder combinational logic circuit;
Fig. 8 is the computational methods of the weighted value of 8 current sources in the sine weighting non-linear DAC;
Fig. 9 is 8-bit 15GHz GaAs HBT ROM-less DDS circuit simulation result.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 2.In this DDS circuit, comprise N-bit streamline accumulator 21, (N-2)-bit width XOR computing array 22, time delay circuit 23, thermometer encoder 24, sine weighting non-linear DAC 25, gilbert (Gilbert) multiplier unit 26 and clock distribution network 27, wherein, N is the natural number greater than 2.
The sinusoidal waveform phase information that DDS structure provided by the present invention adopts thermometer encoder and the non-linear Digital To Analog Convert of sine weighting (DAC) that accumulator is exported is converted to amplitude information.Here, thermometer encoder cooperates with the sine weighting non-linear DAC finishes the conversion of phase place to amplitude, and it is indispensable to complement each other.
Usually the binary format coding that in digital circuit, uses, when being used for the current supply switch of Control current rudder DAC, each current source weighted value all is 2 times of corresponding current source, last position weighted value, and along with increasing progressively of DAC electric current output node electric current sum, to there be a plurality of current switches between " closing " and " opening " state, to switch at every turn, this will cause DAC electric current output node electric current sum to change and have burr (Glitch), thereby make the deterioration of DDS output waveform signals.In addition, because each current source weighted value of binary format coding requirement all is 2 times of corresponding current source, last position weighted value, when the DAC figure place was big, the maximum weighted value of current source was very big with the ratio of minimum weight value, and semiconductor technology can not be realized.
As example, be illustrated in figure 3 as the 3-bit binary coding to the conversion of 7-bit thermometer coding.Can see, along with the decimal numeral of representative increases progressively, thermometer coding has only a bit to change at every turn, and corresponding to having only a current switch state to switch between " closing " and " opening " state among the DAC, all the other all current switches all keep original state constant.Obviously, adopt the DAC of thermometer coding, its current switch is avoided occurring simultaneously a plurality of states and is switched, thereby with respect to binary-coded DAC monotonicity is preferably arranged, bring less Glitch, so Spurious Free Dynamic Range (SFDR) performance of DAC output is changed.
In addition, all identical based on all current source weighted values among the linear DAC of thermometer coding form, on semiconductor technology realizes, the better matching performance is arranged, also can bring SFDR performance preferably.The shortcoming of thermometer coding form is the increase of circuit complexity, and the width of the thermometer coding form of N-bit binary coded format correspondence is (2
N-1)-bit.
Include (2 in the sine weighting non-linear DAC
N-1) individual current source and current switch, the value of current source is a sine weighting, so be non-linear DAC.Consider sine-shaped symmetry, low (N-2)-bit data among the N-bit result of accumulator output are carried out the XOR operation with the second high position data 2nd-MSB respectively separately, output (N-2)-bit width result data is realized the expansion of sinusoidal waveform from first quartile (monotonic increase) to second quadrant (monotone decreasing); The first high position data 1st-MSB among the N-bit result of the streamline accumulator output of process time delay carries out multiplication mutually with the signal of sine weighting non-linear DAC output, has realized that sinusoidal waveform is from first, second quadrant to the three, four-quadrant expansion.So the calculating of the weighted value of each current source of sine weighting non-linear DAC only needs to consider the range value of sinusoidal waveform in the first quartile part.
It should be noted that, the ROM-less DDS that the FREQUENCY CONTROL word width is N-bit, low (N-2)-bit data among the N-bit result of accumulator output are carried out the XOR operation with the second high position data 2nd-MSB respectively separately, output (N-2)-bit width result data enters into thermometer encoder, so the width of thermometer coding form is (2
N-2-1)-bit.
Describe below in the sine weighting non-linear DAC (2
N-2-1) computational methods of individual current source weighted value.
The phase place of sinusoidal waveform one-period is divided into 2
NEqual portions, promptly getting on the sinusoidal waveform of one-period equidistantly is (2 pi/2s
N) radian 2
NThe pairing amplitude of individual point is come the sinusoidal waveform in whole cycle of match, and corresponding to the first quartile part then has 2
N/ 4=2
N-2Individual, their institute's corresponding phase values are
These are 2 years old
N-2The pairing sinusoidal waveform amplitude of phase place is for to ask SIN function separately to them, for
Calculate this 2
N-2Each is worth the poor (for lowest-order values of value previous with it individual value
Calculate itself and 0 poor), and will obtain 2
N-2Individual difference is respectively for the highest order amplitude
With the second high-order amplitude
Poorly (be made as X here, promptly have
Carry out normalization, obtain one 2
N-2The sequence of number:
Establishing this sequence for convenient description is
These are 2 years old
N-2Individual value is removed first value a
1In addition, remaining (2
N-2-1) individual value is in the sine weighting non-linear DAC (2
N-2-1) weighted value of individual current source, each current source all has the switch of a correspondence, by (2 of thermometer coding output
N-2-1)-the bit Data Control its " open " and " closing " state; First is worth a
1Can be used as a weighted value that is in the current source of " often closing " state.So in fact sine weighting non-linear DAC one has 2
N-2Current source with different weights value, its output all links together, and constitutes the current summation node.
The computational methods of each current source weighted value and DAC circuit form are as shown in Figure 4 in the sine weighting non-linear DAC.The electric current of supposing the highest order current source is I (in the side circuit as I=0.1mA), then 2
N-2The electric current of individual current source (as current source among Fig. 4 41) is
(2 of thermometer encoder output
N-2-1)-bit Data Control (2
N-2-1) individual current switch 42; 43 for electric current summation and electric current to voltage transitions, in side circuit, correspond to all current sources be connected to same node, and be voltage signal with electric current and conversion of signals through a resistance; 44 is the Gilbert multiplier unit, the first high position data 1st-MSB among the N-bit result of the streamline accumulator output of process time delay carries out multiplication mutually with the signal of sine weighting non-linear DAC output, has realized that sinusoidal waveform is from first, second quadrant to the three, four-quadrant expansion.
Each circuit module as mentioned above, with common mating reactions of electronic circuit module such as accumulator, XOR computing array and clock distribution networks, finish the operation of whole DDS circuit, output is by the high quality sine waveform of N-bit frequency control word and clock frequency specified frequency.
Below in conjunction with a specific embodiment the present invention is described in further detail.Present embodiment is a ROM-less DDS who adopts GaAs HBT design, and its frequency control word is 8-bit, and clock frequency is 15GHz, and its Circuits System block diagram as shown in Figure 5.Need to prove that 8-bit accumulator 51 output results' minimum 3 bit data are clipped, only remaining high 5 bit data, wherein highest order data 1st-MSB enters into Gilbert unit 56 through time delay circuit 53; The second high position data 2nd-MSB carries out the XOR computing respectively to its excess-three bit data in XOR computing array 52, output 3-bit result data.Accumulator output result and sinusoidal waveform phase relation are as shown in Figure 6.Thermometer encoder 54 is converted to 7-bit thermometer coding formatted data with the 3-bit binary coded format data of 52 outputs, the logical operation of thermometer encoder combinational logic circuit as shown in Figure 7, wherein 3-bit binary coded format data are b from a high position to the low level
2b
1b
0, 7-bit thermometer coding formatted data is a from a high position to the low level
6a
5a
4a
3a
2a
1a
0The computational methods of the weighted value of 8 current sources in the sine weighting non-linear DAC 55, as shown in Figure 8.The current value that we choose the normallized current source is 0.5mA, so the current value of 8 current sources is respectively:
[1.5mA，2.5mA，2.5mA，2.0mA，2.0mA，1.5mA，1.0mA，0.5mA]。
Be illustrated in figure 9 as 8-bit 15GHz GaAs HBT ROM-less DDS circuit and be time domain and frequency domain simulation result at 1 o'clock at FREQUENCY CONTROL K.According to the operation principle of DDS, the frequency of its sine wave output should be
This DDS circuit adopts GaAs HBT technological design, and all circuit structures have all adopted the fully differential structure, and the phase phasic difference is 180 ° a two-way output waveform as seen from Figure 9; Can be seen that by spectrogram the frequency of output waveform is 58.5MHz, meets fully with Theoretical Calculation, its amplitude is-6.57dBm; The spurious signal component frequency of amplitude peak is 1.817GHz, and its amplitude is-36.57dBm, thereby the Spurious Free Dynamic Range that can calculate output waveform is:
SFDR＝(-6.57dBm)-(-36.57dBm)＝30dBc。
Actual design embodiment shows, adopt the DDS circuit of ROM-less DDS structural design provided by the present invention, eliminated the waveform storage ROM in the traditional structure fully, thereby circuit work frequency is improved significantly, power consumption and area are also significantly reduced simultaneously.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. ROM-less DDS circuit structure, it is characterized in that, comprise the streamline accumulator, XOR unit, thermometer encoder, sine weighting non-linear DAC and the Gilbert multiplier unit that connect successively, wherein, the streamline accumulator also is connected in the Gilbert multiplier unit.
2. ROM-less DDS circuit structure according to claim 1, it is characterized in that, described streamline accumulator is a N-bit streamline accumulator, N is the natural number greater than 2, be used for will input the operation that adds up of N-bit frequency control word, in each clock cycle, export an accumulation result, and will export to described Gilbert multiplier unit through the N-bit result of time delay to described XOR unit.
3. ROM-less DDS circuit structure according to claim 1, it is characterized in that, described XOR unit is (N-2)-bit width XOR computing array, N is the natural number greater than 2, be used for low (N-2)-bit data of the N-bit result of described streamline accumulator output are carried out the XOR operation with the second high position data 2nd-MSB respectively separately, and to described thermometer encoder output (N-2)-bit width result data.
4. ROM-less DDS circuit structure according to claim 3 is characterized in that, this XOR computing array has been realized the expansion of second quadrant of sinusoidal waveform from the monotonically increasing first quartile to monotone decreasing.
5. ROM-less DDS circuit structure according to claim 1, it is characterized in that, described thermometer encoder, be used for the binary coded format digital coding of (N-2)-bit width of described XOR unit output thermometer coding formatted data, and export to described sine weighting non-linear DAC for [2^ (N-2)-1]-bit width.
6. ROM-less DDS circuit structure according to claim 1, it is characterized in that, described sine weighting non-linear DAC comprises [2^ (N-2)-1] individual current source, the switch of each current source is controlled by the corresponding position in the thermometer coding formatted data of [2^ (N-2)-the 1]-bit width of described thermometer encoder output respectively, and the current value of current source is a sine weighting.
7. ROM-less DDS circuit structure according to claim 6, it is characterized in that, logic " height " or " low " according to corresponding of the thermometer coding formatted data of [2^ (N-2)-1]-bit width, the corresponding current sources switch cuts out or opens in the described sine weighting non-linear DAC, the electric current of corresponding weighted value is joined on the output node of DAC, total current on the DAC output node is converted to voltage signal through a resistance, the range value of this voltage signal has represented sinusoidal waveform first, the range value of second quadrant, this voltage signal are exported to described Gilbert multiplier unit.
8. ROM-less DDS circuit structure according to claim 1, it is characterized in that, described Gilbert multiplier unit is used for and will carries out multiplication mutually with the voltage signal that described sine weighting non-linear DAC is exported through the N-bit result's of the streamline accumulator of time delay output the first high position data 1st-MSB, has realized that sinusoidal waveform is from first, second quadrant to the three, four-quadrant expansion.
9. ROM-less DDS circuit structure according to claim 1 is characterized in that, the output signal of described Gilbert multiplier unit is the output signal of whole ROM-less DDS circuit.
10. ROM-less DDS circuit structure according to claim 1, it is characterized in that, this structure further comprises a clock distribution network, and this clock distribution network is exported to streamline accumulator, XOR unit and thermometer encoder simultaneously with the clock signal that receives.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100919617A CN102006066B (en) | 2009-09-02 | 2009-09-02 | ROM-less DDS circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100919617A CN102006066B (en) | 2009-09-02 | 2009-09-02 | ROM-less DDS circuit structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102006066A true CN102006066A (en) | 2011-04-06 |
| CN102006066B CN102006066B (en) | 2012-06-27 |
Family
ID=43813183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100919617A Active CN102006066B (en) | 2009-09-02 | 2009-09-02 | ROM-less DDS circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102006066B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102394644A (en) * | 2011-09-08 | 2012-03-28 | 华东师范大学 | Fitting method of cosine signal |
| CN102891680A (en) * | 2011-07-22 | 2013-01-23 | 中山大学 | Direct frequency synthesizer |
| CN104897994A (en) * | 2015-06-10 | 2015-09-09 | 中国科学院光电技术研究所 | FPGA-based full-digital high-precision multipath frequency sweep module |
| CN115102553A (en) * | 2022-08-26 | 2022-09-23 | 深圳市汇顶科技股份有限公司 | Device for converting binary code into thermometer code and electronic equipment |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101109973A (en) * | 2007-07-11 | 2008-01-23 | 北京大学深圳研究生院 | Waveform generator based on direct numerical frequency synthesizer |
| CN101286185A (en) * | 2008-06-05 | 2008-10-15 | 北京北广科数字广播电视技术有限公司 | Numerical frequency synthesis circuit compiler accomplishing method based on linear interpolation structure |
-
2009
- 2009-09-02 CN CN2009100919617A patent/CN102006066B/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102891680A (en) * | 2011-07-22 | 2013-01-23 | 中山大学 | Direct frequency synthesizer |
| CN102394644A (en) * | 2011-09-08 | 2012-03-28 | 华东师范大学 | Fitting method of cosine signal |
| CN102394644B (en) * | 2011-09-08 | 2013-05-01 | 华东师范大学 | Fitting method of cosine signal |
| CN104897994A (en) * | 2015-06-10 | 2015-09-09 | 中国科学院光电技术研究所 | FPGA-based full-digital high-precision multipath frequency sweep module |
| CN115102553A (en) * | 2022-08-26 | 2022-09-23 | 深圳市汇顶科技股份有限公司 | Device for converting binary code into thermometer code and electronic equipment |
| CN115102553B (en) * | 2022-08-26 | 2022-12-23 | 深圳市汇顶科技股份有限公司 | Device for converting binary code into thermometer code and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102006066B (en) | 2012-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103488245B (en) | Phase amplitude conversion method in DDS and device | |
| GB2415845A (en) | Numerically controlled oscillator and method of operation | |
| CN102006066B (en) | ROM-less DDS circuit structure | |
| CN103346791B (en) | There is the Direct Digital Frequency Synthesizers simplifying AND and rebuild ADD logic array | |
| CN111900990A (en) | Current steering type digital-to-analog converter based on hybrid coding | |
| CN102006067B (en) | DDS (Digital Display Scope) circuit structure with waveform correction ROM (Read Only Memory) | |
| US7579973B2 (en) | Analog-to-digital converter | |
| KR101085106B1 (en) | Direct digital frequency synthesizer using hybrid digital to analog converter and synthesizing method thereof | |
| US7205913B2 (en) | Efficient data-directed scrambler for noise-shaping mixed-signal converters | |
| CN102857226A (en) | Successive approximation type analog-to-digital converter | |
| CN104852733A (en) | Dynamic element matching encoder | |
| CN102394653A (en) | Digital analog converter and digital analog conversion method | |
| CN104579352A (en) | Device and method for converting codes from thermometer codes to binary codes based on FPGA | |
| US11616509B1 (en) | Programmable dynamic element matching encoder for a digital-to-analog converter (DAC) and method of programming for a plurality of sampling intervals | |
| CN113157247B (en) | Reconfigurable integer-floating point multiplier | |
| CN104852734A (en) | Time relaxation-intertwined zeroing dynamic element matching encoder | |
| CN109672446B (en) | Sectional pseudo data weighted average DEM circuit | |
| US7603398B2 (en) | Data converter and a delay threshold comparator | |
| Baikady et al. | Area and Power Efficient Architecture for Direct Digital Frequency Synthesizer | |
| CN109639276B (en) | Double-time-interleaved current-steering DAC with DRRZ correction function | |
| Yao et al. | Hardware simplification to the delta path in a MASH 111 delta–sigma modulator | |
| CN103684452B (en) | A kind of method and apparatus of dynamic cell coupling | |
| CN108696280B (en) | Digital-to-analog converter | |
| KR20160101509A (en) | Frequency synthesizer using nonlinear digital to analog converter and method thereof | |
| NL1010298C2 (en) | Flash analog-to-digital converter. |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180903 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20181106 Address after: 215000 Jiangsu Suzhou Industrial Park 99 Jinji Hu Road 99 Suzhou Nancheng 1 building 505 room Patentee after: Zhongke core (Suzhou) Microelectronics Technology Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Beijing Zhongke micro Investment Management Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190815 Address after: Unit 505, 218 A7 Floor, Xinghu Street, Suzhou Industrial Park, Jiangsu Province Patentee after: ACELA MICRO CO.,LTD. Address before: Room 505, No. 99 Jinjihu Avenue, Suzhou Industrial Park, Jiangsu Province Patentee before: Zhongke core (Suzhou) Microelectronics Technology Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| CP03 | Change of name, title or address |
Address after: Room 708-1, Building 1, Northwest District, Suzhou Nanocity, No. 99 Jinjihu Avenue, Suzhou Industrial Park, Suzhou Area, China (Jiangsu) Free Trade Pilot Zone, Suzhou City, Jiangsu Province, 215124 Patentee after: Xunxin Microelectronics (Suzhou) Co.,Ltd. Address before: 215000 unit 505, a7 / F, 218 Xinghu street, Suzhou Industrial Park, Suzhou City, Jiangsu Province Patentee before: ACELA MICRO CO.,LTD. |
|
| CP03 | Change of name, title or address |