TWI469148B - System and method for erasing data of a flash memory - Google Patents
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Description
本發明涉及一種資料擦除系統及方法，尤其涉及一種快閃記憶體資料擦除系統及方法。The present invention relates to a data erasing system and method, and more particularly to a flash memory data erasing system and method.
快閃記憶體(Flash memory)是在20世紀80年代末逐漸發展起來的一種新型非易失性半導體記憶體，它結合了以往EPROM結構簡單、密度高和EPROM在系統的電可擦除性的一些優點，實現了高密度、低成本和高可靠性。Flash memory is a new type of non-volatile semiconductor memory that was developed in the late 1980s. It combines the simple structure of EPROM, high density and the electrical erasability of EPROM in the system. Some advantages are achieved in high density, low cost and high reliability.
目前，大多數通訊裝置採用了快閃記憶體做為儲存介質。所述快閃記憶體包括多個固定大小的區塊，所述區塊大小通常為128bytes、64bytes、32bytes、16bytes或者8bytes，在對快閃記憶體進行擦除時是以所述區塊為單位進行擦除。正確擦除後的快閃記憶體處於正常狀態：可寫入新的資料，並且寫入的資料格式正確，可以被正確讀取。但是，當在擦除過程中出現異常，例如：通訊裝置突然斷電，則會造成擦除後的區塊處於錯誤狀態：不能寫入新的資料；或者，可以寫入新的資料，但是寫入後的資料格式錯誤，不能被正確讀取。Currently, most communication devices use flash memory as a storage medium. The flash memory includes a plurality of fixed-size blocks, and the block size is usually 128 bytes, 64 bytes, 32 bytes, 16 bytes, or 8 bytes, and is performed in units of the blocks when erasing the flash memory. Erase. The flash memory after proper erasure is in a normal state: new data can be written, and the written data is in the correct format and can be read correctly. However, when an abnormality occurs during the erasing process, for example, the communication device suddenly loses power, the erased block is in an error state: new data cannot be written; or, new data can be written, but written The format of the data after the entry is incorrect and cannot be read correctly.
鑒於以上資料，有必要提供一種快閃記憶體資料擦除系統及方法，可以對快閃記憶體進行多次擦除，使擦除後的快閃記憶體處於正常狀態。In view of the above information, it is necessary to provide a flash memory data erasing system and method, which can erase the flash memory multiple times, so that the erased flash memory is in a normal state.
一種快閃記憶體資料擦除系統，該系統運行於安裝有快閃記憶體的通訊裝置中，該系統包括：初始化模組，用於當需要對該快閃記憶體進行資料擦除時，設置該快閃記憶體中區塊的當前擦除次數和最大擦除次數，並初始化當前擦除次數值為0；擦除模組，用於對該快閃記憶體中需進行資料擦除的一個區塊進行一次資料擦除，並將當前擦除次數加1；設置模組，用於將該進行擦除後的區塊的第一個位元設置為0；判斷模組，用於當該擦除後的區塊中第一個位元以外的其他位元都為1時，判斷是否繼續擦除該快閃記憶體的其他區塊；及提示模組，用於當該擦除後的區塊中除了第一個位元以外的其他位元不全為1，並且該區塊的當前擦除次數值等於最大擦除次數值時，提示用戶該快閃記憶體出現異常。A flash memory data erasing system running in a communication device equipped with a flash memory, the system comprising: an initialization module, configured to set when the data is to be erased for the flash memory The current erasure count and the maximum erasure count of the block in the flash memory, and initialize the current erasure count value to 0; the erase module is used for one of the flash memory to be erased. The block performs a data erasure and increases the current erasure count by one; the setting module is configured to set the first bit of the erased block to 0; the judging module is used for When the other bits except the first bit in the erased block are all 1, it is judged whether to continue erasing other blocks of the flash memory; and the prompting module is used for the erased The other bits in the block except the first bit are not all 1, and when the current erasure count value of the block is equal to the maximum erasure count value, the user is prompted to have an abnormality in the flash memory.
一種快閃記憶體資料擦除方法，應用於安裝有快閃記憶體的通訊裝置中，該方法包括如下步驟：(a)當需要對快閃記憶體進行資料擦除時，設置該快閃記憶體中區塊的當前擦除次數和最大擦除次數值；(b)初始化當前擦除次數值為0；(c)對快閃記憶體中需進行資料擦除的一個區塊進行一次資料擦除，並將擦除次數值加1；(d)將該進行擦除後的區塊的第一個位元設置為0；(e)判斷該擦除後的區塊中第一個位元以外的其他位元是否都為1；(f)當該擦除後的區塊中第一個位元以外的其他位元都為1時，若需要繼續擦除該快閃記憶體的其他區塊，則返回至步驟(b)；或者，(g)當該擦除後的區塊中除了第一個位元以外的其他位元不全為1時，判斷該區塊的當前擦除次數值是否小於最大擦除次數值；(h)當該擦除後的區塊中除了第一個位元以外的其他位元不全為1，並且該區塊的當前擦除次數等於最大擦除次數值時，提示用戶快閃記憶體出現異常；或者，當該擦除後的區塊中除了第一個位元以外的其他位元不全為1，並且該區塊的當前擦除次數值小於最大擦除次數值時，返回至步驟(c)。A flash memory data erasing method is applied to a communication device equipped with a flash memory, the method comprising the following steps: (a) setting the flash memory when data erasing of the flash memory is required The current erasure number and the maximum erasure count value of the block in the body; (b) initializing the current erasure count value to 0; (c) performing a data wipe on a block in the flash memory that needs to be erased by data. Divide and add the erasure count value to 1; (d) set the first bit of the erased block to 0; (e) determine the first bit in the erased block Whether all other bits except 1 are; (f) when all the bits other than the first bit in the erased block are 1, if it is necessary to continue erasing other areas of the flash memory Block, return to step (b); or, (g) when the erased block other than the first bit is not all 1, determine the current erasure value of the block Whether it is less than the maximum erasure count value; (h) when the erased block is not all bits other than the first bit, and the block When the current erasure number is equal to the maximum erasure number value, the user is prompted to have an abnormality in the flash memory; or, when the erased block is not all bits except the first bit, the area is not all When the current erasure count value of the block is less than the maximum erasure count value, the process returns to step (c).
相較於習知技術，所述的快閃記憶體資料擦除系統及方法，可以設置快閃記憶體的最大擦除次數，當擦除後快閃記憶體未處於正常狀態並且當前擦除次數小於最大擦除次數時，再次對該快閃記憶體進行擦除，使擦除後的快閃記憶體處於正常狀態。Compared with the prior art, the flash memory data erasing system and method can set the maximum erasure frequency of the flash memory, and the flash memory is not in the normal state and the current erasure times after erasing. When the number of erasures is less than the maximum number of erasures, the flash memory is erased again, so that the erased flash memory is in a normal state.
如圖1所示，係本發明快閃記憶體資料擦除系統的應用環境圖。所述的快閃記憶體資料擦除系統10應用於安裝有快閃記憶體12的通訊裝置1上。所述的通訊裝置1可以是手機、個人數位助理(personal digital assistant，簡稱PDA)、掌上電腦或其他任意適用的移動終端。所述的快閃記憶體12用於儲存通訊裝置1中的文檔。所述快閃記憶體資料擦除系統10用於對快閃記憶體12中的資料進行擦除，使擦除後快閃記憶體12處於正常狀態。As shown in FIG. 1, it is an application environment diagram of the flash memory data erasing system of the present invention. The flash memory data erasing system 10 is applied to the communication device 1 on which the flash memory 12 is mounted. The communication device 1 can be a mobile phone, a personal digital assistant (PDA), a palmtop computer or any other suitable mobile terminal. The flash memory 12 is used to store documents in the communication device 1. The flash memory data erasing system 10 is configured to erase data in the flash memory 12 so that the flash memory 12 is in a normal state after erasing.
如圖2所示，係本發明快閃記憶體資料擦除系統的功能模組圖。該快閃記憶體資料擦除系統10包括：初始化模組100、擦除模組102、設置模組104、判斷模組106及提示模組108。As shown in FIG. 2, it is a functional module diagram of the flash memory data erasing system of the present invention. The flash memory data erasing system 10 includes an initialization module 100, an erasing module 102, a setting module 104, a determining module 106, and a prompting module 108.
所述初始化模組100用於當需要對快閃記憶體12進行資料擦除時，設置該快閃記憶體中區塊的資料擦除參數。所述快閃記憶體12包括多個固定大小的區塊，所述區塊大小通常為128bytes、64bytes、32bytes、16bytes或者8bytes，在對快閃記憶體12進行擦除時是以所述區塊為單位進行擦除。所述資料擦除參數包括快閃記憶體12的當前擦除次數和最大擦除次數。The initialization module 100 is configured to set a data erasure parameter of the block in the flash memory when the data is to be erased to the flash memory 12. The flash memory 12 includes a plurality of fixed size blocks, and the block size is usually 128 bytes, 64 bytes, 32 bytes, 16 bytes, or 8 bytes, which is the block when erasing the flash memory 12 Erase for the unit. The data erase parameter includes the current erase count and the maximum erase count of the flash memory 12.
所述初始化模組100還用於初始化設置的資料擦除參數。在本實施例中，所述初始化模組100初始化當前擦除次數值為0，初始化最大擦除次數值為3。The initialization module 100 is further configured to initialize the set data erasure parameter. In this embodiment, the initialization module 100 initializes the current erasure count value to 0, and initializes the maximum erasure count value to 3.
所述擦除模組102用於對快閃記憶體12中需進行資料擦除的一個區塊進行一次資料擦除，並將當前擦除次數值加1。The erasing module 102 is configured to perform a data erasure on a block in the flash memory 12 that needs to be erased, and add the current erasure value to 1.
所述設置模組104用於將該進行擦除後的區塊的第一個Bit(位元)設置為0。快閃記憶體12中每個區塊的第一個Bit用於標示該區塊的狀態，若區塊的第一Bit為0，則表示該區塊處於可被寫入資料的狀態，若區塊的第一Bit為1，則表示該區塊處於不可被寫入資料的狀態。The setting module 104 is configured to set the first bit (bit) of the block after the erasure to 0. The first bit of each block in the flash memory 12 is used to indicate the state of the block. If the first bit of the block is 0, it indicates that the block is in a state in which data can be written. The first bit of the block is 1, indicating that the block is in a state in which data cannot be written.
所述判斷模組106用於判斷該擦除後的區塊中第一個位元以外的其他位元是否都為1。若該擦除後的區塊中第一個位元以外的其他位元都為1，則表示該區塊處於正確格式的狀態；若該擦除後的區塊中第一個位元以外的其他位元不全為1，則表示該區塊的資料處於錯誤格式的狀態，例如：亂碼。The determining module 106 is configured to determine whether all the bits other than the first bit in the erased block are all 1. If the bit other than the first bit in the erased block is 1, it indicates that the block is in the correct format state; if the erased block is other than the first bit in the block If the other bits are not all 1, it means that the data of the block is in an error format state, for example: garbled.
所述判斷模組106還用於當該擦除後的區塊中第一個位元以外的其他位元都為1時，判斷是否繼續擦除該快閃記憶體12的其他區塊。若需刪除的資料佔用多個區塊，當還有區塊的資料未擦除時，判斷繼續擦除該快閃記憶體12的其他未擦除區塊；當所有區塊的資料都擦除完成時，判斷不繼續擦除該快閃記憶體12的其他區塊。The determining module 106 is further configured to determine whether to continue erasing other blocks of the flash memory 12 when all the bits other than the first bit in the erased block are 1. If the data to be deleted occupies multiple blocks, when there is still data of the block is not erased, it is judged to continue to erase other unerased blocks of the flash memory 12; when all the blocks of the data are erased Upon completion, it is judged that the other blocks of the flash memory 12 are not erased.
所述判斷模組106還用於當該擦除後的區塊中第一個位元以外的其他位元不全為1時，判斷該區塊的當前擦除次數值是否小於3。The determining module 106 is further configured to determine whether the current erasure number value of the block is less than 3 when all the bits other than the first bit in the erased block are not all ones.
所述提示模組108用於當該擦除後的區塊中除了第一個位元以外的其他位元不全為1，並且該區塊的當前擦除次數值等於3時，則提示用戶快閃記憶體12出現異常，以便用戶及時進行相對應的處理。The prompting module 108 is configured to prompt the user to be fast when the number of bits other than the first bit in the erased block is not all 1, and the current erasure number of the block is equal to 3. The flash memory 12 is abnormal, so that the user can perform corresponding processing in time.
如圖3所示，係本發明快閃記憶體資料擦除方法的較佳實施方式的流程圖。步驟S10，當需要對快閃記憶體12進行資料擦除時，初始化模組100設置該快閃記憶體中區塊的資料擦除參數。所述資料擦除參數包括快閃記憶體12的當前擦除次數和最大擦除次數。3 is a flow chart of a preferred embodiment of the flash memory data erasing method of the present invention. In step S10, when data erasure is required for the flash memory 12, the initialization module 100 sets the data erasure parameter of the block in the flash memory. The data erase parameter includes the current erase count and the maximum erase count of the flash memory 12.
步驟S12，初始化模組100初始化當前擦除次數值為0，初始化最大擦除次數值為3。In step S12, the initialization module 100 initializes the current erasure count value to 0, and initializes the maximum erasure count value to 3.
步驟S14，擦除模組102對快閃記憶體12中需進行資料擦除的一個區塊進行一次資料擦除，並將當前擦除次數值加1。In step S14, the erasing module 102 performs a data erasure on a block in the flash memory 12 that needs to be erased, and adds the current erasure value to 1.
步驟S16，設置模組104將該進行擦除後的區塊的第一個Bit(位元)設置為0。快閃記憶體12中每個區塊的第一個Bit用於標示該區塊的狀態，若區塊的第一Bit為0，則表示該區塊處於可被寫入資料的狀態，若區塊的第一Bit為1，則表示該區塊處於不可被寫入資料的狀態。In step S16, the setting module 104 sets the first bit (bit) of the block after erasure to 0. The first bit of each block in the flash memory 12 is used to indicate the state of the block. If the first bit of the block is 0, it indicates that the block is in a state in which data can be written. The first bit of the block is 1, indicating that the block is in a state in which data cannot be written.
步驟S18，判斷模組106判斷該擦除後的區塊中第一個位元以外的其他位元是否都為1。若該擦除後的區塊中第一個位元以外的其他位元都為1，則表示該區塊處於正確格式的狀態；若該擦除後的區塊中除了第一個位元以外的其他位元不全為1，則表示該區塊的資料處於錯誤格式的狀態，例如：亂碼。In step S18, the determining module 106 determines whether all the bits other than the first bit in the erased block are all 1. If the bit other than the first bit in the erased block is 1, it indicates that the block is in the correct format state; if the erased block is in addition to the first bit If the other bits are not all 1, it means that the data of the block is in an error format state, for example: garbled.
步驟S20，當該擦除後的區塊中第一個位元以外的其他位元都為1時，判斷模組106判斷是否繼續擦除該快閃記憶體12的其他區塊。若需刪除的資料佔用的多個區塊，當還有區塊的資料未擦除時，判斷繼續擦除該快閃記憶體12的其他未擦除區塊；當所有區塊的資料都擦除完成時，判斷不繼續擦除該快閃記憶體12的其他區塊。當判斷模組106判斷繼續擦除該快閃記憶體12的其他區塊時，返回至步驟S12；或者，當判斷模組106判斷不繼續擦除該快閃記憶體12的其他區塊時，結束流程。In step S20, when all the bits other than the first bit in the erased block are 1, the determining module 106 determines whether to continue erasing other blocks of the flash memory 12. If the data to be deleted is occupied by multiple blocks, when there is still data of the block is not erased, it is judged to continue to erase other unerased blocks of the flash memory 12; when all the pieces of data are wiped When completed, it is judged that the other blocks of the flash memory 12 are not erased. When the determining module 106 determines to continue to erase other blocks of the flash memory 12, the process returns to step S12; or, when the determining module 106 determines not to continue to erase other blocks of the flash memory 12, End the process.
步驟S22，當該擦除後的區塊中除了第一個位元以外的其他位元不全為1時，判斷模組106判斷該區塊的當前擦除次數值是否小於3。In step S22, when the bits other than the first bit in the erased block are not all 1, the determining module 106 determines whether the current erasure value of the block is less than 3.
步驟S24，當該擦除後的區塊中除了第一個位元以外的其他位元不全為1，並且該區塊的當前擦除次數值等於3時，提示模組108提示用戶快閃記憶體12出現異常，以便用戶及時進行相對應的處理。或者，當該擦除後的區塊中除了第一個位元以外的其他位元不全為1，並且該區塊的當前擦除次數值等於3時，返回至步驟S14。Step S24, when the other bits except the first bit in the erased block are not all 1, and the current erasure count value of the block is equal to 3, the prompting module 108 prompts the user to flash the memory. The body 12 is abnormal, so that the user can perform the corresponding processing in time. Alternatively, when the bit other than the first bit in the erased block is not all 1, and the current erasure count value of the block is equal to 3, the process returns to step S14.
綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，本發明之範圍並不以上述實施例為限，舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application.
1．．．通訊裝置1. . . Communication device
10．．．快閃記憶體資料擦除系統10. . . Flash memory data erasure system
12．．．快閃記憶體12. . . Flash memory
100．．．初始化模組100. . . Initialization module
102．．．擦除模組102. . . Erase module
104．．．設置模組104. . . Setting module
106．．．判斷模組106. . . Judging module
108．．．提示模組108. . . Prompt module
圖1係本發明快閃記憶體資料擦除系統的應用環境圖。1 is an application environment diagram of a flash memory data erasing system of the present invention.
圖2係本發明快閃記憶體資料擦除系統的功能模組圖。2 is a functional block diagram of a flash memory data erasing system of the present invention.
圖3係本發明快閃記憶體資料擦除方法的較佳實施方式的流程圖。3 is a flow chart of a preferred embodiment of the flash memory data erasing method of the present invention.
1．．．通訊裝置1. . . Communication device
10．．．快閃記憶體資料擦除系統10. . . Flash memory data erasure system
100．．．初始化模組100. . . Initialization module
102．．．擦除模組102. . . Erase module
104．．．設置模組104. . . Setting module
106．．．判斷模組106. . . Judging module
108．．．提示模組108. . . Prompt module
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98116272A TWI469148B (en) | 2009-05-15 | 2009-05-15 | System and method for erasing data of a flash memory |
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| Application Number | Priority Date | Filing Date | Title |
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| TW98116272A TWI469148B (en) | 2009-05-15 | 2009-05-15 | System and method for erasing data of a flash memory |
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| Publication Number | Publication Date |
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| TW201040970A TW201040970A (en) | 2010-11-16 |
| TWI469148B true TWI469148B (en) | 2015-01-11 |
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| TW98116272A TWI469148B (en) | 2009-05-15 | 2009-05-15 | System and method for erasing data of a flash memory |
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| TW (1) | TWI469148B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9490022B2 (en) | 2015-02-02 | 2016-11-08 | Silicon Motion, Inc. | Data storage device and data maintenance method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5621687A (en) * | 1995-05-31 | 1997-04-15 | Intel Corporation | Programmable erasure and programming time for a flash memory |
| US5715193A (en) * | 1996-05-23 | 1998-02-03 | Micron Quantum Devices, Inc. | Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks |
| US6081447A (en) * | 1991-09-13 | 2000-06-27 | Western Digital Corporation | Wear leveling techniques for flash EEPROM systems |
| US6879528B2 (en) * | 2001-06-28 | 2005-04-12 | Matsushita Electric Industrial Co., Ltd. | Control method of nonvolatile memory |
| US20060018227A1 (en) * | 2004-07-23 | 2006-01-26 | Isamu Nakajima | Controller, data memory system, data rewriting method, and computer program product |
-
2009
- 2009-05-15 TW TW98116272A patent/TWI469148B/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6081447A (en) * | 1991-09-13 | 2000-06-27 | Western Digital Corporation | Wear leveling techniques for flash EEPROM systems |
| US5621687A (en) * | 1995-05-31 | 1997-04-15 | Intel Corporation | Programmable erasure and programming time for a flash memory |
| US5715193A (en) * | 1996-05-23 | 1998-02-03 | Micron Quantum Devices, Inc. | Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks |
| US6879528B2 (en) * | 2001-06-28 | 2005-04-12 | Matsushita Electric Industrial Co., Ltd. | Control method of nonvolatile memory |
| TWI242711B (en) * | 2001-06-28 | 2005-11-01 | Matsushita Electric Ind Co Ltd | Nonvolatile memory and control method for nonvolatile memory |
| US20060018227A1 (en) * | 2004-07-23 | 2006-01-26 | Isamu Nakajima | Controller, data memory system, data rewriting method, and computer program product |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9490022B2 (en) | 2015-02-02 | 2016-11-08 | Silicon Motion, Inc. | Data storage device and data maintenance method |
| TWI573142B (en) * | 2015-02-02 | 2017-03-01 | 慧榮科技股份有限公司 | Data storage device and data maintenance method thereof |
Also Published As
| Publication number | Publication date |
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| TW201040970A (en) | 2010-11-16 |
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