TWI463715B - Vertical organic thin film transistor and manufacturing method thereof - Google Patents

Description

Vertical organic thin film transistor and manufacturing method thereof

The invention relates to a crystal crystal and a manufacturing method thereof, in particular to a vertical organic thin film transistor and a manufacturing method thereof.

The industry generally uses planar transistors as the basic circuit components. Generally, a so-called planar transistor means that a gate channel of a transistor is parallel to both surfaces of a substrate, and a drain/source region of the transistor is respectively disposed at both ends of the gate channel. .

Planar transistors have the advantage of being easy to integrate with circuits, and thus are widely used in the manufacture of integrated circuits. However, the planar transistor occupies more area of the substrate surface, so that the integration of the integrated circuit cannot be improved. In addition, in the field of liquid crystal displays, as the screen becomes increasingly finer, the area of the single pixel is smaller and smaller, resulting in an increasing proportion of the area of the pixel area of the existing planar thin film transistor ^{, which} causes The aperture ratio is reduced, and the contrast is not high.

Therefore, in order to overcome the area limitation of planar transistors, vertical transistors have been proposed. However, the method of manufacturing a vertical type transistor is not suitable for mass production because it requires a complicated multi-pass exposure developing process.

On the other hand, the display has been developed toward a lighter, thinner, flexible target, and an Organic Thin Film Transistor (OTFT) with a lower dependence on the substrate has been developed, and its greatest advantage lies in the component. It can be fabricated at low temperature (<200 °C), can be applied to plastic substrates, and the characteristics of the transistor components can be maintained when the panel is bent.

Accordingly, a vertical organic thin film transistor has been proposed to overcome the above problems. However, vertical organic thin film transistors are more difficult to fabricate. In general, the use of a conventional semiconductor process to fabricate a vertical structure requires multiple film formation processes and patterning processes, and thus a multi-face mask is required. Therefore, not only is the production process more complicated, but also the manufacturing cost increases. Moreover, the characteristics of the organic semiconductor after the lithography process are destroyed, so that the organic thin film transistor of the vertical structure produced by this method cannot obtain good element characteristics.

Fujimoto Kiyoshi et al., in Advanced Materials, 19, 525, 2007, proposed the use of polystyrene (PS) nanospheres themselves to repel each other, and to control the electrostatic control of the substrate to produce a vertical organic thin film transistor. However, electrostatically controlling the positional stability of the polystyrene sphere on the substrate is not good, so the position of the vertical channel corresponding to the position of the polystyrene sphere cannot be precisely controlled. In addition, it utilizes aluminum as a gate metal, and an oxide layer (alumina Al ₂ O ₃ ) naturally formed of aluminum is used as an insulating layer, and a depletion layer is formed by a contact interface of the insulating layer and the organic semiconductor layer. . However, the thickness of the oxide layer is very thin, so the voltage applied thereto should not be too large to avoid damage of the vertical organic thin film transistor. Furthermore, in general, since the conductivity of the organic thin film transistor is inferior to that of the general inorganic thin film transistor, it is necessary to use a metal having a better conductivity as an electrode, and the use of aluminum as a gate electrode in the document will result in The resulting vertical organic thin film transistor has poor electrical characteristics.

In view of the above, an object of the present invention is to provide a vertical organic thin film transistor which can use a metal having good conductivity as a gate electrode, and an insulating layer of a predetermined thickness is disposed thereon to solve the withstand voltage and electrical characteristics. Good question.

Another object of the present invention is to provide a method of fabricating the above-described vertical organic thin film transistor which overcomes the high cost problem of conventional multi-mask process using a micro-contact technique.

For the above purpose, the vertical organic thin film transistor of the preferred embodiment of the present invention comprises a substrate, a source layer, a first patterned insulating layer, a patterned gate layer, and a second patterned insulating layer. An organic semiconductor layer and a drain layer.

The source layer is disposed on a surface of the substrate. The first patterned insulating layer is disposed on the source layer and exposes a partial surface of the source layer. The patterned gate layer is correspondingly disposed on the first patterned insulating layer. The second patterned insulating layer has a predetermined thickness, and the second patterned insulating layer covers the patterned gate layer and the first patterned insulating layer, and exposes the partial surface. The organic semiconductor layer covers the second patterned insulating layer and the partial surface. The drain layer is disposed on the organic semiconductor layer, wherein the organic semiconductor layer serves as a vertical channel between the source layer and the drain layer.

In a preferred embodiment, the second patterned insulating layer has a predetermined thickness of between 10 nm and 2 μm, and the second patterned insulating layer is an inorganic insulating layer, such as tantalum nitride. In addition, the first patterned insulating layer is an organic insulating layer, and the material thereof is polyimine.

To achieve another object, the present invention provides a method for fabricating a vertical organic thin film transistor, comprising the steps of: embossing a source layer on a substrate using a first film; using a second film Stamping a first patterned insulating layer on the source layer, the first patterned insulating layer covering the source layer but exposing a partial surface of the source layer; using the second film in the first Stamping a patterned gate layer on the patterned insulating layer; forming a second patterned insulating layer having a predetermined thickness by using a mask process, the second patterned insulating layer covering the patterned gate layer and The first patterning the insulating layer and exposing the partial surface of the source layer; using the third film to emboss an organic semiconductor layer on the second patterned insulating layer and the partial surface; The third film core embosses a drain layer on the organic semiconductor layer.

In one embodiment, the imprinting is performed in a soft contact process. Preferably, the materials of the first, second and third membrane cores are nickel or polydimethyl siloxane (PDMS). In one embodiment, the reticle process is a lift off method.

According to the vertical organic thin film transistor of the present invention and a method of fabricating the same, the second patterned insulating layer is formed using only a mask process, and the predetermined thickness is controlled to adjust the electrical characteristics of the vertical organic thin film transistor. This solves the problem of poor pressure resistance and electrical characteristics. In addition, the manufacturing method of the present invention adopts a soft printing forming process, which overcomes the high cost problem that conventionally requires multiple mask processes.

In order to make the above description of the present invention more comprehensible, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

The present specification provides various embodiments to illustrate the technical features of various embodiments of the present invention. The configuration of the components in the embodiments is for the purpose of clearly illustrating the disclosure and is not intended to limit the invention. The portions of the drawings in the different embodiments are repeated for the purpose of simplifying the description and are not intended to relate to the different embodiments.

Please refer to FIG. 1 , which illustrates a vertical organic thin film transistor according to a preferred embodiment of the present invention. It should be noted that it is not represented by actual ratio. The vertical organic thin film transistor 100 includes a substrate 110, a source layer 120, a first patterned insulating layer 130, a patterned gate layer 140, a second patterned insulating layer 150, and an organic semiconductor layer 160. And a drain layer 170. The substrate 110 is preferably a flexible substrate, such as a plastic substrate, and preferably made of polyethylene naphthalate (PEN), ethylene terephthalate (PET), polyether oxime (PES), and polyfluorene. Imine (PI). However, the present invention is not limited to being implemented as a flexible substrate, and a general glass substrate can also be implemented.

The source layer 120 is disposed on the surface of the substrate 110, and the material thereof is preferably gold. It should be noted that, in FIG. 1 , only partial representation is shown, and the source layer 120 does not cover the entire surface of the substrate 110 . The first patterned insulating layer 130 is disposed on the source layer 120 and exposes a partial surface 122 of the source layer 120. The material of the first patterned insulating layer 130 is preferably polyimine (PI) or fluorinated polymer (CYTOP).

The patterned gate layer 140 is disposed on the first patterned insulating layer 130, and is preferably made of a high conductivity metal such as gold or silver, thereby increasing the conductivity of the organic semiconductor. Accordingly, an oxide layer is less likely to be formed on the patterned gate layer 140.

The second patterned insulating layer 150 has a predetermined thickness D. The second patterned insulating layer 150 covers the side of the patterned gate layer 140 and the first patterned insulating layer 130, and exposes the source. This partial surface 122 of layer 120. It should be noted that the second patterned insulating layer 150 is formed by a photomask process (the details of which are detailed later), so that the predetermined thickness D can be controlled. The second patterned insulating layer 150 has a predetermined thickness of between 10 nm and 2 μm, and the second patterned insulating layer 150 is an inorganic insulating layer, such as tantalum nitride (SiN _X ) or tantalum oxide ( SiO ₂ ).

The organic semiconductor layer 160 covers the second patterned insulating layer 150 and the partial surface 122 to be in contact with the source layer 120. Preferably, the material of the organic semiconductor layer 160 is pentacene or copper phthalocyanine (CuPc). The drain layer 170 is disposed on the organic semiconductor layer 160, wherein the organic semiconductor layer 160 serves as a vertical channel between the source layer 120 and the drain layer 170.

Compared with the prior art, the present invention utilizes a photomask process to fabricate the second patterned insulating layer 150, and can control the predetermined thickness D to adjust the electrical characteristics of the vertical organic thin film transistor. For example, the patterned gate layer 140 and the drain layer 170 can be regarded as two parallel metal plates of a capacitor, and a dielectric (the second patterned insulating layer 150 and the organic semiconductor layer 160) is filled between the two plates. Then, the size of the capacitor is proportional to the area A of the metal plate and the dielectric coefficient ε of the medium, and inversely proportional to the distance d between the two plates, that is, C=(εA)/d. Therefore, the present invention can control the predetermined thickness D of the second patterned insulating layer 150, further control the distance d between the two plates, and change the capacitance value, thereby improving the conventionally formed oxide layer (alumina) only in the prior art. The thickness of the insulating layer is too thin to apply a large voltage.

The steps of fabricating the above-described vertical organic thin film transistor 100 will be described in detail below. Please refer to FIG. 2, which is a flow chart showing a method for fabricating a vertical organic thin film transistor according to a preferred embodiment of the present invention. The method begins in step S10.

Please refer to FIG. 3, which shows a schematic diagram of step S10. In step S10, the source layer 120 is embossed on a substrate 110 by a first film core 220. It should be noted that the above imprinting is performed by a micro contact process. Specifically, the first film core 220 is first coated with nano gold particles 125 or other suitable material, and then the nano gold particles 125 are imprinted on the substrate 110, and then released by the prior art. The type of nano gold particles 125 remains on the substrate 110. Wherein the first film core 220 is preferably nickel or a soft polydimethyl siloxane (PDMS).

Please refer to FIG. 4, which shows a schematic diagram of step S20. In step S20, a first patterned insulating layer 130 is embossed on the source layer 120 by using a second film encapsulation 240. The first patterned insulating layer 130 covers the source layer 120 but exposes the source. A partial surface 122 of layer 120. Similarly, the above embossing refers to a soft contact process. For example, the second film member 240 is first adhered to polyimine (PI) 135 or other suitable material, and the polyimide 135 is imprinted on the source layer 120. Wherein the second membrane core 240 is preferably nickel or a soft polydimethyl siloxane (PDMS).

Please refer to FIG. 5, which shows a schematic diagram of step S30. In step S20, the patterned gate layer 140 is embossed on the first patterned insulating layer 130 by the second film core 240. It should be noted that the patterned gate layer 140 has the same contour as the first patterned insulating layer 130, so that the same mold core can be used, that is, the second film core 240. Similarly, the second film core 240 is first coated with nano gold particles 125, and the nano gold particles 125 are imprinted on the first patterned insulating layer 130.

Please refer to FIGS. 6A-6C, and FIGS. 6A-6C are schematic diagrams of step S40. In step S40, a second patterned insulating layer 150 having a predetermined thickness D is formed by a mask process, and the second patterned insulating layer 150 covers the patterned gate layer 140 and the first patterned insulating layer. 130, and exposing the partial surface 122 of the source layer 120. In the preferred embodiment, the reticle process is a lift off method. Specifically, a photoresist structure 152 is formed on the partial surface 122 by a photomask as shown in FIG. 6A. Next, an inorganic insulating layer 154 is deposited thereon, such as tantalum nitride (SiN _X ) or yttrium oxide (SiO ₂ ), as shown in FIG. 6B. Finally, the photoresist structure 152 and a portion of the inorganic insulating layer 154 are removed by using a stripping agent to obtain the second patterned insulating layer 150, as shown in FIG. 6C.

Please refer to FIG. 7 , which illustrates a schematic diagram of step S50 . In step S50, the organic semiconductor layer 160 is embossed on the second patterned insulating layer 150 and the partial surface 122 by a third film core 260. Similarly, the third film 260 is first adhered to pentacene 165 or other suitable material, and pentacene 165 is embossed on the second patterned insulating layer 150 and the partial surface 122. Wherein the third membrane 260 is preferably nickel or soft polydimethyl siloxane (PDMS).

Please refer to FIG. 8 , which shows a schematic diagram of step S60 . In step S60, the third film core 260 is used to emboss the drain layer 170 on the organic semiconductor layer 160, and finally the vertical organic thin film transistor 100 of the preferred embodiment is obtained. It should be noted that the drain layer 170 has the same contour as the organic semiconductor layer 160, so that the same mold core can be used, that is, the third film core 260. Similarly, the third film core 260 is first adhered to the nano gold particles 125 or other suitable material, and the nano gold particles 125 are imprinted on the organic semiconductor layer 160.

In summary, according to the vertical organic thin film transistor of the present invention and the manufacturing method thereof, the second patterned insulating layer 150 is formed using only one mask process, and the predetermined thickness D can be controlled to adjust the vertical organic The electrical characteristics of the thin film transistor are used to solve the problem of poor pressure resistance and electrical characteristics. In addition, the manufacturing method of the present invention adopts a soft printing forming process, which overcomes the high cost problem that conventionally requires multiple mask processes.

While the invention has been described above in terms of the preferred embodiments, the invention is not intended to limit the invention, and the invention may be practiced without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

100‧‧‧Vertical organic thin film transistor

110‧‧‧Substrate

120‧‧‧Source layer

122‧‧‧Partial surface

125‧‧•nano gold particles

130‧‧‧First patterned insulation

135‧‧‧ Polyimine

140‧‧‧ patterned gate layer

150‧‧‧Second patterned insulation

152‧‧‧Light-resisting structure

154‧‧‧Inorganic insulation

160‧‧‧Organic semiconductor layer

165‧‧‧ pentacene

170‧‧‧汲pole

220‧‧‧First film kernel

240‧‧‧Second film kernel

260‧‧‧ third membrane

D‧‧‧Predetermined thickness

D‧‧‧ distance between two boards

Fig. 1 is a view showing a vertical organic thin film transistor of a preferred embodiment of the present invention.

2 is a flow chart showing a method of fabricating a vertical organic thin film transistor according to a preferred embodiment of the present invention.

FIG. 3 is a schematic diagram of step S10.

FIG. 4 is a schematic diagram of step S20.

FIG. 5 is a schematic diagram of step S30.

6A to 6C are diagrams showing the step S40.

FIG. 7 is a schematic diagram of step S50.

FIG. 8 is a schematic diagram of step S60.

100. . . Vertical organic thin film transistor

110. . . Substrate

120. . . Source layer

122. . . Partial surface

130. . . First patterned insulating layer

140. . . Patterned gate layer

150. . . Second patterned insulating layer

160. . . Organic semiconductor layer

170. . . Bungee layer

D. . . Predetermined thickness

d. . . Distance between two plates

Claims (10)

A vertical organic thin film transistor comprising: a substrate; a source layer disposed on the surface of the substrate; a first patterned insulating layer disposed on the source layer and exposing a portion of the source layer a patterned gate layer correspondingly disposed on the first patterned insulating layer; a second patterned insulating layer having a predetermined thickness, the second patterned insulating layer covering the patterned gate layer and The first patterned insulating layer has one side and exposes the partial surface; an organic semiconductor layer covering the second patterned insulating layer and the partial surface; and a drain layer disposed on the organic semiconductor layer The organic semiconductor layer serves as a vertical channel between the source layer and the drain layer. The vertical organic thin film transistor according to claim 1, wherein the second patterned insulating layer has a predetermined thickness of between 10 nm and 2 μm. The vertical organic thin film transistor according to claim 1, wherein the second patterned insulating layer is an inorganic insulating layer. The vertical organic thin film transistor according to claim 3, wherein the inorganic insulating layer is made of tantalum nitride or hafnium oxide. The vertical organic thin film transistor according to claim 1, wherein The first patterned insulating layer is an organic insulating layer. The vertical organic thin film transistor according to claim 3, wherein the material of the organic insulating layer is polyimine (PI) or fluorinated polymer (CYTOP). A method for fabricating a vertical organic thin film transistor, comprising the steps of: stamping a source layer on a substrate by using a first film; and stamping a source layer on the source layer by using a second film; a first patterned insulating layer covering the source layer but exposing a partial surface of the source layer; and stamping a first patterned insulating layer on the first patterned insulating layer Patterning a gate layer; forming a second patterned insulating layer having a predetermined thickness by a mask process, the second patterned insulating layer covering the patterned gate layer and the first patterned insulating layer a side surface, and exposing the partial surface of the source layer; using the third film core to emboss an organic semiconductor layer on the second patterned insulating layer and the partial surface; and using the third film A drain layer is imprinted on the organic semiconductor layer. The method for fabricating a vertical organic thin film transistor according to claim 7, wherein the imprinting is performed by a soft printing molding process. The method for producing a vertical organic thin film transistor according to claim 7, wherein the material of the first, second and third film cores is nickel or polydimethyl siloxane. The vertical organic thin film transistor according to claim 7 of the patent application scope The manufacturing method, wherein the mask process is a one-off method.