TWI463551B - Method for manufacturing flash memory - Google Patents

Description

Flash memory production method

The present invention relates to a method of fabricating an electronic component, and more particularly to a method of fabricating a flash memory.

Flash Memory is a non-volatile memory device that saves data without power consumption, and can be deleted or written multiple times during operation. In addition, compared to other memory devices, flash memory has lower read latency, better dynamic shock resistance, significant speed advantage when writing large amounts of data, and has a better cost structure. It is the most widely adopted technology for non-volatile solid-state storage, for example, it can be applied to notebook computers, digital walkmans, digital cameras, mobile phones, game consoles and other related products.

1A to 1C are cross-sectional views showing a manufacturing process of a conventional flash memory device. First, referring to FIG. 1A, a plurality of shallow trench isolation structures 102 are formed in the substrate 100 to define the active regions 105.

Next, referring to FIG. 1B, a tunneling dielectric layer 104 and a polysilicon layer 106 are sequentially formed on the substrate 100 of the active region 105. As the process shrinks, the width of the active area 105 also decreases. Therefore, after the polysilicon layer 106 is formed by the deposition process, a hole 110 is often generated in the polysilicon layer 106. A portion of the shallow trench isolation structure 102 is then removed to expose portions of the sidewalls of the polysilicon layer 106. Thereafter, formed on the substrate 100 Inter-gate dielectric layer 108. Since the polysilicon layer 106 has holes 110 therein, the dielectric material will build up in the holes 110 when the inter-gate dielectric layer 108 is formed.

Then, referring to FIG. 1C, a polysilicon layer 112 is formed on the substrate 100. After that, a patterning process is performed to define a plurality of word lines. Figure 2 is a top plan view of the process of Figure 1C, wherein Figure 1C is a cross-sectional view taken along line II' of Figure 2; As shown in FIG. 2, after the polysilicon layer 112 and the underlying film layer are patterned, a plurality of word lines 216 are defined.

However, since the dielectric material is deposited in the holes 110, after the polysilicon layer 112 is patterned, a residual structure 218 (a dielectric material and/or a polysilicon material) is formed on the substrate 100 between the word lines 216. The material is partially oxidized to oxide in subsequent thermal processes. As such, after the contact windows are formed on the substrate 100 between the word lines 216, these residual structures 218 can cause electrical problems in the contact windows, thereby affecting the device performance.

In view of this, the present invention provides a method of fabricating a flash memory that avoids the generation of holes in a conductor layer that is a floating gate.

The invention provides a method for manufacturing a flash memory. A substrate is provided, a patterned mask layer is formed on the substrate, and an isolation structure is formed in the substrate. The top surface of the isolation structure is coplanar with the top surface of the patterned mask layer. An etching process is performed, the etching process includes: removing a portion of the patterned mask layer; removing a portion of the isolation structure at a corner of the adjacent patterned mask layer such that a width of a top portion of the isolation structure is less than a width of the bottom portion. Repeat the etching process at least once. Remove the patterned mask layer. A first dielectric layer is formed on the substrate. A first conductor layer is formed on the oxide layer. A portion of the first conductor layer and a portion of the isolation structure are removed. Forming a second dielectric layer on the first conductor layer and the isolation structure. A second conductor layer is formed on the second dielectric layer.

In an embodiment of the invention, the first conductor layer is formed by, for example, forming a layer of a conductor material on the substrate, and the layer of the conductor material covers the isolation structure. Then, a planarization process is performed to remove a portion of the conductor material layer and remove the top portion of the isolation structure.

In one embodiment of the invention, the above method of removing a portion of the patterned mask layer is, for example, wet etching using hot phosphoric acid.

In an embodiment of the invention, the thickness of the patterned mask layer removed during the etching process is, for example, between 200 Å and 600 Å.

In one embodiment of the invention, the method of removing a portion of the isolation structure adjacent the corners of the patterned mask layer is, for example, wet etching using diluted hydrofluoric acid.

In an embodiment of the invention, the thickness of the isolation structure removed during the etching process is, for example, between 12.5 Å and 37.5 Å.

In an embodiment of the present invention, the method for forming the isolation structure is, for example, first using a patterned mask layer as a mask to remove a portion of the substrate to form a trench. Next, a layer of isolation material is formed on the substrate and fills the trench. Thereafter, a planarization process is performed to remove the layer of isolation material outside the trench.

In an embodiment of the invention, a portion of the isolation structure may also be removed after the planarization process and prior to the etching process.

In an embodiment of the invention, after removing the patterned mask layer And before the formation of the oxide layer, an oxidation process can also be performed to form a sacrificial oxide layer on the substrate. Then, the sacrificial oxide layer is removed.

In one embodiment of the invention, the above method of removing the sacrificial oxide layer is, for example, wet etching using diluted hydrofluoric acid.

Based on the above, the present invention has a wider process between the top portions of adjacent isolation structures by performing two or more etching processes (this etching process includes one patterning mask layer etching process and one isolation structure etching process). The distance, and thus the formation of a conductor layer as a floating gate, can be avoided, and holes are formed in this conductor layer.

The above described features and advantages of the present invention will be more apparent from the following description.

3A-3H are cross-sectional views showing a manufacturing process of a flash memory according to an embodiment of the invention.

First, referring to FIG. 3A, a substrate 300 is provided. The substrate 300 is, for example, a crucible substrate. A patterned mask layer 302 is then formed on the substrate 300. The material of the patterned mask layer 302 is, for example, a nitride. Incidentally, an oxide layer may be formed as a buffer layer (not shown) before forming the mask layer 302, thereby reducing the stress between the mask layer 302 and the substrate 300. Next, an etching process is performed by patterning the mask layer 302 as a mask to form a trench 303 in the substrate 300. Then, a layer of the spacer material is formed on the substrate 300 and fills the trench 303. The material of the layer of isolating material is, for example, an oxide. After that, a planarization process (for example, a chemical mechanical polishing process) is performed to remove the trench A layer of isolation material outside of 303 to form isolation structure 304. After the planarization process described above, the top surface of the isolation structure 304 and the top surface of the patterned mask layer 302 are coplanar. An active region 305 is defined between adjacent isolation structures 304. Active region 305 has a width d1.

Next, referring to FIG. 3B, the oxide remaining on the active region 305 is removed. The method of removing the residual oxide is, for example, wet etching using diluted hydrofluoric acid. In particular, since the material of the isolation structure 304 is an oxide, in addition to removing the oxide remaining on the active region 305 during the wet etching process, a portion of the isolation structure 304 is simultaneously removed. The surface of the isolation structure 304 is made lower than the surface of the patterned mask layer 302.

Then, the etching process of the present invention is performed. The etching process includes a patterned mask layer etching process and a primary isolation structure etching process, which will be described in detail below. First, referring to FIG. 3C, a patterned mask layer etching process is performed to remove a portion of the patterned mask layer 302 such that the surface of the patterned mask layer 302 is lower than the surface of the isolation structure 304 to expose the isolation structure 304. Part of the side wall. In this step, for example, wet etching is performed using hot phosphoric acid, and the thickness of the removed patterned mask layer 302 is, for example, between 200 Å and 600 Å. Then, referring to FIG. 3D, an isolation structure etching process is performed to remove a portion of the isolation structure 304 at a corner of the adjacent patterned mask layer 302 such that the width of the top portion 304a of the isolation structure 304 is less than the width of the bottom portion. In the present embodiment, the top portion 304a is the portion that is etched by the isolation structure, and the bottom portion is the portion that is not etched by the isolation structure. In this step, for example, using diluted The hydrofluoric acid is wet etched and the removed isolation structure 304 has a thickness between about 12.5 Å and 37.5 Å. After the etching process of the present invention (steps illustrated in FIGS. 3C-3D), the width d2 between the top portions 304a of adjacent isolation structures 304 may be greater than the active region 305 having a width d1.

Next, referring to FIG. 3E, the etching process is repeated once, that is, the patterned mask layer etching process and the first isolation structure etching process are performed again, so that the width d3 between the top portions 304a of the adjacent isolation structures 304 is greater than that of FIG. 3D. The width in d2. In this embodiment, the secondary etching process (including one patterning mask layer etching process and one isolation structure etching process) is repeated, but the present invention is not limited thereto, and in other embodiments, it may be repeated three times. Or more than three etching processes to provide the desired width between the top portions 304a of adjacent isolation structures 304.

Then, referring to FIG. 3F, the patterned mask layer 302 is removed. The method of removing the patterned mask layer 302 is, for example, wet etching with hot phosphoric acid. After the patterned mask layer 302 is completely removed, an ion implantation step can be performed to form a well region (not shown) in the substrate 300. Next, a sacrificial oxide layer (not shown) is selectively formed on the substrate 300. The formation method of the sacrificial oxide layer is, for example, a thermal oxidation method. The sacrificial oxide layer can transform the substrate 300 damaged in the ion implantation step described above into an oxide layer. Then, the sacrificial oxide layer is removed. After sacrificing the oxide layer, the substrate 300 does not have a portion that is damaged during the ion implantation step.

Referring to FIG. 3F, a first dielectric layer 306 is formed on the substrate 300. The first dielectric layer 306 is used as a material for the tunneling dielectric layer in the flash memory. The material of the first dielectric layer 306 is, for example, an oxide, and the formation method thereof is, for example, a thermal oxidation method. Then, a conductor material layer 307 is formed on the first dielectric layer 306. The material of the conductor material layer 307 is, for example, polycrystalline germanium. In the present embodiment, since the top portion 304a of the adjacent isolation structure 304 has a large width d ₃ between the conductive material layer 307, it is possible to avoid formation of the hole in the conductor material layer due to poor coverage. 307.

Next, referring to FIG. 3G, the substrate 300 is planarized to remove a portion of the conductor material layer 307, and the top portion 304a of the isolation structure 304 is removed, thereby forming the first conductor layer 308. The first conductor layer 308 is used as a floating gate in the flash memory. In particular, after the top portion 304a of the isolation structure 304 is removed, the adjacent conductor layers 308 can be prevented from being too close to cause a disturb problem in the subsequent formation of the flash memory during operation.

Then, referring to FIG. 3H, a portion of the isolation structure 304 is removed such that the surface of the isolation structure 304 is lower than the surface of the first conductor layer 308 to expose portions of the sidewalls of the first conductor layer 308. In this way, the overlapping area between the floating gate and the control gate in the subsequently formed flash memory can be increased to increase the gate coupling ratio (GCR). Then, a second dielectric layer 310 is formed on the substrate 300. The material of the second dielectric layer 310 is a composite layer composed of an oxide/nitride/oxide. Next, a second conductor layer 312 is formed on the second dielectric layer 310. The material of the second conductor layer 312 is, for example, polysilicon. The second conductor layer 312 is used as a material for controlling the gate and word lines of the flash memory. Next, a patterning process is performed to define the word lines and gate structures. Thereafter, a doping process is performed to form a doped region as a source/drain region of the flash memory. The above described patterning process and doping process are well known to those skilled in the art and will not be described herein. In this embodiment, due to the guide The body material layer 307 does not have holes, so that no dielectric material is filled into the holes when the second dielectric layer 312 is formed. In this way, after the word line is defined, there is no dielectric material or conductor material remaining between adjacent word lines, which can avoid the formation of contact windows on the substrate 300 between the word lines. The electrical problem of the contact window.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 300‧‧‧ base

102, 304‧‧‧ isolation structure

104‧‧‧Tunnel dielectric layer

105, 305‧‧‧ active area

106, 112‧‧‧ polycrystalline layer

108‧‧‧Interruptor dielectric layer

110‧‧‧ hole

216‧‧‧ character line

218‧‧‧Residual structure

216‧‧‧ character line

218‧‧‧Residual structure

302‧‧‧ patterned mask layer

303‧‧‧ Ditch

304a‧‧‧Top part

306‧‧‧First dielectric layer

307‧‧‧layer of conductor material

308‧‧‧First conductor layer

310‧‧‧Second dielectric layer

312‧‧‧Second conductor layer

D1, d2, d3‧‧‧ width

I-I'‧‧‧ hatching

1A-1C are cross-sectional views showing a manufacturing process of a flash memory according to the prior art, wherein FIG. 1C is a cross-sectional view taken along line II-' of FIG. 2.

2 is a top plan view of the flash memory after performing the steps described in FIG. 1C.

3A-3H are cross-sectional views showing a manufacturing process of a flash memory according to an embodiment of the invention.

300‧‧‧Base

302‧‧‧ patterned mask layer

303‧‧‧ Ditch

304‧‧‧Isolation structure

305‧‧‧active area

d ₃ ‧‧‧Width

Claims (10)

A method of fabricating a flash memory, comprising: providing a substrate on which a patterned mask layer is formed, and an isolation structure is formed in the substrate, wherein a top surface of the isolation structure and the patterned mask The top surface of the curtain layer is coplanar; an etching process is performed, the etching process includes: removing a portion of the patterned mask layer; and removing the adjacent patterning after removing a portion of the patterned mask layer a portion of the isolation structure at a corner of the mask layer such that a width of a top portion of the isolation structure is less than a width of the bottom portion; repeating the etching process at least once; removing the patterned mask layer; Forming a first dielectric layer on the substrate; forming a first conductor layer on the oxide layer; removing a portion of the first conductor layer and a portion of the isolation structure; and the first conductor layer and the isolation structure Forming a second dielectric layer thereon; and forming a second conductor layer on the second dielectric layer. The method for fabricating a flash memory according to claim 1, wherein the forming method of the first conductor layer comprises: forming a conductor material layer on the substrate, the conductor material layer covering the isolation structure And performing a planarization process, removing portions of the conductor material layer and removing The top portion of the isolation structure. The method of fabricating a flash memory according to claim 1, wherein the method of removing a portion of the patterned mask layer comprises wet etching using hot phosphoric acid. The method of fabricating a flash memory according to claim 1, wherein the patterned mask layer is removed in a thickness of between 200 Å and 600 Å in the etching process. The method of fabricating a flash memory according to claim 1, wherein the method of removing a portion of the isolation structure adjacent to a corner of the patterned mask layer comprises wet using diluted hydrofluoric acid. Etching. The method of fabricating a flash memory according to claim 1, wherein the isolation structure is removed in a thickness of between 12.5 Å and 37.5 Å in the etching process. The method for fabricating a flash memory according to claim 1, wherein the method for forming the isolation structure comprises: removing the portion of the substrate by using the patterned mask layer as a mask to form a trench Forming a layer of isolation material on the substrate and filling the trench; and performing a planarization process to remove the layer of isolation material outside the trench. The method of fabricating a flash memory according to claim 7, wherein after the performing the planarization process and before performing the etching process, a portion of the isolation structure is further removed. The method of fabricating the flash memory of claim 1, wherein after the removing the patterned mask layer and before forming the oxide layer, the method further comprises: performing an oxidation process to Forming a sacrificial oxide layer on the substrate; and removing the sacrificial oxide layer. The method of fabricating a flash memory according to claim 9, wherein the method of removing the sacrificial oxide layer comprises wet etching using diluted hydrofluoric acid.