TWI458304B - Data transmitting apparatus and method of transmitting signal thereof - Google Patents

Description

Data transmission device and method for transmitting signal

The present invention relates to a data transmission apparatus and method, and more particularly to a data transmission apparatus and method suitable for a DMX512 signal.

The DMX512 protocol was first introduced by the United States of Institutes for Theatre Technology (USITT) in 1986 as a data transmission standard and is a commonly used control protocol in the field of entertainment lighting. DMX512 communication mode adopts asynchronous communication format. Each dimming data consists of 11 bits, including one start time, 8 bit data byte and two stop bits, and each time 512 dimming can be transmitted. data. The current stage lighting control mostly uses the DMX512 protocol for stage lighting control.

Because the DMX512 protocol does not have addressing capabilities, luminaires that use the DMX512 protocol typically require a single chip (such as 8051 or Microchip's PIC16F628A) for data decoding and addressing. Each luminaire receives the dimming data in the DMX512 according to its own address, that is, the data byte in the slot. If a single luminaire needs to use multiple dimming data, multiple addresses need to be set. In the prior art, each circuit of the digital dimming controller has a digital multiplex address (DMX Address), and the user can set each of them with the finger-opening key built in the digital dimming controller. The digital multiplex address (DMX Address) of the loop is used to set the corresponding address.

However, in the circuit system, the DMX512 protocol signal will cause waveform distortion due to serial connection, causing the serial signal to violate the time specification of the DMX512 protocol (for example, the bit time specification: the minimum value is 3.92us, the maximum value is 4.08us), so that the string The connected device cannot read the correct set value. Moreover, the address setting needs to be individually set for each device, which is quite troublesome, so the setting position of the dimmer cannot be adjusted at will.

The present invention provides a data transmission device that transmits signals by a plurality of serially connected circuit units, each circuit unit inverting its waveform and extending the time of the header to cover the time after capturing the corresponding dimming data. The position of the slot is read, and then the adjusted signal is transmitted to the circuit unit of the next stage. Thereby, the serially connected circuit unit can capture the dimming data in the signal according to the sequence of the series connection and avoid waveform distortion according to the sequence of the serial connection, and the signal transmitted corresponds to the signal format of the DMX512.

The invention provides a method for transmitting a signal. In the process of transmitting, the signal is inverted and the marking signal in the signal header is extended to cover the time slot that has been read, so that the circuit unit of the next stage can directly read the corresponding Signal, and do not need to set the corresponding address.

In the above, the present invention provides a data transmission device, wherein the data transmission device includes a first circuit unit that receives the first signal and performs a waveform adjustment on the first signal to output a second signal, wherein the waveform The adjusting includes inverting a waveform of the first signal, wherein the first signal corresponds to a signal format of the DMX 512. The first signal includes a header and a plurality of time slots, wherein the time slot is located after the header, wherein the waveform adjustment further comprises extending a length of the header to cover N time slots in the time slot to generate the foregoing Two signals, N is a positive integer.

In an embodiment of the invention, the first circuit unit reads the data in the N time slots in the first signal before the first circuit unit extends the header.

In an embodiment of the present invention, the data transmission device further includes a second circuit unit coupled to the first circuit unit for receiving the second signal, and reading the M time slots of the second signal Data, the M time slots are located after the N time slots, and after reading the M time slots, extend the length of the header to cover the M time slots that have been read and extend the The second signal after the header is inverted to produce a third signal, M being a positive integer.

In an embodiment of the invention, wherein the first signal corresponds to a signal format of the DMX 512, the header includes a pre-mark (10, "Mark" time before BREAK), a reset interval and a mark (9, "MARK" Time between Slots), the first circuit unit extends the length of the mark in the header to cover the N time slots.

In an embodiment of the invention, the reset interval includes a reset sequence (12, RESET Sequence) or includes a reset sequence and X set time slots, and X is a positive integer.

In an embodiment of the invention, in the first signal, the mark is located between the reset interval and the N time slots, and the length of the mark is less than 1 second.

In an embodiment of the invention, the reset sequence sequentially includes a break, a MARK After Break, and a start time slot.

In an embodiment of the invention, the start time slot sequentially includes a start time, an octet start code, and two end bits.

In an embodiment of the invention, each of the time slots includes a start time, an octet data byte, and two end bits.

In an embodiment of the invention, the first circuit unit further inverts the second signal and outputs the inverted second signal.

From another point of view, the present invention provides a method for transmitting a signal, comprising the steps of: first receiving a first signal, the first signal having a header and a plurality of time slots, wherein the time slot is located after the header; And then performing a waveform adjustment on the first signal to output a second signal, the waveform adjustment comprising inverting a waveform of the first signal and extending a length of the header to cover N time slots in the time slots, wherein The first signal corresponds to the signal format of the DMX 512, and N is a positive integer. For the remaining implementation details of the method, please refer to the above data transmission device, which will not be described here.

Based on the above, the present invention reverses the signal when transmitting the DMX signal to avoid waveform distortion during the serial transmission, so that the signal can be maintained within the set format time specification, and the header signal is adjusted by extending The mark waveform of the header covers the time slot that has been read, so that the circuit unit of the next stage can directly receive the correct data. By using the technical means of the invention, when transmitting the DMX signal, the individual circuit units do not need to set the address in advance, and only need to be connected in series to obtain the corresponding data according to the serial sequence of the individual circuit units, which is quite convenient in circuit design. . This method can also be applied to other signal transmission methods with headers and time slots. For example, it can be 4x speed DMX512 format, and its signal format is the same as standard DMX512, but the format time specification is one quarter of the standard DMX512 protocol time.

The above described features and advantages of the present invention will be more apparent from the following description.

First embodiment

Please refer to FIG. 1. FIG. 1 is a data transmission device according to the present invention. The data transmission device 100 is formed by serially connecting a plurality of circuit units 110, 120, 130, wherein the first circuit unit 110, the second circuit unit 120, and the third circuit unit 130 represent the first three circuit units. The first circuit unit 110 receives the first signal DMX1 in accordance with the DMX512 format, and then extracts the data of the time slot in the first DMX1 signal and performs waveform adjustment on the first signal DMX1 to output the second signal DMX2. The first signal DMX1 is composed of a header and a plurality of time slots, and the waveform adjustment includes inverting the first signal DMX1 and extending the header to cover the read time slot. Each of the circuit units 110, 120, 130 inverts the received signal and outputs the circuit unit of the next stage, so that the problem of waveform distortion during signal transmission can be avoided. This is because the rising edge time and the falling edge time of the circuit units 110, 120, 130 may not coincide, and the signal may be distorted after passing through the plurality of serially connected circuit units 110, 120, 130. The problem of waveform distortion can be improved by the inverting output, so that the transmitted signal is maintained within the format time specification of the DMX512.

It is worth noting that the waveform inversion can be realized by an inverter, and the next-stage circuit unit can also convert the inverted signal into a waveform of a normal DMX512 signal format by the inverter to facilitate reading and decoding. In addition, the software can also directly decode the original data from the digital data interpreted by the inverted signal. Those skilled in the art can easily infer the remaining embodiments through the disclosure of the present embodiment, and will not be described here.

Next, in addition to the above-described waveform inversion, the waveform adjustment of the first signal DMX1 further includes extending the header. The waveform adjustment manner for the extended header is further described as follows: the first circuit unit 110 captures the time slot in the first DMX1 signal and extends the length of the mark (Mark) in the header of the first signal DMX1 to cover the captured Time slot to generate a second signal DMX2. Similarly, after capturing the data of the first time slot in the second DMX2 signal, the second circuit unit 110 further lengthens the length of the mark (Mark) in the header of the second signal DMX2 to cover the captured data. Time slot to generate a third DMX signal DMX3. And so on, each serially connected circuit unit will extend the length of the mark (Mark) in the header after the corresponding data is captured to cover the time slot that has been captured, and then output the adjusted signal to The circuit unit of the next stage.

Since the standard DMX512 format specifies the tag time ("MARK" Time Between Slots) can be 0 to 1 second, and a DMX512 packet (DMX512 packet) can be up to 1 second. Therefore, even if the mark time is extended to cover the captured time slot, the adjusted DMX signal will still conform to the DMX512 format. Each circuit unit can directly capture the data of the top slot in the received DMX signal, and does not need to address to select the desired time slot.

2A and 2B, FIG. 2A is a waveform diagram of the first signal DMX1 according to the first embodiment of the present invention. 2B is a waveform diagram of a second signal DMX2 according to the first embodiment of the present invention. The technical means for adjusting the first signal DMX1 by the first circuit unit 110 can be clearly understood by comparing FIG. 2A with FIG. 2B. In FIG. 2A, the first signal DMX1 conforms to the standard DMX512 format, and the meanings of the individual labels are as follows: "1" indicates the length of the Break ("SPACE" for Break), and "2" indicates the post mark after the interruption. ("MARK" After Break, MAB), "3" indicates the time slot of a time slot, which consists of a starting time "4", an 8-bit data byte and two ending bits. 7", "8" is composed. "4" indicates the start time (START Time), "5" indicates the Least Significant Data Bit, "6" indicates the Most Significant Data Bit, "7" and "8""" indicates the end bit (STOP Bit), "9" indicates the mark time between adjacent time slots ("MARK" Time Between Slots), and "10" indicates the mark time before the interruption of "1"("MARK" Before Break, MBB), "11" indicates Break to Break Time, and "12" indicates RESET Sequence, which includes interrupt "1", rear mark "2", and start slot SLOT ₀ The start time slot SLOT ₀ includes a start time "4", a start code "14" and two end bits "7", "8". "13" indicates the time of a DMX512 packet (DMX512 Packet), "14" indicates the start code (START CCODE), and can also be called the data byte of the start time slot (SLOT ₀ ), and "15" indicates the first SLOT ₁ Data byte, "16" represents the data slot of the Nth time slot (SLOT _N Data byte), N is a positive integer and 2≦N≦512, each of which The data byte is 8 bits. For the format of DMX512, please refer to the specification of DMX512, which is not mentioned here.

In this embodiment, the first mark time "10" in the first signal DMX1 is positioned as a front mark, and the header SH includes a front mark "10", a reset interval RE, and a reset interval RE. the first mark "9" (located between the labeled sLOT _{0 1} starting slot when the slot sLOT). It should be noted that the reset interval RE may include only the reset sequence "12" or the reset sequence "12" and X set time slots, and X is a positive integer. The data in the set time slot can be used as a data setting for each circuit unit, and can also be used as a time slot for transmitting communication data between the circuit units, and the embodiment is not limited.

After the header SH, there are a plurality of time slots, and adjacent slots are separated by a mark "9". When the circuit unit 110 receives the first signal DMX1, it will retrieve the data byte "15" in the foremost time slot SLOT ₁ , and then extend the length of the mark "9" located in the header SH to make the mark "9" covers time slot SLOT ₁ to generate second signal DMX2. The signal waveform of the second signal DMX2 is as shown in FIG. 2B, wherein the extended mark "9" is represented by "9X", and the extended header SH is represented by SHX. As can be seen from Fig. 2B, the mark "9X" has already covered the time slot SLOT _{1 that} has been read. The level of the mark "9" is logic high, so the position of the original time slot SLOT ₁ will become a logic high mark, and the mark originally between the time slot SLOT ₁ and the time slot SLOT _{2 will} be combined with the mark "9X". ". Since the length of the extended mark "9X" is still less than 1 second, the waveform of the second signal DMX2 shown in Fig. 2B still conforms to the standard DMX512 format specification.

As shown in FIG. 2B, since the time slot SLOT ₁ has been replaced by the mark "9X", in the second signal DMX2, the time slot at the foremost position becomes the time slot SLOT ₂ after the original time slot SLOT ₁ (not The second circuit unit 120 can directly read the data byte in the time slot SLOT ₂ . Then, the mark "9X" is extended again so that it covers the time slot SLOT ₂ to generate the third DMX signal DMX3. And so on, the circuit unit connected in series will extend the mark “9X” after overwriting the corresponding data byte to cover the read time slot, and then output the adjusted DMX signal to the next level. Circuit unit.

Thereby, the individual circuit units need not be distinguished by addressing, and the circuit unit of each stage only needs to retrieve the data of the first time slot to obtain the correct data. The individual circuit units can determine the obtained data by adjusting the order of the serial connections. The user can also adjust the data received by each circuit unit by adjusting the data in the respective time slots. By using the above technical means, as long as the circuit unit is connected in series, the data can be transmitted using the signal conforming to the DMX512 format, and the individual circuit units do not need to additionally set the addressing circuit.

It can be seen from the above that the waveform inversion output can avoid waveform distortion, so that the transmitted signal is maintained in the DMX format time specification, and the extension of the header and the output can make the setting of the address free, so as long as the above FIG. 2B is The second signal DMX2 is inverted and output to avoid the problem of waveform distortion. Please refer to FIG. 2C. FIG. 2C is an inverted waveform of FIG. 2B. In this embodiment, the two waveform adjustment modes are combined, so that the DMX signal can be transmitted in the serial-free serial circuit, and the waveform distortion can be avoided, so that the circuit design using the DMX format signal is more convenient. In addition, it is worth noting that in the waveform adjustment of the first signal DMX1, first performing the inversion and then performing the header extension, or performing the extension of the header and then performing the inversion does not affect the second signal DMX2. The waveform is as shown in FIG. 2C, so the embodiment does not limit the order of waveform adjustment. In addition, the specific effect can be achieved by simply using the inversion or the header extension. As described above, the embodiment can also use the inversion or header extension to generate the second signal DMX2 according to the design requirements.

It is to be noted that the above-mentioned circuit unit 110, 120, 130 is, for example, a driving circuit of a light-emitting diode display or a luminaire, wherein each time slot includes driving data of one light-emitting diode, and the weight correction can be added in the circuit unit ( The Gamma Correction) function converts the linear digital image data of the original DMX512 into a gradation change suitable for the vision. However, this embodiment is not limited. As long as the circuit is driven by the DMX signal, the technical means of the embodiment can be utilized to solve the problem of serial connection and addressing. In addition, the circuit units 110, 120, and 130 can also be implemented by using an embedded chip, wherein the function of adjusting the waveform can be implemented by a firmware or a hardware circuit, and the embodiment is not limited.

In addition, the above DMX signal is not limited to the standard DMX512 protocol, for example, the 4x speed DMX512 format (the signal format is the same as the standard DMX512, but the format time specification is one quarter of the standard DMX512 protocol time), as long as it corresponds to the standard DMX512. The extended signal format is within the technical protection of this patent.

Second embodiment

Since the amount of data required for different electronic devices is different, for a high-resolution LED display device, a single time slot may not include the required amount of data, so multiple time slots can be used to transfer a single stroke. Drive data. The data transmission device 100 of the first embodiment, wherein the first circuit unit 110 can read data of a plurality of time slots at a time, after reading the data, the first circuit unit 110 extends the first signal DMX1. The header SH covers a plurality of time slots that have been read to generate a next second signal DMX2. It is worth noting that the number of time slots read each time is not limited, and can be expressed by N, where N is a positive integer.

For example, when three time slots are read at a time, that is, N is equal to 3, please refer to FIG. 3A and FIG. 3B, which is a waveform diagram of the first signal DMX1 according to the second embodiment of the present invention. FIG. 3B is a schematic diagram showing the waveform of the second signal DMX2 according to the second embodiment of the present invention. In Fig. 3A, the first four time slots SLOT ₁ ~ SLOT _{4 are shown} , the first circuit unit 110 reads the first three time slots SLOT ₁ ~ SLOT ₃ , and then lengthens the length of the mark "9" in the header SH. The first three time slots SLOT ₁ ~ SLOT ₃ are read to cover the second signal DMX2, as shown in FIG. 3B. In Fig. 3B, the extended header SH is indicated by SHX, and the extended mark "9" is also indicated by "9X". Similarly, each stage of the circuit unit will extend the mark "9X" after reading the data of the corresponding time slot to cover the time slot that has been read, and then generate a signal conforming to the DMX512 format for transmission to the circuit unit of the next stage.

In addition, when the number of circuit units connected in series is large, in order to avoid the electrical difference of the individual circuit units during the transmission of the DMX signal (for example, the rising time and the falling time of the signal are inconsistent) Causes distortion of the signal waveform. In this embodiment, the circuit units 110-130 of each stage can invert the signal (convert the logic high potential to the logic low level and the logic low level to the logic high level) after outputting the signal, and then output. The problem of signal distortion can be avoided. Taking the second embodiment as an example, the first circuit unit 110 inverts the signal waveform shown in FIG. 3B and outputs it to the second circuit unit 120, as shown in FIG. 3C, and FIG. 3C shows the inverted waveform of FIG. 3B. The rest of the analogy is no longer exhaustive.

Third embodiment

In the above embodiment, the reset interval RE may be composed of a reset sequence "12" and X set time slots, and X is equal to 1 as an example. However, the present invention is not limited thereto. Please refer to FIG. 4A and FIG. 4B. 4A is a waveform diagram of the first signal according to the third embodiment of the present invention. 4B is a waveform diagram of a second signal according to a third embodiment of the present invention. The header SH in FIG. 4A includes a reset interval RE and a set time slot, that is, the time slot SLOT _{1 is} used as the set time slot, so the first signal DMX2 processed by the first circuit unit 110 retains the header. The reset sequence "12" and the time slot SLOT ₁ in the SH are then covered with M read time slots. In this embodiment, M is equal to 2 as an example, but the present invention is not limited thereto, and thus is extended. The mark 9X will cover the time slot SLOT ₂ and the time slot SLOT ₃ . Referring to FIG. 4B, the extended header SHX retains the time slot SLOT ₁ as a set time slot. The set time slot can be used by the circuit units 110-130 to communicate data, communicate with each other, set addresses, or return data. . In addition, the set time slot can also be realized by adding a new time slot directly before the time slot SLOT ₁ , which has no effect on the transmission format.

It should be noted that the values of the above X and M may be determined according to design requirements. The embodiment is not limited, and the number of time slots read and covered by the second circuit unit 120, for example, M, M is a positive integer. In this embodiment, the value of M is also not limited, and may be determined according to design requirements. In other words, in the embodiment, the number of time slots included in the header SH and the number of time slots covered by the individual circuit units are not limited, as long as the individual circuit units extend the header coverage after reading. The time slot that has been taken can achieve the effect of transferring data without setting an address. Similarly, the signal of FIG. 4B can also be output after the inversion, and those skilled in the art should be easily inferred from the above embodiments, and will not be described here.

Fourth embodiment

Although the first embodiment and the second embodiment illustrate the technical means of the present invention by taking a standard DMX signal as an example, the present invention is not limited to the standard DMX signal, and can also be applied to a signal generally having a header and a time slot. The transmission method also extends the length of the header after the slot is read to cover the time slot that has been read, and the number of slots read each time is not limited. Next, the technical means of the embodiment will be further described by taking a single time slot as an example.

Referring to FIG. 1, FIG. 5A and FIG. 5B, FIG. 5A is a waveform diagram of a first signal according to a fourth embodiment of the present invention. Figure 5B is a waveform diagram of a second signal in accordance with a third embodiment of the present invention. The first circuit unit 110, after reading the data of the slot SLOT ₁ , extends the header SH to cover the slot SLOT ₁ to generate a second signal, as shown in FIG. 4B. And so on, the second circuit unit 110 reads the data of the time slot SLOT ₂ and then extends the header SHX to cover the time slot SLOT ₂ .

By using the technical means of the present implementation, the serially connected circuit units do not need to be individually addressed, as long as the time slot after the header is directly read, the corresponding data can be obtained, and the signal is maintained in the format time specification by inversion. In the driving circuit of a light-emitting diode or a liquid crystal display, the data transmission method can utilize the technical means of the present invention, so that the data can be sequentially transferred to the driving chip of the next stage to achieve the data transmission requirement, and the circuit can be simplified. structure.

Fifth embodiment

From another point of view, the first embodiment described above can be summarized as a method for transmitting a DMX signal. Please refer to FIG. 1 to FIG. 6 simultaneously. FIG. 6 is a flowchart of a method for transmitting a DMX signal according to a fifth embodiment of the present invention. First, the first signal DMX1 is transmitted to the first circuit unit 110 (step S610), and then the data of the N time slots (such as SLOT ₁ ) in the first signal DMX1 is captured by the first circuit unit 110 (ie, the data byte) ) (S620). After the data is read, the length of the mark of the header SH in the first signal DMX1 is extended so that the mark covers the N time slots that have been captured to adjust the first signal DMX1 (step S630). Then, the adjusted first signal DMX1 is inverted (step S640), and then the second signal DMX2 is generated (step S650). Then, the second signal DMX2 is outputted to the second circuit unit 120 (step S660), and the second circuit unit 120 is caused to capture the data (ie, the data byte) of the M time slots (SLOT ₂ ) in the second signal DMX2 ( Step S670). And so on, the second circuit unit 120 also lengthens the length of the mark in the header SH of the second signal DMX2 to cover the M time slots captured, and then inverts the adjusted second signal DMX2 to generate The third DMX signal DMX3 is to the circuit unit of the next stage. Where N and M are positive integers, and N and M may be the same or different. It should be noted that the above steps S630 and S640 may be reversed, and the waveform of the second signal DMX2 is not affected.

It can be seen from the above that since the read time slot is covered by the mark, the circuit unit of each stage can directly retrieve the data of the first time slot located behind the header to obtain the correct data. Accordingly, the circuit unit maintains the signal in the format time specification by inverting, and the data in the DMX signal can be correctly obtained without setting the addressing circuit. For the remaining implementation details of the implementation method, please refer to the description of the first embodiment above, and no further description is provided herein.

Sixth embodiment

Similarly, the present invention is not limited to the DMX signal, and a method for transmitting a signal can be summarized by the above first to third embodiments. Referring to FIG. 7, FIG. 7 is a method for transmitting a signal according to a fifth embodiment of the present invention. flow chart. First, a first signal is outputted, the first signal having a header and a plurality of time slots, the time slot being located after the header (step S710), and then receiving the first signal (step S720). Next, the length of the header is extended so that the header covers the N time slots in the above-described time slot to adjust the first signal (step S730). Then, the adjusted first signal is inverted (step S740), and then a second signal is generated (step S750). Next, the second signal is output (step S760), where N is a positive integer. The number of time slots (N) covered by the header may be determined according to the amount of data required, and the embodiment is not limited. For the remaining implementation details of the implementation method, please refer to the description of the first to fifth embodiments above, and no further description is provided herein.

In summary, according to the format specification of the DMX512, the present invention performs waveform adjustment on the DMX signal in the process of transmitting the DMX signal, so that the circuit of the next stage can directly receive the corresponding data and can improve the waveform distortion problem. In the present invention, the individual circuit units maintain the signal in the format time specification by inverting, and do not need to preset an address, and the corresponding data can be obtained through the serial sequence thereof, thereby using the DMX signal. The circuit design is more convenient. In addition, this method also applies signal transmission generally having a header and a time slot, and also has the effect of simplifying the circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ data transmission device

110, 120, 130‧‧‧ circuit unit

1-16‧‧‧DMX512 signal format

DMX1‧‧‧ first signal

DMX2‧‧‧ second signal

DMX3‧‧‧ third DMX signal

SLOT ₀ ‧‧‧ Start slot

SLOT ₁ ~SLOT _N ‧‧‧ time slot

9X‧‧‧posted mark

SH‧‧‧ heading

SHX‧‧‧ Extended Header

S610~S670‧‧‧ Flowchart steps

S710~S770‧‧‧ Flowchart steps

1 is a data transmission device in accordance with the present invention.

2A is a waveform diagram of a first signal DMX1 according to a first embodiment of the present invention.

2B is a waveform diagram of a second signal DMX2 according to the first embodiment of the present invention.

2C is the inverted waveform of FIG. 2B.

3A is a waveform diagram of a first signal DMX1 according to a second embodiment of the present invention.

FIG. 3B is a schematic diagram showing the waveform of the second signal DMX2 according to the second embodiment of the present invention.

FIG. 3C is the inverted waveform of FIG. 3B.

4A is a waveform diagram of a first signal according to a third embodiment of the present invention.

4B is a waveform diagram of a second signal according to a third embodiment of the present invention.

Fig. 5A is a waveform diagram showing a first signal according to a fourth embodiment of the present invention.

Figure 5B is a waveform diagram of a second signal in accordance with a fourth embodiment of the present invention.

6 is a flow chart of a method of transmitting a DMX signal in accordance with a fifth embodiment of the present invention.

7 is a flow chart of a method of transmitting a signal in accordance with a sixth embodiment of the present invention.

SLOT ₀ . . . Start slot

SLOT ₁ ~SLOT _N . . . Time slot

9X. . . Extended mark

SHX. . . Extended header

1-8, 10-14, 16. . . DMX512 signal format

Claims (21)

A data transmission device, comprising: a first circuit unit, receiving the first signal and performing a waveform adjustment on the first signal to output a second signal, wherein the waveform adjustment comprises inverting the first a signal waveform, wherein the first signal corresponds to a signal format of the DMX 512, and the first signal includes a header and a plurality of time slots, wherein the time slots are located after the header, wherein the waveform adjustment further comprises extending the The length of the header is to cover the N time slots in the time slots to generate the second signal, and N is a positive integer. The data transmission device of claim 1, wherein the first circuit unit reads data in the N time slots in the first signal before the first circuit unit extends the header. The data transmission device of claim 1, further comprising a second circuit unit coupled to the first circuit unit for receiving the second signal, and reading M time slots of the second signal In the data, the M time slots are located after the original N time slots, and after reading the M time slots, extend the length of the header to cover the M time slots that have been read and Extending the second signal after the header is inverted to generate a third signal, M being a positive integer. The data transmission device of claim 1, wherein the header sequentially includes a front mark, a reset interval and a mark, and the first circuit unit extends the length of the mark in the header to Cover the above N time slots. The data transmission device of claim 4, wherein The reset interval includes a reset sequence. The data transmission device of claim 4, wherein the reset interval comprises a reset sequence and X set time slots, and X is a positive integer. The data transmission device of claim 4, wherein the mark is located between the reset interval and the N time slots. The data transmission device of claim 4, wherein the length of the mark is less than 1 second. The data transmission device of claim 5, wherein the reset sequence sequentially includes an interrupt, a post mark, and a start time slot. The data transmission device of claim 1, wherein each of the time slots comprises a start time, a data byte and two end bits. A method for transmitting a signal, comprising: receiving a first signal, the first signal having a header and a plurality of time slots, wherein the time slots are located after the header; and performing a waveform adjustment on the first signal a second signal, the waveform adjustment includes inverting a waveform of the first signal, and the first signal corresponds to a signal format of the DMX 512, wherein the waveform adjustment further comprises extending a length of the header to cover the time slots N time slots to generate the second signal, N being a positive integer. The method of claim 11, wherein extending the length of the header such that the header covers the N time slots in the time slots to generate the second signal further comprises: reading the above Information in N time slots. The method of claim 11, further comprising: receiving the second signal; extending the length of the header so that the header covers the M time slots in the time slots and extending the header The second signal is inverted to generate a third signal, wherein the M time slots are located after the N time slots, M is a positive integer; and the third signal is output. The method of claim 11, wherein the header comprises a pre-mark, a reset interval and a mark. The method of claim 14, wherein the reset interval comprises a reset sequence. The method of claim 14, wherein the reset interval comprises a reset sequence and X set time slots, and X is a positive integer. The method of claim 14, wherein the mark is located between the reset interval and the N time slots. The method of claim 14, wherein the length of the mark is less than 1 second. The method of claim 15, wherein the reset sequence sequentially includes an interrupt, a post mark, and a start time slot. The method of claim 19, wherein the start time slot sequentially includes a start time, a start code, and two end bits. The method of claim 11, wherein each of the time slots comprises a start time, a data byte and two end bits.