TWI458268B - Parallel based 5 bypass bin cabac decoder - Google Patents

Description

Parallel five-pass bit full-text adaptive binary arithmetic codec

The invention relates to a multi-bit full-text adaptive binary arithmetic coding decoder, in particular to a parallel five-pass bit full-text adaptive binary arithmetic coding decoder.

The Context-adaptive Binary Arithmetic Coding (CABAC) decoding algorithm uses basic continuous operations to calculate ranges, offsets, and look-up tables for context variables. Full-text adaptive binary arithmetic coding and decoding data dependent characteristics, resulting in full-time adaptive binary arithmetic coding decoding must be 3 billion operations per second when processing high-definition images in real time, thus making full-text adaptive binary arithmetic coding and decoding difficult Achieve high speed decoding. Basically, the bit-encoding decoder of full-text adaptive binary arithmetic coding includes a decision bit decoder and a bypass bit decoder. Through experiments, it is known that 80%-90% of all bits are encoded into decision bits. Yuan, and the remaining bits are encoded as bypass bits. Although the method of using parallel architecture to improve the performance of full-text adaptive binary arithmetic coding has been disclosed in U.S. Patent No. 7,262,722 to Jahanghir et al., the full-text adaptive binary arithmetic coding decoding algorithm is not like the video of other H.264/AVC standards. Decoding tools, it is not easy to use parallel architecture to improve the performance of full-text adaptive binary arithmetic coding. Because full-text adaptive binary arithmetic coding and decoding uses sequential sequential decoding, continuous sequential decoding makes full-text adaptive binary arithmetic coding decoding a major bottleneck in the H.264/AVC standard.

An embodiment of the present invention provides a parallel five-pass bit full-text adaptive binary arithmetic codec, which includes a three-by-pass bit decoder, suitably coupled to a two-way bypass bit decoder. The three bypass bit decoder includes a first input for receiving a bit stream, a second input for receiving a plurality of range values, and a first output for outputting a first bypass bit a second output terminal for outputting a second bypass bit, a third output terminal for outputting a third bypass bit and a fourth output terminal for outputting a shift bit stream to the second Bypass bit decoder. The second bypass bit decoder includes a first input for receiving the shift bit stream, a second input for receiving the plurality of range values, and a first output for outputting a fourth side The road bit and a second output are used to output a fifth bypass bit.

The third bypass bit decoder further includes a first circuit having the first input coupled in series, a first adder, a first multiplexer, and the first output; a second circuit coupled in parallel The first circuit has a second input coupled in series, the first adder, the first multiplexer, and the first output; a third circuit having the series coupled in series An input terminal, a second multiplexer, a third multiplexer, and the second output, wherein the third multiplexer is controlled by an output of the first multiplexer; a fourth circuit is connected in parallel with the first multiplexer a third circuit having the second input terminal coupled in series, a second adder, the second multiplexer, the third multiplexer, and the second output, wherein the second multiplexer The device is controlled by the output of the second adder; a fifth circuit is connected in parallel to the third circuit, the fifth circuit has the first input terminal, a third adder, and a fourth multiplexer coupled in series, The third multiplexer and the second output end; a sixth circuit is connected in parallel to the third circuit, the sixth circuit has a series connection a second input terminal, a fourth adder, the fourth multiplexer, the third multiplexer, and the sixth output terminal, wherein the fourth multiplexer is controlled by an output of the fourth adder a seventh circuit having the first input terminal, a fifth multiplexer, a sixth multiplexer, a seventh multiplexer, and the third output coupled in series; an eighth circuit is connected in parallel a seventh circuit, the eighth circuit having the first input end coupled in series, a fifth adder, an eighth multiplexer, a ninth multiplexer, the seventh multiplexer, and the third output The third multiplexer, the fifth multiplexer and the ninth multiplexer of the three bypass bit decoders are all controlled by the same signal.

The second bypass bit decoder includes a first circuit having the first input coupled in series, a first adder, a first multiplexer, and the first output; a second circuit is coupled in parallel a first circuit, the second circuit having the second input coupled in series, the first adder, the first multiplexer, and the first output; a third circuit having the first coupled in series An input terminal, a second multiplexer, a third multiplexer, and the second output, wherein the third multiplexer is controlled by an output of the first multiplexer.

The second bypass bit decoder further includes a fourth circuit connected in parallel to the third circuit, the fourth circuit having the second input terminal coupled in series, a second adder, the second multiplexer, the a third multiplexer and the second output, wherein the second multiplexer is controlled by an output of the second adder; a fifth circuit is coupled in parallel to the third circuit, the fifth circuit having the series coupled a first input end, a third adder, a fourth multiplexer, the third multiplexer and the second output end; a sixth circuit is connected in parallel to the third circuit, the sixth circuit has a series coupling The second input terminal, a fourth adder, the fourth multiplexer, the third multiplexer, and the sixth output, wherein the fourth multiplexer is controlled by an output of the fourth adder.

Figure 1 is a schematic diagram of a video processing system 10 that determines a multi-bit bin decoder. The video processing system 10 includes a video source 11, a video processor 12, and a video display 13. The video source 11 may be a reproduced or transmitted video signal that has been compressed and/or encoded using the H.264/AVC standard, wherein the H.264/AVC standard uses context-based adaptive binary arithmetic coding (context-based adaptive binary arithmetic coding). The coding, CABAC) technique performs compression and/or coding. The video source 11 outputs the H.264/AVC signal to the video processor 12 for decoding and reconstitution of the original video signal, and then outputs the video signal to the video display 13 for viewing by the user.

The video processor 12 can include a processor, a decoder 20, and a memory. The processor is configured to control the operation of the video processor 12; the decoder 20 is configured to decode the transmitted video signal; the memory is used to temporarily store the video signal, to store the data used in the decoding process, and/or to view The table is used as a work area, and in addition, the memory is also used as a junction between the sink area and different parts of the video processor 12. Additionally, decoder 20 may include one or more registers 25, 40, a decision bin decoder 35, and a bypass bin decoder 30.

2 is a schematic diagram showing a series of bypass bit decoders 200 applied to the video processing system 10 of FIG. In FIG. 2, the input end of a first connection module 205 is configured to receive n-1 bits in the current offset and bit stream, and the output end of the first connection module 205 is coupled to a first A first input of a multiplexer 221 and a first input of a first adder 231. The first link module 205 joins the current offset and n-1 bits in the bit stream, and outputs a first result including the shift offset and n-1 bits in the bit stream to the first The second input end of the first adder 231 is configured to receive the range signal. In the first adder 231, the first result will deduct the range signal to generate a first difference, and then the first adder 231 outputs The first difference is input to the second input end of the first multiplexer 221, wherein the first difference is further input to the control input of the first multiplexer 221 as the control signal of the first multiplexer 221.

The first input end of the second connection module 207 is configured to receive n-2 bits in the bit stream, and the second input end of the second connection module 207 is coupled to the output end of the first multiplexer 221. The output of the second multiplexer 207 is coupled to the first input end of a second multiplexer 223 and the first input end of a second adder 233. . The second connection module 207 connects the signal output by the first multiplexer 221 and the n-2 bits in the bit stream, and outputs a second result to the second multiplexer 223; the second adder 233 The second input terminal is configured to receive the first difference value output by the first multiplexer 221, and in the second adder 233, the second result is subtracted from the first difference value to generate a second difference value, and then the second adder 233 outputs The second difference is input to the second input of the second multiplexer 223, and the second difference is further input to the control input of the second multiplexer 223 as the control signal of the second multiplexer 223.

The first input end of the third connection module 209 is configured to receive n-3 bits in the bit stream, and the second input end of the third connection module 209 is coupled to the output end of the second multiplexer 223. The output of the third connection module 209 is coupled to the first input end of a third multiplexer 225 and the first input end of a third adder 235. . The third connection module 209 connects the signal output by the second multiplexer 223 and the n-3 bits in the bit stream, and outputs a third result to the third multiplexer 225; the third adder 235 The second input terminal is configured to receive the second difference value output by the second multiplexer 223. In the third adder 235, the third result is subtracted from the second difference value to generate a third difference value, and then the third adder 235 outputs The third difference is input to the second input of the third multiplexer 225, wherein the third difference is further input to the control input of the third multiplexer 225 as the control signal of the second multiplexer 223.

The first input end of the fourth connection module 211 is configured to receive n-4 bits in the bit stream, and the second input end of the fourth connection module 211 is coupled to the output end of the third multiplexer 225. The output of the fourth connection module 211 is coupled to the first input end of a fourth multiplexer 227 and the first input end of a fourth adder 237. . The fourth connection module 211 connects the signal output by the third multiplexer 225 and the n-4 bits in the bit stream, and outputs a fourth result to the fourth multiplexer 227; the fourth adder 237 The second input terminal is configured to receive the third difference value output by the third multiplexer 225. In the fourth adder 237, the fourth result is subtracted from the third difference value to generate a fourth difference value, and then the fourth adder 237 outputs The fourth difference is to the second input of the fourth multiplexer 227, wherein the fourth difference is further input to the control input of the fourth multiplexer 227 as the control signal of the fourth multiplexer 227.

As shown in Figure 2, the series process can be extended infinitely depending on design considerations. In addition, it should be understood that the number of bypass bit decoders per cycle is directly related to the length of the series chain (the critical path shown by the dashed line in Fig. 2).

Please refer to Figure 3. Figure 3 is a schematic diagram showing a parallel two-pass bit decoder 300 in accordance with an embodiment of the present invention. As shown in FIG. 3, the second bypass bit decoder 300 includes a BYPASS1_A 305 and a BYPASS2_B 350. BYPASS1_A 305 and BYPASS2_B 350 together achieve the result of decoding the two bypass bits per cycle.

In the BYPASS1_A 305, the first input end of the BYPASS1_A 305 is coupled to the first input end of a multiplexer 315 and the first input end of an adder 310 for receiving a shift offset value and a bit stream. The first input value is generated after the four bits are connected, and the second input end of the BYPASS1_A 305 is coupled to the second input end of the adder 310 for receiving the range value, and the output end of the BYPASS1_A 305 is coupled to the The output of the tool 315. In adder 310, the first concatenated value will be subtracted from the range value received by the second input of adder 310, and then the second input of multiplexer 315 receives a difference output by adder 310. The output of the multiplexer 315 is used to output bin1 and offset1, that is, the output of BYPASS1_A 305 outputs bin1 and offset1.

In BYPASS2_B 350, the first input of BYPASS2_B 350 is used to receive a second link value generated by an offset two-bit value and a third and fourth bit in the bit stream, BYPASS2_B 350 The two inputs are used to receive the range value, and the output of the BYPASS2_B 350 is coupled to the output of the multiplexer 390.

A first input of a multiplexer 380 and a first input of a first adder 365 are coupled to the first input of the BYPASS2_B 350 for receiving the second link value. In the first adder 365, the second link value is subtracted from the range value received by the second input of the first adder 365 to generate a first result difference. The second input end of the multiplexer 380 and the control input end are coupled to the output end of the first adder 365 for receiving the first result difference, according to whether the first result difference is greater than a predetermined value, such as zero, It is decided to switch the signal output by the multiplexer 380. A first input end of the second adder 360 is coupled to the first input end of the BYPASS2_B 350 for receiving the second link value. In the second adder 360, the second link value is subtracted from the range value of the two bits received by the second input of the second adder 360 to generate a second result difference. The first input end of the multiplexer 385 is coupled to the output of the second adder 360 for receiving the second resulting difference. A first input end of the third adder 355 is coupled to the first input end of the BYPASS2_B 350 for receiving the second link value. In a third adder 355, the second link value is subtracted from the range value of the three bits received by the second input of the third adder 355 to generate a third result difference. The second input end of the multiplexer 385 and the control input end are coupled to the output end of the third adder 355 for receiving the third result difference, according to whether the third result difference is greater than a predetermined value, such as zero, It is decided to switch the signal output by the multiplexer 385. The first input end of a multiplexer 390 receives the signal output from the multiplexer 380, the second input receives the signal output from the multiplexer 385, and the control input receives the signal output from the multiplexer 315 of the BYPASS1_A 305. The signal output from the multiplexer 390 is controlled according to whether the signal output from the multiplexer 315 of the BYPASS1_A 305 is greater than a predetermined value, such as zero. The output of the multiplexer 390 is used to output bin2 and offset2, that is, the output of BYPASS2_B 350 outputs bin2 and offset2.

The design concept of the one-two bypass bit decoder and the one-by-three bypass bit decoder is the same. According to the following equation:

Off’1=offset<<1+stream[4] or offset<<1+stream[4]-range(1)

Off'2=Off’1<<1+stream[3] or Off’1<<1+stream[3]-range(2)

Substituting Off'1 into equation (2)

Off'2={(offset<<1+stream[4])<<1+stream[3] or (offset<<1+stream[4]-range)<<1+stream[3] or {(offset <<1+stream[4])<<1+stream[3]}-range or (offset<<1+stream[4]-range)<<1+stream[3]-range

Off'2=offset<<2+stream[4:3] or offset<<2+stream[4:3]-2*range or offset<<2+stream[4:3]-1*range or offset< <2+stream[4:3]-3*range

Therefore, Off'2 (bin2) can be selected by off'1 (bin1) to generate a clock faster than the serial architecture.

Please refer to FIG. 4, which is a schematic diagram of a parallel three-pass bit decoder 400 according to another embodiment of the present invention. As shown in FIG. 4, the triple bypass bit decoder 400 includes a BYPASS1a 405, a BYPASS2a 420, and a BYPASS3 450. BYPASS1a 405 has the same components and functions as BYPASS1_A 305 of Figure 3. The first input of BYPASS1a 405 is the same as the first input of BYPASS1_A 305. It is used to receive a shift offset value and a bit. The first link value generated after the four bits in the stream are connected, the second input of BYPASS1a 405 is the same as the second input of BYPASS1_A 305, and is used to receive the range value, the output of BYPASS1a 405 and the output of BYPASS1_A 305. The same output bin1 and offset1. The adder 410 of Fig. 4 corresponds to the adder 310 of Fig. 3, and the multiplexer 415 of Fig. 4 corresponds to the multiplexer 315 of Fig. 3, therefore, the operation of the adder 410 and the multiplexer 415 will not be described again. process.

BYPASS2a 420 has the same components and functions as BYPASS2_B 350 in Figure 3. The first input of BYPASS2a 420 is the same as the first input of BYPASS2_B 350. It is used to receive an offset two bit value and bit. The second connection value generated after the third and fourth bits in the meta-stream, the second input of BYPASS2a 420 is the same as the second input of BYPASS2_B 350, and is used to receive the range value, the output of BYPASS2a 420 and BYPASS2_B The output of the 350 outputs bin2 and offset2 as well. Further, adders 426, 424, and 422 of BYPASS2a 420 correspond to adders 365, 360, and 355 of BYPASS2_B 350; multiplexers 430, 440, and 435 of BYPASS2a 420 correspond to multiplexers 380, 385, and 390 of BYPASS2_B 350. . Therefore, the operation of BYPASS2a 420 will not be described again.

The BYPASS 3 450 is now added to improve the second bypass bit decoder 300 of FIG. 3 to become the triple bypass bit decoder 400 of FIG. The first input of the BYPASS3 450 is configured to receive a third link value generated by a shift offset value and a fourth to second bit in the bit stream. The second input of the BYPASS3 450 is used to receive the range value, and the output of the BYPASS3 450 is coupled to the output of the seventh multiplexer 485.

In BYPASS3 450, a first input end of a first multiplexer 470, a first input end of a first adder 451, a first input end of a second adder 453, and a third adder 455 An input, a first input of a fourth adder 457, a first input of a fifth adder 459, a first input of a sixth adder 461, and a first input of a seventh adder 463 The end is coupled to the first input of the BYPASS3 450 for receiving the third connection value.

In the first adder 451, the third link value is deducted from the range value of the one bit received by the second input terminal of the first adder 451 to generate a first difference value. The second input end of the first multiplexer 470 and the control input end are coupled to the output end of the first adder 451 for receiving the first difference, according to whether the first difference is greater than a predetermined value, such as zero, It is decided to switch the signal output by the first multiplexer 470.

In the second adder 453, the third link value is subtracted from the range value of the two bits received by the second input terminal of the second adder 453 to generate a second difference value. The first input end of the second multiplexer 472 is coupled to the output of the second adder 453 for receiving the second difference. In the third adder 455, the third link value is subtracted from the range value of the three bits received by the second input of the third adder 455 to generate a third difference. The second input end of the second multiplexer 472 and the control input end are coupled to the output end of the third adder 455 for receiving the third difference, according to whether the third difference is greater than a predetermined value, such as zero, It is decided to switch the signal output by the second multiplexer 472.

In the fourth adder 457, the third link value is deducted from the range value of the four bits received by the second input of the fourth adder 457 to generate a fourth difference value. The first input end of the third multiplexer 474 is coupled to the output of the fourth adder 457 for receiving the fourth difference. In the fifth adder 459, the third link value is subtracted from the range value of the five-bit received by the second input of the fifth adder 459 to generate a fifth difference. The second input end of the third multiplexer 474 and the control input end are coupled to the output end of the fifth adder 459 for receiving the fifth difference, according to whether the fifth difference is greater than a predetermined value, such as zero, It is decided to switch the signal output by the third multiplexer 474.

In the sixth adder 461, the third link value deducts the range value of the six-bit received by the second input terminal of the sixth adder 461 to generate a sixth difference value. A first input end of a fourth multiplexer 476 is coupled to an output of the sixth adder 461 for receiving a sixth difference. In the seventh adder 463, the third link value is subtracted from the range value of the seven-bit received by the second input of the seventh adder 463 to generate a seventh difference. The second input end of the fourth multiplexer 476 and the control input end are coupled to the output end of the seventh adder 463 for receiving the seventh difference, according to whether the seventh difference is greater than a predetermined value, such as zero, It is decided to switch the signal output by the fourth multiplexer 476.

The first input of the fifth multiplexer 480 receives the signal output by the first multiplexer 470, the second input receives the signal output by the second multiplexer 472, and the control input receives the output of the multiplexer 415 of the BYPASS1a 405. The signal is output according to whether the signal output by the multiplexer 415 of the BYPASS1a 405 is greater than a predetermined value, such as zero, to control the signal output by the fifth multiplexer 480. The first input of the sixth multiplexer 482 receives the signal output by the third multiplexer 474, the second input receives the signal output by the fourth multiplexer 476, and the control input receives the output of the multiplexer 415 of the BYPASS1a 405. The signal is controlled according to whether the signal output by the multiplexer 415 of the BYPASS1a 405 is greater than a predetermined value, such as zero, to control the signal output by the sixth multiplexer 482. The first input of the seventh multiplexer 485 receives the signal output by the fifth multiplexer 480, the second input receives the signal output by the sixth multiplexer 482, and the control input receives the output of the multiplexer 435 of the BYPASS2a 420. Signal. The output of the seventh multiplexer 485 is used to output bin3 and offset3, that is, the output of the BYPASS3 450 outputs bin3 and offset3.

Please refer to Figure 5. Figure 5 illustrates a schematic diagram of how to form a parallel five-pass bit decoder 500 by coupling the three-pass bit decoder 400 of Figure 4 and the two-pass bit decoder 300 of Figure 3.

As shown in FIG. 5, the input of the triple bypass bit decoder 400 receives the appropriate bit stream and range values, and the output of the triple bypass bit decoder 400 is used to output bin1, bin2, bin3, and shift. Bit stream. The input of the second bypass bit decoder 300 then receives the shift bit stream and range values, while the output of the second bypass bit decoder 300 is used to output bin4 and bin5.

In summary, the traditional bypass bit decoder is a sequence design with a lengthy computation path and easy implementation. The bypass bit decoder proposed by the invention can improve the shortcoming of the traditional bypass bit decoder with a long operation path, and can save about 40% of the operation time. For example, a conventional five-pass bit decoder that requires about 6.66 ns (150 MHz) of decoding time per cycle to decode five bits, but the five-pass bit decoder of the present invention requires only 4 ns (250 MHz, Fujitsu 90 nm) Process).

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Video processing system

11. . . Video source

12. . . Video processor

13. . . Video display

20. . . decoder

25, 40. . . Register

35. . . Decision bit decoder

30, 200. . . Bypass bit decoder

205. . . First link module

207. . . Second link module

209. . . Third link module

211. . . Fourth link module

221, 470. . . First multiplexer

223, 472. . . Second multiplexer

225, 474. . . Third multiplexer

227, 476. . . Fourth multiplexer

480. . . Fifth multiplexer

482. . . Sixth multiplexer

485. . . Seventh multiplexer

231, 451. . . First adder

233, 453. . . Second adder

235, 455. . . Third adder

237,457. . . Fourth adder

459. . . Fifth adder

461. . . Sixth adder

463. . . Seventh adder

300. . . Second bypass bit decoder

305. . . BYPASS1_A

350. . . BYPASS2_B

315, 380, 385, 390, 415, 430, 440, 435. . . Multiplexer

310, 365, 360, 355, 410, 426, 424, 422. . . Adder

400. . . Triple bypass bit decoder

405. . . BYPASS1a

420. . . BYPASS2a

450. . . BYPASS3

500. . . Five bypass bit decoder

Figure 1 is a schematic diagram of a video processing system.

Figure 2 illustrates a schematic diagram of a series bypass bit decoder suitable for use in the video processing system of Figure 1.

Figure 3 is a schematic diagram showing a parallel two-pass bit decoder in accordance with an embodiment of the present invention.

Figure 4 is a schematic illustration of another embodiment of the present invention illustrating a parallel three-pass bit decoder.

Figure 5 is a schematic illustration of another embodiment of the present invention illustrating a parallel five-pass bit decoder.

300. . . Second bypass bit decoder

400. . . Triple bypass bit decoder

500. . . Five bypass bit decoder

Claims (17)

A parallel five-pass bit full-text adaptive binary arithmetic codec includes: a three-by-pass bit decoder, having a first input for receiving a bit stream and a second input for receiving a plurality of range values, a first output terminal for outputting a first bypass bit, a second output terminal for outputting a second bypass bit, and a third output terminal for outputting a third bypass bit a bit, and a fourth output terminal for outputting a shift bit stream; and a second bypass bit decoder having a third input coupled to the fourth output of the three bypass bit decoder The terminal is configured to receive the shift bit stream, a fourth input end is configured to receive the plurality of range values, a fifth output end is configured to output a fourth bypass bit, and a sixth output end is used to output a fourth bypass bit. A fifth bypass bit is output. The decoder of claim 1, wherein the two bypass bit decoder further comprises: a first circuit having a third input of the two bypass bit decoders coupled in series, a first addition a first multiplexer and a fifth output of the second bypass bit decoder; and a second circuit coupled in parallel with the first circuit, the second circuit having the two bypass bits coupled in series a fourth input of the meta decoder, the first adder, the first multiplexer, and a fifth output of the two bypass bit decoder. The decoder of claim 2, wherein the two bypass bit decoder further comprises: a third circuit having a third input end of the two bypass bit decoders coupled in series, a second plurality a sixth output of the second multiplexer and the second bypass bit decoder; wherein the third multiplexer is controlled by a signal output by the first multiplexer. The decoder of claim 3, wherein the two bypass bit decoder further comprises: a fourth circuit parallel to the third circuit, the fourth circuit having the two bypass bit decoding coupled in series a fourth input of the device, a second adder, the second multiplexer, the third multiplexer, and a sixth output of the second bypass bit decoder; wherein the second multiplexer is The signal control of the second adder output. The decoder of claim 4, wherein the two bypass bit decoder further comprises: a fifth circuit connected in parallel to the third circuit, the fifth circuit having the two bypass bit decoding coupled in series a third input terminal, a third adder, a fourth multiplexer, the third multiplexer, and a sixth output of the second bypass bit decoder; and a sixth circuit connected in parallel a third circuit, the sixth circuit having a fourth input end of the two bypass bit decoder coupled in series, a fourth adder, the fourth multiplexer, the third multiplexer, and the two sides a sixth output of the road bit decoder; wherein the fourth multiplexer is controlled by a signal output by the fourth adder. A parallel five-pass bit full-text adaptive binary arithmetic codec, comprising a three-by-pass bit decoder, having a first input for receiving a bit stream and a second input for receiving a complex number Range values, a first output for outputting a bypass bit, a second output for outputting a bypass bit, a third output for outputting a bypass bit, and a fourth output for a fourth output And outputting a shift bit stream; and a bypass bit decoder having a first input for receiving the shift bit stream, and a second input for receiving the plurality of range values, The first output terminal is for outputting a bypass bit, and the second output terminal is for outputting a bypass bit. The decoder of claim 6, wherein the three bypass bit decoder further comprises: a first circuit having a first input of the three bypass bit decoder coupled in series, a first addition a first multiplexer and a first output of the three bypass bit decoder; and a second circuit coupled in parallel with the first circuit, having the three bypass bit decoder coupled in series a second input, the first adder, the first multiplexer, and a first output of the three bypass bit decoder. The decoder of claim 7, wherein the three bypass bit decoder further comprises: a third circuit having a first input end of the three bypass bit decoder coupled in series, a second plurality a second output of the third multiplexer and the third bypass bit decoder; wherein the third multiplexer is controlled by a signal output by the first multiplexer. The decoder of claim 8, wherein the three bypass bit decoder further comprises: a fourth circuit parallel to the third circuit, the fourth circuit having the three bypass bit decoding coupled in series a second input of the second input, a second adder, the second multiplexer, and a second output of the three bypass bit decoder; wherein the second multiplexer is The signal control of the second adder output. The decoder of claim 9, wherein the three bypass bit decoder further comprises: a fifth circuit connected in parallel to the third circuit, the fifth circuit having the three bypass bit decoding coupled in series a first input end, a third adder, a fourth multiplexer, the third multiplexer, and a second output of the three bypass bit decoder; and a sixth circuit coupled in parallel a third circuit having a second input of the triple bypass bit decoder coupled in series, a fourth adder, the fourth multiplexer, the third multiplexer, and the third bypass bit decoding a second output of the device; wherein the fourth multiplexer is controlled by a signal output by the fourth adder. The decoder of claim 10, wherein the three bypass bit decoder further comprises: a seventh circuit having a first input terminal, a fifth plurality of the three bypass bit decoders coupled in series a third output of the third multiplexer, a seventh multiplexer, and the third bypass bit decoder; and an eighth circuit connected in parallel to the seventh circuit, the eighth circuit having a series a first input end of the three bypass bit decoder coupled, a fifth adder, an eighth multiplexer, a ninth multiplexer, the seventh multiplexer, and the third bypass bit The third output of the decoder. The decoder of claim 11, wherein a control input of the third multiplexer of the three bypass bit decoder, a control input of the fifth multiplexer, and a control of the ninth multiplexer The input end is coupled to the output end of the first multiplexer, and the signal output by the first multiplexer is used to control the third multiplexer, the fifth multiplexer and the ninth multiplexer. The decoder of claim 12, wherein a control input of the seventh multiplexer of the three bypass bit decoder is coupled to an output of the third multiplexer, the output of the third multiplexer The signal is used to control the seventh multiplexer. The decoder of claim 13, wherein the two bypass bit decoder further comprises: a first circuit having a first input of the two bypass bit decoders coupled in series, a first addition a first multiplexer and a first output of the second bypass bit decoder; and a second circuit coupled in parallel with the first circuit, the second circuit having the two bypass bits coupled in series a second input of the meta decoder, the first adder, the first multiplexer, and a first output of the two bypass bit decoder. The decoder of claim 14, wherein the two bypass bit decoder further comprises: a third circuit having a first input end of the two bypass bit decoders coupled in series, a second plurality a second output of the second multiplexer and the second bypass bit decoder; wherein the third multiplexer is controlled by a signal output by the first multiplexer. The decoder of claim 15, wherein the two bypass bit decoder further comprises: a fourth circuit parallel to the third circuit, the fourth circuit having the two bypass bit decoding coupled in series a second input of the second input, a second adder, the second multiplexer, and a second output of the second bypass bit decoder; wherein the second multiplexer is The signal control of the second adder output. The decoder of claim 16, wherein the two bypass bit decoder further comprises: a fifth circuit connected in parallel to the third circuit, the fifth circuit having the two bypass bit decoding coupled in series a first input end, a third adder, a fourth multiplexer, the third multiplexer, and a second output of the second bypass bit decoder; and a sixth circuit coupled in parallel a third circuit, the sixth circuit having a second input of the two bypass bit decoders coupled in series, a fourth adder, the fourth multiplexer, the third multiplexer, and the two sides a sixth output of the road bit decoder; wherein the fourth multiplexer is controlled by a signal output by the fourth adder.