201134106 六、發明說明： 【發明所屬之技術領域】 本發明係有關於-種多位元全文自適應二進制算術編嗎的解碼 器，尤指一種並聯的五旁路位元全文自適應二進制算術編碼解碼器。 【先前技術】 全文自適應二進制算術編碼(C0ntext_adaptiveBinaryArithmetic Coding，CABAC)解碼演算法是利用基本的連續運算去計算用於情 境變數的範圍、偏移和查閱表。全文自適應二進制算術編碼解碼的 資料相依特性，導致在即時處理高清晰度影糾，全文自適應二進 制算術編碼解碼須做每秒3〇億次的運算，因此使全文自適應二進制 算術編碼解碼很難達到高速解碼4本上，全文自適應二進制算術 編碼之位元解碼器包含—決定位元解碼H和-旁路位元解碼器，透 過實驗，可知財位元巾侃被編碼成決粒元，而其 餘位元被編域旁路位心軸版_『等發明人的美國專利第 ，，22號已揭路使用细平行架構改善全文自適應二進制算術 爲碼的效此的方去’但全文自適應二進制算術編碼解碼演算法不像 其他H.264/AVC標準之魏解碼卫具，要個平行轉去改善全文 自適應二進制算術編碼的效能並不容易。因為全文自適應二進制算 術編碼觸雜崎續順序_•碼，純賴鱗的解碼會使得全 201134106 文㈣紅進制算術編碼解碼成為Η.%4/就標準主要的瓶頸 【發明内容】 本發明之-實施例提供一種並聯的五旁 =編碼輸，其包含—三旁路蝴，適當=:進 以輸出一第二旁路位元、 旁路位元和一第四輸出端用以輸出一 第^輸出端用以輸出—第 以幹出以接收複數個範圍值、-第-輸出端用 以輸出-第-旁路位元、一第二輸出端用 旁路位元解碼器。該二旁路位元解碼器包含-第 範圍值、一第一輸位凡流、-第二輸入端用以接收該複數個 以輸出-第五旁:位元輸出一第四旁路位元和-第二輸出端用 輸二:=解：1含，電路具有串聯_該第-路並聯於該第-電路，㈣/4和該第—輸出端；一第二電 該第-加法H、驾r電路具有_她_第二輸入端、 聯翻該第：::工第器㈣第一輸出端;一第三電路具有串 出端，其代第”帛—夕马、-第三多工器和該第二輸 第二加法器、該第二多工器 、 第四電路具有串聯耦接的該第二輸入端、一 、該第三多工器和該第二輸出端，其中 201134106 該第二多工器受該第二加法器的輪 ::τ路具有串聯耦接的•二== 該第三電路，該第六電路q °韻二輸出端；-第六電路並聯於 法器、該第四多:器接的該第二輸入端'-第四加 多工器受該第四加奸的_二其中該第四 第-輸入端、-第五多I器、丄夕 〃有串聯麵接的該 三輸出端；一第八電路並聯=工益、一第七多工器和該第 接的該第-輸入端、一第五加：七：了第八電路具有串_ 多工器、二多=其中該三旁路位元解碼器的該第三 第五和該第九h器皆受到-相同訊號控制。 人端該碼：二;路具有_接的該第-輪 f於該第一電路，該第二電路具有串=接=:電路 :-加法器、該第一多工器和該第一輸出端；=、該 _的該第-輸入端、一第二多工器 二 =有串聯 端，其中該第三多工器受該第一多工器的輪出控制和销二輸出 該一旁路位冗解碍器另包含一第四電路並聯於該 四電路具有串聯轉接的該第二輸入端、 路，該 工器、該第三多工器和該第二輸出端，射該該第二多 加法器的輸出控制;-第五電路並聯於該第三二 201134106 有串聯耦接的該第一輸入端、一第三加法器、一第四多工器、該第 二多工器和該第二輸出端；一第六電路並聯於該第三電路’該第六 電路具有串聯耦接的該第二輸入端、一第四加法器、該第四多工器、 該第三多工器和該第六輸出端，其中該第四多工器受該第四加法器 的輸出控制。 【實施方式】 魯 第1圖是決定多位元的位元解碼器(bindecoder)的視訊處理系統 1〇之不意圖。視訊處理系統1〇包含一視訊源u、一視訊處理器 和-視峨不器13。視訊源u可以是已利用H264/AVC標準進行 壓縮及/或糾的重製或傳輸的視簡號，其巾h,264/avc標準是採 用全文自適應二進制算術編碼(c〇n祕based心邱⑽㈣ arithmetic coding, 11 H.264/AVC峨至視訊處理器12進行解碼和重組成原始視訊訊 鲁號/〇成後再藉由視訊處理器u輸出至視訊顯示器u以供使 觀看。 器2可包含一處理器、一解碼器20和一記憶體。該 處理器用以控制視訊處理器12 n解碼器20用以對傳來的視 =====憶體用以暫存視訊訊號、用以儲存在解碼過程 II S 閱表，以及用以當作工作區，除此之外，記 憶體也用作匯流區和視訊處理器 ’、 U 4分的聯結。另外，解碼 201134106 器20可包含-或多個暫存器25、4〇，一決定位元解顿_〇η础 decoders ’以及一旁路位元解碼器⑽卿㈤⑽·。 第2圖係說明適用於第1 _視訊處理系統1〇的串聯的旁路位 元解碼器200之示意圖。在第2圖中，一第一連結模組2〇5的輸入 端用以接收目前偏移和位元流中的W個位元，而第一連姓模组2〇5 的輸出端搞接於-第-多工器221的第一輸入端和一第一°加法器 231的第-輸入端。第-連結· 2〇5連結目前偏移和位元流中的 n-1個位元後，輸出包含移位偏移和位元流中的叫固位元的一第一 結果至第-多工器221 ;第-加法器231的第二輸入端用以接收範 圍訊號，在第-加法器231中，第一結果將扣除範圍訊號產生一第 -差值，然後第-加法器说輸出第一差值至第一多工器2?1的第 :輸入端’其中第-差值另輸入至第一多工器221的控制輸入端做 為第一多工器221的控制訊號。 一第二連結模組207的第-輸入端用以接收位元流中的Μ個 位元，第二連結模組207的第二輪入蝴妾於第一多工器221的輸 出端，用以接收第-多工器221輸出的訊號，第二連結模組2〇7的 輸出端於-第二多工器223的第一輸入端和一第二加料加 。第二連結模組207連結第一多工器221輸出的訊號 和位兀"U_中的n_2個位TG後，輸出-第二結果至第二多工器⑵. 第二加法器加的第二輸入端用以接收第一多工器221輪出的第一 差值’在第二加法!i 233中，第二結果將扣除第—差值產生一第二 201134106 差值’然後第二加法器233輸出第_ * , 化入被# ^ ^ 一差值至第二多工器223的第二 輸入鈿，其中第二差值另輸入至第-夕 ^ ^ τ ^ —夕工器223的控制輸入端做為 第一多工器223的控制訊號。 位-一!三連結模組209的第一輪入端用以接收位元流中的Μ個 =，第三連結模組的第二輸入轉接於201134106 VI. Description of the Invention: [Technical Field] The present invention relates to a multi-bit full-text adaptive binary arithmetic coding decoder, especially a parallel five-pass bit full-text adaptive binary arithmetic coding decoder. [Prior Art] The C0ntext_adaptive Binary Arithmetic Coding (CABAC) decoding algorithm uses basic continuous operations to calculate ranges, offsets, and look-up tables for context variables. Full-text adaptive binary arithmetic coding and decoding data dependent characteristics, resulting in high-definition shadow correction in real-time processing, full-text adaptive binary arithmetic coding decoding must be done 300 million operations per second, thus making full-text adaptive binary arithmetic coding and decoding very Difficult to achieve high-speed decoding 4, the full-text adaptive binary arithmetic coding bit decoder includes - determine the bit decoding H and - bypass bit decoder, through experiments, it can be known that the financial element is encoded into granules And the remaining bits are coded by the domain bypass version of the mandrel version _ "the inventor's US patent, the 22nd has been used to improve the full-text adaptive binary arithmetic for the code to use the fine parallel architecture" The full-text adaptive binary arithmetic coding and decoding algorithm is not as easy as other H.264/AVC standard Wei decoding aids. It is not easy to improve the performance of full-text adaptive binary arithmetic coding. Because the full-text adaptive binary arithmetic coding touches the sequence of _• code, the decoding of purely scaly scales will make the whole 201134106 text (four) red-ary arithmetic coding and decoding become Η.%4/ the main bottleneck of the standard [invention] The embodiment provides a parallel five-pass = coded input, including - three bypass butterfly, appropriate =: to output a second bypass bit, a bypass bit and a fourth output for outputting a The first output terminal is used for outputting - the first output is for receiving a plurality of range values, the -th output terminal is for outputting the -th bypass bit bit, and the second output terminal is for bypassing the bit bit decoder. The two bypass bit decoder includes - a range value, a first bit stream, a second input for receiving the plurality of outputs - a fifth side: a bit output a fourth bypass bit And - the second output uses two inputs: = solution: 1 contains, the circuit has a series _ the first path is connected in parallel to the first circuit, (four) / 4 and the first output terminal; a second electrical the first addition - H The driving circuit has _ her_second input terminal, the first turning of the first::: the first output of the working device (four); a third circuit has a serial output, the generation of the first "帛-夕马,-third The multiplexer and the second second adder, the second multiplexer, and the fourth circuit have the second input, the third multiplexer, and the second output coupled in series, wherein 201134106 The second multiplexer is subjected to the wheel of the second adder::τ road has a series coupling; two == the third circuit, the sixth circuit q ° rhyme two output; - the sixth circuit is connected in parallel The fourth input device of the device: the fourth input multiplexer is subjected to the fourth stalker _ two of the fourth first input terminal, the fifth fifth multi-device, 丄There is a series connection in the evening Three output terminals; an eighth circuit parallel = work benefits, a seventh multiplexer and the first input of the first input, a fifth plus: seven: the eighth circuit has a string _ multiplexer, two more = the third fifth and the ninth h of the three bypass bit decoders are all controlled by the same signal. The human end code: two; the road has the first wheel f of the first a circuit, the second circuit having a string = connection =: circuit: - an adder, the first multiplexer and the first output; =, the first input of the _, a second multiplexer = There is a series end, wherein the third multiplexer is controlled by the first multiplexer and the pin 2 is outputted. The bypass multiplexer further comprises a fourth circuit connected in parallel to the four circuit with series switching The second input end, the path, the work tool, the third multiplexer and the second output end, and the output control of the second multi-adder; the fifth circuit is connected in parallel with the third two 201134106 The first input end, a third adder, a fourth multiplexer, the second multiplexer and the second output end coupled in series; a sixth circuit is connected in parallel to the third electric The sixth circuit has the second input coupled in series, a fourth adder, the fourth multiplexer, the third multiplexer, and the sixth output, wherein the fourth multiplexer Controlled by the output of the fourth adder. [Embodiment] Lu 1 is a video processing system for determining a multi-bit bit decoder. The video processing system 1 includes a video source. u, a video processor and a video device. The video source u may be a picture format of a reproduction or transmission that has been compressed and/or corrected by the H264/AVC standard, and the towel h, 264/avc standard is Full-text adaptive binary arithmetic coding (c〇n secret based on Qiuqiu (10) (4) arithmetic coding, 11 H.264/AVC峨 to video processor 12 for decoding and recombining the original video signal Lu/〇 and then by video processing The u is output to the video display u for viewing. The processor 2 can include a processor, a decoder 20, and a memory. The processor is configured to control the video processor 12 n decoder 20 to use the transmitted video to temporarily store the video signal, to be stored in the decoding process, and to be used as a reference. In addition to the work area, the memory is also used as a connection between the sink area and the video processor', U 4 points. In addition, the decoding 201134106 may include - or a plurality of registers 25, 4, a decision bit solution _ 〇 base decoders ' and a bypass bit decoder (10) qing (5) (10). Fig. 2 is a view showing a series of bypass bit decoders 200 applicable to the first video processing system. In FIG. 2, the input end of a first connection module 2〇5 is used to receive the current offset and W bits in the bit stream, and the output of the first connected last module 2〇5 is connected. The first input of the first-multiplexer 221 and the first input of a first adder 231. After the first link · 2〇5 links the current offset and n-1 bits in the bit stream, the output includes a shift offset and a first result of the bit fix in the bit stream to the first-to-multiple The second input end of the first adder 231 is configured to receive the range signal. In the first adder 231, the first result will deduct the range signal to generate a first difference value, and then the first adder outputs the first A difference is input to the first input end of the first multiplexer 2?1: wherein the first difference is further input to the control input of the first multiplexer 221 as a control signal of the first multiplexer 221. The first input end of the second connection module 207 is configured to receive one of the bit streams in the bit stream, and the second round of the second connection module 207 is input to the output end of the first multiplexer 221, To receive the signal outputted by the multiplexer 221, the output of the second connection module 2〇7 is applied to the first input of the second multiplexer 223 and a second feed. The second connection module 207 connects the signal output by the first multiplexer 221 and the n_2 bits TG in the position quot"U_, and outputs the second result to the second multiplexer (2). The second adder adds The second input is configured to receive the first difference 'rounded by the first multiplexer 221' in the second addition!i 233, and the second result is subtracted from the first difference to generate a second 201134106 difference 'and then the second The adder 233 outputs the _*, and is converted into a second input 被 of the ^^^ difference to the second multiplexer 223, wherein the second difference is further input to the first eve ^^ τ^ The control input serves as a control signal for the first multiplexer 223. The first round of the bit-one! triple link module 209 is used to receive one of the bitstreams, and the second input of the third linker module is switched to
=以接收第二多工器223輸出的訊號，第三連結模組二 接於一第三多工器225的第—輸入端和一第三加法器235 H峰第三連結模_連結第二多1器如輸出的訊號 和位域中的η_3個位錢，輸出—第三結果至第三多工器奶. ^三加法器235的第二輸入端用以接收第二多工器如輸出的第二 差值，在第三加法11 235中，第三結果將扣除第二差值產生一第三 差值’然後第三加法器235輸出第三差值至第三多工器225的第二 =端’其中第三差值另輸入至第三多卫器225的控制輸入端做為 第一多工器223的控制訊號。 一第四連結模組211的第-輸入端用以接收位元流中的以個 位元，第四連結模組211的第二輸入端耦接於第三多工器2乃的輸 出端’用以接收第三多工器225輸出的訊號，第四連結模組2ΐι的 輸出^輕接於一第四多工器227的第一輸入端和一第四加法琴237 的第一輪入端。第四連結模組211連結第三多工器225輸出的訊號 和位元流中的n-4個位元後，輸出一第四結果至第四多工器227 ; 第四加法器237的第二輸入端用以接收第三多工器225輪出的第三 9 201134106 差值，在第四加法ϋ 237中，第四結果將扣除第三差值產生一 差值，然後第四加法器237輪出第四差值至第四多工器η? 輸入端，其中第四差值另輸入至第四多工器奶的控制輸入端心 第四多工器227的控制訊號。 *'、、 如第2圖所示，串聯可依設計考量無岐伸。糾，也靡 明瞭，母擔％旁路位7C解碼器的數目和串聯鍵的長度(第2圖虛 不的關鍵路徑)直接相關。 請參照第3圖。第3圖係本發明的一實施例說明並聯的二旁路 位元解碼器3⑻的示意圖。如第3圖所示，二旁路位元解碼器_ 包含一 BYPASS1_A305 和一 BYPASS2 B 35〇。游綱—八3〇5 與 BYPASS2_B 350 -起達成每循環解碼二：^路位元的結果。 在·細一A305中，BYPASS1—A3〇5的第一輸入端柄接於 -多工器315的第-輸入端和-加法器31〇的第一輸入端，用以接 收由一移位偏移值和位元流中的4個位元連結後所產生一第一連結 值’ BYPASS1—A305的第二輸入端搞接於加法器31〇的第二輸入 端，用以接收範圍值，BYPASS1_A305的輸出端耗接於多工器315 的輸出端。在加法器31G中，第-連結值將扣除由加法器31〇的第 二輸入端所接收之範圍值，然後多工器315的第二輸人端接收加法 器310輸出的一差值。*多工H 315的輸出端用以輸出_和 offsetl，亦即 BYPASS1_A305 的輸出端輸出 binl 和 〇ffsetl。 201134106 在BYPASS2_B 350中，BYPASS2_B 350的第一輸入端用以接 收由一偏移二位元值和位元流中的第三和第四位元連結後所產生一 第二連結值，BYPASS2_B 350的第二輸入端用以接收範圍值， BYPASS2—B 350的輸出端耦接於多工器390的輸出端。 一多工器380的第一輸入端和一第一加法器365的第一輸入端 耦接於BYPASS2_B 350的第一輸入端用以接收第二連結值。在第 加法器365中，第二連結值扣除第一加法器365的第二輸入端所 接收的範圍值，產生—第—結果差值。多卫器380的第二輸入端和 控制輸入端輕接於第-加法器365的輸出端，用以接收第一結果差 值。根據第-結果差值是否大於—預定值，例如零，去決定切換多 工器380輸出的訊號。一第二加法器36〇的第一輸入端輕接於 BYPASS2J 35G的第—輸人端用以接收第二連結值。在第二加法器 360中第二連結值扣除第二加法器的第二輸入端所接收之二 位元的範圍值，產生一筮—么士 接純多工器385的第一輸入端輕 妾=第一加法器的輪出端，用以接收第二結衫值。一第三加 輸入端輕接於BYPASS2-B 350的第-輸入端用以 法器355的:值il在一第三加法器355中’第二連結值扣除第三加 “,第一輸入端所接收之三位元的範圍值，產生一第三社果 的輸出Τ’器用：第二輸入端和控制輸入端輕接於第 預定值，娜^第二結果差值，減第三結果錄是否大於一 °零’去決定切換多工器385輸出的訊號。一多工器· 201134106 H 工器380輪出的訊號，第二輸入端接收㈣ 輸出的訊號’控制輸入端接收bypas 耠 根據職一的多工_輸出的訊號是:輸 、預疋值’例如零’去控制多1器輸出的訊號。而多1器3 9〇 的輪出端用以輸出bin2和。ffset2 ’亦即BYpASS2_B 35()的輸出端 輸出 bin2 和 〇ffset2。 -旁路位元解碼器和-三旁路位元解碼器的設計理念是相 同的。根據以下方程式： 籲= receiving the signal output by the second multiplexer 223, the third connection module is connected to the first input end of a third multiplexer 225 and a third adder 235 H peak third connection mode _ link second More than one device such as the output signal and η_3 bits in the bit field, the output - the third result to the third multiplexer milk. The second input of the three adder 235 is used to receive the second multiplexer such as the output The second difference, in the third addition 11 235, the third result will subtract the second difference to generate a third difference ' and then the third adder 235 outputs the third difference to the third multiplexer 225 The second = terminal 'the third difference is additionally input to the control input of the third multi-guard 225 as the control signal of the first multiplexer 223. The first input end of the fourth connection module 211 is configured to receive one bit in the bit stream, and the second input end of the fourth connection module 211 is coupled to the output end of the third multiplexer 2 For receiving the signal output by the third multiplexer 225, the output of the fourth connection module 2ΐ is lightly connected to the first input end of a fourth multiplexer 227 and the first round end of a fourth harpsichord 237. . The fourth connection module 211 connects the signal output by the third multiplexer 225 and the n-4 bits in the bit stream, and outputs a fourth result to the fourth multiplexer 227; the fourth adder 237 The second input terminal is configured to receive the third 9 201134106 difference of the third multiplexer 225, and in the fourth addition 237, the fourth result will subtract the third difference to generate a difference, and then the fourth adder 237 The fourth difference is taken to the fourth multiplexer η? input, wherein the fourth difference is further input to the control signal of the fourth multiplexer 227 of the control input end of the fourth multiplexer milk. *',, as shown in Figure 2, the series can be considered in accordance with the design. Correction also shows that the number of the parent bypass % 7C decoder is directly related to the length of the serial key (the critical path of Figure 2). Please refer to Figure 3. Figure 3 is a schematic diagram showing a parallel bypass bit decoder 3 (8) in accordance with an embodiment of the present invention. As shown in Figure 3, the second bypass bit decoder _ contains a BYPASS1_A305 and a BYPASS2 B 35〇.游纲—八三〇5 and BYPASS2_B 350 - to achieve the result of decoding two loops per channel: ^ road bits. In the fine A305, the first input end of BYPASS1 - A3 〇 5 is connected to the first input end of the - multiplexer 315 and the first input end of the - adder 31 , for receiving a shift bias The second input end of the first connection value 'BYPASS1_A305 generated after the shifting and the four bits in the bit stream are connected is connected to the second input end of the adder 31〇 for receiving the range value, BYPASS1_A305 The output is connected to the output of the multiplexer 315. In the adder 31G, the first-link value will be deducted from the range value received by the second input terminal of the adder 31, and then the second input terminal of the multiplexer 315 receives a difference value output from the adder 310. * The output of the multiplex H 315 is used to output _ and offsetl, that is, the output of BYPASS1_A305 outputs binl and 〇ffsetl. In the BYPASS2_B 350, the first input of the BYPASS2_B 350 is configured to receive a second link value generated by the offset two-bit value and the third and fourth bits in the bit stream, BYPASS2_B 350 The second input is used to receive the range value, and the output of the BYPASS2-B 350 is coupled to the output of the multiplexer 390. A first input of a multiplexer 380 and a first input of a first adder 365 are coupled to the first input of the BYPASS2_B 350 for receiving the second link value. In the adder 365, the second link value is deducted from the range value received by the second input of the first adder 365 to produce a -first result difference. The second input of the multi-guard 380 and the control input are lightly coupled to the output of the adder 365 for receiving the first resulting difference. The signal output by the switching multiplexer 380 is determined based on whether the first-to-result difference is greater than a predetermined value, such as zero. The first input end of a second adder 36A is lightly connected to the first input end of the BYPASS2J 35G for receiving the second link value. In the second adder 360, the second connection value is deducted from the range value of the two bits received by the second input end of the second adder, and the first input end of the multiplexer-only pure multiplexer 385 is generated. = the wheel end of the first adder for receiving the second knot value. A third input terminal is lightly connected to the first input of the BYPASS2-B 350 for the 355: the value il is in a third adder 355, the second connection value is deducted by the third addition, the first input The range value of the received three-bits is used to generate a third output of the device: the second input terminal and the control input terminal are lightly connected to the predetermined value, and the second result difference is subtracted from the third result. Whether it is greater than one ° zero' to determine the signal outputted by the multiplexer 385. A multiplexer · 201134106 H 380 rounds the signal, the second input receives (four) the output signal 'control input receives bypas 耠The multiplexed_output signal is: input, pre-valued 'such as zero' to control the output of the multi-unit output. The multi-unit 3 9 轮 round-out is used to output bin2 and .ffset2 ', ie BYpASS2_B The output of 35() outputs bin2 and 〇ffset2. - The design concept of the bypass bit decoder and the -three bypass bit decoder is the same. According to the following equation:
Off’ 1 = offSet«l+ stream[4]或 0ffset<<1+ stream[4] _ range ⑴Off’ 1 = offSet«l+ stream[4] or 0ffset<1+ stream[4] _ range (1)
Off’2 = Off’ l«l+ stream[3]或 〇ff’ 1<<H stream[3：)__ range (2) 將Off’l代入到方程式(2)可得 Off’2={(〇ffset«l+stream[4])«l+stream[3]或（offset«l + stream[4] - range) «1+ stream[3] · 或{(offset«l+stream[4])«l + stream[3]} - range 或(offset«l + stream[4] — range) «1 + stream[3] - range Off’2 = offset«2 + stream[4:3] 或 offset«2 + stream[4:3] - 2*range 或 offset«2 + stream[4:3] - l*range 或 offset«2 + stream[4:3] - 3*range 12 201134106 因此，可藉由off’l (binl)選擇〇ff，2(bin2)，產生比串聯架構更 快的時脈。 凊參照第4圖，第4圖係本發明的另一實施例說明一並聯的三 旁路位tl解碼器4〇〇的示意圖。如第4圖所示，三旁路位元解碼器 400 包 g — BYPASSla 405、一 BYPASS2a 420 和一 BYPASS3 450。 BYPASSla4〇5和第3圖的BYPASS1_A3()5 一樣有相對應的元件和 功月b’其中BYPASSla405的第一輸入端和bypass1_a3〇5的第一 輸入端一樣，係用以接收由一移位偏移值和位元流中的4個位元連 結後所產生第一連結值，BYPASSla405的第二輸入端和 BYPASS 1—A 305的第二輸入端-樣’係肖以接收範圍值，BypASS i & 405的輸出端和BYPASS1_A3〇5的輸出端一樣輸出Wni和〇饱如。 第4圖的加法器410對應第3圖的加法器31〇,第4圖的多工器415 則對應第3圖的多工器315，因此，不再贅述加法器彻和多工器 415的運作過程。 BYPASS2a420和第3 _BYPASS2_B350 -樣有相對應的元 件和功旎，其中BYPASS2a420的第一輸入端和bypasS2_B 350 的第一輸入端一樣，係用以接收由一偏移二位元值和位元流中的第 三和第四位元後所產生第二連結值，BYpASS2a420的第二輸入端 和BYPASS2—B 350的第二輸人端一樣，係用以接收範圍值， BYPASS2a 420的輸出端和BYPASS2JB 35〇的輸出端一樣輸出_ 和0ffset2。此外’ BYPASS2a 420的加法器426、424和422對應於 13 201134106 BYPASS2一B 350 的加法器 365、360 和 355 ; BYPASS2a 420 的多工 器430、440和435則對應於BYPASS2JB 35〇的多工器38〇、385 和390。因此，不再贅述BYPASS2a42〇的運作過程。 現在加入BYPASS3 450用以改善第3圖的二旁路位元解碼器 300成為第4圖的三旁路位元解碼器4〇〇。B45〇的第一輸 入端用以接收由-移位偏移值和位元流中的第四至第二位元連結後 所產生-第二連結值。BYPASS3 45G的第二輸人端用以接收範圍 值’ BYPASS3 450的輸出端柄接於第七多工器485的輸出端。 在BYPASS3 450中，一第一多工器47〇的第一輸入端、一第一 加法器451的第-輸入端、一第二加法器初的第一輸入端、一第 二加法器455的第-輸入端、一第四加法器457的第一輸入端、一 第五加法器459的第-輸入端、一第六加法器461的第一輸入端以 及一第七加法器463的第-輸入端辆接於BypASS3 的第一輸入 端用以接收第三連結值。 在第-加法器451中，第三連結值扣除第一加法器451的第二 輸入端所接收的-位元的範圍值，產生一第—差值。第—多工器獨 的第二輸人端和控制輸人端難於第—加法器451 接收第-差值，根卿-差值是否大於―預定值，例如；；去= 切換第一多工器470輸出的訊號。 、 201134106 在第二加法器453中，第三連結值扣除 •輸入端所接收的二位元的範圍值，產生一第二^法1^453一的第二 472的第-輸人端耗接於第二加法器^二多工器 差值。在第三加法器松中，第三連結值^出；:力用^接收第二 二輸入端所接收的三位元的範圍值，產生法器455的第 ?的第二輸人端和控制輸入端_於第三加;^第二多工器 用以接收第三差值，根據第三差值是否大於-預定值，^^ ’ 決定切換第二多工器4?2輸出的訊號。 ；零’去 在第四加法器457令，第三連結值扣除 ::輪收的四位元的範圍值’產生一第四差值。:第 差值的接於第四加法器457的輪出端，用以接收細 以馳職入端嫌帛五_ 459的輸出端， 決定:ί五差值’根據第五差值是否大於—預定值，例如零，去 Α疋切換第三多工器474輸出的訊號。 ^第六加法器461中，第三連結值扣除第六加法器461的第二 二Γ:的六位元的範圍值，產生一第六差值。-第四多工器 的，輸入_接於第六加法器461的輪出端，用以接收第六 一二二第七加法器463中，第三連結值扣除第七加法器463的第 一輸入^所接收的七位元的範圍值，產生—第七差值。第 15 201134106 476的第二輸入端和控制輸入端耦接於第七加法器463的輪出端， 用以接收第七差值，根據第七差值是否大於一預定值，例如零，去 決定切換第四多工器476輸出的訊號。 一第五多工器480的第一輸入端接收第一多工器470輪出的訊 说，第一輸入端接收第一多工器472輸出的訊號’控制輸入端接收 BYPASSU405的多工器415輸出的訊號，根據BYPASSla4〇5的多 工器415輸出的訊號是否大於一預定值，例如零，去控制第五多工 器480輸出的訊號。一第六多工器482的第一輸入端接收第三多工 器474輸出的訊號，第二輸入端接收第四多工器476輸出的訊號， 控制輸入端接收BYPASS la 405的多工器415輸出的訊號，根據 BYPASSla405的多工器415輸出的訊號是否大於一預定值，例如 零’去控制第六多工器482輸出的訊號。一第七多工器485的第一 ，入端接收第五多工器輸出的訊號，第二輸人端接收第六多工 益482輸出的訊號’控制輸入端接收BypAss2a 的多工器奶 輸出的訊號。而第七多工器485的輸出端用以輸出咖和砲犯， 亦即BYPASS3 45〇的輸出端輸出咖和滿犯。 月^、’、第5圖第5圖係說明如何藉她合第4圖的三旁路位 ^碼器400和第3圖的二旁路位元解碼器3⑻去形成一並聯的五 旁路位兀解碼器500的示意圖。 第5圖所不一旁路位兀解石馬器姻的輸入端接收適當的位 201134106 元流和制值，三旁路位元解的輸出朗以輸出_、 bin2、bin3轉位位元流。賴二旁路位轉 1&長的運算路徑以 ^合易實現的相設計。本㈣所提出的旁路位元解碼器能夠改善 傳統的旁職元解碼H具枚長的縣路徑的輕， 40%的運算_。例如，—傳統的五旁路位元解碼器，其每循環解 碼五位元的運算時間需要約6勤⑽MHz)，但本發明的五旁路位 讀碼器僅需要4nS(250MHz，Fujitsu 90nm製程）。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均㈣化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖係視訊處理系統之示意圖。 第2圖說明適用於第1圖的視訊處理祕的串聯旁路位元解碼琴之 示意圖。 ° 第3圖係本發明的一實施例說明並聯的二旁路位元解碼器之示意 圖。 第4圖係本發明的另一實施例說明並聯的三旁路位元解碼器之示意 17 201134106 圖。 第5圖係本發明的另一實施例說明並聯的五旁路位元解碼器之示意 圖。 【主要元件符號說明】 10 視訊處理系統 11 視訊源 12 視訊處理器 13 視訊顯示器 20 解碼器 25、40 暫存器 35 決定位元解碼器 30、200 旁路位元解碼器 205 第一連結模組 207 第二連結模組 209 第三連結模組 211 第四連結模組 221 ' 470 第一多工器 223 ' 472 第二多工器 225 > 474 第三多工器 227、476 第四多工器 480 第五多工器 201134106 482 第六多工器 485 第七多工器 231 ' 451 第一加法器 233 ' 453 第二加法器 235、455 第三加法器 237 > 457 第四加法器Off'2 = Off' l«l+ stream[3] or 〇ff' 1<<H stream[3:)__ range (2) Substituting Off'l into equation (2) yields Off'2={( 〇ffset«l+stream[4])«l+stream[3] or (offset«l + stream[4] - range) «1+ stream[3] · or {(offset«l+stream[4]) «l + stream[3]} - range or (offset«l + stream[4] — range) «1 + stream[3] - range Off'2 = offset«2 + stream[4:3] or offset«2 + stream[4:3] - 2*range or offset«2 + stream[4:3] - l*range or offset«2 + stream[4:3] - 3*range 12 201134106 So, by off' l (binl) selects 〇ff, 2(bin2) to generate a faster clock than the serial architecture. Referring to Fig. 4, a fourth embodiment of the present invention is a schematic diagram showing a parallel three bypass bit tl decoder 4A. As shown in FIG. 4, the triple bypass bit decoder 400 includes g_BYPASSla 405, a BYPASS2a 420, and a BYPASS3 450. BYPASSla4〇5 has the same components and power month b' as BYPASS1_A3()5 in Figure 3. The first input of BYPASSla405 is the same as the first input of bypass1_a3〇5, which is used to receive a shift. The shift value and the first link value generated after the four bits in the bit stream are connected, the second input of the BYPASSla 405 and the second input of the BYPASS 1-A 305 are received to receive the range value, and the BypASS i The output of the & 405 outputs the same Wni and 〇 as the output of BYPASS1_A3〇5. The adder 410 of Fig. 4 corresponds to the adder 31A of Fig. 3, and the multiplexer 415 of Fig. 4 corresponds to the multiplexer 315 of Fig. 3, and therefore, the adder and the multiplexer 415 are not described again. Operation process. BYPASS2a420 and 3rd _BYPASS2_B350 - have corresponding components and functions, wherein the first input of BYPASS2a420 is the same as the first input of bypasS2_B 350, and is received by an offset two-bit value and bit stream. The second link value generated after the third and fourth bits, the second input of BYpASS2a420 is the same as the second input end of BYPASS2-B 350, and is used to receive the range value, the output of BYPASS2a 420 and BYPASS2JB 35 The output of 〇 outputs _ and 0ffset2 as well. In addition, adders 426, 424, and 422 of 'BYPASS2a 420 correspond to adders 365, 360, and 355 of 13 201134106 BYPASS2-B 350; multiplexers 430, 440, and 435 of BYPASS2a 420 correspond to multiplexers of BYPASS2JB 35〇 38〇, 385 and 390. Therefore, the operation of BYPASS2a42〇 will not be repeated. The BYPASS 3 450 is now added to improve the second bypass bit decoder 300 of FIG. 3 to become the triple bypass bit decoder 4 of FIG. The first input of the B45 port is configured to receive the second link value generated by the -shift offset value and the fourth to second bit in the bit stream. The second input end of the BYPASS3 45G is used to receive the range value. The output of the BYPASS3 450 is connected to the output of the seventh multiplexer 485. In BYPASS3 450, a first input end of a first multiplexer 47A, a first input end of a first adder 451, a first input end of a second adder, and a second adder 455 a first input terminal, a first input terminal of a fourth adder 457, a first input terminal of a fifth adder 459, a first input terminal of a sixth adder 461, and a first adder of a seventh adder 463 The input terminal is connected to the first input of the BypASS3 for receiving the third link value. In the first adder 451, the third link value is deducted from the range value of the -bit received by the second input terminal of the first adder 451 to generate a first difference value. The second input end and the control input end of the first multiplexer are difficult to receive the first difference value, and the root-difference value is greater than a predetermined value, for example; go to = switch the first multiplex The signal output by the device 470. In the second adder 453, the third link value deducts the range value of the two bits received by the input end, and generates a second input method of the second input method of the second method 1^453. In the second adder ^ two multiplexer difference. In the third adder loose, the third link value is output; the force receives the range value of the three bits received by the second input terminal, and generates the second input end and the control input of the 455 The second multiplexer is configured to receive the third difference, and according to whether the third difference is greater than a predetermined value, ^^ ' determines to switch the signal output by the second multiplexer 4? ; zero' go in the fourth adder 457, the third link value deducts the range value of the four-bits of the rounds to generate a fourth difference. The difference value is connected to the round output end of the fourth adder 457, for receiving the output of the fine 以 帛 帛 _ 459, determining: ί five difference ' according to whether the fifth difference is greater than - A predetermined value, such as zero, is used to switch the signal output by the third multiplexer 474. In the sixth adder 461, the third link value is deducted from the range value of the second bit of the second adder of the sixth adder 461 to generate a sixth difference value. - the fourth multiplexer, the input_ is connected to the round-out end of the sixth adder 461 for receiving the sixth one-two-second seventh adder 463, and the third link value is subtracted from the first of the seventh adder 463 Enter the range value of the seven-bit received by ^ to generate the - seventh difference. The second input end and the control input end of the 15th 201134106 476 are coupled to the rounding end of the seventh adder 463 for receiving the seventh difference, and determining whether the seventh difference is greater than a predetermined value, for example, zero. The signal output by the fourth multiplexer 476 is switched. The first input end of the fifth multiplexer 480 receives the instruction of the first multiplexer 470, and the first input receives the signal output by the first multiplexer 472. The control input receives the multiplexer 415 of the BYPASSU 405. The output signal is controlled according to whether the signal output by the multiplexer 415 of the BYPASSla 4〇5 is greater than a predetermined value, such as zero, to control the signal output by the fifth multiplexer 480. The first input of a sixth multiplexer 482 receives the signal output by the third multiplexer 474, the second input receives the signal output by the fourth multiplexer 476, and the control input receives the multiplexer 415 of the BYPASS la 405. The output signal is based on whether the signal output by the multiplexer 415 of the BYPASSla 405 is greater than a predetermined value, such as zero', to control the signal output by the sixth multiplexer 482. The first of the seventh multiplexer 485 receives the signal output by the fifth multiplexer, and the second input receives the signal of the sixth multiplex 482 output. The control input receives the multiplexer milk output of the BypAss2a. Signal. The output of the seventh multiplexer 485 is used to output coffee and guns, that is, the output of the BYPASS3 45〇 output coffee and guilty. Month ^, ', Figure 5, Figure 5 shows how to use the three bypass bit code 400 of Figure 4 and the second bypass bit decoder 3 (8) of Figure 3 to form a parallel five bypass. A schematic diagram of the decoder 500. In the fifth figure, the input end of the smashing stone device receives the appropriate bit. The current flow and the value are calculated. The output of the three bypass bit solution is output to the _, bin2, bin3 transposition bit stream. Lai 2 bypass bit turns 1 & long computation path to achieve phase design. The bypass bit decoder proposed in this (4) can improve the lightness of the traditional side-by-side element decoding H-length county path, 40% of the operation_. For example, a conventional five-pass bit decoder that requires about 6 bits (10) MHz for decoding the five-bit per cycle, but the five-bypass bit reader of the present invention requires only 4 nS (250 MHz, Fujitsu 90 nm process). ). The above is only the preferred embodiment of the present invention, and all the modifications and modifications made by the scope of the present invention should fall within the scope of the present invention. [Simple description of the drawing] Fig. 1 is a schematic diagram of a video processing system. Fig. 2 is a view showing a series bypass bit decoding piano applied to the video processing secret of Fig. 1. Figure 3 is a schematic illustration of a parallel two-pass bit decoder in accordance with an embodiment of the present invention. Figure 4 is a schematic diagram of a parallel three-way bit decoder illustrated by another embodiment of the present invention. Figure 5 is a schematic illustration of another embodiment of the present invention illustrating a parallel five-pass bit decoder. [Main component symbol description] 10 Video processing system 11 Video source 12 Video processor 13 Video display 20 Decoder 25, 40 Register 35 Determine bit decoder 30, 200 Bypass bit decoder 205 First link module 207 second connection module 209 third connection module 211 fourth connection module 221 '470 first multiplexer 223 ' 472 second multiplexer 225 > 474 third multiplexer 227, 476 fourth multiplex 480 fifth multiplexer 201134106 482 sixth multiplexer 485 seventh multiplexer 231 '451 first adder 233 '453 second adder 235, 455 third adder 237 > 457 fourth adder
459 第五加法器 461 第六加法器 463 第七加法器 300 二旁路位元解碼器 305 BYPASS 1_A 350 BYPASS2B 315 、 380 、385、390、415、430、440、435 310 > 365 、360、355、410、426、424、422 400 三旁路位元解碼器 405 BYPASS la 420 BYPASS2a 450 BYPASS3 500 五旁路位元解碼器 多工器 加法器 19459 fifth adder 461 sixth adder 463 seventh adder 300 two bypass bit decoder 305 BYPASS 1_A 350 BYPASS2B 315, 380, 385, 390, 415, 430, 440, 435 310 > 365, 360, 355, 410, 426, 424, 422 400 Triple Bypass Bit Decoder 405 BYPASS la 420 BYPASS2a 450 BYPASS3 500 Five Bypass Bit Decoder Multiplexer Adder 19