TWI456579B - 提昇錯誤更正能力之方法以及相關之記憶裝置及其控制器 - Google Patents
提昇錯誤更正能力之方法以及相關之記憶裝置及其控制器 Download PDFInfo
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
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Claims (23)
- 一種提昇錯誤更正能力之方法,該方法係應用於一記憶裝置的控制器,該方法不需要增加錯誤更正碼引擎(Error Correction Code Engine,ECC Engine)編/解碼位元數就能提昇該控制器的錯誤更正能力,該方法包含有:檢查解碼編碼後資料的一疊代次數是否達到一上限,其中該上限係事先決定於該控制器中,且該編碼後資料係經由一編碼程序所編碼,該編碼程序包含有:針對一資料位元陣列之複數列,分別計算複數個第一奇偶校驗碼(Parity Code);針對該資料位元陣列之複數行所形成的複數組,分別計算複數個第二奇偶校驗碼,其中該些組中之每一組包含該些行中之兩行或更多行,且該些組彼此不重疊;以及進行對應於該些第一、第二奇偶校驗碼之編碼;當該疊代次數達到該上限,回報解碼失敗,否則利用至少一部分之該第二奇偶校驗碼來針對相對應行執行第一錯誤更正,之後基於該第一錯誤更正,檢查原本具有至少一錯誤的至少一列是否完全地被更正;當原本具有至少一錯誤之該列具有尚未被更正的錯誤,執行對應該複數列中的一列或是更多列的操作,來依據該第一奇偶校驗碼的至少一部分來執行第二錯誤更正,並進一步檢查原本具有至少一錯誤之該列是否仍具有尚未被更正的錯誤;以及 當原本具有至少一錯誤之該列仍具有尚未被更正的錯誤,增加該疊代次數並且重新檢查解碼該編碼後資料之該疊代次數是否達到該上限,以疊代地執行至少該第一錯誤更正或是該第二錯誤更正,直到該編碼後資料成功地被解碼或是該解碼失敗被回報。
- 如申請專利範圍第1項所述之方法,其中該疊代次數代表疊代進行該第一錯誤更正以及該第二錯誤更正的至少其中之一的次數。
- 如申請專利範圍第1項所述之方法,其中該些組各自的行數彼此相等,以及每一組的資料位元之數量等於每一列的資料位元之數量。
- 如申請專利範圍第1項所述之方法,其中該資料位元陣列以及該些第一、第二奇偶校驗碼係儲存於該記憶裝置中之一快閃記憶體(Flash Memory)。
- 一種提昇錯誤更正能力之方法,該方法係應用於一記憶裝置的控制器,該方法不需要增加錯誤更正碼引擎(Error Correction Code Engine,ECC Engine)編/解碼位元數就能提昇該控制器的錯誤更正能力,該方法包含有:針對一資料位元陣列之複數列,分別計算複數個第一奇偶校驗碼 (Parity Code);針對該資料位元陣列之複數行所形成的複數組,分別計算複數個第二奇偶校驗碼,其中該些組中之每一組包含該些行中之兩行或更多行,且該些組彼此不重疊;以及進行對應於該些第一、第二奇偶校驗碼之編/解碼;其中該些組各自的行數彼此相等,以及每一組的資料位元之數量等於每一列的資料位元之數量。
- 如申請專利範圍第5項所述之方法,其中每一列的位元組(Byte)之數量等於每一組的行之數量;以及該些列的數量等於該些組的數量。
- 如申請專利範圍第6項所述之方法,其中每一列具有1024位元組的資料,且該些列的數量等於8;每一組具有該些行中之1024行,且該些組的數量等於8;以及每一第一奇偶校驗碼具有42位元組,且每一第二奇偶校驗碼具有14位元組。
- 一種記憶裝置,其錯誤更正能力在不需要增加錯誤更正碼引擎(Error Correction Code Engine,ECC Engine)編/解碼位元數的狀況下就能提昇,該記憶裝置包含有:一快閃記憶體(Flash Memory),該快閃記憶體包含複數個區塊;以及一控制器,用來存取(Access)該快閃記憶體以及管理該複數 個區塊,其中該控制器之錯誤更正碼引擎係藉由利用該控制器中之微處理器及/或控制邏輯來實施,以及該錯誤更正碼引擎包含有:一第一奇偶校驗碼(Parity Code)計算模組,用來針對一資料位元陣列之複數列,分別計算複數個第一奇偶校驗碼;以及複數個第二奇偶校驗碼計算模組,用來針對該資料位元陣列之複數行所形成的複數組,分別計算複數個第二奇偶校驗碼,其中該些組中之每一組包含該些行中之兩行或更多行,且該些組彼此不重疊;其中該錯誤更正碼引擎係用來進行對應於該些第一、第二奇偶校驗碼之編碼以產生編碼後資料;該錯誤更正碼引擎係用來檢查解碼編碼後資料的一疊代次數是否達到一上限,其中該上限係事先決定於該控制器中;當該疊代次數達到該上限,該錯誤更正碼引擎回報解碼失敗,否則該錯誤更正碼引擎利用至少一部分之該第二奇偶校驗碼來針對相對應行執行第一錯誤更正,之後基於該第一錯誤更正,檢查原本具有至少一錯誤的至少一列是否完全地被更正;當原本具有至少一錯誤之該列具有尚未被更正的錯誤,該錯誤更正碼引擎執行對應該複數列中的一列或是更多列的操作,來依據該第一奇偶校驗碼的至少一部分來執行第二錯誤更正,並進一步檢查原本具有至少一錯誤之該列是否仍具有尚未被更正的錯誤;以及 當原本具有至少一錯誤之該列仍具有尚未被更正的錯誤,該錯誤更正碼引擎增加該疊代次數並且重新檢查解碼該編碼後資料之該疊代次數是否達到該上限,以疊代地執行至少該第一錯誤更正或是該第二錯誤更正,直到該編碼後資料成功地被解碼或是該解碼失敗被回報。
- 如申請專利範圍第8項所述之記憶裝置,其中該疊代次數代表疊代進行該第一錯誤更正以及該第二錯誤更正的至少其中之一的次數。
- 如申請專利範圍第8項所述之記憶裝置,其中該些組各自的行數彼此相等,以及每一組的資料位元之數量等於每一列的資料位元之數量。
- 如申請專利範圍第8項所述之記憶裝置,其中在該錯誤更正碼引擎係用來進行對應於該些第一、第二奇偶校驗碼之編碼的狀況下,該控制器將該資料位元陣列以及該些第一、第二奇偶校驗碼儲存於該快閃記憶體。
- 一種記憶裝置,其錯誤更正能力在不需要增加錯誤更正碼引擎(Error Correction Code Engine,ECC Engine)編/解碼位元數的狀況下就能提昇,該記憶裝置包含有:一快閃記憶體(Flash Memory),該快閃記憶體包含複數個區 塊;以及一控制器,用來存取(Access)該快閃記憶體以及管理該複數個區塊,其中該控制器之錯誤更正碼引擎係藉由利用該控制器中之微處理器及/或控制邏輯來實施,以及該錯誤更正碼引擎包含有:一第一奇偶校驗碼(Parity Code)計算模組,用來針對一資料位元陣列之複數列,分別計算複數個第一奇偶校驗碼;以及複數個第二奇偶校驗碼計算模組,用來針對該資料位元陣列之複數行所形成的複數組,分別計算複數個第二奇偶校驗碼,其中該些組中之每一組包含該些行中之兩行或更多行,且該些組彼此不重疊;其中該錯誤更正碼引擎係用來進行對應於該些第一、第二奇偶校驗碼之編/解碼;其中該些組各自的行數彼此相等,以及每一組的資料位元之數量等於每一列的資料位元之數量。
- 如申請專利範圍第12項所述之記憶裝置,其中每一列的位元組(Byte)之數量等於每一組的行之數量;以及該些列的數量等於該些組的數量。
- 如申請專利範圍第13項所述之記憶裝置,其中每一列具有1024位元組的資料,且該些列的數量等於8;每一組具有該些 行中之1024行,且該些組的數量等於8;以及每一第一奇偶校驗碼具有42位元組,且每一第二奇偶校驗碼具有14位元組。
- 如申請專利範圍第12項所述之記憶裝置,其中在該錯誤更正碼引擎係用來進行對應於該些第一、第二奇偶校驗碼之解碼的狀況下,該資料位元陣列係讀取自該快閃記憶體,並且該錯誤更正碼引擎依據透過計算所取得之該些第一、第二奇偶校驗碼以及讀取自該快閃記憶體之第一、第二奇偶校驗碼進行錯誤偵測或錯誤更正。
- 一種記憶裝置之控制器,其錯誤更正能力在不需要增加錯誤更正碼引擎(Error Correction Code Engine,ECC Engine)編/解碼位元數的狀況下就能提昇,該控制器係用來存取(Access)該記憶裝置中之一快閃記憶體(Flash Memory),該快閃記憶體包含複數個區塊,該控制器包含有:一唯讀記憶體(Read Only Memory,ROM),用來儲存一程式碼;以及一微處理器,用來執行該程式碼以控制對該快閃記憶體之存取以及管理該複數個區塊;其中該控制器之錯誤更正碼引擎係藉由利用該控制器中之控制邏輯及/或執行該程式碼之該微處理器來實施,以及該錯誤更正碼引擎包含有:一第一奇偶校驗碼(Parity Code)計算模組,用來針對一資料 位元陣列之複數列,分別計算複數個第一奇偶校驗碼;以及複數個第二奇偶校驗碼計算模組,用來針對該資料位元陣列之複數行所形成的複數組,分別計算複數個第二奇偶校驗碼,其中該些組中之每一組包含該些行中之兩行或更多行,且該些組彼此不重疊;其中該錯誤更正碼引擎係用來進行對應於該些第一、第二奇偶校驗碼之編碼以產生編碼後資料;該錯誤更正碼引擎係用來檢查解碼編碼後資料的一疊代次數是否達到一上限,其中該上限係事先決定於該控制器中;當該疊代次數達到該上限,該錯誤更正碼引擎回報解碼失敗,否則該錯誤更正碼引擎利用至少一部分之該第二奇偶校驗碼來針對相對應行執行第一錯誤更正,之後基於該第一錯誤更正,檢查原本具有至少一錯誤的至少一列是否完全地被更正;當原本具有至少一錯誤之該列具有尚未被更正的錯誤,該錯誤更正碼引擎執行對應該複數列中的一列或是更多列的操作,來依據該第一奇偶校驗碼的至少一部分來執行第二錯誤更正,並進一步檢查原本具有至少一錯誤之該列是否仍具有尚未被更正的錯誤;以及當原本具有至少一錯誤之該列仍具有尚未被更正的錯誤,該錯誤更正碼引擎增加該疊代次數並且重新檢查解碼該編碼後資料之該疊代次數是否達到該上限,以疊代地執行至少該第一錯誤更正或是該第二錯誤更正,直到該編碼後資料成功地被解碼 或是該解碼失敗被回報。
- 如申請專利範圍第16項所述之控制器,其中該疊代次數代表疊代進行該第一錯誤更正以及該第二錯誤更正的至少其中之一的次數。
- 如申請專利範圍第16項所述之控制器,其中該些組各自的行數彼此相等,以及每一組的資料位元之數量等於每一列的資料位元之數量。
- 如申請專利範圍第16項所述之控制器,其中在該錯誤更正碼引擎係用來進行對應於該些第一、第二奇偶校驗碼之編碼的狀況下,該控制器將該資料位元陣列以及該些第一、第二奇偶校驗碼儲存於該快閃記憶體。
- 如申請專利範圍第16項所述之控制器,其中在該錯誤更正碼引擎係用來進行對應於該些第一、第二奇偶校驗碼之解碼的狀況下,該資料位元陣列係讀取自該快閃記憶體,並且該錯誤更正碼引擎依據透過計算所取得之該些第一、第二奇偶校驗碼以及讀取自該快閃記憶體之第一、第二奇偶校驗碼進行錯誤偵測或錯誤更正。
- 一種記憶裝置之控制器,其錯誤更正能力在不需要增加錯誤更 正碼引擎(Error Correction Code Engine,ECC Engine)編/解碼位元數的狀況下就能提昇,該控制器係用來存取(Access)該記憶裝置中之一快閃記憶體(Flash Memory),該快閃記憶體包含複數個區塊,該控制器包含有:一唯讀記憶體(Read Only Memory,ROM),用來儲存一程式碼;以及一微處理器,用來執行該程式碼以控制對該快閃記憶體之存取以及管理該複數個區塊;其中該控制器之錯誤更正碼引擎係藉由利用該控制器中之控制邏輯及/或執行該程式碼之該微處理器來實施,以及該錯誤更正碼引擎包含有:一第一奇偶校驗碼(Parity Code)計算模組,用來針對一資料位元陣列之複數列,分別計算複數個第一奇偶校驗碼;以及複數個第二奇偶校驗碼計算模組,用來針對該資料位元陣列之複數行所形成的複數組,分別計算複數個第二奇偶校驗碼,其中該些組中之每一組包含該些行中之兩行或更多行,且該些組彼此不重疊;其中該錯誤更正碼引擎係用來進行對應於該些第一、第二奇偶校驗碼之編/解碼;其中該些組各自的行數彼此相等,以及每一組的資料位元之數量等於每一列的資料位元之數量。
- 如申請專利範圍第21項所述之控制器,其中每一列的位元組 (Byte)之數量等於每一組的行之數量;以及該些列的數量等於該些組的數量。
- 如申請專利範圍第22項所述之控制器,其中每一列具有1024位元組的資料,且該些列的數量等於8;每一組具有該些行中之1024行,且該些組的數量等於8;以及每一第一奇偶校驗碼具有42位元組,且每一第二奇偶校驗碼具有14位元組。
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