TWI454063B - Clamping circuit and common voltage generating circuit - Google Patents
Clamping circuit and common voltage generating circuit Download PDFInfo
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- TWI454063B TWI454063B TW100125942A TW100125942A TWI454063B TW I454063 B TWI454063 B TW I454063B TW 100125942 A TW100125942 A TW 100125942A TW 100125942 A TW100125942 A TW 100125942A TW I454063 B TWI454063 B TW I454063B
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Description
本發明有關於箝位電路以及共模電壓產生電路,特別有關於使用可調式電流源的箝位電路以及共模電壓產生電路。The present invention relates to a clamp circuit and a common mode voltage generating circuit, and more particularly to a clamp circuit using a variable current source and a common mode voltage generating circuit.
傳統上,會使用一箝位電路來提供類比數位轉換器的共模電壓。第1圖繪示了習知技術中使用箝位電路來提供共模電壓的示意圖。第1圖中所舉的電路為電視訊號處理電路,其包含了一數位訊號處理電路101、一類比數位轉換器103、一箝位電路105、以及兩電容107、109。類比數位轉換器103具有兩輸入端104、106,用以分別接收電視訊號Vin 和Vip 以形成一差動訊號。類比數位轉換器103用以接收類比的電視訊號,並轉成數位電視訊號給數位訊號處理電路101處理。至於何時以及要提供多大的共模電壓給類比數位轉換器103來處理電視訊號,為熟知此項技藝者所知悉,故在此不再贅述。Traditionally, a clamp circuit is used to provide the common mode voltage of an analog digital converter. FIG. 1 is a schematic diagram showing the use of a clamp circuit to provide a common mode voltage in the prior art. The circuit shown in FIG. 1 is a television signal processing circuit including a digital signal processing circuit 101, an analog digital converter 103, a clamp circuit 105, and two capacitors 107, 109. The analog digital converter 103 has two inputs 104, 106 for receiving the television signals V in and V ip , respectively, to form a differential signal. The analog digital converter 103 is configured to receive the analog television signal and convert it into a digital television signal for processing by the digital signal processing circuit 101. As to when and how much common mode voltage is to be supplied to the analog digital converter 103 for processing television signals, as will be appreciated by those skilled in the art, no further details are provided herein.
箝位電路105用以對類比數位轉換器103之輸入路徑上的電容107和109進行充電,用以提供共模電壓Vcm 給類比數位轉換器103。然而,傳統的箝位電路通常都是提供固定的充電電流。以第1圖中的箝位電路105為例,其係由多個電阻111、113和115和開關元件117、119組成。因此,若開關元件117、119導通,電阻111、113和115便形成一分壓電路產生Vmid ,並據此輸出電流至電容107、109進行充電。然而,這樣的電流結構容易造成充電電流的浪費。舉例來說,當電容已經快被充至最大電壓時,流向A路徑的電流便會變小,而流至B路徑的電流便會變大。如此一來,大部份的電流便會被浪費掉,而造成了無謂的功率消耗。Clamp circuit 105 is used to charge capacitors 107 and 109 on the input path of analog-to-digital converter 103 to provide common mode voltage V cm to analog digital converter 103. However, conventional clamp circuits typically provide a fixed charging current. Taking the clamp circuit 105 in Fig. 1 as an example, it is composed of a plurality of resistors 111, 113 and 115 and switching elements 117, 119. Therefore, if the switching elements 117, 119 are turned on, the resistors 111, 113, and 115 form a voltage dividing circuit to generate Vmid , and accordingly, current is output to the capacitors 107, 109 for charging. However, such a current structure is liable to cause a waste of charging current. For example, when the capacitor is already charged to the maximum voltage, the current flowing to the A path becomes smaller, and the current flowing to the B path becomes larger. As a result, most of the current is wasted, resulting in unnecessary power consumption.
因此本發明之一目的為提供一種可動態調整充放電電流的箝位電路。It is therefore an object of the present invention to provide a clamp circuit that dynamically adjusts the charge and discharge current.
本發明之另一目的為提供一種可動態調整充放電電流的共模電壓產生電路。Another object of the present invention is to provide a common mode voltage generating circuit that can dynamically adjust a charge and discharge current.
本發明之一實施例揭露了一種箝位電路,包含:一控制電路,用以產生一控制訊號;至少一可調式電流源,用以接收該控制訊號,以提供至少一充電電流來對至少一電容進行充電或使該電容進行放電,以產生一箝位電壓;以及一比較器,根據該箝位電壓以及一參考電壓來產生一比較結果,且該控制電路根據該比較結果來產生該控制訊號。An embodiment of the present invention discloses a clamping circuit including: a control circuit for generating a control signal; and at least one adjustable current source for receiving the control signal to provide at least one charging current for at least one Capacitor charging or discharging the capacitor to generate a clamping voltage; and a comparator, generating a comparison result according to the clamping voltage and a reference voltage, and the control circuit generates the control signal according to the comparison result .
本發明之另一實施例揭露了一種共模電壓產生電路,用以產生一類比數位轉換器的一共模電壓,包含:一控制電路,用以產生一控制訊號;至少一可調式電流源,用以接收該控制訊號,以提供至少一充電電流來對該類比數位轉換器之訊號輸入路徑上至少一電容進行充放電,以產生該共模電壓;以及一比較器,根據該共模電壓以及一參考電壓來產生一比較結果,且該控制電路根據該比較結果來產生該控制訊號。Another embodiment of the present invention discloses a common mode voltage generating circuit for generating a common mode voltage of an analog converter, comprising: a control circuit for generating a control signal; and at least one adjustable current source for Receiving the control signal to provide at least one charging current to charge and discharge at least one capacitor on the signal input path of the analog-to-digital converter to generate the common mode voltage; and a comparator according to the common mode voltage and a The reference voltage is used to generate a comparison result, and the control circuit generates the control signal based on the comparison result.
依據前述實施例,可視充電狀況動態的調整充放電的電流,因此可減少不必要的功率消耗。According to the foregoing embodiment, the charging and discharging current is dynamically adjusted in accordance with the visual charging condition, and thus unnecessary power consumption can be reduced.
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解,硬體製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式,而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語,故應解釋成「包含但不限定於」。以外,「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此,若文中描述一第一裝置耦接於一第二裝置,則代表該第一裝置可直接電氣連接於該第二裝置,或透過其他裝置或連接手段間接地電氣連接至該第二裝置。Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.
第2圖繪示了根據本發明之實施例的箝位電路200之電路圖。箝位電路200係使用單一可調式電流源來對不同的電容進行充放電以俺生箝位電壓。如第2圖所示,箝位電路200包含了一控制電路201、一可調式電流源203,以及一比較器205。控制電路201用以產生控制訊號CS。箝位電路200亦可視為一共模電壓產生電路,用以產生共模電壓給一類比數位轉換器。然而箝位電路200亦可運用在其他電子裝置上,來提供箝位電壓給一目標電子裝置。可調式電流源203用以接收控制訊號CS,以提供一充電電流IC1 、IC2 來對電容209、211進行充電或提供電容209、211之放電路徑,以產生箝位電壓Vclamp 。比較器205(此例中為一磁滯比較器)根據箝位電壓Vclamp 以及一參考電壓Vref 來產生一比較結果,且控制電路201根據比較結果來產生控制訊號CS。請留意,於此實施例,輸入端212和214所接收的訊號Vip 和Vin 可以為單端輸入訊號,亦即Vip 和Vin 中僅有其中一個具有小訊號部份。或者,Vip 和Vin 中可以兩個均具有小訊號部份。在此實施例中,可調式電流源203具有N型金氧半導體電晶體215以及P型金氧半導體電晶體217。這些金氧半導體電晶體之閘極分別接收控制訊號CS,因此可根據不同的控制訊號CS產生不同的電流。請留意可調式電流源203亦可由其他電路代替,不限於由P型金氧半導體電晶體和N型金氧半導體電晶體所組成。FIG. 2 is a circuit diagram of a clamp circuit 200 in accordance with an embodiment of the present invention. Clamp circuit 200 uses a single adjustable current source to charge and discharge different capacitors to generate a clamping voltage. As shown in FIG. 2, the clamp circuit 200 includes a control circuit 201, an adjustable current source 203, and a comparator 205. The control circuit 201 is configured to generate a control signal CS. Clamp circuit 200 can also be considered as a common mode voltage generating circuit for generating a common mode voltage to an analog to digital converter. However, the clamp circuit 200 can also be applied to other electronic devices to provide a clamp voltage to a target electronic device. The adjustable current source 203 is configured to receive the control signal CS to provide a charging current I C1 , I C2 to charge the capacitors 209 , 211 or to provide a discharge path of the capacitors 209 , 211 to generate a clamping voltage V clamp . The comparator 205 (in this example, a hysteresis comparator) generates a comparison result based on the clamp voltage V clamp and a reference voltage V ref , and the control circuit 201 generates the control signal CS based on the comparison result. Please note that in this embodiment, the signals V ip and V in received by the inputs 212 and 214 can be single-ended input signals, that is, only one of V ip and V in has a small signal portion. Alternatively, both V ip and V in can have small signal portions. In this embodiment, the tunable current source 203 has an N-type MOS transistor 215 and a P-type MOS transistor 217. The gates of these MOS transistors receive the control signal CS, respectively, so that different currents can be generated according to different control signals CS. Please note that the adjustable current source 203 can also be replaced by other circuits, and is not limited to being composed of a P-type MOS transistor and an N-type MOS transistor.
箝位電路200可更具有一開關元件208,用以使類比數位轉換器213上的兩訊號接收路徑之箝位電壓Vclamp 等電壓。其詳細的運作方式為:箝位電路200可運作在一通常模式和一箝位模式。在通常模式下,開關元件208不導通,且箝位電路200不運作(亦即可調式電流源203內的金氧半導體電晶體關閉),類比數位轉換器213便依照電容209和211所形成的箝位電壓Vclamp 來動作。而在箝位模式下,開關元件208在箝位電路200依照前述之動作對電容209和211進行充電或放電前會導通,如此可使類比數位轉換器213上的兩訊號接收路徑之箝位電壓Vclamp 變成相同的位準,然後箝位電路200會依照前述之動作來對電容209和211進行充電或放電。於一實施例中,訊號Vip 和Vin 在箝位模式被控制成不具有小訊號部份,如此才不會干擾到箝位電壓的判斷。The clamping circuit 200 can further have a switching element 208 for making a voltage equal to the clamping voltage V clamp of the two signal receiving paths on the analog converter 213. The detailed operation mode is that the clamp circuit 200 can operate in a normal mode and a clamp mode. In the normal mode, the switching element 208 is not turned on, and the clamp circuit 200 does not operate (ie, the MOS transistor in the modulating current source 203 is turned off), and the analog digital converter 213 is formed according to the capacitors 209 and 211. The clamp voltage V clamp operates . In the clamp mode, the switching element 208 is turned on before the clamping circuit 200 charges or discharges the capacitors 209 and 211 according to the foregoing actions, so that the clamping voltage of the two signal receiving paths on the analog-to-digital converter 213 can be made. The V clamp becomes the same level, and then the clamp circuit 200 charges or discharges the capacitors 209 and 211 in accordance with the aforementioned actions. In one embodiment, the signals V ip and V in are controlled in the clamp mode to have no small signal portions so as not to interfere with the determination of the clamp voltage.
第3圖繪示了根據本發明之實施例的箝位電路之動作示意圖。控制電路201係以一D型正反器來施行之。而可調式電流源203中的金氧半導體電晶體係由比較器205之輸出S0 以及控制電路201之輸出S1 的組合來控制。例如,可用一邏輯電路202接收S0 、S1 後,產生一輸出訊號Out,但並非限定使用硬體的邏輯電路來根據S0 、S1 控制可調式電流源203中的金氧半導體電晶體,亦可經由其他方式來控制。如第3圖所示,當自比較器205輸出之訊號S0 的值為0,而自控制電路201輸出的訊號S1 為0時,可調式電流源203的P型金氧半導體電晶體215為導通,N型金氧半導體電晶體217為不導通。此時可調式電流源203會對電容209和211進行充電。而當訊號S0 的值為1,訊號S1 為1時,可調式電流源203的P型金氧半導體電晶體215為不導通,N型金氧半導體電晶體217為導通。此時電容209、和211會進行放電。上述充電或放電之動作,即為前述之箝位模式。而當訊號S0 、訊號S1 之組合為(0,1)或(1,0)時,便為通常模式,可調式電流源203的P型金氧半導體電晶體215和N型金氧半導體電晶體217均為不導通。FIG. 3 is a schematic diagram showing the operation of the clamp circuit according to an embodiment of the present invention. The control circuit 201 is implemented as a D-type flip-flop. And an adjustable current source 203 in the power MOS crystal system is controlled by a combination of the comparator outputs S 0 and 205. The output control circuit 201 is S 1. For example, a logic circuit 202 can receive an output signal Out after receiving S 0 , S 1 , but does not limit the logic circuit using hardware to control the MOS transistor in the adjustable current source 203 according to S 0 , S 1 . It can also be controlled by other means. As shown in FIG. 3, when the value of the signal S 0 outputted from the comparator 205 is 0, and the signal S 1 output from the control circuit 201 is 0, the P-type MOS transistor 215 of the adjustable current source 203 To be turned on, the N-type MOS transistor 217 is non-conductive. At this time, the adjustable current source 203 charges the capacitors 209 and 211. When the value of the signal S 0 is 1, and the signal S 1 is 1, the P-type MOS transistor 215 of the adjustable current source 203 is non-conductive, and the N-type MOS transistor 217 is turned on. At this time, the capacitors 209, and 211 are discharged. The above charging or discharging action is the aforementioned clamping mode. When the combination of the signal S 0 and the signal S 1 is (0, 1) or (1, 0), it is the normal mode, the P-type MOS transistor 215 and the N-type MOS semiconductor of the adjustable current source 203. The transistors 217 are all non-conductive.
第4圖繪示了根據本發明之另一實施例的箝位電路400之電路圖。相較於箝位電路200,箝位電路400亦具有控制電路401、可調式電流源403、407以及比較器405,可調式電流源403、407亦被控制電路401來對類比數位轉換器413之兩訊號接收路徑上的電容409和411進行充放電。箝位電路200以及箝位電路400之差別在於箝位電路200係以同一可調式電流源203來對不同電容209和211進行充放電,而箝位電路400係使用不同的可調式電流源403、407來分別對不同的電容409、411進行充放電,因此箝位電路200和箝位電路400之電路結構略有不同。箝位電路400不包含箝位電路200的開關元件208,且具有兩個比較器405、406。可調式電流源403、407分別對電容409、411進行充放電,且比較器405、406分別比較電容409和411所形成的箝位電壓並將比較結果傳送至控制電路401。FIG. 4 is a circuit diagram of a clamp circuit 400 in accordance with another embodiment of the present invention. Compared with the clamp circuit 200, the clamp circuit 400 also has a control circuit 401, adjustable current sources 403, 407 and a comparator 405. The adjustable current sources 403, 407 are also controlled by the control circuit 401 for the analog digital converter 413. Capacitors 409 and 411 on the two signal receiving paths are charged and discharged. The difference between the clamp circuit 200 and the clamp circuit 400 is that the clamp circuit 200 charges and discharges the different capacitors 209 and 211 by the same adjustable current source 203, and the clamp circuit 400 uses different adjustable current sources 403, 407 to charge and discharge the different capacitors 409, 411, respectively, so the circuit structure of the clamp circuit 200 and the clamp circuit 400 are slightly different. Clamp circuit 400 does not include switching element 208 of clamp circuit 200 and has two comparators 405, 406. The adjustable current sources 403, 407 charge and discharge the capacitors 409, 411, respectively, and the comparators 405, 406 compare the clamp voltages formed by the capacitors 409 and 411, respectively, and transmit the comparison results to the control circuit 401.
箝位電路400之動作可如下所示:當箝位電路400操作於一箝位模式時,比較器405和406分別比較箝位電壓和參考電壓Vref 來產生控制訊號CS。而當箝位電路400操作於一通常模式時,可調式電流源403、407不動作(即其內的P型金氧半導體電晶體415、419和N型金氧半導體電晶體417、421關閉),類比數位轉換器413便依據電容409和411所產生的箝位電壓正常動作。箝位電路400之其他動作或電路細節與箝位電路200相同,故在此不再贅述。The action of the clamp circuit 400 can be as follows: When the clamp circuit 400 operates in a clamp mode, the comparators 405 and 406 compare the clamp voltage and the reference voltage V ref , respectively, to generate the control signal CS. When the clamp circuit 400 is operated in a normal mode, the adjustable current sources 403, 407 are inactive (ie, the P-type MOS transistors 415, 419 and the N-type MOS transistors 417, 421 are turned off). The analog digital converter 413 operates normally according to the clamp voltage generated by the capacitors 409 and 411. Other operations or circuit details of the clamp circuit 400 are the same as those of the clamp circuit 200, and therefore will not be described herein.
依據前述實施例,可視充電狀況動態的調整充放電的電流,因此可減少不必要的功率消耗。According to the foregoing embodiment, the charging and discharging current is dynamically adjusted in accordance with the visual charging condition, and thus unnecessary power consumption can be reduced.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
200、400...箝位電路200, 400. . . Clamp circuit
201、401...控制電路201, 401. . . Control circuit
202...邏輯電路202. . . Logic circuit
203、403、407...可調式電流源203, 403, 407. . . Adjustable current source
205、405、406...比較器205, 405, 406. . . Comparators
208...開關元件208. . . Switching element
209、211、409、411...電容209, 211, 409, 411. . . capacitance
212、214、412、414...輸入端212, 214, 412, 414. . . Input
213、413...類比數位轉換器213, 413. . . Analog digital converter
215、415、419...N型金氧半導體電晶體215, 415, 419. . . N-type MOS transistor
217、417、421...P型金氧半導體電晶體217, 417, 421. . . P-type MOS transistor
第1圖繪示了習知技術中使用箝位電路來提供共模電壓的示意圖。FIG. 1 is a schematic diagram showing the use of a clamp circuit to provide a common mode voltage in the prior art.
第2圖繪示了根據本發明之實施例的箝位電路之電路圖。FIG. 2 is a circuit diagram of a clamp circuit in accordance with an embodiment of the present invention.
第3圖繪示了根據本發明之實施例的箝位電路之動作示意圖。FIG. 3 is a schematic diagram showing the operation of the clamp circuit according to an embodiment of the present invention.
第4圖繪示了根據本發明之另一實施例的箝位電路之電路圖。FIG. 4 is a circuit diagram of a clamp circuit in accordance with another embodiment of the present invention.
200...箝位電路200. . . Clamp circuit
201...控制電路201. . . Control circuit
203...可調式電流源203. . . Adjustable current source
205...比較器205. . . Comparators
208...開關元件208. . . Switching element
209、211...電容209, 211. . . capacitance
212、214...輸入端212, 214. . . Input
213...類比數位轉換器213. . . Analog digital converter
215...N型金氧半導體電晶體215. . . N-type MOS transistor
217...P型金氧半導體電晶體217. . . P-type MOS transistor
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CN116470855B (en) * | 2023-06-19 | 2023-09-01 | 深圳市微源半导体股份有限公司 | Operational amplifier circuit, operational amplifier and linear power supply |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200704164A (en) * | 2005-07-05 | 2007-01-16 | Mediatek Inc | Clamping circuit |
US7538581B2 (en) * | 2006-08-01 | 2009-05-26 | Supertex, Inc. | Fast AC coupled level translator |
US7724043B1 (en) * | 2007-07-10 | 2010-05-25 | National Semiconductor Corporation | Common mode controller for a sample-and-hold circuit |
US7834696B2 (en) * | 2008-04-04 | 2010-11-16 | Infineon Technologies Ag | Common mode control circuitry for multi-stage operational amplifiers |
-
2011
- 2011-07-22 TW TW100125942A patent/TWI454063B/en not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200704164A (en) * | 2005-07-05 | 2007-01-16 | Mediatek Inc | Clamping circuit |
US7538581B2 (en) * | 2006-08-01 | 2009-05-26 | Supertex, Inc. | Fast AC coupled level translator |
US7724043B1 (en) * | 2007-07-10 | 2010-05-25 | National Semiconductor Corporation | Common mode controller for a sample-and-hold circuit |
US7834696B2 (en) * | 2008-04-04 | 2010-11-16 | Infineon Technologies Ag | Common mode control circuitry for multi-stage operational amplifiers |
Also Published As
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TW201306489A (en) | 2013-02-01 |
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MM4A | Annulment or lapse of patent due to non-payment of fees |